JP4930204B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a small semiconductor element is accommodated in a substrate, such as a so-called chip size semiconductor device, and a manufacturing method thereof.

  In recent years, the demand for high-density mounting of semiconductor integrated circuits has become stronger as electronic devices become more sophisticated, smaller, and lighter. Along with this, there is a demand for miniaturization of semiconductor packages, increase in the number of pins, and finer pitch of external terminals.

  A so-called WLP (Wafer Level Package) that packages a plurality of semiconductor chips at a wafer level as a semiconductor package developed from a chip size level package in order to meet the demand for downsizing the semiconductor device. (For example, refer to Patent Document 1).

  Furthermore, as a next-generation SiP (System in Package) technology, a so-called EWLP (Embedded Wafer Level Package) in which the WLP is accommodated in a recess provided in a wiring board has been attracting attention (for example, Patent Documents). 2).

An example of the configuration of the EWLP is shown in FIG. FIG. 11 is a schematic cross-sectional view showing the configuration of the EWLP type semiconductor device 100.
In the semiconductor device 100 (EWLP), the first substrate core material 101, the insulating layer 102 disposed on one main surface of the first substrate core material 101, and the insulating layer 102 are disposed on the insulating layer 102. A substrate 104 is formed with the provided second substrate core material 103, and a semiconductor chip (WLP) 200 is accommodated in a recess 104A provided through the second substrate core material 103 and the insulating layer 102. ing.

  In the substrate 104, electrodes 105 and 106 are disposed in the first substrate core material 101, the insulating layer 102, and the second substrate core material 103 so as to penetrate these. On the second substrate core material 103, wiring layers 107 and 108 that are electrically connected to the electrodes 105 and 106 are disposed.

A third substrate core material 109 is disposed on the wiring layers 107 and 108.
In the third substrate core material 109, electrodes 110 and 111 that are electrically connected to the wiring layers 107 and 108 are disposed through the substrate core material 109, and are further provided in the semiconductor chip 200. The electrodes 113 and 114 that are electrically connected to the electrode pad 201 are also provided through the third substrate core material 109.

In addition, wiring layers 115, 116, and 117 that are electrically connected to the electrodes 110, 111, 113, and 114 are disposed on one main surface of the third substrate core material 109.
An insulating layer 118 is disposed on one main surface of the third substrate core material 109 so as to cover the wiring layers 115, 116, and 117. External connection electrode terminals 122 made of solder balls are disposed at the tips of the provided electrodes 119, 120, and 121, respectively.

A method for forming such an EWLP semiconductor device 100 will be described with reference to FIGS.
A so-called multilayer wiring board forming technique is used to first form a substrate 104 composed of a laminated structure of a first substrate core material 101, an insulating layer 102, and a second substrate core material 103.

  The concave portion 104A in the substrate 104 is formed by selectively laminating an insulating layer or selectively removing the insulating layer. The electrodes 105 and 106 penetrating the substrate 104 are formed by filling a through hole provided in the substrate 104 with a conductive material such as copper (Cu) by a so-called through-hole plating method. Furthermore, wiring layers 107 and 108 are disposed on the second substrate core material 103 so as to be electrically connected to the electrodes 105 and 106.

  The semiconductor chip 200 is accommodated in the recess 104A of the substrate 104, and a third substrate core material 109 is disposed so as to cover the semiconductor chip 200, the wiring layers 107 and 108, and the like (FIG. 12). (See (A)).

Next, an opening is selectively formed in the third substrate core material 109.
That is, a part of the third substrate core material 109 is selectively removed by a laser processing method to form the opening 109A. As a result, the electrode pad 201 on the semiconductor chip 200 and a part of the wiring layers 107 and 108 are exposed (see FIG. 12B).

  Next, a metal plating layer 110 that covers the third substrate core material 109 and fills the opening 109A is connected to the electrode pad 201 and the wiring layers 107 and 108 (FIG. 12C). )reference).

  Next, a photoetching process is applied to selectively remove the metal plating layer 110, and electrodes 111, 112, 113, 114 that are electrically connected to the electrode pad 201 and the wiring layers 107, 108 on the semiconductor chip 200, and wiring Layers 115, 116, and 117 are formed (see FIG. 13A).

Next, an insulating layer 118 is formed to cover the wiring layers 115, 116, and 117, and an opening is formed in the insulating layer 118 by applying a photoetching process.
Then, metal plating is performed in the opening to fill and form the electrodes 119, 120, and 121 (see FIG. 13B).

Thereafter, external connection electrode terminals 122 made of solder balls are disposed on the exposed portions of the electrodes 119, 120, and 121 to obtain the semiconductor device structure shown in FIG.
As described above, in the EWLP type semiconductor device 100, the WLP type semiconductor chip 200 is accommodated in the recess 104A formed in the substrate 104 to achieve a highly integrated module.
JP 2000-353762 A JP 2003-298005 A

  In the configuration of EWLP shown in FIG. 11, the electrode pad 201 is provided on the semiconductor chip 200, but no electrode terminal is provided on the electrode pad 201.

Therefore, in the structure of the semiconductor chip 200, it is difficult to perform a so-called package test or the like on the semiconductor chip 200 before being housed in the substrate 104.
The manufacturing method of EWLP shown in FIGS. 12 and 13 is similar to the manufacturing method using WLP shown in Patent Document 1.

In such a manufacturing method, a lamination process such as an insulating layer, a photolithography process, and the like are repeatedly performed on the semiconductor chip 200, and the manufacturing process is long and complicated.
Therefore, in the EWLP manufacturing method, the productivity is low and the manufacturing cost is increased.

  The present invention has been made in view of the above points, and a semiconductor device that can accommodate a small semiconductor element such as a chip-sized semiconductor device in a substrate and has a higher inspection efficiency, and a method for manufacturing the same. The purpose is to provide.

In order to solve the above problems, the present invention provides a semiconductor element comprising an electrode having a concave cross-sectional shape, an electrode disposed on the semiconductor element, and an electrode having a concave cross-sectional shape of the semiconductor element and the second wiring Corresponding to the electrode of the substrate, comprising a first wiring substrate in which sharp electrode terminals are disposed, and a resin layer formed between the semiconductor element and the first wiring substrate, The semiconductor element is accommodated in the recess of the second wiring substrate having the recess, and the first wiring substrate is sharpened to the recess of the electrode having a concave cross-sectional shape of the semiconductor element and the electrode of the second wiring substrate. And the resin layer surrounds the electrode having a concave cross-sectional shape of the semiconductor element and the sharp electrode terminal of the first wiring board. .

Further, in the present invention, in order to solve the above-described problems, a step of forming an electrode having a concave cross-sectional shape on an electrode pad of a semiconductor element, and a semiconductor element in a concave portion of a second wiring board having a concave portion And a sharp electrode terminal corresponding to the electrode of the semiconductor element and the electrode of the second wiring board is arranged on the semiconductor element arranged in the recess of the second wiring board. And a sharp electrode terminal in the first wiring board, the step of disposing the first wiring board, and the recess of the electrode having a concave cross section in the semiconductor element and the electrode of the second wiring board. Between the semiconductor element and the first wiring board, a resin layer is formed between the semiconductor element and the first wiring board to surround the electrode having a concave cross-sectional shape and the sharp electrode terminal of the first wiring board. A method of manufacturing a semiconductor device, comprising: There is provided.

  According to the present invention, a semiconductor device structure capable of manufacturing a semiconductor device in which a small semiconductor element is accommodated inside a substrate, such as a so-called chip-sized semiconductor device, with high productivity and at low cost, and a manufacturing method therefor Is realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<Semiconductor device>
FIG. 1 shows a cross-sectional structure of a main part of a semiconductor device according to the present invention.

  That is, the semiconductor device 1 (EWLP) according to the present invention includes a semiconductor chip (semiconductor element) 20 (WLP), a substrate 10 that accommodates the semiconductor chip 20, a wiring substrate 30 disposed so as to cover them, and the wiring substrate 30. The external connection electrode terminal 40 is provided on the other main surface.

  That is, in the semiconductor device 1 (EWLP), the substrate 10 that houses and holds the semiconductor chip 20 is disposed on the first substrate core material 10a and one main surface of the first substrate core material 10a. An insulating layer 10b is provided, and a second substrate core material 10c is provided on the insulating layer 10b.

  Further, in the substrate 10, electrodes 10d and 10e are selectively disposed in the first substrate core material 10a, the insulating layer 10b, and the second substrate core material 10c so as to penetrate these. .

  Further, wiring layers 10f and 10g electrically connected to the electrodes 10d and 10e are selectively disposed on the second substrate core material 10c, and the wiring layers 10f and 10g are covered with an insulating layer 10h. .

  The semiconductor chip (WLP) 20 is accommodated in the recess 15 provided through the insulating layer 10 h, the second substrate core material 10 c, and the insulating layer 10 b, and is fixed by the adhesive member 21.

  In the substrate 10 having such a configuration, the substrate core materials 10a and 10c are made of an organic insulating resin containing glass fiber or the like. As the resin, an organic insulating resin such as epoxy resin, bismaleimide triazine, or polyimide is used.

On the other hand, the insulating layers 10b and 10h are made of an organic insulating resin such as epoxy resin or polyimide.
The electrodes 10d and 10e and the wiring layers 10f and 10g are made of, for example, copper (Cu).

  The electrodes 10d and 10e are formed by filling a hole provided through the substrate core materials 10a and 10c and the insulating layer 10b with a conductive material such as copper (Cu) by a so-called through-hole plating method.

  Further, the wiring layers 10f and 10g are formed by forming a copper (Cu) layer on the surface of the substrate core material 10c and then performing a selective etching process (so-called photolithography method) or by a selective plating method.

  Further, as the adhesive member 21 for fixing the semiconductor chip 20 in the recess 15 of the substrate 10, an adhesive made of epoxy resin, polyimide resin, acrylic resin, or the like is applied. The amount of the adhesive member 21 is selected so as to be between the bottom and side surfaces of the semiconductor chip 20 and the substrate 10.

  In the semiconductor chip 20, a wafer process is applied to one main surface (upper surface) of a semiconductor substrate such as Si (silicon) or gallium arsenide (GaAs), so that an active element such as a transistor or a passive element such as a capacitor element. In addition, an electronic circuit region is formed including a wiring layer for connecting these functional elements (not shown).

  An electrode pad 20a connected to the electronic circuit region is disposed on the upper surface of the semiconductor chip 20, and a bump having a concave cross section as an external connection electrode terminal on the electrode pad 20a ( Bump) electrode 20b is provided.

The section is a section perpendicular to the main surface of the semiconductor chip 20 on which the electronic circuit region is formed.
The electrode pad 20a is made of a metal mainly composed of copper (Cu) or aluminum (Al). The bump electrode 20b having a concave cross-sectional shape is composed of solder, gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

A method of forming the bump electrode 20b having a concave cross-sectional shape will be described later.
In the semiconductor device 1, the wiring substrate 30 is placed on the semiconductor chip 20 housing portion of the substrate 10.

An insulating layer 31 is disposed between the wiring substrate 30 and the semiconductor chip 20 and the substrate 10.
In the wiring board 30, a plurality of wiring layers 30 b are selectively disposed on one main surface (facing surface facing the semiconductor chip 20) of the wiring board core material 30 a made of an insulator. A sharp electrode terminal 30c is selectively disposed on the layer 30b.

  The sharp electrode terminal 30c is selectively connected to the bump electrode 20b having a concave cross-sectional shape in the semiconductor chip 20, and the wiring layer 10f disposed on the second substrate core material 10c. , 10g are selectively connected through the insulating layer 10h.

Further, in the wiring board 30, electrodes 30 d are selectively disposed through the wiring board core material 30 a.
Further, a wiring layer 30e that conducts to the electrode 30d or a non-conducting wiring layer 30f is selectively disposed on the other main surface (non-opposing surface to the semiconductor chip 20) of the wiring board core member 30a. Yes.

  An insulating layer 32 is provided so as to cover the wiring layer 30e or the wiring layer 30f, and the wiring layer exposed in the opening selectively formed in the insulating layer 32 has an external connection electrode. Solder balls constituting the terminals 40 are provided.

That is, the arrangement structure of the external connection electrode terminals 40 is a so-called BGA (Ball Grid Array) structure.
Here, the wiring board core material 30a is formed of an organic insulating resin containing glass fibers.

On the other hand, the insulating layers 31 and 32 are made of an organic insulating resin such as epoxy resin or polyimide.
The sharp electrode terminal 30c is made of gold (Au), silver (Ag), copper (Cu), or an alloy thereof. A method for forming the sharp electrode terminal 30c will be described later.

Further, the wiring layers 30b, 30e, 30f and the electrode 30d are made of, for example, copper (Cu).
In the semiconductor device 1, the number of substrate core materials 10a and 10c or electrode terminals 30c and the number of insulating layers 10b and 10h disposed between the layers are limited to the configuration shown in FIG. It is not something.

Similarly, the electrodes 10d, 10e, 30d and the wiring layers 10f, 10g, 30e, 30f are not limited to the configuration shown in FIG.
Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.

  Here, in order to increase the efficiency of manufacturing a semiconductor device, the substrate 10 having a large size is applied, and a manufacturing mode in which a plurality of semiconductor chips are accommodated in the large size substrate 10 is adopted. Is disclosed.

However, in FIG. 2 to FIG. 4, a process for forming one semiconductor device among a plurality of semiconductor devices formed using the large substrate is characteristically shown.
In FIG. 2 to FIG. 4, the broken lines extending to the left and right simulate the state where a large-sized substrate is applied.

First, a process in which the semiconductor chip 20 is housed and fixed in the recess 15 provided in the substrate 10 is shown in FIG.
When the substrate 10 is formed, a so-called multilayer wiring substrate forming technique is used to form a laminated structure of the first substrate core material 10a, the insulating layer 10b, and the second substrate core material 10c. .

Then, a conductive material such as copper (Cu) is filled in a hole provided through the multilayer structure by a so-called through-hole plating method, and electrodes 10d and 10e are formed.
Further, on the second substrate core material 10c, wiring layers 10f and 10g are arranged in conduction with the electrodes 10d and 10e.

After the wiring layers 10f and 10g are formed, the insulating layer 10h is formed as a cover.
The concave portion 15 in the substrate 10 made of the laminated structure is formed by arranging the insulating layer 10b provided with an opening in advance on the first substrate core material 10a, the laminated arrangement of the substrate core material 10c, or the substrate after lamination. It is formed by selectively removing the core material 10c and the insulating layer 10b.

  When housing and fixing the semiconductor chip 20 in the recess 15, as shown in FIG. 2A, a thermosetting adhesive member 21 is arranged in advance on the bottom of the recess 15, and a bonding tool is used. The semiconductor chip 20 held by (not shown) is lowered into the recess 15.

A bump electrode 20b having a concave cross section is formed on the upper surface of the semiconductor chip 20 by a manufacturing method described later.
On the other hand, the substrate 10 is held on a bonding stage (not shown) and heated as necessary.

At this stage, the adhesive member 21 is pasty.
The semiconductor chip 20 lowered into the recess 15 is pressed by the bonding tool and fixed onto the substrate core material 10a via the adhesive member 21.

FIG. 2B shows a state where the semiconductor chip 20 is fixed onto the substrate core material 10a via the adhesive member 21.
By applying a load by the bonding tool, the paste-like adhesive member 21 wraps around the semiconductor chip 20 between the semiconductor chip 20 and the substrate core material 10a and is thermally cured by heating.

As a result, the semiconductor chip 20 is fixed in the recess 15 in the substrate 10 via the adhesive member 21.
Next, the wiring substrate 30 is mounted on and fixed to the substrate 10 on which the semiconductor chip 20 is accommodated and fixed.

That is, as shown in FIG. 3A, the wiring substrate 30 held by the bonding tool (not shown) is lowered onto the substrate 10 in which the semiconductor chip 20 is accommodated and fixed.
At this time, the substrate 10 is held on a bonding stage (not shown) and preheated as necessary. On the other hand, the wiring board 30 is also preheated as necessary.

  As described above, in the wiring board 30, the wiring layer 30b is selectively disposed on one main surface (opposite surface to the semiconductor chip 20) of the wiring board core material 30a made of an insulator. A sharp electrode terminal 30c is selectively disposed on 30b.

The surface of the wiring board 30 around the sharp electrode terminal 30c is covered with an insulating layer 31 made of a thermoplastic resin.
On the other hand, a wiring layer 30e that conducts to the electrode 30d or a non-conducting wiring layer 30f is disposed on the other main surface (non-opposing surface to the semiconductor chip 20) of the wiring board core member 30a. An insulating layer 32 is disposed over the layers selectively.

The wiring board 30 is lowered and pressed against the board 10 by a bonding tool while heating. (Not shown)
Due to this pressing, among the sharp electrode terminals 30c provided on the wiring substrate 30, the electrode terminals 30c corresponding to the semiconductor chip 20 are received in the recesses of the bump electrodes 20b in the semiconductor chip 20. Thus, the electrode terminal 30c and the bump electrode 20b are mechanically connected in a fitted state.

On the other hand, the other electrode terminal 30c penetrates the insulating layer 10h and is connected to the wiring layers 10f and 10g on the second substrate core material 10c.
Such a state is shown in FIG.

  As described above, the insulating layer 31 made of a thermoplastic resin develops plasticity by applying a load and heating with a bonding tool, and flows between the semiconductor chip 20 and the insulating layer 10 h of the substrate 10 and the wiring substrate 30. To do. Then, the space between the semiconductor chip 20 and the insulating layer 10 h of the substrate 10 and the wiring substrate 30 is filled.

On the other hand, the insulating layer 10h made of an organic resin becomes low elastic by heating.
Note that the adhesive member 21 exhibits elasticity by heating, and the thickness of the adhesive member 21 located on the lower surface of the semiconductor chip 20 becomes thinner than the state shown in FIG.

  Then, when the insulating layer 31 becomes a predetermined temperature or lower and is hardened, the sharp electrode terminals 30c on the wiring board 30, the bump electrodes 20b disposed on the semiconductor chip 20, and the sharpness on the wiring board 30 are obtained. The electrode terminals 30c and the wiring layers 10f and 10g disposed on the substrate 10 are more firmly connected.

The insulating layer 31 is not limited to a thermoplastic resin, and a thermosetting resin may be used.
That is, a thermosetting resin layer is formed on the first main surface of the wiring board 30 so that the tip of the sharp electrode terminal 30c is exposed, and the wiring board 30, the semiconductor chip 20, and the substrate 10 are formed. Then, the thermosetting resin is cured by heating, and the sharp electrode terminal 30c, the wiring layers 10f and 10g, and the bump electrode 20b can be connected by pressure contact.

  In this way, after the wiring substrate 30 covering the substrate 10 containing the semiconductor chip 20 is disposed, the solder balls constituting the external connection electrode terminals 40 are arranged on the other main surface of the wiring substrate 30. Set up.

That is, as shown in FIG. 4, on the wiring layers 30e and 30f on the other main surface of the wiring substrate 30, the solder balls are formed by the reflow method, and the external connection electrode terminals 40 are disposed.
As described above, when a substrate having a large size is applied as the substrate 10 and a manufacturing configuration in which a plurality of semiconductor chips are accommodated in the large size substrate 10 is adopted, the external connection made of the solder balls is used. After the formation of the electrode terminals 40, the substrate 10 and the wiring substrate 30 are cut into individual pieces by dicing, and the semiconductor device 1 shown in FIG. 1 is formed.

  In such a manufacturing method of the semiconductor device 1, the wiring substrate 30 is connected to the substrate 10 and the semiconductor chip 20 in one step. Therefore, the semiconductor device 1 in which the thin semiconductor chip (WLP) is built can be manufactured with a simpler process.

  That is, a semiconductor device with a built-in WLP can be easily manufactured without going through the steps of forming a film in the wiring layer formation of the upper layer of WLP that has been made in the conventional EWLP manufacturing process or repeating the photolithography process. be able to.

  By using this crimping method, the sharp electrode terminal 30c on the wiring substrate 30 and the bump electrode 20b of the semiconductor chip 20 or the wiring layers 10f and 10g can be mechanically and effectively connected. . Therefore, the connection reliability between the electrode terminal 30c, the bump electrode 20b, and the wiring layers 10f and 10g can be improved as compared with the conventional ELWP.

  At this time, since the sharp electrode terminal 30c in the wiring substrate 30 is received and connected to the concave portion of the bump electrode 20b in the semiconductor chip 20, it has higher connection reliability.

Further, since one main surface of the semiconductor chip 20, the substrate 10, and the wiring substrate 30 is covered with the resin 31e, the semiconductor chip 20 to be thinned can be protected.
As described above, the semiconductor device 1 can incorporate the thinned semiconductor chip 20, and can be thinned.

  In addition, since the sharp electrode terminal 30c, the bump electrode 20b having a concave cross-sectional shape, and the wiring layer 10g are directly pressed and connected, the narrow gap between the bump electrodes 20b having a concave cross-sectional shape is formed. Pitching can be easily achieved. Further, a metal paste such as a solder paste or a conductive paste is applied as a member for making these electrical connections. Therefore, these paste materials exhibit a buffering effect, absorb an impact on the semiconductor chip 20, and reduce damage to the semiconductor chip 20.

  Further, since the concave bump electrode 20b is formed on the semiconductor chip 20 before the semiconductor chip 20 is accommodated and mounted on the substrate 10, the semiconductor chip 20 is tested (for example, electrical characteristic inspection or the like). Can be easily performed through the bump electrode 20b. As a result, inspection efficiency is improved.

  Thus, in the semiconductor device 1, the productivity as a semiconductor device is further improved, and the cost can be reduced. Furthermore, the reliability and inspection efficiency as a semiconductor device are further improved.

  When the semiconductor device 1 having such a configuration is manufactured by the manufacturing method as described above, the bump electrode 20b having a concave cross-sectional shape disposed in advance on the semiconductor chip 20 is shown in FIGS. It can be formed by various methods shown and used.

Here, the parts shown in FIG. 1 are denoted by the same reference numerals, and the electrode pad 20a portion disposed on the main surface of the semiconductor substrate is shown enlarged.
As described above, prior to the placement of the bump electrode 20b having a concave cross-sectional shape on the semiconductor substrate, an active element such as a transistor, a passive element such as a capacitive element, An electronic circuit region having a wiring layer for connecting these elements is formed.

And the electrode pad 20a connected to the said wiring layer is arrange | positioned on the main surface of the semiconductor substrate in which the said electronic circuit area | region is formed.
The surface of the semiconductor substrate including the edge of the electrode pad 20a is covered with a passivation layer 20c made of an organic insulating film.

<Method 1 of Forming Bump Electrode 20b>
A method 1 of forming the bump electrode 20b having a concave cross-sectional shape will be described with reference to FIG.

In the first forming method, a printing mask 50 is provided on the semiconductor substrate 22 (see FIG. 5A).
The printing mask 50 does not open the entire upper surface area of one electrode pad 20a, and a mask pattern 50a is disposed above the center of the electrode pad 20a.

That is, the printing mask 50 masks the central portion of the electrode pad 20a and the main surface of the semiconductor substrate 22 other than the electrode pad 20a region.
Accordingly, the electrode pad 20a is masked by exposing a plane in the vicinity of the peripheral edge thereof.

A metal paste 23 is deposited on the electrode pad 20a by a printing method using the printing mask 50.
As the metal paste 23, a solder paste composed of eutectic solder or lead-free solder, or a conductive paste composed of gold (Au), silver (Ag), copper (Cu), or an alloy paste thereof. Can be used.

  By depositing the metal paste 23 by the printing method using the printing mask 50, the deposition site and deposition amount are limited on the electrode pad 20a due to the presence of the mask 50a. 23 is deposited.

  That is, the mask 50a prevents or restricts the deposition of the metal paste 23 on the central portion of the electrode pad 20a, and the metal paste 23 passes through the opening around the mask 50a in the central portion of the electrode pad 20a. Is deposited.

Therefore, the metal paste 23 is deposited on the electrode pad 20a with a distribution with a small deposition amount at the center, that is, the cross-sectional shape is concave (see FIG. 5B).
The deposited metal paste 23 is heated (cured) for a predetermined time at a temperature of 50 to 300 ° C., for example.

As a result, a metal bump electrode 20b is formed on the electrode pad 20a with a distribution shape with a small deposition amount at the center, that is, a cross-sectional shape having a concave shape (see FIG. 5C). ).
As described above, the bump electrode 20b having a concave cross-sectional shape can be formed by using the following forming method.

<Method of forming bump electrode 2>
A method 2 for forming a bump electrode having a concave cross section will be described with reference to FIGS.

In the second forming method, the base metal layer 51 and the resist layer 52 are laminated on the semiconductor substrate 22 including the electrode pad 20a.
The base metal layer 51 is, for example, titanium (Ti) and is deposited by a sputtering method.

  Further, the resist layer 52 disposed on the base metal layer 51 is selectively disposed so as to expose the base metal layer 51 formed on the electrode pad 20a (FIG. 6A). reference).

Note that a plating (plating) seed layer may be further formed on the base metal layer 51 as necessary.
Next, a thick metal layer 24 is deposited on the underlying metal layer 51 using the resist layer 52 as a mask. That is, the metal layer 24 is formed on the electrode pad 20a by electroplating (plating) using the base metal layer 51 as a current-carrying electrode and the resist layer 52 as a mask (see FIG. 6B).

As the metal constituting the metal layer 24, gold (Au), silver (Ag), copper (Cu), or an alloy thereof is applied.
In this electroplating process, the density of the metal layer 24 to be deposited is made sparse by setting the current density to a high density or adjusting the components of the plating solution, and bubbles 24a are formed inside. Shall be included.

  In this manner, the metal layer 24 having a sparse density and containing bubbles 24a is formed on the electrode pad 20a so as to protrude beyond the thickness of the resist layer 52 (FIG. C)).

Next, the exposed portions of the resist layer 52 and the base metal layer 51 are removed (see FIG. 7A).
The resist layer 52 is removed by, for example, an ashing process, and the exposed base metal layer 51 is removed by etching.

Thereafter, as described above, the metal layer 24 whose density is sparse and contains the bubbles (voids) 24a is subjected to remelting (reflow) treatment.
By performing the remelting process at a predetermined reflow temperature and a predetermined time, the bubbles (voids) 24a included in the metal layer 24 move upward in the center of the metal layer 24 (FIG. 7B )reference).

And the bubble (void) 24a which moved to the center part upper part of the said metal layer 24 is discharge | released outside the metal layer 24 in a molten state.
Due to the discharge of the bubbles 24a, the metal layer 24 located at the central portion of the electrode pad 20a is depressed to form a so-called crater shape (see FIG. 7C).

As a result, after the remelting (reflow) process, the bump electrode 20b having a concave cross-sectional shape is formed on the electrode pad 20a.
The bump electrode 20b having a concave cross-sectional shape can also be formed using the following forming method.

<Method 3 of Forming Bump Electrode 20b>
A method 3 of forming a bump electrode having a concave cross section will be described with reference to FIG.
In the formation method 3, the base metal layer 51 and the resist layer 52 are laminated on the semiconductor substrate 22 including the electrode pad 20 a.

The base metal layer 51 is, for example, titanium (Ti) and is deposited by a sputtering method.
Further, the resist layer 52 disposed on the base metal layer 51 is disposed so as to selectively expose the base metal layer 51 formed on the electrode pad 20a (see FIG. 8A). ).

That is, the resist layer 52a is selectively disposed at a substantially central portion of the electrode pad 20a.
A seed layer for the plating layer may be further formed on the base metal layer 51 as necessary.

  Next, a thick metal layer 24 is deposited on the underlying metal layer 51 using the resist layer 52 as a mask. That is, the metal layer 24 is selectively formed on the electrode pad 20a by an electroplating (plating) method using the base metal layer 51 as a current-carrying electrode and the resist layer 52 as a mask.

As the metal constituting the metal layer 24, solder, gold (Au), silver (Ag), copper (Cu), or an alloy thereof is applied.
At the time of the electroplating (plating), the metal layer 24 is exposed around the resist layer 52a because the resist layer 52a is disposed at a substantially central portion of the electrode pad 20a. Deposited on the underlying metal layer 51.

The thickly deposited metal layer 24 is continuously integrated on the resist layer 52a (see FIG. 8B).
Next, the resist 52 and the base metal layer 51 around the deposited metal layer 24 are removed.

The resist layer 52 is removed by, for example, an ashing process, and the exposed base metal layer 51 is removed by etching.
As a result, on the electrode pad 20a, a metal bump electrode 20b having a distribution with a small amount of deposition in the central portion thereof, that is, having a concave cross section is formed (see FIG. 8C). .

Thus, the bump electrode 20b having a concave cross-sectional shape can also be formed by using the following forming method.
<Method 4 for Forming Bump Electrode 20b>
A method 4 of forming a bump electrode having a concave cross section will be described with reference to FIG.

  In this method, a mold 60 in which a plurality of cavities 60a corresponding to the outer shape of the bump electrode 20b are provided on one main surface is prepared in advance, and the metal paste 26a is disposed in the cavity 60a of the mold 60. (See FIG. 9A).

That is, a convex portion is provided at the center of each cavity 60a, and the introduction form of the metal paste is limited by the presence of the convex portion.
Further, the interval between the plurality of cavities 60a in the mold 60 is set corresponding to the interval between the electrode pads 20a disposed on the semiconductor substrate 22.

Then, the metal paste 26 is supplied into the cavity 60a by a printing method or the like.
The metal paste 26 is composed of a solder paste such as eutectic solder or lead-free solder paste. Instead, a conductive paste such as gold (Au), silver (Ag), copper (Cu), or an alloy paste thereof can be applied.

Next, the metal paste 26 received in the cavity 60a is cured (cured) to form a metal layer 26b.
When the solder paste is used, the curing temperature is set below the melting temperature of the solder. Moreover, when using an electrically conductive paste, it sets to 50-300 degreeC, for example.

Further, the heating time is adjusted as necessary.
Next, the metal layer 26 b held by the mold 60 is brought into contact with the electrode pad 20 a on the semiconductor substrate 22.

  That is, the semiconductor substrate 22 and the mold 60 are aligned, and the metal layer 26b is brought into contact with the electrode pad 20a of the semiconductor substrate 22 through the conductive paste 27 (see FIG. 9B).

The metal paste 27a is the same material (component) as the metal paste 26a.
Next, heat treatment is performed again, the metal paste 27a is cured (cured), and the metal layer 26b in the cavity 60a and the electrode pad 20a are fixed.

  Here, the curing condition of the metal paste 27a is set to be equal to or lower than the melting temperature of the solder when the solder paste is used. Moreover, when using an electrically conductive paste, it sets to 50-300 degreeC.

Further, if necessary, the heating time is adjusted and cured.
Thereafter, the mold 60 is separated from the semiconductor substrate 22 to expose the bump electrode 20b having a concave cross-sectional shape. The concave portion is formed corresponding to the convex portion in the cavity 60 a in the mold 60.

As a result, the bump electrode 20b having a concave cross section is disposed on the electrode pad 20a via the metal layer 27b (see FIG. 9C).
On the other hand, the sharp electrode terminal 30c disposed on the wiring board 30 can be formed by the following manufacturing method.

In this case as well, the same reference numerals are given to the portions described in FIG.
<Method for Forming Electrode Terminal 30c>
A method for forming the sharp electrode terminal 30c will be described with reference to FIG.

First, the printing mask 70 is positioned on the substrate core material 30a constituting the wiring substrate 30 (see FIG. 10A).
The printing mask 70 is provided with through-holes 70a corresponding to the electrode terminal setting positions in the wiring layer 30b selectively disposed on the surface of the substrate core material 30a.

  The through-hole 70a has a relatively large area corresponding to the surface area of the wiring layer on the surface side (one main surface) of the wiring layer 30b, and is on the side far from the wiring layer 30b ( The other main surface) has a small area, and its cross-sectional shape has a so-called taper shape.

The printing mask 70 is disposed in close contact with the substrate core material 30a, and a metal paste is filled into the through hole 70a through the opening having the small area.
As the conductive paste, a paste containing gold (Au), silver (Ag), copper (Cu), or an alloy thereof is applied.

After the metal paste is filled, the printing mask 70 is removed.
Next, the metal paste on the substrate core material 30a is heated and dried to solidify the metal paste to form electrode terminals 30c. The heat treatment temperature is set to, for example, 50 to 300 ° C.

  The electrode terminal 30c formed by solidifying the metal paste is formed with an inclined side surface corresponding to the shape of the through-hole 70a formed in the printing mask 70, and the shape is formed from the surface of the wiring layer 30b. It has a conical or pyramidal sharpened shape so as to protrude substantially vertically (see FIG. 10B).

By such a process, the sharp electrode terminal 30c is selectively disposed on the wiring layer 30b of the substrate core material 30a.
(Appendix 1) A semiconductor element comprising an electrode having a concave cross-sectional shape;
A first wiring board provided on the semiconductor element, wherein a sharp electrode terminal is provided corresponding to an electrode having a concave cross-sectional shape of the semiconductor element;
Comprising
A semiconductor device, wherein a sharp electrode terminal of the first wiring board is received in the concave portion of an electrode having a concave cross-sectional shape of the semiconductor element.

(Additional remark 2) The said semiconductor element is accommodated in this recessed part of the 2nd wiring board which has a recessed part, The semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the semiconductor element is a wafer level package (WLP), and at least one concave electrode is disposed on a main surface of the semiconductor element.

  (Supplementary Note 4) The second wiring board includes at least one substrate core material, at least one insulating layer formed on the substrate core material, and at least one electrode penetrating the substrate core material and the insulating layer. The semiconductor device according to claim 2, further comprising: at least one wiring layer disposed on the substrate core material that is electrically connected to the electrode.

  (Supplementary Note 5) The first wiring board includes at least one substrate core material, at least one insulating layer formed on a main surface of the substrate core material, and at least one penetrating the substrate core material and the insulating layer. Two electrodes, at least one wiring layer disposed on the substrate core material conducting to the electrodes, and at least one sharp electrode terminal formed on the wiring layer. The semiconductor device according to appendix 1, which is characterized.

(Appendix 6) A step of forming an electrode having a concave cross-sectional shape on an electrode pad of a semiconductor element;
A step of disposing a wiring board on which the sharp electrode terminals corresponding to the electrodes of the semiconductor element are disposed on the semiconductor element;
A step of press-fitting a sharp electrode terminal in the wiring board into the concave portion of the electrode having a concave cross-sectional shape in the semiconductor element;
A method for manufacturing a semiconductor device, comprising:

(Appendix 7) Before the step of disposing the wiring board on the semiconductor element,
Disposing the semiconductor element in the concave portion of the second wiring board having the concave portion;
The method for manufacturing a semiconductor device according to appendix 6, wherein:

(Appendix 8) The electrode having a concave cross-sectional shape,
Disposing a printing mask having an opening at a position of the pad portion excluding a part of the center of the electrode pad on a semiconductor substrate on which a plurality of electrode pads are formed;
Printing a metal paste on the electrode pad through the printing mask;
Drying the printed metal paste;
The method for manufacturing a semiconductor device according to appendix 6, wherein:

(Supplementary note 9) The electrode having a concave cross-sectional shape,
Forming a metal layer having voids therein on a plurality of electrode pads;
Reflowing the metal layer in which the voids are present;
The method for manufacturing a semiconductor device according to appendix 6, wherein:

(Supplementary Note 10) The electrode having a concave cross-sectional shape,
A step of selectively disposing a resist on the main surface of the semiconductor substrate other than the center portion of the plurality of electrode pads and the electrode pad region;
Forming a metal layer on the portion where the electrode pad is exposed from the resist;
The method for manufacturing a semiconductor device according to appendix 6, wherein:

(Additional remark 11) In formation of the electrode in which the said cross-sectional shape has concave shape,
Supplying a first metal paste to a mold provided with a cavity corresponding to the shape of the concave electrode;
Curing the first metal paste in the cavity;
Bringing the cured first metal paste into contact with the electrode pad via a second metal paste, and curing the second metal paste;
7. The method of manufacturing a semiconductor device according to appendix 6, wherein the concave electrode is formed on the electrode pad by separating the mold from the cured first metal paste.

(Supplementary Note 12) Before arranging the wiring board, the electrode terminals are arranged on the wiring board, and in the arrangement of the electrode terminals,
Printing a metal paste on the wiring layer with a mask for printing that masks the main surface of the wiring board other than a part of the wiring layer disposed on the wiring board;
Drying the printed metal paste;
The method for manufacturing a semiconductor device according to appendix 6, wherein:

  (Additional remark 13) The manufacturing method of the semiconductor device of Additional remark 6 characterized by the through-hole of a reverse taper or a forward taper being provided in the said mask for printing.

It is a principal part cross-sectional schematic diagram which shows the structure of the semiconductor device by this invention. FIG. 3 is a schematic cross-sectional view (No. 1) of relevant parts showing a method for manufacturing a semiconductor device according to the present invention. FIG. 6 is a schematic cross-sectional view (No. 2) of relevant parts showing a method for manufacturing a semiconductor device according to the present invention. FIG. 6 is a schematic cross-sectional view (No. 3) of relevant parts showing the method for manufacturing a semiconductor device according to the present invention. It is a principal part cross-sectional schematic diagram which shows the formation method 1 of a bump electrode. FIG. 6 is a schematic cross-sectional view of a relevant part showing a bump electrode forming method (Part 1); FIG. 9 is a schematic cross-sectional view of a main part showing a bump electrode forming method (Part 2); It is a principal part cross-sectional schematic diagram which shows the formation method 3 of a bump electrode. It is a principal part cross-sectional schematic diagram which shows the formation method 4 of a bump electrode. It is a principal part cross-sectional schematic diagram which shows the formation method of an electrode terminal. It is a principal part cross-sectional schematic diagram which shows the structure of the conventional EWLP. It is a principal part cross-sectional schematic diagram (the 1) which shows the manufacturing method of the conventional EWLP. It is a principal part cross-sectional schematic diagram (the 2) which shows the manufacturing method of the conventional EWLP.

Explanation of symbols

1,100 Semiconductor device 10 Substrate 10a, 10c, 101, 103 Substrate core material 10b, 10h, 31, 32 Insulating layer 10d, 10e, 30d, 105, 106 Electrode 10f, 10g, 30b, 30e, 30f Wiring layer 15, 104A Recess 20, 200 Semiconductor chip 20a, 201 Electrode pad 20b Bump electrode 20c Organic insulating film 21 Adhesive member 22 Semiconductor substrate 23, 26a, 27a Metal paste 24, 25, 26b, 27b Metal layer 24a Void 30 Wiring substrate 30c Electrode terminal 40, 122 Electrode terminal 50, 70 Mask for printing 51 Base metal layer 52 Resist 60 Type 60a Cavity 70a Through hole

Claims (4)

A semiconductor element comprising an electrode having a concave cross-sectional shape;
A first wiring board provided on the semiconductor element, wherein a sharp electrode terminal is provided corresponding to an electrode having a concave cross-sectional shape of the semiconductor element and an electrode of the second wiring board. When,
A resin layer formed between the semiconductor element and the first wiring board;
Comprising
The semiconductor element is accommodated in the recess of the second wiring board having a recess,
The sharp electrode terminal of the first wiring board is received in the concave portion of the electrode having a concave cross-sectional shape of the semiconductor element and the electrode of the second wiring board,
The semiconductor device, wherein the resin layer surrounds an electrode having a concave cross-sectional shape of the semiconductor element and a sharp electrode terminal of the first wiring board. Forming an electrode having a concave cross-sectional shape on an electrode pad of a semiconductor element;
Disposing the semiconductor element in the recess of the second wiring substrate having the recess;
Sharp electrode terminals corresponding to the electrodes of the semiconductor element and the electrodes of the second wiring board are arranged on the semiconductor element arranged in the recess of the second wiring board. Placing a first wiring board;
A step of press-fitting a sharp electrode terminal in the first wiring board into the concave part of the electrode having a concave cross-sectional shape in the semiconductor element and the electrode of the second wiring board ;
Forming a resin layer between the semiconductor element and the first wiring board to surround an electrode having a concave cross-sectional shape of the semiconductor element and the sharp electrode terminal of the first wiring board; ,
A method for manufacturing a semiconductor device, comprising: The electrode having a concave cross-sectional shape,
Disposing a printing mask having an opening at a position excluding a part of the center of the electrode pad on a semiconductor substrate on which a plurality of electrode pads are formed;
Printing a metal paste on the electrode pad through the printing mask;
Drying the printed metal paste;
The method of manufacturing a semiconductor device according to claim 2, wherein Forming an electrode having a concave cross-sectional shape on an electrode pad of a semiconductor element;
A step of disposing a wiring board on which the sharp electrode terminals corresponding to the electrodes of the semiconductor element are disposed on the semiconductor element;
Pressing a sharp electrode terminal in the wiring board into the concave portion of the electrode having a concave cross-sectional shape in the semiconductor element, and
The electrode having a concave cross-sectional shape,
Disposing a printing mask having an opening at a position excluding a part of the center of the electrode pad on a semiconductor substrate on which a plurality of electrode pads are formed;
Printing a metal paste on the electrode pad through the printing mask;
Drying the printed metal paste;
A method for manufacturing a semiconductor device, comprising:

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