JP2020004926A - Wiring board and manufacturing method thereof - Google Patents
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Abstract
Description
本発明は、配線基板及び配線基板の製造方法に関する。 The present invention relates to a wiring board and a method for manufacturing the wiring board.
近年、携帯電話や通信端末に代表される電子機器の高機能化、高性能化はめざましく、これら電子機器には、半導体チップが配線基板に実装された半導体パッケージが広く使用されている。半導体チップを配線基板に実装する形態として、従来から用いられてきたリードフレームやピン、ワイヤを用いたものから、最近では半導体チップを直接配線基板に表面実装するフリップチップ（Ｆｌｉｐ Ｃｈｉｐ−Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ、ＦＣ−ＢＧＡ）方式のパッケージの採用が進んでいる。 2. Description of the Related Art In recent years, electronic devices typified by mobile phones and communication terminals have been significantly improved in function and performance, and semiconductor packages in which semiconductor chips are mounted on wiring boards are widely used for these electronic devices. As a form of mounting a semiconductor chip on a wiring board, a flip chip (Flip Chip-Ball Grid Array) that directly mounts a semiconductor chip on a surface of a wiring board, instead of a conventional one using a lead frame, pins, and wires, has been used. , FC-BGA) type packages are being adopted.
一般のＦＣ−ＢＧＡ配線基板は、図６にその概略を示すように、配線層５１を多層化したビルドアップ配線構造となっている。ＦＣ−ＢＧＡ配線基板５０は、厚めのコア層５７の表裏にコア層５７よりは薄い配線層５１（絶縁樹脂５３／配線パターン５２）を複数積み重ね、上下の配線パターン５２間を導通ビア５６で接続し、アレイ配置された半導体チップ側の第一の端子電極５４と、マザーボード側の第二の端子電極間５５との導通をとったものである。 A general FC-BGA wiring board has a build-up wiring structure in which wiring layers 51 are multilayered, as schematically shown in FIG. In the FC-BGA wiring board 50, a plurality of wiring layers 51 (insulating resin 53 / wiring pattern 52) thinner than the core layer 57 are stacked on the front and back of the thicker core layer 57, and the upper and lower wiring patterns 52 are connected by the conductive vias 56. Then, conduction is established between the first terminal electrodes 54 on the semiconductor chip side arranged in the array and the second terminal electrodes 55 on the motherboard side.
近年の半導体チップの高集積化に伴いＦＣ−ＢＧＡ配線基板も半導体チップを実装する端子電極の狭ピッチ化、配線パターンの微細化が求められている。このため、シリコン上に配線を形成してチップ実装用の基板（シリコンインターポーザ）とし、ＦＣ−ＢＧＡ配線基板に実装する方式が特許文献１に開示されている。 With the recent increase in the degree of integration of semiconductor chips, the pitch of terminal electrodes for mounting semiconductor chips on FC-BGA wiring boards has been required to be narrower and wiring patterns have to be finer. For this reason, Patent Literature 1 discloses a method in which wiring is formed on silicon to be used as a chip mounting substrate (silicon interposer) and mounted on an FC-BGA wiring substrate.
一方で、ＣＰＵ、ＧＰＵ、メモリといった複数の半導体チップを同じ配線基板上に実装する製品が開発され、こうした製品には従来よりも大面積の配線基板が求められている。大面積の配線基板を製造するために、特許文献１のシリコンインターポーザ方式のように半導体チップ製造プロセスを採用すると、配線基板製品形状は四角であるので、円形状であるシリコンウエハに面付けすることは効率が悪くコストが嵩む。また配線基板に複数の半導体チップを実装するためには、実装工程時の熱処理による反り挙動を抑えることが課題となる。 On the other hand, products have been developed in which a plurality of semiconductor chips, such as CPUs, GPUs, and memories, are mounted on the same wiring board, and such products require a wiring board having a larger area than before. If a semiconductor chip manufacturing process is adopted as in the case of the silicon interposer method of Patent Document 1 in order to manufacture a large-area wiring board, the wiring board product shape is a square, so that it is imposed on a circular silicon wafer. Is inefficient and costly. In addition, in order to mount a plurality of semiconductor chips on a wiring board, it is necessary to suppress a warping behavior due to a heat treatment in a mounting process.
反り抑制の課題として特許文献２には、ＦＣ−ＢＧＡ配線基板のコア層、及びその両面の絶縁樹脂として、補強材入りの絶縁樹脂を積層して配線基板の剛性を高め、かつ狭ピッチの端子電極が必要な半導体チップを実装する側（インターポーザ側）のビルドアップ配線層にのみ特に微細な配線（微細配線）を有する配線層を複数層形成する技術が提案されている。 As a problem of warpage suppression, Patent Literature 2 discloses that a rigid layer containing a reinforcing material is laminated as a core layer of an FC-BGA wiring board and insulating resins on both surfaces thereof to increase the rigidity of the wiring board and to provide terminals having a narrow pitch. There has been proposed a technique of forming a plurality of wiring layers having particularly fine wiring (fine wiring) only on a build-up wiring layer on a side (interposer side) on which a semiconductor chip requiring electrodes is mounted.
しかしながら、特許文献２の構造には以下のような問題点がある。すなわち、インターポーザ側に複数層の絶縁樹脂層を形成するため、絶縁樹脂の硬化収縮により製造プロセス中に基板が反る。また、コア層の両面のビルドアップ配線層に用いられる補強材入り絶縁樹脂はビア穴の加工が困難であるため、ビアの狭ピッチ化が妨げられる。 However, the structure of Patent Document 2 has the following problems. That is, since a plurality of insulating resin layers are formed on the interposer side, the substrate warps during the manufacturing process due to the curing shrinkage of the insulating resin. In addition, it is difficult to process the via holes in the insulating resin containing the reinforcing material used for the build-up wiring layers on both sides of the core layer, so that the narrow pitch of the vias is prevented.
本発明は上記の事情に鑑みてなされたものであって、配線基板の製造プロセス中の反りを抑制し、狭ピッチの端子電極と微細配線を備える、大型で低コストな配線基板と、その製造方法を提供することを目的とする。 The present invention has been made in view of the above circumstances, and suppresses warpage during a manufacturing process of a wiring board, and includes a large-size, low-cost wiring board including terminal electrodes and fine wirings with a narrow pitch, and a manufacturing method thereof. The aim is to provide a method.
上記の課題を解決するために、本発明の配線基板は以下の特徴を備える。 In order to solve the above problems, a wiring board according to the present invention has the following features.
本発明の一態様に係る配線基板は、ビルドアップ配線層からなる第二配線基板と、第二配線基板に接合された第一配線基板と、を備え、第二配線基板と第一配線基板とはそれぞれ表面から突出した端子（突起電極）を介して電気的に接合され、第一配線基板及び第二配線基板の隙間に絶縁樹脂が充填され、第一配線基板は、順に第一最外層、配線層、第二最外層から成り、第一最外層、第二最外層の少なくとも一方に補強材を含む、ことを特徴とする。 The wiring board according to one embodiment of the present invention includes a second wiring board made of a build-up wiring layer, and a first wiring board joined to the second wiring board, and the second wiring board and the first wiring board. Are electrically connected via terminals (protruding electrodes) protruding from the respective surfaces, a gap between the first wiring board and the second wiring board is filled with an insulating resin, and the first wiring board is sequentially provided with a first outermost layer, It comprises a wiring layer and a second outermost layer, and at least one of the first outermost layer and the second outermost layer contains a reinforcing material.
本発明の別の態様に係る配線基板の製造方法は、前記本発明の一態様に係る配線基板の製造方法であって、四角形状の支持基板上に、順に剥離層、及び第一配線基板を形成し、第一配線基板を第二配線基板に接合した後、支持基板を剥離する、ことを特徴とする。 A method for manufacturing a wiring board according to another aspect of the present invention is the method for manufacturing a wiring board according to one aspect of the present invention, wherein a release layer and a first wiring board are sequentially formed on a rectangular support substrate. After forming and bonding the first wiring board to the second wiring board, the support substrate is peeled off.
また、本発明の別の態様に係る配線基板の製造方法は、支持基板の厚みが第一配線基板の厚みの１０倍以上であり、かつ０．１ｍｍ〜２．０ｍｍであることが好ましい。 Further, in the method for manufacturing a wiring board according to another aspect of the present invention, it is preferable that the thickness of the supporting substrate is at least 10 times the thickness of the first wiring board and is 0.1 mm to 2.0 mm.
さらに、本発明の別の態様に係る配線基板の製造方法は、支持基板の材質はガラスであり、支持基板を通して剥離層にレーザーを照射することにより、第一配線基板から支持基板を剥離する工程を含むことが好ましい。 Further, in the method of manufacturing a wiring board according to another aspect of the present invention, the step of peeling the support substrate from the first wiring substrate by irradiating a laser to the release layer through the support substrate, wherein the material of the support substrate is glass It is preferable to include
本発明の配線基板及び配線基板の製造方法によれば、配線基板の製造プロセス中の反りが抑制され、近年必要とされる狭ピッチの端子電極と微細配線を備える、大型で低コストな配線基板と、その製造方法が得られる。すなわち、充分な厚みの支持基板と、剛性の高い配線基板となり、製造プロセスに適合した水準の反り量で製造することができる。また、四角形状の支持基板を採用することにより面付け効率が高くなりコストが抑えられる。さらに別の観点では、良品と選別された第二配線基板に個片化した良品の第一配線基板を接合することにより、収率の低下を防止することができる。 ADVANTAGE OF THE INVENTION According to the wiring board and the manufacturing method of the wiring board of this invention, the warpage during the manufacturing process of a wiring board is suppressed, and the large-sized and low-cost wiring board provided with the narrow pitch terminal electrode and fine wiring required in recent years And a manufacturing method thereof. That is, the supporting substrate has a sufficient thickness and the wiring substrate has high rigidity, and can be manufactured with a warpage of a level suitable for the manufacturing process. In addition, the adoption of the rectangular support substrate increases the imposition efficiency and suppresses the cost. From another viewpoint, the yield can be prevented from lowering by joining the singulated non-defective first wiring board to the non-defective second wiring board.
以下、本発明の好適な一実施形態について、添付図面を参照しつつ説明する。但し、以
下に説明する各図においてそれぞれ同じものについては同一符号を付す。また各図面は発明の効果を理解しやすくするため適宜省略及び誇張してある。さらに本実施形態は本発明の技術的思想を説明するために例示するものであり、各部の材料、形状、配置、寸法等のパラメータを下記のものに限定するものではない。各パラメータは請求項の規定の範囲内で変更できる。
Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. However, in each of the drawings described below, the same components are denoted by the same reference numerals. Each drawing is omitted or exaggerated as appropriate in order to facilitate understanding of the effects of the invention. Furthermore, this embodiment is an example for explaining the technical idea of the present invention, and does not limit parameters such as materials, shapes, arrangements, dimensions, and the like of the respective parts to the following. Each parameter can be changed within the scope of the claims.
［本発明の配線基板］
図１（ａ）は、本発明の一実施形態に係り、第二配線基板２０に第一配線基板１０が接合された配線基板１００の模式断面図である。配線基板１００は、ビルドアップ配線層からなる第二配線基板２０と、第二配線基板２０に接合された第一配線基板１０と、を備え、第二配線基板２０と第一配線基板１０とはそれぞれ表面から突出した端子（突起電極、本例ではんだバンプ６）を介して電気的に接合され、かつ、第一配線基板１０及び第二配線基板２０の隙間に絶縁樹脂（絶縁性の接着部材、具体的にはアンダーフィル９）が充填されている。第一配線基板１０の上面（第二配線基板２０とは逆側の面）には半導体チップ（不図示）を実装するための接続パッド７が形成されている。突起電極は、はんだバンプ以外に、Ｃｕポスト（Ｃｕピラー）、または金バンプ等であってもよい。
[Wiring board of the present invention]
FIG. 1A is a schematic cross-sectional view of a wiring board 100 in which a first wiring board 10 is joined to a second wiring board 20 according to an embodiment of the present invention. The wiring board 100 includes a second wiring board 20 made of a build-up wiring layer, and a first wiring board 10 joined to the second wiring board 20. The second wiring board 20 and the first wiring board 10 Each is electrically connected via terminals (protruding electrodes, solder bumps 6 in this example) projecting from the surface, and is provided with an insulating resin (insulating adhesive member) in a gap between the first wiring board 10 and the second wiring board 20. Specifically, an underfill 9) is filled. Connection pads 7 for mounting a semiconductor chip (not shown) are formed on the upper surface of the first wiring substrate 10 (the surface opposite to the second wiring substrate 20). The bump electrode may be a Cu post (Cu pillar), a gold bump, or the like other than the solder bump.
図１（ｂ）は、本発明の一実施形態に係る、第一配線基板１０のみを、より詳しく示す模式断面図である。第一配線基板１０は、配線基板１００のインターポーザに相当する部分であり、順に第一最外層３、配線層４、第二最外層５から成り、第一最外層３、第二最外層５の少なくとも一方に補強材を含んでいる。配線層４は、必要な層数（図では３層）からなる配線層であり、絶縁樹脂４ａと配線パターン８ａ、８ｂ、・・・により構成されている。第一最外層３には前記の接続パッド７が形成され、第二最外層５には、第二配線基板２０とはんだバンプ６を介して接合するためのパッド表面処理層７ａが形成されている。 FIG. 1B is a schematic cross-sectional view showing only the first wiring substrate 10 according to one embodiment of the present invention in more detail. The first wiring board 10 is a portion corresponding to an interposer of the wiring board 100, and is composed of a first outermost layer 3, a wiring layer 4, and a second outermost layer 5 in that order. At least one includes a reinforcing material. The wiring layer 4 is a wiring layer having a required number of layers (three layers in the figure), and includes an insulating resin 4a and wiring patterns 8a, 8b,... The connection pads 7 are formed on the first outermost layer 3, and the pad surface treatment layer 7 a for bonding to the second wiring board 20 via the solder bumps 6 is formed on the second outermost layer 5. .
本発明の配線基板１００は、従来通りの配線ルール・材料を用いたＦＣ−ＢＧＡ配線基板である第二配線基板２０に加えて、第一配線基板１０を備え、第一配線基板１０は第一最外層３、配線層４、第二最外層５から成るので、第一配線基板１０の第一最外層３に形成される接続パッド７のピッチを、従来のように配線基板に半導体チップを直接実装する場合の配線ピッチよりも狭くすることができる。それとともに、第一配線基板１０の配線層４では、半導体チップを直接実装する従来の配線基板よりも微細な配線を使用することができる。すなわち、第一配線基板１０の第一最外層３に狭ピッチの端子電極を形成し、配線層４に微細な配線パターンを形成することで、端子電極の狭ピッチ化と微細配線化に対応することができる。 The wiring board 100 of the present invention includes a first wiring board 10 in addition to a second wiring board 20 which is an FC-BGA wiring board using a conventional wiring rule and material. Since it is composed of the outermost layer 3, the wiring layer 4, and the second outermost layer 5, the pitch of the connection pads 7 formed on the first outermost layer 3 of the first wiring board 10 is reduced by directly connecting the semiconductor chip to the wiring board as in the conventional case. It can be narrower than the wiring pitch when mounting. At the same time, the wiring layer 4 of the first wiring board 10 can use finer wiring than a conventional wiring board on which a semiconductor chip is directly mounted. That is, by forming a terminal electrode having a narrow pitch on the first outermost layer 3 of the first wiring substrate 10 and forming a fine wiring pattern on the wiring layer 4, it is possible to cope with a narrow pitch of the terminal electrodes and fine wiring. be able to.
また、第一最外層３、第二最外層５の少なくとも一方に補強材を含むので、従来のＦＣ−ＢＧＡ配線基板よりも剛性の高い配線基板となり、製造プロセス中の反りが抑えられる。 Further, since the reinforcing material is contained in at least one of the first outermost layer 3 and the second outermost layer 5, the wiring board has higher rigidity than the conventional FC-BGA wiring board, and the warpage during the manufacturing process is suppressed.
［本発明の配線基板の製造方法］
図２は、本発明の一実施形態に係る、配線基板の製造方法のうち、第一配線基板の製造工程までの主要部を工程順に示す模式断面図である。尚、図２は、図１、図３、図４の第二配線基板と接合前後の図とは上下反転している。
[Method of Manufacturing Wiring Board of the Present Invention]
FIG. 2 is a schematic cross-sectional view showing, in the order of steps, a main part of a method of manufacturing a wiring board according to an embodiment of the present invention, up to the manufacturing process of the first wiring board. Note that FIG. 2 is upside down from the view before and after bonding with the second wiring board in FIGS. 1, 3, and 4.
まず、図２（ａ）に示すように、支持体１の上に剥離層２を形成する。支持基板１には、ガラス基板を用いることができる。ガラス基板は表面が平坦であり、狭ピッチな端子電極や微細配線を形成するために好適である。また、ガラス基板はＣＴＥ（熱膨張係数）が小さい、すなわち熱プロセス中の伸縮が小さいため、後述の第二配線基板との接合の際に好適である。プロセス中の反りを抑制するため、支持基板１としてのガラス基板の厚みは５００μｍ以上であることが望ましい。実用的には０．５ｍｍ〜２．０ｍｍの範囲内でよい。 First, a release layer 2 is formed on a support 1 as shown in FIG. As the support substrate 1, a glass substrate can be used. The glass substrate has a flat surface and is suitable for forming terminal electrodes and fine wirings with a narrow pitch. Further, since the glass substrate has a small CTE (coefficient of thermal expansion), that is, a small expansion and contraction during a thermal process, it is suitable for bonding to a second wiring substrate described later. In order to suppress warpage during the process, the thickness of the glass substrate as the support substrate 1 is desirably 500 μm or more. Practically, it may be in the range of 0.5 mm to 2.0 mm.
剥離層２は、光の照射により分解可能な樹脂を含んでいる。本実施形態における光はレーザー光であるので、剥離層２に含まれる樹脂として、レーザー光が照射されることによって熱分解可能な樹脂が用いられる。剥離層２に含まれる樹脂としては、例えばエポキシ樹脂、アクリル樹脂、ポリウレタン樹脂、シリコーン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂のうちの１種またはこれらの樹脂の２種類以上が混合された樹脂等が用いられる。剥離層２の厚さは、例えば０．１μｍ〜１０μｍである。 The release layer 2 contains a resin that can be decomposed by light irradiation. Since the light in this embodiment is a laser beam, a resin that can be thermally decomposed by irradiating the laser beam is used as the resin included in the peeling layer 2. The resin contained in the release layer 2 is, for example, one of an epoxy resin, an acrylic resin, a polyurethane resin, a silicone resin, a polyester resin, an oxetane resin, and a maleimide resin, or a resin in which two or more of these resins are mixed. Are used. The thickness of the release layer 2 is, for example, 0.1 μm to 10 μm.
次に、図２（ｂ）に示すように、第一最外層３、必要な層数（図では３層）の配線層４、第二最外層５を順に形成し、第一配線基板１０を作製する。第一配線基板１０の厚みは５０〜１００μｍであるので、支持基板１の厚みは第一配線基板１０の厚みの１０倍以上であるものが望ましい。本発明の実施形態によれば、充分に厚い支持基板１上に比較的薄い第一配線基板１０を形成することにより、製造プロセス中の反りが抑えられる。 Next, as shown in FIG. 2B, a first outermost layer 3, a required number of wiring layers 4 (three layers in the figure), and a second outermost layer 5 are sequentially formed, and the first wiring substrate 10 is formed. Make it. Since the thickness of the first wiring board 10 is 50 to 100 μm, the thickness of the support substrate 1 is desirably 10 times or more the thickness of the first wiring board 10. According to the embodiment of the present invention, by forming the relatively thin first wiring board 10 on the sufficiently thick support substrate 1, warpage during the manufacturing process can be suppressed.
第一最外層３、第二最外層５で用いる樹脂としては、感光性の熱硬化性絶縁樹脂を用いる。例えばエポキシ系、シアネート系、ポリイミド系樹脂のいずれかを用いることができる。熱硬化性絶縁樹脂は、例えばシリカフィラーが含むが、アルミナ等の無機フィラーを使用してもよい。第一最外層３、第二最外層５の少なくとも一方に含む補強材としては、ガラスクロスが好適であるが、この他に耐熱性・機械強度に優れたカーボンファイバー、液晶ポリマー繊維等であってもよい。 As the resin used for the first outermost layer 3 and the second outermost layer 5, a photosensitive thermosetting insulating resin is used. For example, any one of epoxy-based, cyanate-based, and polyimide-based resins can be used. The thermosetting insulating resin includes, for example, a silica filler, but may use an inorganic filler such as alumina. As a reinforcing material contained in at least one of the first outermost layer 3 and the second outermost layer 5, glass cloth is suitable, but in addition, carbon fiber, liquid crystal polymer fiber, etc. having excellent heat resistance and mechanical strength are used. Is also good.
接続パッド７を有する第一最外層３の形成は、例えば、まず剥離層２上に銅箔（不図示）を形成し、該銅箔上に第一最外層３を構成する感光性絶縁樹脂を塗工、露光、現像し、開口部を形成した後、ベークを実施する。次に該開口部に、銅箔をシード層として電解めっきを行うことにより接続パッド７を形成する。尚、剥離層２の上には、紫外線で硬化する接着剤を塗布して接着層（不図示）を形成してもよい。 The first outermost layer 3 having the connection pads 7 is formed, for example, by first forming a copper foil (not shown) on the release layer 2 and then forming a photosensitive insulating resin constituting the first outermost layer 3 on the copper foil. After coating, exposing, developing and forming an opening, baking is performed. Next, connection pads 7 are formed in the openings by performing electrolytic plating using a copper foil as a seed layer. Note that an adhesive curable by ultraviolet rays may be applied on the release layer 2 to form an adhesive layer (not shown).
接続パッド７の構造は、第一配線基板１０を第二配線基板２０と接合した後、支持基板１や剥離層２を除去し、図１（ａ）のように、接続パッド７を露出させたときに、接続パッド７の表面が、例えばＡｕとなるように銅箔側からＡｕ／Ｎｉ／Ｃｕとめっき層を形成する。このとき、ＡｕへのＣｕ拡散を防止するため、銅箔とＡｕとの間に薄いＮｉ層を形成してからＡｕ／Ｎｉ／Ｃｕのめっきを行う。 The structure of the connection pad 7 is such that after bonding the first wiring substrate 10 to the second wiring substrate 20, the support substrate 1 and the release layer 2 are removed, and the connection pad 7 is exposed as shown in FIG. Sometimes, Au / Ni / Cu and a plating layer are formed from the copper foil side so that the surface of the connection pad 7 becomes, for example, Au. At this time, in order to prevent diffusion of Cu into Au, a thin Ni layer is formed between the copper foil and Au, and then Au / Ni / Cu plating is performed.
次に、配線層４中の配線パターン８ａ、８ｂ、・・・の形成は、例えば以下のように行う。第一配線基板１０の配線層４に用いられる絶縁樹脂４ａは感光性エポキシ系樹脂を使用することが好ましいが、ポリイミド系樹脂であってもよい。まず、第一最外層３上に感光性エポキシ系樹脂等の絶縁樹脂をスピンコート法等により塗布する。感光性エポキシ系樹脂は比較的低温で硬化することができ、この後のビア穴を形成した後のキュア（硬化）による収縮が少なく好ましい。 Next, the formation of the wiring patterns 8a, 8b,... In the wiring layer 4 is performed, for example, as follows. The insulating resin 4a used for the wiring layer 4 of the first wiring board 10 is preferably a photosensitive epoxy resin, but may be a polyimide resin. First, an insulating resin such as a photosensitive epoxy resin is applied on the first outermost layer 3 by a spin coating method or the like. The photosensitive epoxy resin can be cured at a relatively low temperature, and is less likely to shrink due to curing (curing) after the formation of the via hole.
次に、第一最外層３上に導通ビア４ｂの穴形状を形成する。本実施形態では絶縁樹脂４ａに感光性エポキシ系樹脂を使用しており、露光、及び現像を行うことにより導通ビア４ｂの穴形状を形成することができる。非感光のポリイミド系樹脂を使用する場合、レーザー光照射によって導通ビア４ｂの穴形状を形成しても良い。 Next, a hole shape of the conductive via 4b is formed on the first outermost layer 3. In this embodiment, a photosensitive epoxy resin is used for the insulating resin 4a, and the hole shape of the conductive via 4b can be formed by performing exposure and development. When a non-photosensitive polyimide resin is used, the hole shape of the conductive via 4b may be formed by laser beam irradiation.
次に、アッシング等で残渣を除去した後、例えばＴｉとＣｕを連続でスパッタし、電解銅めっきのシード層を形成する。このシード層の上に導通ビア４ｂ、及び微細配線パターンを形成するが、Ｔｉは下層の絶縁樹脂との密着性を向上することができ、めっき後のパ
ターン剥がれ、倒れを防止する効果を有する。その他、チタン−タングステン（ＴｉＷ）とＣｕのスパッタ連続処理等にてシード層を形成しても良い。
Next, after removing the residue by ashing or the like, for example, Ti and Cu are continuously sputtered to form a seed layer of electrolytic copper plating. A conductive via 4b and a fine wiring pattern are formed on the seed layer. Ti can improve the adhesion to the underlying insulating resin, and has an effect of preventing pattern peeling and falling after plating. In addition, the seed layer may be formed by continuous sputtering of titanium-tungsten (TiW) and Cu.
次に、レジストパターンを形成し、その開口部、及び上記導通ビア４ｂの穴形状内に電解銅めっきにて、導通ビア４ｂと配線パターンを形成する。さらに、レジストパターンを除去した後、配線パターンをマスクとして、シード層としたスパッタＣｕとスパッタＴｉとをエッチングする。 Next, a resist pattern is formed, and a conductive via 4b and a wiring pattern are formed by electrolytic copper plating in the opening and the hole shape of the conductive via 4b. Further, after removing the resist pattern, the sputter Cu and the sputter Ti serving as the seed layer are etched using the wiring pattern as a mask.
以上説明した導通ビアと配線パターン形成工程を、積み重ねる配線層数に合わせて繰り返し、配線層４を形成する。 The conductive via and wiring pattern forming process described above is repeated according to the number of wiring layers to be stacked, and the wiring layer 4 is formed.
続いて、第二最外層５にバンプ形成を行うために、まず、配線層４を覆うように、第二最外層５となる感光性絶縁樹脂を塗工、露光、現像し、接続端子部を開口させた後、ベークを実施する。この開口部に銅の酸化を抑制し、はんだの濡れ性を高めるためニッケル・パラジウム・金めっきやＯＳＰ（Ｏｒｇａｎｉｃ Ｓｏｌｄｅｒａｂｉｌｉｔｙ Ｐｒｅｓｅｒｖａｔｉｖｅ）を施し、パッド表面処理層７ａを形成する。 Subsequently, in order to form a bump on the second outermost layer 5, first, a photosensitive insulating resin to be the second outermost layer 5 is coated, exposed, and developed so as to cover the wiring layer 4, and the connection terminal portion is formed. After opening, baking is performed. Nickel-palladium-gold plating or OSP (Organic Solderability Preservative) is applied to the opening to suppress copper oxidation and increase solder wettability, thereby forming a pad surface treatment layer 7a.
その後、前記開口部に、はんだペーストを印刷、またははんだボールを振り込み、リフローすることにより、図２（ｃ）に示すように、第二最外層５にはんだバンプ６が形成される。また、バンプははんだだけではなく銅ピラーや銅コアボールを含んでもよい。 Thereafter, a solder paste is printed on the opening or a solder ball is transferred and reflowed to form a solder bump 6 on the second outermost layer 5 as shown in FIG. 2C. Further, the bumps may include not only solder but also copper pillars and copper core balls.
図３は、本発明の一実施形態に係る、配線基板の製造方法のうち、図２の製造工程に続く製造工程の主要部を工程順に示す模式断面図であり、図４は、図３の製造工程に続く製造工程の主要部を工程順に示す模式断面図である。 FIG. 3 is a schematic cross-sectional view showing, in the order of steps, a main part of a manufacturing process following the manufacturing process of FIG. 2 in the method of manufacturing a wiring board according to one embodiment of the present invention, and FIG. It is a schematic cross section which shows the principal part of a manufacturing process following a manufacturing process in order of a process.
支持基板１と剥離層２が付いた第一配線基板１０を個片化し、図３に示すように近接させ、別に製造した第二配線基板２０に接合する。接合は、第一配線基板１０、第二配線基板２０それぞれの対応する位置にはんだバンプ６が接触するよう位置合わせを行い、仮圧着し、リフローし、アンダーフィル９により樹脂封止を行う。個片化にはダイシング、スクライビング、レーザー加工などの工法が採用できる。 The first wiring board 10 provided with the support substrate 1 and the release layer 2 is divided into individual pieces, brought close to each other as shown in FIG. 3, and joined to a separately manufactured second wiring board 20. The bonding is performed such that the solder bumps 6 are brought into contact with the corresponding positions of the first wiring board 10 and the second wiring board 20, temporarily press-bonded, reflowed, and resin-sealed with the underfill 9. For singulation, methods such as dicing, scribing, and laser processing can be adopted.
アンダーフィル９は、第二配線基板２０と第一配線基板１０とを固定、及び封止するために用いられる絶縁性の接着剤である。アンダーフィル９としては、例えば、エポキシ樹脂、ポリウレタン樹脂、シリコン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂のうちの１種またはこれらの樹脂の２種類以上が混合された樹脂に、フィラーとしてシリカ、酸化チタン、酸化アルミニウム、酸化マグネシウム、または酸化亜鉛等を加えた材料を用いることができる。 The underfill 9 is an insulating adhesive used for fixing and sealing the second wiring board 20 and the first wiring board 10. As the underfill 9, for example, an epoxy resin, a polyurethane resin, a silicone resin, a polyester resin, an oxetane resin, and a resin in which two or more of these resins are mixed, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added can be used.
続いて図４に示すように、支持基板１を剥離層２から除去する。除去の方法は、ガラスの支持基板１越しにレーザー光１５を適宜走査しながら照射して、第一配線基板１０からガラス基板１を剥離層２とともに除去する。このとき、接続パッド７の形成時にシード層として用いた銅箔（不図示）をともに除去することが望ましい。 Subsequently, as shown in FIG. 4, the support substrate 1 is removed from the release layer 2. As a method of removing, the glass substrate 1 is removed from the first wiring substrate 10 together with the release layer 2 by irradiating the glass substrate 1 with a laser beam 15 while appropriately scanning the substrate. At this time, it is desirable to remove both the copper foil (not shown) used as the seed layer when forming the connection pads 7.
あるいは、支持基板１と剥離層２の界面から支持基板１のみを除去した後、粘着テープ等の粘着性の部材により、剥離層２（または剥離層２と不図示の接着層）及び銅箔を剥離してもよい。すなわち、粘着テープ等を支持基板１が接着されていた領域の少なくとも一部に貼り付け、粘着テープ等を剥がすことにより、第一配線基板１上に残存する剥離層や接着層、銅箔を除去する。 Alternatively, after removing only the support substrate 1 from the interface between the support substrate 1 and the release layer 2, the release layer 2 (or the release layer 2 and an adhesive layer (not shown)) and the copper foil are separated by an adhesive member such as an adhesive tape. You may peel off. That is, an adhesive tape or the like is attached to at least a part of the area where the support substrate 1 has been adhered, and the adhesive tape or the like is peeled off to remove a peeling layer, an adhesive layer, and a copper foil remaining on the first wiring substrate 1. I do.
銅箔をともに剥離しない場合は、銅箔と既述の薄いＮｉ層とをエッチングし、表面にＡ
ｕが露出した、半導体チップを実装する接続パッド７を露出させる。このようにして本発明の配線基板１００が完成する。
If the copper foil is not peeled off together, the copper foil and the thin Ni layer described above are etched and A
The connection pad 7 on which the semiconductor chip is mounted, on which u is exposed, is exposed. Thus, the wiring board 100 of the present invention is completed.
図５は、本発明の一実施形態に係る、配線基板の製造方法のうち、配線基板の製品面付け効率を説明するための模式平面図である。本発明の製造方法では、支持基板（基板サイズα）は円形状基板３０ではなく、四角形状基板４０を用いるので、一般に四角形状をしている配線基板（製品サイズβ）を効率良く面付けすることができる。また支持基板１にはガラス基板を用いることができるので、半導体素子製造プロセスよりも安価な配線基板製造プロセスを活用できるため、低コストで配線基板を製造することができる。 FIG. 5 is a schematic plan view for explaining the product imposition efficiency of the wiring board in the method for manufacturing a wiring board according to one embodiment of the present invention. In the manufacturing method of the present invention, since the support substrate (substrate size α) uses the square substrate 40 instead of the circular substrate 30, the generally rectangular wiring substrate (product size β) is efficiently imposed. be able to. Further, since a glass substrate can be used as the support substrate 1, a wiring substrate manufacturing process that is less expensive than a semiconductor element manufacturing process can be used, and thus a wiring substrate can be manufactured at low cost.
さらには、以下のような効果がある。第一配線基板にあたる配線層をビルドアップ基板上に直接形成する従来の工法では、不良品のビルドアップ基板の上にも配線層を作り込んでしまうことがあるのに対し、本発明では、第二配線基板はすでに良品と選別されたビルドアップ基板を用い、これに第一配線基板を接合することにより、高収率で配線基板を生産することができる。また、１００μｍ以下と薄い第一配線基板を単体で第二配線基板に接合することは通常困難であるが、本発明の配線基板の製造方法では、厚みのある支持基板が付いたまま接合するので従来の半導体製品の実装と同じ技術を活用することができ、かつ、支持基板は後で取り除くためシリコンインターポーザよりも全体として薄い配線基板が実現できる。 Further, there are the following effects. In the conventional method of forming the wiring layer corresponding to the first wiring board directly on the build-up board, the wiring layer may be formed also on the defective build-up board. As the second wiring substrate, a build-up substrate that has already been selected as a non-defective product is used, and the first wiring substrate is joined to the build-up substrate, whereby a wiring substrate can be produced with a high yield. Also, it is usually difficult to bond the first wiring board as thin as 100 μm or less to the second wiring board by itself, but in the method of manufacturing a wiring board of the present invention, the bonding is performed with the thick supporting substrate attached. The same technology as that for mounting a conventional semiconductor product can be used, and since the supporting substrate is removed later, a wiring substrate that is thinner than the silicon interposer as a whole can be realized.
＜比較例＞
第一配線基板の厚みに対して１０倍を超えない厚み、すなわち第一配線基板５０μｍ厚に対して０．３ｍｍ厚のガラス基板上で第一配線基板の製造を行ったところ、絶縁樹脂の硬化収縮や配線層形成時の応力により、ガラス基板が、第一配線基板側が内側になる形状に湾曲してしまい、配線形成のための製造プロセスに供することができなくなった。また、ガラス基板の割れによる不具合の割合も高くなった。
<Comparative example>
When the first wiring board was manufactured on a glass substrate having a thickness of not more than 10 times the thickness of the first wiring board, that is, 0.3 mm thickness with respect to the 50 μm thickness of the first wiring board, the insulating resin was cured. Due to the shrinkage and the stress at the time of forming the wiring layer, the glass substrate is curved into a shape in which the first wiring substrate side is inside, and cannot be provided to the manufacturing process for forming the wiring. In addition, the ratio of defects due to cracks in the glass substrate also increased.
＜その他の実施形態＞
以上説明した本発明の実施形態は単なる例示に過ぎず、本発明を限定するものではない。従って本発明は、その要旨を逸脱しない範囲での改変が可能である。例えば支持基板はガラス基板でなく別のレーザー透過性に優れた材料でもよいし、剥離層にレーザー照射以外の方法で剥離できる材料を採用し、支持基板として金属のような不透明な基板を使用してもよい。
<Other embodiments>
The embodiments of the present invention described above are merely examples, and do not limit the present invention. Therefore, the present invention can be modified without departing from the gist thereof. For example, the support substrate is not limited to a glass substrate, but may be another material having excellent laser permeability.The release layer may be made of a material that can be peeled off by a method other than laser irradiation. You may.
本発明は、マザーボードと半導体チップの間に、インターポーザを介在させる配線基板を備える半導体装置に利用可能である。 INDUSTRIAL APPLICABILITY The present invention is applicable to a semiconductor device including a wiring board having an interposer interposed between a motherboard and a semiconductor chip.
１・・・・支持基板
２・・・・剥離層
３・・・・第一最外層
４・・・・配線層
４ａ・・・絶縁樹脂
４ｂ・・・導通ビア
５・・・・第二最外層
６・・・・はんだバンプ
７・・・・接続パッド
７ａ・・・パッド表面処理層
８ａ、８ｂ、８ｃ・・・・配線パターン
９・・・・アンダーフィル
１５・・・レーザー光
１００・・配線基板
１０・・・第一配線基板
２０・・・第二配線基板
３０・・・円形状基板
４０・・・四角形状基板
α・・・・基板サイズ
β・・・・製品サイズ
５０・・・一般のＦＣ−ＢＧＡ配線基板
５１・・・配線層
５２・・・配線パターン
５３・・・絶縁樹脂
５４・・・第一の端子電極
５５・・・第二の端子電極
５６・・・導通ビア
５７・・・コア層
５８・・・スル−ホール
５９・・・スルーホールめっき
1 ... support substrate 2 ... release layer 3 ... first outermost layer 4 ... wiring layer 4a ... insulating resin 4b ... conductive via 5 ... second outermost layer Outer layer 6 Solder bump 7 Connection pad 7a Pad surface treatment layer 8a, 8b, 8c Wiring pattern 9 Underfill 15 Laser light 100 Wiring board 10 First wiring board 20 Second wiring board 30 Circular board 40 Square board α Board size β Product size 50 General FC-BGA wiring board 51 Wiring layer 52 Wiring pattern 53 Insulating resin 54 First terminal electrode 55 Second terminal electrode 56 Conducting via 57 ... Core layer 58 ... Through hole 59 ... Through hole plating
Claims (4)
ビルドアップ配線層からなる第二配線基板と、前記第二配線基板に接合された第一配線基板と、を備え、
前記第二配線基板と前記第一配線基板とはそれぞれ表面から突出した端子（突起電極）を介して電気的に接合され、
前記第一配線基板及び前記第二配線基板の隙間に絶縁樹脂が充填され、
前記第一配線基板は、順に第一最外層、配線層、第二最外層から成り、
前記第一最外層、前記第二最外層の少なくとも一方に補強材を含む、
ことを特徴とする配線基板。 A wiring board for mounting a semiconductor element,
A second wiring board made of a build-up wiring layer, and a first wiring board joined to the second wiring board,
The second wiring board and the first wiring board are electrically connected to each other via terminals (protruding electrodes) protruding from the surface,
An insulating resin is filled in the gap between the first wiring board and the second wiring board,
The first wiring board includes a first outermost layer, a wiring layer, and a second outermost layer in order,
The first outermost layer, including a reinforcing material in at least one of the second outermost layer,
A wiring board characterized by the above-mentioned.
前記第一配線基板を前記第二配線基板に接合した後、前記支持基板を剥離する、
ことを特徴とする請求項１に記載の配線基板の製造方法。 On a square supporting substrate, a release layer is formed in order, and the first wiring substrate,
After joining the first wiring board to the second wiring board, peeling the support substrate,
2. The method for manufacturing a wiring board according to claim 1, wherein:
ことを特徴とする請求項２に記載の配線基板の製造方法。 The thickness of the support substrate is at least 10 times the thickness of the first wiring substrate, and 0.1 mm to 2.0 mm,
The method for manufacturing a wiring board according to claim 2, wherein:
ことを特徴とする請求項２、または３に記載の配線基板の製造方法。 The material of the support substrate is glass, by irradiating a laser to the release layer through the support substrate, including a step of peeling the support substrate from the first wiring substrate,
The method for manufacturing a wiring board according to claim 2 or 3, wherein:
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