JP2013102062A - Semiconductor mounting member and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor mounting member having high reliability and a method for manufacturing the same.SOLUTION: In the semiconductor mounting member, a second substrate 300 includes an upwardly projecting second connection conductor 332P, and a first substrate 500 includes an upwardly projecting first connection conductor 872P. For instance, a stress generated when the semiconductor mounting member is mounted on an external substrate is released to the first substrate side through the first connection conductor 872P and to the second substrate side through the second connection conductor 332P, and thereby the stress applied to a brittle semiconductor element 90 having high toughness can be relaxed.

Description

The present invention relates to a semiconductor mounting member including a second substrate and a first substrate mounted on the second substrate via bumps, and a method for manufacturing the same.

As a package substrate of a semiconductor device, a build-up multilayer wiring board formed by alternately laminating interlayer resin insulation layers and conductor patterns on a core substrate is used for high integration. Here, in order to further increase the integration rate and shorten the wiring distance, a coreless build-up multilayer wiring board excluding a thick core substrate has been proposed. In Patent Document 1, a conductive filler is filled in a concave portion of a metal plate, an insulating layer and a conductor pattern are stacked on the metal plate, and then the metal plate is removed by etching, whereby an electrode made of a conductive filler. A method of manufacturing a coreless build-up multilayer wiring board comprising:

US2008 / 0188037A1

In recent years, there is a tendency that the material for forming a semiconductor element is made low-k. In such a case, the semiconductor element becomes vulnerable to various thermal stresses.
For this reason, for example, thermal stress generated when the semiconductor device described in Patent Document 1 is mounted on an external substrate and thermal stress generated after mounting are alleviated as much as possible, and such thermal stress is prevented from being applied to the semiconductor element. Is required.

An object of the present invention is to provide a semiconductor mounting member having high reliability.

The invention according to claim 1 is a first via for connecting a plurality of first insulating layers, a first conductor pattern formed on the first insulating layer, and the first conductor patterns positioned above and below. A first substrate having a conductor; a plurality of second insulating layers mounted on the first substrate; a second conductor pattern formed on the second insulating layer; and the second conductor positioned above and below A second substrate having a second via conductor for connecting the patterns, a first bump provided on the first substrate, for connecting a semiconductor element to the first substrate, and provided on the second substrate A semiconductor mounting member having a second bump for connecting the first substrate to the second substrate,
The first substrate has a first connection conductor protruding from a surface of the first insulating layer located in the outermost layer of the first insulating layer, and the second substrate is an outermost layer of the second insulating layer. A second connection conductor protruding from the surface of the second insulating layer located is provided, the first bump is provided on the first connection conductor, and the second bump is provided on the second connection conductor.

In the semiconductor mounting member of the present invention, for example, thermal stress generated by the difference in thermal expansion coefficient between the semiconductor element and the first substrate is first transmitted to the first substrate side through the first connection body. Furthermore, the thermal stress transmitted to the first substrate side is transmitted to the second substrate side via the second connector. That is, the thermal stress generated by the difference in thermal expansion coefficient between the semiconductor element and the first substrate is transmitted to the side away from the semiconductor element through the first connection body and the second connection body. As a result, it is possible to reduce the thermal stress applied to the semiconductor element as much as possible.

It is sectional drawing of the semiconductor mounting member which concerns on the Example of this invention. It is a principal part enlarged view of a semiconductor mounting member. It is sectional drawing of a semiconductor mounting member. It is process drawing which shows the manufacturing process of a 2nd board | substrate. It is process drawing which shows the manufacturing process of a 2nd board | substrate. It is process drawing which shows the manufacturing process of a 2nd board | substrate. It is process drawing which shows the manufacturing process of a 2nd board | substrate. It is process drawing which shows the manufacturing process of a 2nd board | substrate. It is process drawing which shows the manufacturing process of a 2nd board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate. It is process drawing which shows the manufacturing process of a 1st board | substrate.

A semiconductor mounting member according to an embodiment of the present invention will be described with reference to the cross-sectional views of FIGS. 1 shows a part of the semiconductor mounting member, FIG. 2 shows an enlarged connection portion of the semiconductor mounting member, and FIG. 3 shows the entire semiconductor mounting member.
The semiconductor mounting member 10 includes a second substrate 300 and a first substrate 500 mounted on the second substrate 300 via bumps 28.

The second substrate 300 includes a core substrate 30 having a first surface (upper surface) F and a second surface (back surface) S. A conductor pattern 34 is provided on the first surface (upper surface) F, and a conductor pattern 34 is provided on the second surface (back surface) S.
The conductor pattern 34 on the first surface F and the conductor pattern 334 on the second surface S are connected via a through-hole conductor 36. The through-hole conductor 36 is formed by filling the through hole 28 provided in the core substrate with copper plating.

Interlayer insulating layers (second insulating layers) 50 and 150 and conductor patterns 58 and 158 are alternately stacked on the first surface F of the core substrate 330. The upper and lower conductor patterns are electrically connected through via conductors 60 and 160.
On the outermost interlayer insulating layer 150, solder resist layers 370a and 370b having openings 371 are respectively provided. In addition, the “second insulating layer located in the outermost layer” in claim 1 means the solder resist layer 370a.

A second connection conductor 332P is formed on the conductor pattern 158 exposed from the opening 371. The second connection conductor 332P is formed of the same material (for example, copper) as the material forming the conductor pattern. In addition, it is preferable to form the 2nd connection conductor 332P from a solder at the point which can relieve | moderate a thermal stress effectively.

The upper surface of the second connection conductor 332P protrudes upward (on the first substrate side) from the surface of the solder resist layer 370a. The side surface of the second connection conductor 332P is inclined so that the diameter becomes smaller toward the upper side (first substrate side). Furthermore, the side surface of the second connection conductor 332P has a shape recessed in an arc shape. Thereby, compared with the case where the 2nd connection conductor 332P has a perpendicular | vertical side surface, the contact area with the bump 28 mentioned later increases. As a result, it becomes easy to relieve the thermal stress through the second connection conductor 332P.
A bump 28 is provided on the second connection conductor 332P so as to cover the second connection conductor 332P. The first substrate is mounted on the second substrate via the bumps 28.

The first substrate 500 does not have a core substrate. The first substrate 500 includes first insulating layers 650 and 750, solder resists 850 and 550, conductor patterns 658 and 758, and via conductors 660 and 760. A semiconductor chip 90 is mounted on the first main surface of the first substrate 500. The semiconductor chip 90 is sealed with a sealing resin 98.
The first insulating layer forming the first substrate 500 does not contain a reinforcing material such as glass cloth, glass nonwoven fabric, aramid cloth, or aramid nonwoven fabric.
The thickness of the first substrate 500 is thinner than the second substrate 300 and is 20 to 30 μm.

A conductor pattern 658 is formed on the first insulating layer 650. A hole 651 (via hole) is formed in the first insulating layer 650, and a via conductor 660 (second conductor pattern) made of plating is provided in the hole 651. The via conductor 660 passes through the first insulating layer 650. A solder resist 550 is formed on the surface of the first insulating layer 650 opposite to the surface on which the conductor pattern 658 is formed. The solder resist 550 has an opening 556 that exposes the conductor pattern 534 to which the via conductor 660 is connected. The “first insulating layer located in the outermost layer” in claim 1 means the solder resist layer 850.

Bumps 28 are formed on the conductor pattern 534 exposed through the openings 556 via a surface treatment film (not shown). This surface treatment film is made of, for example, Ni and Au.

A first insulating layer 750 is formed on the first insulating layer 650 and the conductor pattern 658. In addition, a conductor pattern 758 (first conductor pattern) is formed on the first insulating layer 750. Further, a hole 751 (via hole) is formed in the first insulating layer 750. Then, by filling the hole 751 with a conductor (for example, copper plating), the conductor in the hole 751 becomes a via conductor 760 (filled conductor). Conductive pattern 658 and conductive pattern 758 are electrically connected to each other via via conductor 760.

The first insulating layers 650 and 750 and the solder resists 850 and 550 are made of, for example, a photosensitive resin. However, the present invention is not limited to this, and the first insulating layers 650 and 750 and the solder resists 850 and 550 may be made of a material other than the photosensitive resin.
The linear expansion coefficient of the first insulating layer is 10 to 25 ppm, which is smaller than the linear expansion coefficient of the second insulating layer.

Each of the conductor pattern 658 and the via conductor 660 includes, for example, a first conductor film 652 formed on the insulating layer 650 and a second conductor film 653 formed on the first conductor film 652 as shown in FIG. , 656. Each of the conductor pattern 758 and the via conductor 760 includes a first conductor film 752 formed on the insulating layer 750 and second conductor films 753 and 756 formed on the first conductor film 752. . Here, the first conductor films 652 and 752 are formed in a two-layer structure of, for example, TiN (lower layer) and Ti (upper layer) because it is easy to ensure both prevention of ion migration and adhesion to the insulating layer. It is preferred that These two layers are formed by sputtering, for example. The second conductor films 653, 656, 753, and 756 are preferably formed of Cu, for example, in terms of electrical resistance. In the present embodiment, the second conductor films 653, 656, 753, and 756 are composed of electroless copper plating films 653 and 753 and electrolytic copper plating films 656 and 756 thereon. At this time, instead of the electroless copper plating films 653 and 753, a copper thin film formed by a sputtering method may be employed.

On the insulating layer 750, a solder resist 850 having an opening 851 exposing a part of the conductor pattern 758 is formed. A first connection conductor 872P is formed on the conductor pattern 758 exposed in the opening 851 of the solder resist 850. The first connection conductor 872P is made of the same material (for example, copper) as the material forming the conductor pattern. Note that the first connection conductor 872P is preferably formed from solder in that thermal stress can be effectively relieved.

The upper surface of the first connection conductor 872P protrudes upward (semiconductor element side) from the surface of the solder resist layer 850. The side surface of the first connection conductor 872P is inclined so that the diameter becomes smaller toward the upper side (semiconductor element side). Furthermore, the side surface of the first connection conductor 872P has a shape that is recessed in an arc. Thereby, compared with the case where the 1st connection conductor 872P has a perpendicular | vertical side surface, the contact area with the bump 28 mentioned later increases. As a result, it becomes easy to relieve the thermal stress through the first connection conductor 872P.
A bump 828 is provided on the first connection conductor 872P so as to cover the first connection conductor 872P. A semiconductor element 90 is mounted on the first substrate 500 via the bumps 828.

The internal structure of the semiconductor element is shown in FIG. The semiconductor element 90 includes an electrode 92, an insulating film 95 having a through hole 97, a via conductor 94 formed in the through hole 97 on the electrode 92, and the via conductor 94 exposed from the insulating film 95. And a third conductor post 96P formed thereon. The third conductor post is made of copper plating.

The first substrate 500 and the semiconductor element 90 are connected via solder bumps 828 provided between the first conductor post 872P on the first substrate 500 side and the third conductor post 96P on the semiconductor element 90 side. ing. An underfill resin 99 is filled between the first substrate and the semiconductor element.

In the semiconductor mounting member 10 of the embodiment, the second substrate 300 includes the second connection conductor 332P, and the first substrate 500 includes the first connection conductor 872P. For example, thermal stress generated by the difference in thermal expansion coefficient between the semiconductor element and the first substrate is first transmitted to the first substrate side through the first connection body. Furthermore, the thermal stress transmitted to the first substrate side is transmitted to the second substrate side via the second connector. That is, the thermal stress generated by the difference in thermal expansion coefficient between the semiconductor element and the first substrate is transmitted to the side away from the semiconductor element through the first connection body and the second connection body. As a result, it is possible to reduce the thermal stress applied to the semiconductor element as much as possible.

[Method for manufacturing second substrate]
A method of manufacturing the second substrate described above with reference to FIGS. 1 to 3 will be described with reference to FIGS.
(1) A copper-clad laminate 20A in which a 15 μm copper foil 22 is laminated on both surfaces of a core substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.15 mm is used as a starting material. First, a blackening process is performed on the surface of the copper foil 22 (FIG. 4A).

(2) The first surface F (upper surface) side of the core substrate 30 is irradiated with CO2 laser from the first surface toward the second surface, and the first surface F (upper surface) side of the core substrate 30 is used for through holes. A first opening 28a for forming a through hole is formed (FIG. 4B).

(3) The CO 2 laser is irradiated on the second surface S (back surface) side of the core substrate 30 from the second surface toward the first surface under the same conditions as the first opening 28a formation conditions, and the first opening 28a. A second opening 28b is formed to be connected to (FIG. 4C).

(4) The CO 2 laser is irradiated on the second surface S (back surface) side of the core substrate 30 toward the first surface from the second surface toward the first surface. Then, a third opening 28c is formed to widen the connecting portion between the first opening 28a and the second opening 28b (FIG. 4D).

(5) After the desmear process of the through-hole 28 is performed with permanganic acid, the electroless plating film 31 is formed by the electroless plating process (FIG. 5A).

(6) A plating resist 40 having a predetermined pattern is formed on the electroless plating film 31 on the surface of the core substrate 30 (FIG. 5B).

(7) By electrolytic plating, the electrolytic plating film 32 is formed on the portion where the plating resist 40 is not formed, and the through-hole conductor 36 in which the through hole 28 is filled with plating is formed (FIG. 5C).

(8) The plating resist 40 is peeled off, the electroless plating film 31 and the copper foil 22 under the plating resist are removed by etching, the conductor circuit 34 and the through-hole conductor 36 are formed, and the core substrate 30 is completed (see FIG. 6 (A)).

(9) An interlayer insulating layer 50 is provided on both surfaces of the core substrate 30 that has undergone the above-described steps by vacuum compression laminating a resin film for an interlayer insulating layer that is slightly larger than the core substrate and having a thickness of 50 μm while raising the temperature (FIG. 6 (B)).

(10) Next, a via hole opening 51 having a diameter of 80 μm is provided in the interlayer insulating layer 50 with a CO 2 gas laser (see FIG. 6C). By immersing in an oxidizing agent such as chromic acid or permanganate, the interlayer insulating layer 50 is provided with a roughened surface (not shown).

(11) A catalyst such as palladium is applied to the surface layer of the interlayer insulating layer 50 in advance and immersed in the electroless plating solution for 5 to 60 minutes, whereby the electroless plating film 52 is provided in the range of 0.1 to 5 μm. (FIG. 6 (D)).

(12) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above-described treatment, and a photomask film is placed and exposed, and then developed with sodium carbonate. Provided (FIG. 7A).

(13) Next, an electrolytic plating film 56 having a thickness of 15 μm is formed by electrolytic plating (see FIG. 7B).

(14) After the plating resist 54 is peeled and removed, the electroless plating film 52 under the plating resist is dissolved and removed by etching, and a conductor circuit 58 and a via conductor 60 each including the electroless plating film 52 and the electrolytic plating film 56 are removed. Is formed (FIG. 7C). A roughened surface is formed on the surfaces of the conductor circuit 58 and the via conductor 60 by the etching solution (not shown).

(15) The interlayer insulating layer 150 including the conductor circuit 158 and the via conductor 160 is formed in the same manner as in the above (9) to (14) (FIG. 8A).

(16) A commercially available solder resist composition is applied, and exposed and developed to form solder resist layers 370a and 370b having openings 71 (FIG. 9B).

(17) An electroless plating film 352 is formed on the solder resist layer 370a on the first surface F side. On the other hand, a nickel plating layer / gold plating layer 376 is formed in the opening 71 of the solder resist layer 370b on the second surface S surface side (FIG. 8C).

(18) An electrolytic plating film 356 is formed on the electroless plating film 352 on the first surface side (FIG. 9A).

(19) An etching resist 354 is formed on the electrolytic plating film 356 (FIG. 9B).

(20) The electrolytic plating film 356 and the electroless plating film 352 in the portion where the etching resist 354 is not formed are etched, the etching resist 354 is removed, and the second substrate 300 including the second connection conductor 332P is completed (FIG. 9C). ).

[First substrate manufacturing method]
A method for manufacturing the first substrate will be described with reference to FIGS.
(1) First, a glass plate 510 having a thickness of about 1.1 mm is prepared (FIG. 10A).
The glass plate has a CTE of 3.3 (ppm) or less so that the difference in coefficient of thermal expansion from the silicon IC chip to be mounted is small, and transmits a 308 nm laser beam used in the peeling process described later. It is desirable that the rate is 90% or more.

(2) A peeling layer 512 mainly made of a thermoplastic polyimide resin is provided on the glass plate 510 (FIG. 10B).

(3) A copper foil is laminated on the release layer 512, and a second surface side conductor pattern 534 is formed by patterning (FIG. 10C).

(4) On the release layer 512 and the second surface side conductor pattern 534, a resin film for interlayer resin insulation layer (manufactured by Ajinomoto Co., Inc .; trade name: ABF-45SH) is vacuum-bonded and laminated to form the first resin insulation layer 650 Provided (see FIG. 10D). The resin film for interlayer resin insulation layers includes soluble particles having a particle size of 0.1 μm or less and inorganic particles.

(5) An opening 651 for an electrode body that penetrates the first resin insulating layer 650 and reaches the peeling layer 512 is provided by a CO2 gas laser (see FIG. 10E).

(6) A first conductor layer 652 having a two-layer structure of TiN (lower layer) and Ti (upper layer) is formed on the first resin insulating layer 650 by sputtering (FIG. 11A).

(7) A catalyst such as palladium is applied to the surface layer and immersed in an electroless plating solution for 5 to 60 minutes to provide an electroless plating film 653 (FIG. 11B).

(8) A commercially available photosensitive dry film is affixed on the electroless plating film 653, a photomask film is placed and exposed, developed with sodium carbonate, and a plating resist 654 having a thickness of about 15 μm is formed. (FIG. 11C).

(9) Electroless plating is performed using the electroless plating film 653 as a power feeding layer to form an electrolytic plating film 656 (FIG. 11D).

(10) The plating resist 654 is peeled and removed. Then, the electroless plating film 653 and the first conductor layer 652 under the peeled plating resist are removed, and the first conductor pattern 658 including the first conductor layer 652, the electroless plating film 653 and the electrolytic plating film 56, and the first via. A conductor 660 is formed (FIG. 12A).

(111) The second resin insulation layer 750, the first conductor pattern 758, and the second via conductor 760 are formed on the first resin insulation layer 650 and the first conductor pattern 658 in the same manner as the above (4) to (10). (FIG. 12B).

(12) A solder resist layer 850 having an opening 851 is formed (FIG. 12C).

(13) A first conductor layer 652 having a two-layer structure of TiN (lower layer) and Ti (upper layer) is formed on the first resin insulating layer 650 by sputtering (FIG. 12D).

(14) A catalyst such as palladium is applied to the surface layer and immersed in an electroless plating solution, whereby an electroless plating film 853 is provided (FIG. 13A).

(15) An electrolytic plating film 856 is formed on the electroless plating film 852 (FIG. 13B).

(16) An etching resist 824 is formed on the electrolytic plating film 856 (FIG. 13C).

(17) The electrolytic plating film 856 and the electroless plating film 852 in the portion where the etching resist 824 is not formed are etched, the first conductor layer 652 is peeled off, the etching resist 824 is removed, and the first connection conductor 872P is formed (FIG. 13 (D)).

(18) The solder bump 828 is connected via the first connection conductor 872P, and the semiconductor element 90 is mounted (FIGS. 14A and 14B).

(19) After the underfill 99 is filled between the first substrate 500 and the semiconductor element 90, the semiconductor element 90 is sealed with the mold resin 98 in the mold (FIG. 14C).

(20) Next, a laser beam of 308 nm is transmitted through the glass plate 510 and applied to the release layer 512, and the release layer 512 is softened. Then, the glass plate 510 is slid with respect to the first substrate 500, and the glass plate 510 is peeled off (FIG. 15A).

(21) The peeling layer 512 is removed by ashing (FIG. 15B).

(22) A solder resist layer 550 having an opening 556 is formed on the insulating layer 650 (FIGS. 15C and 16A).

(23) Solder bumps 28 are formed in the openings 556 of the solder resist layer (FIG. 16B).

[Mounting the first board to the second board]
As shown in FIG. 3, the first substrate 300 is mounted on the second connection conductor 332 </ b> P of the second substrate 300 via the solder bumps 28.

DESCRIPTION OF SYMBOLS 10 Semiconductor mounting member 90 Semiconductor element 300 2nd board | substrate 332P 2nd connection conductor 50,150 1st insulation layer 500 1st board | substrate 650,750 1st insulation layer 872P 1st connection conductor

Claims (10)

A first substrate having a plurality of first insulating layers, a first conductor pattern formed on the first insulating layer, and a first via conductor connecting the first conductor patterns positioned above and below;
A second via conductor that mounts the first substrate and connects a plurality of second insulating layers, a second conductor pattern formed on the second insulating layer, and the second conductor patterns positioned above and below A second substrate having:
A first bump provided on the first substrate for connecting a semiconductor element to the first substrate;
A second bump provided on the second substrate for connecting the first substrate to the second substrate;
A semiconductor mounting member having
The first substrate has a first connection conductor protruding from the surface of the first insulating layer located in the outermost layer of the first insulating layer,
The second substrate has a second connection conductor protruding from the surface of the second insulating layer located in the outermost layer of the second insulating layer,
The first bump is provided on the first connection conductor;
The second bump is provided on the second connection conductor. The semiconductor mounting member according to claim 1, wherein:
The plurality of first insulating layers do not have a reinforcing material. The semiconductor mounting member according to claim 1, wherein:
The thickness of the first substrate is smaller than the thickness of the second substrate. The semiconductor mounting member according to claim 1, wherein:
The first substrate has a thickness of 20 to 30 μm. The semiconductor mounting member according to claim 1, wherein:
The linear expansion coefficient of the first insulating layer is smaller than the linear expansion coefficient of the second insulating layer. The semiconductor mounting member according to claim 1, wherein:
The second connection conductor has a side surface that is inclined so that its diameter decreases toward the first substrate side. The semiconductor mounting member according to claim 6:
The second connection conductor has a side surface that is recessed in an arc. The semiconductor mounting member according to claim 1, wherein:
The first connection conductor has a side surface that is inclined so that its diameter decreases toward the semiconductor element side. The semiconductor mounting member according to claim 8, wherein:
The first connection conductor has a side surface that is recessed in an arc. The method for manufacturing a semiconductor mounting member according to claim 1.

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