JP2010161419A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2010161419A
JP2010161419A JP2010096232A JP2010096232A JP2010161419A JP 2010161419 A JP2010161419 A JP 2010161419A JP 2010096232 A JP2010096232 A JP 2010096232A JP 2010096232 A JP2010096232 A JP 2010096232A JP 2010161419 A JP2010161419 A JP 2010161419A
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Prior art keywords
solder
substrate
conductive paste
semiconductor
electrode pads
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JP2010096232A
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JP5404513B2 (en
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Yuji Nishitani
祐司 西谷
Tomoshi Oide
知志 大出
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Sony Interactive Entertainment Inc
Sony Corp
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Sony Corp
Sony Computer Entertainment Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To achieve a thinner wiring substrate with a narrower pitch without detracting reliability. <P>SOLUTION: A method of manufacturing a semiconductor device includes steps of: applying a conductive paste 200 containing solder to an upper surface of a substrate for semiconductor chips 11; mounting a semiconductor chip 30 in each of areas of the substrate for semiconductor chips 11; and then heat-treating it at a solder-melting temperature thereby bonding electrode pads 25 to solder bumps 32 with the solder 210 contained in the conductive paste 200. Portions bonded with the solder 210 are coated with insulating resin 212 contained in the conductive paste 200. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体基板および半導体装置に関する。より具体的には、本発明は、コアレスな半導体基板およびこれを用いた半導体装置に関する。   The present invention relates to a semiconductor substrate and a semiconductor device. More specifically, the present invention relates to a coreless semiconductor substrate and a semiconductor device using the same.

近年、コンピュータ、携帯電話、ＰＤＡ（Personal Digital Assistance）などの電子機器の小型化、高機能化・高速化に伴い、こうした電子機器向けのＩＣ（集積回路）、ＬＳＩ（大規模集積回路）などの半導体チップを搭載した半導体装置のさらなる小型化、薄型化、高速化および高密度が要求されている。   In recent years, as electronic devices such as computers, mobile phones, and PDAs (Personal Digital Assistance) have become smaller, more advanced, and faster, such ICs (integrated circuits) and LSIs (Large Scale Integrated Circuits) for such electronic devices have been developed. There is a demand for further downsizing, thinning, high speed and high density of a semiconductor device on which a semiconductor chip is mounted.

半導体装置を小型化、薄型化する技術として、半導体チップを、ベース基板を有しない、いわゆるコアレス基板の上に実装する手法が知られている。コアレス基板は、金属箔などからなるベース基板の上に、配線層を含む配線基板をビルドアップした後、ベース基板を配線基板から剥離することにより得ることができる（特許文献１参照）。   As a technique for reducing the size and thickness of a semiconductor device, a technique of mounting a semiconductor chip on a so-called coreless substrate that does not have a base substrate is known. The coreless substrate can be obtained by building up a wiring substrate including a wiring layer on a base substrate made of metal foil or the like and then peeling the base substrate from the wiring substrate (see Patent Document 1).

従来は、配線基板からベース基板を除去することによってコアレス基板を製造した後、コアレス基板の上に半導体チップなどの電子部品を実装することにより半導体装置を製造していた。   Conventionally, after manufacturing a coreless substrate by removing a base substrate from a wiring substrate, a semiconductor device is manufactured by mounting electronic components such as a semiconductor chip on the coreless substrate.

特開２００５−２３６２４４号公報JP 2005-236244 A

本発明の目的は、信頼性を損なうことなく、配線基板をより薄型化、狭ピッチ化することができる半導体装置を製造する技術の提供にある。   An object of the present invention is to provide a technique for manufacturing a semiconductor device capable of making a wiring board thinner and narrower without impairing reliability.

本発明のある態様は、半導体装置の製造方法である。当該製造方法は、電極パッドが上面に設けられた配線基板を用意する工程と、電極パッドを被覆するように、配線基板の上面にはんだと絶縁樹脂とが混練された導電性ペーストを塗布する工程と、電極パッドに対応する外部電極端子が設けられた半導体チップをフェイスダウンした状態で、外部電極端子に対応するして設けられた、はんだバンプを介して導電性ペーストの上に搭載する工程と、はんだが溶融する温度で加熱を行い、電極パッドとはんだバンプとを導電性ペーストに含まれるはんだで接合する工程と、を備え、導電性ペーストに含まれる絶縁樹脂で、電極パッドとはんだバンプとを接合するはんだを被覆させることを特徴とする。   One embodiment of the present invention is a method for manufacturing a semiconductor device. The manufacturing method includes a step of preparing a wiring substrate having electrode pads provided on the upper surface, and a step of applying a conductive paste in which solder and insulating resin are kneaded on the upper surface of the wiring substrate so as to cover the electrode pads. And mounting on the conductive paste via solder bumps provided corresponding to the external electrode terminals in a state where the semiconductor chip provided with the external electrode terminals corresponding to the electrode pads is face-down. Heating the solder at a temperature at which the solder melts, and joining the electrode pad and the solder bump with the solder contained in the conductive paste. It is characterized by covering the solder which joins.

この態様によれば、組み立て時のハンドリング、熱、洗浄水圧などによりはんだ接合部分にダメージが生じることが抑制される。この結果、配線基板をより薄型化、狭ピッチ化することができる。   According to this aspect, damage to the solder joint portion due to handling during assembly, heat, washing water pressure, and the like is suppressed. As a result, the wiring board can be made thinner and narrower.

上記態様の半導体装置の製造方法において、配線基板を用意する工程は、少なくとも１層の層間絶縁膜によって相互に接続された多層配線層を金属基板の上の所定領域に構築する工程と、所定領域の周縁部分に金属基板が残るように金属基板を選択的に除去して、各領域にスティフナーを形成するとともに、各スティフナーで囲まれた部分において多層配線層と電気的に接続された電極パッドを露出させる工程と、を含んでもよい。   In the method of manufacturing a semiconductor device according to the above aspect, the step of preparing the wiring board includes a step of building a multilayer wiring layer interconnected by at least one interlayer insulating film in a predetermined area on the metal substrate, and a predetermined area The metal substrate is selectively removed so that the metal substrate remains on the peripheral portion of the substrate, and stiffeners are formed in each region, and electrode pads electrically connected to the multilayer wiring layer are formed in the portions surrounded by the stiffeners. Exposing.

本発明によれば、信頼性を損なうことなく、配線基板をより薄型化、狭ピッチ化することができる。   According to the present invention, a wiring board can be made thinner and narrower without impairing reliability.

実施の形態に係る半導体基板の構造を示す図である。It is a figure which shows the structure of the semiconductor substrate which concerns on embodiment. 実施の形態に係る半導体基板を製造する方法を示す工程図である。It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. 実施の形態に係る半導体基板を製造する方法を示す工程図である。It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. 実施の形態に係る半導体基板を製造する方法を示す工程図である。It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. 実施の形態に係る半導体基板を製造する方法を示す工程図である。It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. 実施の形態に係る半導体基板を製造する方法を示す工程図である。It is process drawing which shows the method of manufacturing the semiconductor substrate which concerns on embodiment. 実施の形態に係る半導体基板を用いた半導体装置の構造を示す図である。It is a figure which shows the structure of the semiconductor device using the semiconductor substrate which concerns on embodiment. 半導体チップの実装方法を示す工程図である。It is process drawing which shows the mounting method of a semiconductor chip.

図１（Ａ）は、実施の形態に係る半導体基板１１の構造を示す図である。図１（Ｂ）は、半導体基板１１の下面側の構造を示す平面図である。   FIG. 1A is a diagram illustrating a structure of a semiconductor substrate 11 according to the embodiment. FIG. 1B is a plan view showing the structure of the lower surface side of the semiconductor substrate 11.

半導体基板１１は、層間絶縁膜と配線層とが交互に積層された多層配線構造を有する。具体的には、半導体基板１１は、複数の配線層２２が層間絶縁膜２４を介して積層されている。配線層２２には、たとえば銅が用いられる。層が異なる配線層２２間は、層間絶縁膜２４に設けられたビアプラグ２６により電気的に接続されている。半導体チップが実装される側にあたる半導体基板１１の上面側には、電解メッキにより形成されたニッケル、鉛、金またはこれらの合金からなる電極パッド２５がアレイ状に複数配設され、各電極パッド２５の上に、錫、鉛またはこれらの合金からなるＣ４（Controlled Collapse Chip Connection）バンプ２７が設けられている。また、半導体基板１１の上面側には、Ｃ４バンプ２７を取り囲むようにスティフナー１６０が形成されている。   The semiconductor substrate 11 has a multilayer wiring structure in which interlayer insulating films and wiring layers are alternately stacked. Specifically, in the semiconductor substrate 11, a plurality of wiring layers 22 are stacked via an interlayer insulating film 24. For example, copper is used for the wiring layer 22. The wiring layers 22 having different layers are electrically connected by via plugs 26 provided in the interlayer insulating film 24. A plurality of electrode pads 25 made of nickel, lead, gold, or alloys thereof formed by electrolytic plating are arranged in an array on the upper surface side of the semiconductor substrate 11 corresponding to the side on which the semiconductor chip is mounted. A C4 (Controlled Collapse Chip Connection) bump 27 made of tin, lead, or an alloy thereof is provided on the top. A stiffener 160 is formed on the upper surface side of the semiconductor substrate 11 so as to surround the C4 bump 27.

一方、半導体基板１１の下面側には、ボールランド部２９がアレイ状に複数配設されており、各ボールランド部２９にはんだボール５０が接合されている。また、はんだボール５０の隙間部分の層間絶縁膜２４の表面は、ソルダーレジスト膜２８によって被覆されている。   On the other hand, a plurality of ball land portions 29 are arranged in an array on the lower surface side of the semiconductor substrate 11, and a solder ball 50 is joined to each ball land portion 29. Further, the surface of the interlayer insulating film 24 in the gap portion of the solder ball 50 is covered with a solder resist film 28.

本実施の形態の半導体基板１１は、スティフナー１６０により剛性が付与されているため、半導体基板のハンドリングが容易になるとともに、半導体基板における損傷の発生を抑制することができる。スティフナー１６０は、多層配線構造を構築する際の土台となる金属基板の一部を利用して形成されている。これにより、半導体基板１１の部品点数の削減および製造コストの低減を図ることができる。なお、スティフナー１６０の形状は、図１（Ｂ）のように、Ｃ４バンプ２７を取り囲む形態に限られない。たとえば、Ｃ４バンプ２７の群を挟んで、一組の対向する辺にそれぞれ平行に配設されていてもよい。   Since the semiconductor substrate 11 of the present embodiment is given rigidity by the stiffener 160, the semiconductor substrate can be easily handled and the occurrence of damage to the semiconductor substrate can be suppressed. The stiffener 160 is formed by using a part of a metal substrate that serves as a foundation for constructing a multilayer wiring structure. Thereby, the number of parts of the semiconductor substrate 11 can be reduced and the manufacturing cost can be reduced. The shape of the stiffener 160 is not limited to the form surrounding the C4 bump 27 as shown in FIG. For example, the C4 bumps 27 may be disposed in parallel with a pair of opposing sides with the group of C4 bumps 27 interposed therebetween.

（半導体基板の製造方法）
図２〜図６は、実施の形態に係る半導体装置の製造方法を示す工程図である。 (Semiconductor substrate manufacturing method)
2 to 6 are process diagrams showing a method of manufacturing a semiconductor device according to the embodiment.

まず、ベースとなる銅などの金属基板１００の上に多層配線基板を構築する。具体的には、図２（Ａ）および図２（Ｂ）に示すように、金属基板１００の上に、レジスト膜１０２を塗布し、レーザー光の照射により所定の開口を有する形状にパターニングする。金属基板１００は、複数の半導体パッケージの面積に相当する大きさを有する。金属基板１００のサイズは、特に限定されないが、たとえば、５００ｍｍ角、６００×８００ｍｍ角とすることができる。金属基板１００の上に形成されるレジスト膜１０２は、半導体装置が形成される複数の領域毎に所定のパターンを有する。   First, a multilayer wiring substrate is constructed on a metal substrate 100 such as copper serving as a base. Specifically, as shown in FIGS. 2A and 2B, a resist film 102 is applied on the metal substrate 100 and patterned into a shape having a predetermined opening by laser light irradiation. The metal substrate 100 has a size corresponding to the area of a plurality of semiconductor packages. The size of the metal substrate 100 is not particularly limited, but can be, for example, 500 mm square or 600 × 800 mm square. The resist film 102 formed on the metal substrate 100 has a predetermined pattern for each of a plurality of regions where a semiconductor device is formed.

次に、図２（Ｃ）に示すように、レジスト膜１０２をマスクとして、ニッケル、鉛、金またはこれらの合金などからなる電極パッド２５を電解メッキにより金属基板１００の上に形成する。   Next, as shown in FIG. 2C, an electrode pad 25 made of nickel, lead, gold, or an alloy thereof is formed on the metal substrate 100 by electrolytic plating using the resist film 102 as a mask.

次に、図３（Ａ）に示すように、レジスト膜１０２を除去した後、図３（Ｂ）に示すように、金属基板１００の上に層間絶縁膜２４を形成する。   Next, after removing the resist film 102 as shown in FIG. 3A, an interlayer insulating film 24 is formed on the metal substrate 100 as shown in FIG.

次に、図３（Ｃ）に示すように、層間絶縁膜２４の所定の領域をレーザー加工、ドリル加工などにより除去してビアホール１１２を形成する。各ビアホール１１２をレーザー加工により形成することで、ドリル加工の場合と比較して製造コストを低減させることができる。   Next, as shown in FIG. 3C, a predetermined region of the interlayer insulating film 24 is removed by laser processing, drilling, or the like to form a via hole 112. By forming each via hole 112 by laser processing, the manufacturing cost can be reduced as compared with the case of drilling.

次に、図４（Ａ）に示すように、層間絶縁膜２４の表面上、ビアホール１１２の側壁および底部に銅からなるシード層１２０を無電解メッキにより形成する。シード層１２０は、後述する銅の電解メッキ時において、銅が成長するための核となる。   Next, as shown in FIG. 4A, a seed layer 120 made of copper is formed on the surface of the interlayer insulating film 24 on the side walls and bottom of the via hole 112 by electroless plating. The seed layer 120 serves as a nucleus for copper growth during copper electroplating, which will be described later.

次に、図４（Ｂ）に示すように、シード層１２０の上に、レジスト膜１２２を塗布し、レーザー光の照射により所定の開口を有する形状にパターニングする。   Next, as shown in FIG. 4B, a resist film 122 is applied on the seed layer 120 and patterned into a shape having a predetermined opening by irradiation with laser light.

次に、図４（Ｃ）に示すように、レジスト膜１２２をマスクとして、ビアホール１１２に電解メッキにより銅を埋め込んでビアプラグ２６を形成するとともに、層間絶縁膜２４の上に配線層２２を形成する。ビアプラグ２６により、異なる層間の配線層２２が電気的に接続される。   Next, as shown in FIG. 4C, using the resist film 122 as a mask, the via hole 112 is filled with copper by electrolytic plating to form the via plug 26 and the wiring layer 22 is formed on the interlayer insulating film 24. . By the via plug 26, the wiring layers 22 between different layers are electrically connected.

次に、図４（Ｄ）に示すように、レジスト膜１２２を除去した後、エッチングによりレジスト膜１２２の下に存在するシード層１２０を除去するとともに、配線層２２の最表面を除去することにより配線層２２の表面を浄化する。   Next, as shown in FIG. 4D, after removing the resist film 122, the seed layer 120 existing under the resist film 122 is removed by etching, and the outermost surface of the wiring layer 22 is removed. The surface of the wiring layer 22 is purified.

以上説明した図２から図４に示すプロセスを繰り返すことにより、図５（Ａ）に示すような多層配線２０を金属基板１００の上に構築することができる。多層配線２０は、複数の領域において、それぞれ半導体チップを搭載可能な多層配線層を有する。たとえば、層間絶縁膜が６層の構成の場合には、多層配線２０の厚さを３００μｍ程度まで薄型化することができる。続いて、図５（Ｂ）に示すように、レジスト膜（図示せず）をマスクとして、最表面の配線層２２が露出するように、ソルダーレジスト膜２８を層間絶縁膜２４の上に形成する。さらに、配線層２２の上にボールランド部２９を形成する。   The multilayer wiring 20 as shown in FIG. 5A can be constructed on the metal substrate 100 by repeating the processes shown in FIGS. 2 to 4 described above. The multilayer wiring 20 has a multilayer wiring layer in which a semiconductor chip can be mounted in each of a plurality of regions. For example, when the interlayer insulating film has a six-layer structure, the thickness of the multilayer wiring 20 can be reduced to about 300 μm. Subsequently, as shown in FIG. 5B, using a resist film (not shown) as a mask, a solder resist film 28 is formed on the interlayer insulating film 24 so that the outermost wiring layer 22 is exposed. . Further, a ball land portion 29 is formed on the wiring layer 22.

次に、図５（Ｃ）に示すように、各ボールランド部２９にプリント印刷などによりはんだボール５０を接合する。   Next, as shown in FIG. 5C, solder balls 50 are joined to each ball land portion 29 by printing or the like.

次に、図６（Ａ）に示すように、半導体チップを搭載可能な各領域ごとに、金属基板１００の表面にレジスト１５０を形成する。レジスト１５０のパターンは、特に限定されないが、半導体チップを搭載可能な各領域の周縁部分に沿って設けられていることが好ましい。   Next, as shown in FIG. 6A, a resist 150 is formed on the surface of the metal substrate 100 in each region where a semiconductor chip can be mounted. The pattern of the resist 150 is not particularly limited, but is preferably provided along the peripheral portion of each region where a semiconductor chip can be mounted.

次に、図６（Ｂ）に示すように、金属基板１００をエッチングにより選択的に除去し、電極パッド２５および層間絶縁膜２４を露出させる。これにより、金属基板１００の一部がスティフナー１６０として残存する。さらに、フリップチップ実装用のＣ４バンプ２７を電極パッド２５の上にはんだ付けした後、Ｃ４バンプ２７をプレス加工などにより平坦化する。なお、Ｃ４バンプ２７の間に耐熱性に優れた樹脂材料からなるソルダーレジスト（図示せず）を塗布してもよい。ソルダーレジストにより、半導体基板１１にはんだ付けを行う際に、必要な箇所以外にはんだが付着しないように最上層の層間絶縁膜２４を保護することができる。   Next, as shown in FIG. 6B, the metal substrate 100 is selectively removed by etching to expose the electrode pads 25 and the interlayer insulating film 24. Thereby, a part of the metal substrate 100 remains as the stiffener 160. Further, after soldering the C4 bumps 27 for flip chip mounting onto the electrode pads 25, the C4 bumps 27 are flattened by pressing or the like. Note that a solder resist (not shown) made of a resin material having excellent heat resistance may be applied between the C4 bumps 27. With the solder resist, when soldering to the semiconductor substrate 11, the uppermost interlayer insulating film 24 can be protected so that solder does not adhere to other than necessary portions.

次に、図６（Ｃ）に示すように、半導体チップを搭載可能な各領域をダイシング加工により個片化し、半導体基板１１を作製する。   Next, as shown in FIG. 6C, each region where the semiconductor chip can be mounted is separated into pieces by dicing, and the semiconductor substrate 11 is manufactured.

以上の工程により、コアレス基板を形成するためのベースとなる金属基板の一部がスティフナーとして使用されている半導体基板１１が製造される。半導体基板１１は、製造過程で土台あるいは支持基材として使用された金属基板の一部がスティフナーとして用いられているため、スティフナー用の部材を必要としないとともに、スティフナーを貼り付ける工程を削除できるため、半導体基板の製造コストを低減することができる。また、半導体基板１１は、スティフナーにより剛性が付与されているため、個片化後のハンドリングが容易になるとともに、損傷の発生を抑制することができる。   Through the above steps, the semiconductor substrate 11 is manufactured in which a part of the metal substrate serving as a base for forming the coreless substrate is used as a stiffener. Since part of the metal substrate used as the base or support base material in the manufacturing process is used as the stiffener, the semiconductor substrate 11 does not require a stiffener member and can eliminate the step of attaching the stiffener. The manufacturing cost of the semiconductor substrate can be reduced. In addition, since the semiconductor substrate 11 is provided with rigidity by a stiffener, it is easy to handle after singulation, and the occurrence of damage can be suppressed.

図７は、前述の半導体基板１１を用いて半導体チップ３０をパッケージ化した半導体装置１０を示す図である。図７では、半導体基板１１の構造が簡略化されている。半導体チップ３０は、外部電極端子が設けられた表面をフェイスダウンにした状態で、半導体基板１１にフリップチップ実装されている。より具体的には、半導体チップ３０の外部電極端子に設けられた各はんだバンプ３２とそれらに対応する半導体基板１１の上面のＣ４バンプ２７とがはんだ付けされている。半導体チップ３０と半導体基板１１との隙間には、アンダーフィル７０が充填されている。半導体チップ３０と半導体基板１１との間にアンダーフィル７０を設けることにより、温度サイクル時の熱膨張による半導体基板１１と半導体チップ３０との間のギャップ変動によってＣ４バンプ２７が受けるストレスを抑制することができる。さらに、半導体基板１１には、封止樹脂層４０が成型され、半導体基板１１および半導体チップ３０の保護が図られている。   FIG. 7 is a diagram showing a semiconductor device 10 in which a semiconductor chip 30 is packaged using the semiconductor substrate 11 described above. In FIG. 7, the structure of the semiconductor substrate 11 is simplified. The semiconductor chip 30 is flip-chip mounted on the semiconductor substrate 11 with the surface on which the external electrode terminals are provided facing down. More specifically, the solder bumps 32 provided on the external electrode terminals of the semiconductor chip 30 and the corresponding C4 bumps 27 on the upper surface of the semiconductor substrate 11 are soldered. An underfill 70 is filled in a gap between the semiconductor chip 30 and the semiconductor substrate 11. By providing the underfill 70 between the semiconductor chip 30 and the semiconductor substrate 11, it is possible to suppress the stress that the C4 bump 27 receives due to the gap fluctuation between the semiconductor substrate 11 and the semiconductor chip 30 due to thermal expansion during the temperature cycle. Can do. Further, a sealing resin layer 40 is molded on the semiconductor substrate 11 to protect the semiconductor substrate 11 and the semiconductor chip 30.

一方、半導体基板１１の下面には、各ボールランド部２９（図１等参照）上にはんだボール５０が接合され、ボールランド部２９がアレイ状に配設されている。はんだボール５０の間には耐熱性に優れた樹脂材料からなるソルダーレジスト膜２８が塗布されている。ソルダーレジスト膜２８により、半導体基板１１にはんだ付けを行う際に、必要な箇所以外にはんだが付着しないように最下層の層間絶縁膜２４（図１等参照）が保護される。   On the other hand, on the lower surface of the semiconductor substrate 11, solder balls 50 are joined on each ball land portion 29 (see FIG. 1 and the like), and the ball land portions 29 are arranged in an array. A solder resist film 28 made of a resin material having excellent heat resistance is applied between the solder balls 50. The solder resist film 28 protects the lowermost interlayer insulating film 24 (see FIG. 1 and the like) so that solder does not adhere to areas other than necessary when soldering to the semiconductor substrate 11.

はんだボール５０を取り囲むように、スティフナー１６０が形成されている。本実施の形態の半導体装置１０は、スティフナー１６０により剛性が付与されているため、半導体装置のハンドリングが容易になるとともに、半導体装置における損傷の発生を抑制することができる。スティフナー１６０は、多層配線構造を構築する際の土台となる金属基板の一部を利用して形成されている。これにより、半導体装置１０の部品点数の削減および製造コストの低減を図ることができる。   A stiffener 160 is formed so as to surround the solder ball 50. Since the semiconductor device 10 of the present embodiment is given rigidity by the stiffener 160, the semiconductor device can be easily handled and the occurrence of damage in the semiconductor device can be suppressed. The stiffener 160 is formed by using a part of a metal substrate that serves as a foundation for constructing a multilayer wiring structure. Thereby, the number of parts of the semiconductor device 10 can be reduced and the manufacturing cost can be reduced.

上述の実施の形態では、半導体基板にスティフナーを形成し、個片化した後、半導体チップを実装する方法が例示されているが、図６（Ｂ）に示した工程の後、各半導体チップ搭載領域に、それぞれ半導体チップを実装し、さらにトランスファーモールド法を用いて封止樹脂層でパッケージ化した後、図６（Ｃ）と同様に、個片化してもよい。   In the above-described embodiment, a method of mounting a semiconductor chip after forming a stiffener on a semiconductor substrate and separating it into individual pieces is illustrated. However, after the step shown in FIG. Each of the regions may be mounted with a semiconductor chip and further packaged with a sealing resin layer using a transfer molding method, and then separated into individual pieces as in FIG. 6C.

上述した実施の形態では、半導体チップ３０をリフローにより半導体基板１１にフリップチップ実装しているが、以下に説明する手法により半導体チップ３０をフリップチップ実装してもよい。   In the above-described embodiment, the semiconductor chip 30 is flip-chip mounted on the semiconductor substrate 11 by reflow. However, the semiconductor chip 30 may be flip-chip mounted by the method described below.

まず、図８（Ａ）に示すように、Ｃ４バンプ２７（図５（Ｂ）参照）に代えて、はんだ入り導電性ペースト２００を半導体基板１１の上面に塗布する。ここで、はんだ入り導電性ペースト２００は、エポキシなどの絶縁樹脂とはんだとが混練されたペーストである。   First, as shown in FIG. 8A, instead of the C4 bump 27 (see FIG. 5B), a soldered conductive paste 200 is applied to the upper surface of the semiconductor substrate 11. Here, the soldered conductive paste 200 is a paste in which an insulating resin such as epoxy and solder are kneaded.

次に、図８（Ｂ）に示すように、半導体基板１１の各領域に半導体チップ３０を搭載した後、はんだが溶融する温度にて加熱処理を行う。加熱処理により、図８（Ｃ）に示すように、電極パッド２５とはんだバンプ３２とが導電性ペースト２００に含まれていたはんだ２１０によって接合される。はんだ２１０による接合部分は、導電性ペースト２００に含まれていた絶縁樹脂２１２によって被覆される。   Next, as shown in FIG. 8B, after the semiconductor chip 30 is mounted in each region of the semiconductor substrate 11, heat treatment is performed at a temperature at which the solder melts. By the heat treatment, as shown in FIG. 8C, the electrode pad 25 and the solder bump 32 are joined by the solder 210 included in the conductive paste 200. A joint portion by the solder 210 is covered with an insulating resin 212 included in the conductive paste 200.

これによれば、はんだ２１０による接合部分が絶縁樹脂２１２によって保護される。このため、組み立て時のハンドリング、熱、洗浄水圧などによりはんだ２１０による接合部分が破壊もしくはストレスが発生することが抑制される。この結果、多層配線基板をより薄型化、狭ピッチ化することができる。   According to this, the joint portion by the solder 210 is protected by the insulating resin 212. For this reason, it is suppressed that the joint part by the solder 210 is broken or stressed due to handling during assembly, heat, washing water pressure, and the like. As a result, the multilayer wiring board can be made thinner and narrower.

本発明は、上述の各実施の形態に限定されるものではなく、当業者の知識に基づいて各種の設計変更等の変形を加えることも可能であり、そのような変形が加えられた実施の形態も本発明の範囲に含まれうるものである。   The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention.

たとえば、上述の実施の形態では、半導体チップがフリップチップ実装されているが、半導体チップは多層配線基板上にワイヤボンディングされていてもよい。   For example, in the above-described embodiment, the semiconductor chip is flip-chip mounted, but the semiconductor chip may be wire-bonded on the multilayer wiring board.

１０ 半導体装置、１１ 半導体基板、２４ 層間絶縁膜、２５ 電極パッド、２６ ビアプラグ、２７ Ｃ４バンプ、１００ 金属基板、１６０ スティフナー   DESCRIPTION OF SYMBOLS 10 Semiconductor device, 11 Semiconductor substrate, 24 Interlayer insulation film, 25 Electrode pad, 26 Via plug, 27 C4 bump, 100 Metal substrate, 160 Stiffener

Claims (2)

電極パッドが上面に設けられた配線基板を用意する工程と、
前記電極パッドを被覆するように、前記配線基板の上面にはんだと絶縁樹脂とが混練された導電性ペーストを塗布する工程と、
前記電極パッドに対応する外部電極端子が設けられた半導体チップをフェイスダウンした状態で、前記外部電極端子に対応するして設けられた、はんだバンプを介して前記導電性ペーストの上に搭載する工程と、
前記はんだが溶融する温度で加熱を行い、前記電極パッドと前記はんだバンプとを前記導電性ペーストに含まれるはんだで接合する工程と、
を備え、
前記導電性ペーストに含まれる絶縁樹脂で、前記電極パッドと前記はんだバンプとを接合するはんだを被覆させることを特徴とする半導体装置の製造方法。 Preparing a wiring board provided with electrode pads on the upper surface;
Applying a conductive paste in which solder and insulating resin are kneaded on the upper surface of the wiring board so as to cover the electrode pads;
A step of mounting the semiconductor chip provided with the external electrode terminals corresponding to the electrode pads on the conductive paste via the solder bumps provided corresponding to the external electrode terminals in a face-down state. When,
Heating at a temperature at which the solder melts, and joining the electrode pads and the solder bumps with solder contained in the conductive paste;
With
A method of manufacturing a semiconductor device, wherein an insulating resin contained in the conductive paste is coated with a solder that joins the electrode pad and the solder bump. 前記配線基板を用意する工程は、
少なくとも１層の層間絶縁膜によって相互に接続された多層配線層を金属基板の上の所定領域に構築する工程と、
前記所定領域の周縁部分に前記金属基板が残るように前記金属基板を選択的に除去して、各領域にスティフナーを形成するとともに、各スティフナーで囲まれた部分において前記多層配線層と電気的に接続された電極パッドを露出させる工程と、
を含む請求項１に記載の半導体装置の製造方法。 The step of preparing the wiring board includes:
Building a multilayer wiring layer interconnected by at least one interlayer insulating film in a predetermined region on the metal substrate;
The metal substrate is selectively removed so that the metal substrate remains in the peripheral portion of the predetermined region, and stiffeners are formed in each region, and electrically connected to the multilayer wiring layer in a portion surrounded by each stiffener. Exposing the connected electrode pads; and
The manufacturing method of the semiconductor device of Claim 1 containing this.
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