JP7347440B2 - Manufacturing method of wiring board for semiconductor package - Google Patents

Description

The present invention relates to a method of manufacturing a wiring board for a semiconductor package.

In recent years, as semiconductor devices have become faster and more highly integrated, the pitch of connection terminals on semiconductor chips has become narrower, and in response there has been a demand for narrower pitches of connection terminals on wiring boards and miniaturization of wiring. ing. On the other hand, a wiring board for FCBGA (Flip Chip Ball Grid Array) and a motherboard are required to be connected at pitches that are almost the same as in the past. Therefore, in order to connect the FCBGA wiring board and the semiconductor chip, it is necessary to overcome the problem that the dimensions of the terminal electrodes and the pitch of the connection terminals are different from each other.

In order to overcome this problem, interposers have come to be used as thin wiring boards between FCBGA wiring boards and semiconductor chips to change the dimensions of terminal electrodes and the pitch of connection terminals.

However, with the progress of miniaturization on the semiconductor chip side, when manufacturing interposers simply using the same manufacturing technology as FCBGA wiring boards, as the miniaturization (narrowing pitch) of connection terminals is promoted, There was a problem in that the manufacturing yield was lowered due to the corresponding construction of the interposer.

To solve this problem, for example, Patent Document 1 discloses a technique in which wiring is formed on a substrate using silicon to form a wiring substrate (silicon interposer) for connecting semiconductor chips. On the other hand, for example, Patent Document 2 discloses a technique of forming fine wiring after flattening the surface of an FCBGA by CMP (Chemical Mechanical Polishing) or the like without using a silicon interposer.

Here, the silicon interposer is manufactured using a silicon wafer that is manufactured using equipment for semiconductor pre-processing, so it is expensive. In addition, silicon wafers are limited in shape and size, and the number of interposers that can be produced from one wafer is relatively small. A combination of these factors has led to the problem that silicon interposers are relatively expensive. Furthermore, since silicon wafers are not insulators but semiconductors, there is also the problem that transmission characteristics deteriorate.

On the other hand, according to the manufacturing process of flattening the FCBGA wiring board and directly forming fine wiring thereon, as shown in Patent Document 2, there is a problem of deterioration of transmission characteristics as in the case of using a silicon interposer. does not occur. However, this manufacturing process adds a CMP polishing process, etc., which increases the number of manufacturing defects of the FCBGA wiring board itself, as well as manufacturing defects due to the highly difficult formation of fine wiring layers, which further reduces the manufacturing yield. The problem was that it was getting worse. Furthermore, if the FCBGA wiring board is warped or distorted, there is also the problem that mounting of semiconductor chips is hindered.

International Publication No. 2016/052221 JP2014-225671A

Focusing on the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a wiring board for a semiconductor package, which can suppress a decrease in the yield of semiconductor packages and also enable good mounting of semiconductor chips. do.

In order to solve the above problems, a method for manufacturing a wiring board for a semiconductor package according to the present invention includes a first wiring board on which a semiconductor chip is mounted, and an insulated a second wiring board made of a build-up layer formed with a resin layer and a wiring layer, wherein the first wiring board and the second wiring board have protruding electrodes on pad electrodes provided on their surfaces. The wiring board for a semiconductor package is provided with an underfill between the first wiring board and the second wiring board, the thickness of the second wiring board being The width is 10 μm to 100 μm, copper posts are provided on the surface of the second wiring board on which the semiconductor chip is mounted, the first wiring board is an FCBGA wiring board, and the second wiring board is an interposer. A method for manufacturing a wiring board for a semiconductor package, comprising:
The method includes a step of manufacturing the interposer, and a step of connecting the interposer to the FCBGA wiring board,
The manufacturing process of the interposer is as follows:
forming a release layer and an intermediate layer made of a photosensitive resin on the surface of a carrier substrate made of glass as a support;
a step of patterning the intermediate layer by a photolithography process;
After forming a seed layer consisting of an insecure adhesive layer and a conductive layer laminated in this order on the surface of the patterned intermediate layer and exposed release layer, electrolytic copper plating is formed on the seed layer to a thickness equal to or greater than that of the intermediate layer. The process of
A step of forming an intermediate layer of the same height as the copper post by cutting the electrolytic copper plating and the intermediate layer so as to leave the electrolytic copper plating with the same thickness as the intermediate layer;
Form an insulating resin pattern with an opening above the copper post or conductive via, form a trench that will serve as a wiring pattern at the top of the insulating resin pattern, and apply an insulating adhesive layer over the copper post or conductive via and the insulating resin pattern. After forming a conductive layer, electrolytic copper plating is applied thicker than the insulating resin pattern, and by cutting the electrolytic copper plating so that the top of the insulating resin pattern is exposed, electrolytic copper is applied to the trench on the top of the insulating resin pattern. a wiring creation step of forming a conductive via on a wiring pattern filled with copper plating and a copper post or conductive via;
repeating the wiring creation step according to the required number of layers of the wiring pattern to form a multilayer wiring layer with pad electrodes exposed on the top layer;
After forming a photosensitive insulating resin layer on the top layer of the multilayer wiring layer, using a photolithography process to form an insulating resin pattern having an opening for forming a conductive via on the pad electrode;
forming a pad surface treatment layer on the pad electrode;
forming a protruding electrode on the pad surface treatment layer,
The step of connecting the interposer to the FCBGA wiring board includes:
After aligning the FCBGA wiring board and the interposer attached with the carrier board, performing flip-chip mounting;
A step of making the carrier substrate peelable by irradiating the peeling layer with laser light from the carrier substrate side of the interposer;
a step of peeling and removing the carrier substrate from the interposer;
removing the intermediate layer exposed by peeling off the carrier substrate;
The present invention is characterized by comprising a step of removing the non-containing adhesive layer and the conductive layer on the surface of the copper post exposed by removing the intermediate layer to expose the copper post.
Further, the method for manufacturing a wiring board for a semiconductor package of the present invention includes a first wiring board on which a semiconductor chip is mounted, an insulating resin layer and a wiring layer disposed on the surface of the first wiring board on which the semiconductor chip is mounted. a second wiring board made of a formed buildup layer, the first wiring board and the second wiring board are electrically connected via protruding electrodes on pad electrodes provided on the surfaces thereof. A wiring board for a semiconductor package, wherein an underfill is provided between the first wiring board and the second wiring board,
The thickness of the second wiring board is 10 μm to 100 μm,
A copper post is provided on the surface of the second wiring board on which a semiconductor chip is mounted, the first wiring board is a wiring board for FCBGA, and the second wiring board is a wiring board for a semiconductor package, which is an interposer. A manufacturing method,
The method includes a step of manufacturing the interposer, and a step of connecting the interposer to the FCBGA wiring board,
The manufacturing process of the interposer is as follows:
A release layer, a first intermediate layer made of a photosensitive resin, and a seed layer in which an insecure adhesive layer and a conductive layer are laminated in this order are formed in this order on the surface of a carrier substrate made of glass as a support. process and
After forming a second intermediate layer made of a photosensitive resin on the seed layer, patterning the second intermediate layer by a photolithography process;
A process of electrolytic copper plating using the patterned second intermediate layer as a plating mask,
A process of forming an intermediate layer of the same height as the copper post by cutting the electrolytic copper plating and the intermediate layer so as to leave a preset thickness of the electrolytic copper plating;
Form an insulating resin pattern with the upper part of the copper post or conductive via as an opening, form a trench that will serve as a wiring pattern at the top of the insulating resin pattern, and apply an insulating adhesive layer over the copper post or conductive via and the insulating resin pattern. After forming a conductive layer, electrolytic copper plating is applied thicker than the insulating resin pattern, and by cutting the electrolytic copper plating so that the top of the insulating resin pattern is exposed, electrolytic copper is applied to the trench on the top of the insulating resin pattern. a wiring creation step of forming a conductive via on a wiring pattern filled with copper plating and a copper post or conductive via;
repeating the wiring creation step according to the number of required wiring layers to form a multilayer wiring layer with pad electrodes exposed on the top layer;
After forming a photosensitive insulating resin layer on the top layer of the multilayer wiring layer, using a photolithography process to form an insulating resin pattern having an opening for forming a conductive via on the pad electrode;
forming a pad surface treatment layer on the pad electrode;
forming a protruding electrode on the pad surface treatment layer,
The step of connecting the interposer to the FCBGA wiring board includes:
After aligning the FCBGA wiring board and the interposer attached with the carrier board, performing flip-chip mounting;
A step of making the carrier substrate peelable by irradiating the peeling layer with laser light from the carrier substrate side of the interposer;
a step of peeling and removing the carrier substrate from the interposer;
removing the intermediate layer exposed by peeling off the carrier substrate;
The present invention is characterized by comprising a step of removing the non-containing adhesive layer and the conductive layer on the surface of the copper post exposed by removing the intermediate layer to expose the copper post.

According to the present invention, it is possible to provide a method for manufacturing a wiring board for a semiconductor package, which suppresses a decrease in the yield of semiconductor packages and allows a semiconductor chip to be mounted satisfactorily.

FIG. 1 is a cross-sectional view showing an example of a semiconductor chip mounted on an FCBGA wiring board according to an embodiment of the present invention. FIG. 2A is a sectional view showing an example of a second wiring board including a carrier board according to an embodiment of the present invention, and shows an overall image. FIG. 2B is a partially enlarged view showing an example of a second wiring board including a carrier board according to an embodiment of the present invention. FIG. 3A is a cross-sectional view showing an example of a manufacturing process of transferring and bonding a second wiring board to an FCBGA wiring board according to an embodiment of the present invention. FIG. 3B is a cross-sectional view showing an example of a manufacturing process of transferring and bonding the second wiring board to the FCBGA wiring board according to the embodiment of the present invention. FIG. 3C is a cross-sectional view showing an example of a manufacturing process of transferring and bonding the second wiring board to the FCBGA wiring board according to an embodiment of the present invention. FIG. 3D is a cross-sectional view showing an example of a manufacturing process of transferring and bonding the second wiring board to the FCBGA wiring board according to an embodiment of the present invention. FIG. 3E is a cross-sectional view showing an example of a manufacturing process of transferring and bonding the second wiring board to the FCBGA wiring board according to an embodiment of the present invention. FIG. 4A is a cross-sectional view showing an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4B is a cross-sectional view showing an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4C is a cross-sectional view illustrating an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4D is a cross-sectional view showing an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4E is a cross-sectional view showing an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4F is a cross-sectional view showing an example of the manufacturing process of the second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4G is a cross-sectional view illustrating an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4H is a cross-sectional view illustrating an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4I is a cross-sectional view showing an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 4J is a cross-sectional view showing an example of a manufacturing process of a second wiring board with solder bumps according to an embodiment of the present invention. FIG. 5A is a cross-sectional view showing an example of a manufacturing process of a second wiring board according to an embodiment of the present invention. FIG. 5B is a cross-sectional view showing an example of a manufacturing process of the second wiring board according to an embodiment of the present invention. FIG. 5C is a cross-sectional view showing an example of a manufacturing process of the second wiring board according to an embodiment of the present invention. FIG. 5D is a cross-sectional view showing an example of the manufacturing process of the second wiring board according to an embodiment of the present invention. FIG. 5E is a cross-sectional view showing an example of the manufacturing process of the second wiring board according to an embodiment of the present invention. FIG. 5F is a cross-sectional view showing an example of the manufacturing process of the second wiring board according to an embodiment of the present invention. FIG. 6A is a cross-sectional view showing an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 6B is a cross-sectional view showing an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 6C is a cross-sectional view illustrating an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 6D is a cross-sectional view showing an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 6E is a cross-sectional view showing an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 6F is a cross-sectional view illustrating an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 6G is a cross-sectional view showing an example of a manufacturing process of a second wiring board with a fine pattern according to an embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining the shape of the copper post. FIG. 8 is a cross-sectional view showing an example of the connection between a semiconductor chip and a copper post.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A wiring board according to an embodiment of the present invention will be described below with reference to the drawings. However, in each figure described below, mutually corresponding parts are given the same reference numerals, and explanations of overlapping parts are omitted as appropriate. Further, each drawing may be appropriately exaggerated in order to facilitate explanation.

Furthermore, the embodiments of the present invention illustrate configurations for embodying the technical idea of the present invention, and do not specify the material, shape, structure, arrangement, and dimensions of each part. The technical idea of the present invention can be modified in various ways within the technical scope defined by the claims.

Note that in the embodiment described below, the FCBGA wiring board is also referred to as a first wiring board. Further, the second wiring board is a buildup multilayer wiring layer (also referred to as a buildup layer or a multilayer wiring layer) formed on a carrier substrate that is a support. The built-up multilayer wiring layer is used as an interposer. Since it is a thin multilayer wiring layer with a thickness of 10 μm or more and 100 μm or less (preferably 20 μm or more and 50 μm or less), a carrier substrate is essential as a support to enable handling. After the interposer formed on the carrier substrate is flip-chip mounted on the first wiring board, the carrier board is peeled off and removed, so that it does not ultimately remain on the semiconductor package wiring board.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view showing an example of a semiconductor package in which a semiconductor chip is mounted on a wiring board according to the present embodiment.

<Semiconductor package using FCBGA wiring board>
In the semiconductor package according to this embodiment, an interposer 25 is bonded to one surface of an FCBGA wiring board 1 (also referred to as a first wiring board) via solder bumps 24. A copper post (Cu pillar) or a gold bump 31 may be used instead of the solder bump 24. Further, after the semiconductor chip 4 is flip-chip mounted on the interposer 25, the underfill 2 is inserted between the semiconductor chip 4 and the interposer 25 to form a semiconductor package 30. Here, the FCBGA wiring board 1 and the interposer 25 before the semiconductor chip 4 is mounted constitute a semiconductor package wiring board. The interposer 25 includes a second wiring board 3 having a thin multilayer wiring layer including a fine wiring layer formed only of a build-up wiring layer formed by laminating resin and wiring.

7 is a cross-sectional view illustrating the copper post 14 formed on the mounting surface of the multilayer wiring layer 25a of the second wiring board 3 with the semiconductor chip, and FIG. 8 is a cross-sectional view illustrating the copper post 14 (see FIG. 7) and the semiconductor chip. 3 is a cross-sectional view illustrating a state in which a pad portion of a chip 4 is bonded to a pad portion of the chip 4 by a solder bump 33. FIG.

The gap formed when the interposer 25 (multilayer wiring layer 25a of the second wiring board 3) is mounted on the FCBGA wiring board (first wiring board) 1 is filled with an underfill (resin) 2 as an insulating resin member. It is solidified. Furthermore, on the opposite side of the interposer 25 from the FCBGA wiring board 1 (see FIG. 1), the pad portion of the semiconductor chip 4 and the copper post 14 of the second wiring board are connected to solder bumps 33 (or gold bumps), etc. They are joined by a joining means, and the gap between the semiconductor chip 4 and the interposer 25 is filled with the underfill 2. It is preferable that the copper post 14 protrudes from the surface on which it is formed by 5 to 25 μm, more preferably 10 to 20 μm, and its shape is not limited to a columnar shape but may be a film shape or a dome shape. Further, the pitch of the copper posts 14 is preferably 40 to 55 μm in accordance with the pitch of the pad portions of the semiconductor chip 4.

(Underfill)
The underfill 2 is an adhesive used for fixing and sealing the FCBGA wiring board 1 and the interposer 25. As the underfill 2, for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins, and silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used. The underfill 2 may be formed by filling with liquid resin. In addition, instead of the underfill 2, by using an anisotropic conductive film (ACF) or a film-like connecting material (NCF) that has both adhesion and insulation functions as an insulating adhesive member, it is possible to connect the FCBGA wiring board 1 and the interposer. 25 may be fixed and the space between them may be sealed.

Further, the underfill 32 (FIG. 8) is an adhesive used to fix and seal the semiconductor chip 4 and the interposer 25, and is made of the same material as the underfill 2. Note that in this case as well, an anisotropic conductive film (ACF) or a film-like connecting material (NCF) may be used instead of the underfill 32.

The wiring pitch of the electrode portion of the interposer 25 that is bonded to the semiconductor chip 4 (in this case, the pitch of the copper posts 14) is the electrode pitch of the FCBGA wiring board 1 when the semiconductor chip 4 and the FCBGA wiring board 1 are directly bonded. It is narrower than the wiring pitch of the portion (here, the pitch of the solder bumps 24). That is, the side of the interposer 25 on which the semiconductor chip 4 is mounted has finer wiring than the FCBGA wiring board 1 when bonded to the semiconductor chip 4.

For example, in order to comply with the current high band memory (HBM) specifications, the wiring width in the second wiring board 3 needs to be 2 μm or more and 6 μm or less. In order to adjust the characteristic impedance to 50Ω, when the wiring width is 2 μm and the wiring height is 2 μm, the insulation film thickness between the wires is 2.5 μm. The thickness of one layer including wiring is 4.5 μm, and when a 5-layer second wiring board 3 is manufactured with this thickness, the second wiring board 3 becomes an extremely thin interposer with a total thickness of about 25 μm. .

(Relationship between the second wiring board 3 and the multilayer wiring layer 25a of the second wiring board)
FIG. 2A is a cross-sectional view showing an example of a second wiring board including a carrier board according to an embodiment of the present invention. FIG. 2B is an enlarged view of a portion including the solder bumps 24 in FIG. 2A. As shown in FIGS. 2A and 2B, the second wiring board 3 is first mounted on a carrier substrate 5 made of a material such as a glass substrate that is thin and has good flatness and has a coefficient of thermal expansion close to that of a silicon wafer. A peeling layer 6 is formed, and a multilayer wiring layer 25a is formed on the peeling layer 6. A conductive via 17 is exposed at the bottom of an opening formed in the outermost insulating resin layer 21a (see FIG. 4I) on the opposite side of the carrier substrate 5 of the second wiring board 3, and the surface thereof is the pad surface. A processing layer 23 is formed. This makes it possible to form solder bumps 24. Gold bumps or copper bumps can also be used instead of solder bumps 24.

(Second wiring board)
An example of a manufacturing process for transferring and bonding the second wiring board to the FCBGA wiring board will be described with reference to FIGS. 3A to 3E.
As shown in FIG. 3A, the multilayer wiring layer 25a of the second wiring board 3 provided with the solder bumps 24 formed on the carrier board 5 is placed in a position where flip-chip mounting is possible on the separately manufactured wiring board 1 for FCBGA. Deploy. Then, as shown in FIG. 3B, after flip-chip mounting, a resin such as an underfill 2 is filled and hardened between the FCBGA wiring board 1 and the multilayer wiring layer 25a of the second wiring board 3. Thereafter, as shown in FIG. 3C, the peeling layer 6 is decomposed by irradiation with laser light L, and as shown in FIG. 3D, the carrier substrate 5 is peeled and removed from the multilayer wiring layer 25a of the second wiring board 3.

Further, the intermediate layer 8 and the seed layer 11 formed for wiring formation and for providing adhesion between the intermediate layer 8 and the insulating resin are removed from the multilayer wiring layer 25a of the second wiring board 3, as shown in FIG. 3E. Then, the copper posts 14 for connection with the semiconductor chip 4 formed on the second wiring board 3 are exposed. As a result, the semiconductor package wiring board 100 according to this embodiment is formed.

By joining the multilayer wiring layer 25a of the second wiring board 3 with a thickness of 100 μm or less to the FCBGA wiring board 1 in the above procedure, the multilayer wiring layer 25a of the thin second wiring board 3 with a thickness of 100 μm or less can be bonded to the FCBGA wiring board 1. It can be flatly bonded to the wiring board 1 for use. In this way, by electrically connecting and transferring only the multilayer wiring layer 25a of the second wiring board 3 to the FCBGA wiring board 1, which is the first wiring board, the semiconductor package wiring board 100 (FIG. 3E) ) can be obtained. By mounting the semiconductor chip 4 on this semiconductor package wiring board 100, the semiconductor package 30 (FIG. 1) is completed.

Generally, FCBGA wiring boards have high rigidity, and if there is a difference in CTE (coefficient of thermal expansion) with the semiconductor chip, the bond is likely to break, but the stronger the bond, the harder the bond will break. .

In the semiconductor package wiring board 100 according to the present embodiment, the FCBGA wiring board 1 and the semiconductor chip 4 are indirectly bonded via a thin interposer 25. Therefore, CTE differences are less likely to affect each other, and high reliability can be ensured.

<Method for manufacturing wiring board 100 for semiconductor package>
Next, an example of the manufacturing process of the semiconductor package wiring board 100 including the second wiring board 3 according to the present embodiment will be described.

(carrier board)
As the carrier substrate 5, for example, a glass substrate can be used. Glass substrates have excellent smoothness, and low expansion glass has a CTE close to that of silicon wafers, making it possible to form fine patterns in the multilayer wiring layer 25a of the second wiring board 3 with pattern placement accuracy close to that of semiconductor chips. suitable for Furthermore, the carrier substrate 5 is effective in ensuring flatness when bonded to the FCBGA wiring board 1. When a glass substrate is used as the carrier substrate 5, the thickness of the glass substrate is preferably thicker from the viewpoint of suppressing the occurrence of warpage in the manufacturing process. It is about 10 times thicker and can suppress warping caused by the sum of stress in each insulating resin and wiring layer. On the other hand, if the thickness of the glass substrate is too thick, the total weight of the second wiring board 3 and carrier board 5 will increase, making it difficult to transport and cutting into pieces into processing sizes, so The following thicknesses are preferred: Further, the CTE of the glass is preferably about 3 to 9 ppm/°C.

(First manufacturing method of second wiring board)
The first method of manufacturing the second wiring board will be explained using FIGS. 4A to 4J.
First, a wiring board that will become the second wiring board 3 (see FIG. 1) is manufactured. As shown in FIG. 4A, a peeling layer 6 for peeling off the carrier substrate 5 in a later step is formed on one surface of the carrier substrate 5.
The peeling layer 6 is a material that is decomposed by infrared or ultraviolet laser to cause interlayer peeling, and for example, amorphous silicon, carbon-dispersed acrylic resin, or the like can be suitably used. Amorphous silicon can be decomposed by UV-YAG laser irradiation, and carbon-dispersed acrylic resin can be decomposed by infrared laser irradiation.

A photosensitive resist having a thermogravimetric change of 5% or less at 260° C. is coated on this peeling layer 6, and openings corresponding to copper posts and openings serving as alignment marks are formed in the photosensitive resist layer. Then, the intermediate layer 8 is formed (patterning of the intermediate layer by a photolithography process). Examples of materials for such photosensitive resists include negative-type acrylic resins, epoxy resins, and cyclized rubber resins.

Next, as shown in the enlarged view of FIG. 4B, on the intermediate layer 8, a non-containing adhesive layer 9a and a laminated film of a conductive layer 13a made of a low resistance material or a seed made of a single layer of the conductive layer 13a are formed by sputtering. Form layer 11. The intermediate layer 8 and the seed layer 11 constitute a removal layer that can be removed in a later process.

Next, as shown in FIGS. 4B and 4C, an electrolytic copper plating 10a is formed on the seed layer 11, and the electrolytic copper plating 10a deposited on the intermediate layer 8 is processed by CMP (Chemical Mechanical Polishing) or a grinder etc. to the cutting line. Remove by surface cutting means. Through the above steps, the copper post 14 for connection with the semiconductor chip can be formed as shown in FIG. 4D.

Next, as shown in the left diagram of FIG. 4E, an insulating resin 15 is formed on the intermediate layer 8 and the copper post 14. In this embodiment, the insulating resin 15 can be formed by a spin coating method using a photosensitive phenolic resin. In addition to forming by spin coating, the insulating resin 15 can also be formed by compressing and curing an insulating resin film using a vacuum laminator. In this case, the insulating resin 15 with good flatness can be formed. The photosensitive insulating resin is not limited to phenolic resins, and epoxy resins, acrylic resins, mixtures thereof, polyimide resins, and the like can be used. Further, either a positive resist or a negative resist can be used.

In addition, if the intermediate layer 8 and the insulating resin 15 have a high chemical bond and inhibit the releasability of the intermediate layer 8, a layer with high adhesion between both the intermediate layer 8 and the insulating resin 15 may be placed on the intermediate layer 8. A non-seal adhesive layer 9b is formed. The non-seal adhesive layer 9b formed here may be removed together with the intermediate layer 8 after being mounted as the second wiring board 3.

In this embodiment, a photosensitive phenolic resin is used as the insulating resin 15, and as shown in the right diagram of FIG. 4E, conductive vias 17 are formed by performing UV exposure 16 and then development. I can do it. Although a positive resist is used as an example in which the UV-exposed portion is removed by development, a negative resist may also be used. Further, when using a non-photosensitive insulating resin, the conductive via 17 may be formed by removing it by irradiating the portion where the conductive via 17 is to be formed with a laser beam. Note that the trench 12 for forming the fine pattern 7 to be described later can be produced by coating, exposing, and developing a photosensitive resist in this step (creation of an insulating resin pattern).

Next, after surface modification of the insulating resin 15 using UV plasma or oxygen plasma, as shown in FIG. 4F, Ti and Cu are successively sputtered to form the electrolytic copper plating 10b. A seed layer 18a is formed. A fine pattern 7 is formed on this seed layer 18a, but since the sputtered Cu used as the conductive layer has weak adhesion to the insulating resin 15, Ti is formed as an inadhesive layer with the underlying insulating resin 15. is common. The non-tight adhesion layer is not limited to Ti, and may be any material that has adhesion between the conductive layer and the insulating resin 15, such as TiW or ITO.

(Method for forming fine patterns)
The method for forming the fine pattern 7 is to form the trench 12 that will become the fine pattern 7 on the surface of the patterned insulating resin 15, fill the conductive via 17 and the trench 12 with electrolytic copper plating 10b, and then fill the insulating resin 15 with electrolytic copper plating 10b. The unnecessary copper plating 10b on the surface can be removed and formed by CMP or surface cutting means such as a grinder up to the cutting line (see FIGS. 4E to 4F).

Alternatively, as a method for forming the fine pattern 7, as shown in FIG. 6A, a seed layer 18 is first formed on the surfaces of the copper post 14 and the intermediate layer 8 in the state shown in FIG. 4D. Next, as shown in FIG. 6B, openings 19a corresponding to the fine pattern 7 and openings are formed using a removable photosensitive resist 19 on the seed layer 18, which is a laminated film of the insecure adhesive layer 9b and the conductive layer 13b. form 13.
Further, as shown in FIGS. 6C and 6D, electrolytic copper plating 10b is formed on the openings 19a and 13 by electrolytic copper plating, and as shown in FIG. 6E, the surface of the electrolytic copper plating 10b is subjected to CMP or a grinder. Cut the wire down to the cutting line using a surface cutting means such as the above to adjust the wiring thickness to the desired thickness. Thereafter, the photosensitive resist 19 is removed. Furthermore, as shown in FIG. 6F, by removing the conductive layer 13b as the seed layer 18 and the non-containing adhesive layer 9b (see FIG. 6B) by wet etching or dry etching using a reactive gas, electrical connection with the copper post 14 is established. A connected fine pattern 7 can be formed. In this embodiment, the fine pattern 7 refers to a pattern in which lines are 5 μm or less and spaces are 5 μm or less in L (line)/S (space).

The seed layer 18 is formed to have a film thickness of 1 μm or less, preferably 0.3 μm or less, in order to suppress thinning of fine pattern wiring due to side etching when removing by etching, for example, when L/S is required to be 2 μm/2 μm. It's good to do that.
As the method for forming the fine pattern 7, any of the above methods may be used.

The steps shown in FIGS. 4E to 4F are used as wiring layer forming steps (wiring creation steps), and the steps of forming wiring layers shown in FIGS. It is possible to obtain the multilayer wiring layer 25a (see FIG. 2A) of the second wiring board 3, which is composed of a build-up layer with a number of layers and a fine pattern 7. According to this embodiment, since the wiring layers of the build-up layer are sequentially formed on the carrier substrate 5, one wiring layer in the multilayer wiring layer 25a is close to the FCBGA wiring board 1 to be combined, due to the manufacturing process. As the diameter increases, the cross-sectional shape becomes larger; for example, the conductive via has a tapered shape.

Next, as shown in FIG. 4G, an insulating resin layer 21 is formed as the outermost surface of the second wiring board 3 on the FCBGA wiring board 1 side. In this embodiment, the insulating resin layer 21 can be formed using, for example, a photosensitive phenolic resin. An insulating resin layer 21 is formed to cover a region including the pad electrode 20 and the insulating resin 15.

Next, as shown in FIG. 4H, UV exposure 22 is performed and development is performed to form an insulating resin layer 21a having an opening that exposes the pad electrode 20, as shown in FIG. 4I, and then baked. The insulating resin layer 21a is cured and stabilized.

Next, surface treatment is performed to prevent oxidation of Cu on the surface of the pad electrode 20 and to improve wettability of the solder bumps. In this embodiment, for example, a pad surface treatment layer 23 is formed on the surface of the pad electrode 20, in which a nickel layer, a lead layer, and a gold layer (Ni/Pd/Au) are laminated in this order. Note that an OSP (organic sold erability preservative, surface treatment using water-soluble preflux) film may be formed on the surface of the pad electrode 20.

Next, as shown in FIG. 4J, a solder paste is formed on this pad surface treatment layer 23 and then reflowed to form solder bumps 24, which are protruding electrodes. Thereafter, the carrier board 5 is separated into pieces, thereby completing the second wiring board 3 to which the separated carrier board 5 is attached.

(Wiring board 100 for semiconductor package)
Next, a wiring board for a semiconductor package will be explained using FIGS. 3A to 3E.
The second wiring board 3 including the multilayer wiring layer 25a accompanied by the carrier board 5 obtained as described above is flipped onto the FCBGA wiring board 1 (first wiring board) as shown in FIGS. 3A to 3E. The wiring board 100 for a semiconductor package can be obtained by bonding using a chip mounting technique or the like. At this time, by using good products for both the FCBGA wiring board 1 (first wiring board) and the second wiring board 3, the flip chip can be easily removed if either one is defective or both are defective. Since there is no need to carry out a mounting process, this process can be made more efficient.

This will be explained in detail below.
A good FCBGA wiring board 1 and a second wiring board 3 are prepared in advance.
First, as shown in FIGS. 3A and 3B, a flip-chip mounting technique is applied to an FCBGA wiring board 1 designed and manufactured according to the position of the terminals, that is, the solder bumps 24, of the second wiring board 3 with the carrier board 5 attached. The second wiring board 3 with the carrier board 5 attached thereto is joined, and the gap formed between both boards is filled with the underfill 2 and hardened.

Next, as shown in FIG. 3C, the laser beam L is applied to the peeling layer formed at the interface with the carrier substrate 5 from the back surface of the carrier substrate 5, that is, the surface of the carrier substrate 5 on the opposite side from the FCBGA wiring board 1. The carrier substrate 5, which can be peeled off by irradiating the carrier substrate 6, is removed from the second wiring substrate 3 as shown in FIG. 3D.

Next, as shown in FIG. 3E, after the carrier substrate 5 is peeled off, the intermediate layer 8 made of the photosensitive resist is removed using a developing solution or stripping solution for the photosensitive resist.

This intermediate layer 8 is heat resistant and will not completely harden or deteriorate even when exposed to heat during the manufacturing process of the second wiring board 3 or the reflow of solder bumps, and will not be completely cured or deteriorated by the heat generated during the manufacturing process of the second wiring board 3 or the reflow of solder bumps, and can be used with developing solutions and stripping solutions for photosensitive resists. You can use anything that can be easily removed.

Finally, the non-containing adhesion layer 9a on the surface of the copper post 14 is wet etched or dry etched using a reactive gas to expose the copper post 14 connected to the semiconductor chip 4, as shown in FIG. 3E. This completes the semiconductor package wiring board 100.

(Semiconductor chip mounting)
In this embodiment, a solder paste layer is formed on the surface of the copper post 14, and the semiconductor chip 4 is mounted on the multilayer wiring layer 25a side of the second wiring board 3 of the semiconductor package wiring board 100 via the solder paste. By soldering and further filling an underfill 32 between the multilayer wiring layer 25a of the second wiring board 3 and the semiconductor chip 4, a semiconductor package 30 as shown in FIG. 1 can be manufactured.

(Second manufacturing method of second wiring board)
Next, with reference to FIGS. 5A to 5F, a second method for manufacturing the semiconductor package wiring board 100 including the multilayer wiring layer 25a of the second wiring board 3 according to the present embodiment will be described.

As shown in FIG. 5A, a peeling layer 6 for peeling off the carrier substrate 5 in a subsequent step is formed on one surface of the carrier substrate 5. The peeling layer 6 is a material that is decomposed by an infrared or ultraviolet laser and causes interlayer peeling. Examples of such materials include amorphous silicon and carbon-dispersed acrylic resin.

Next, as shown in FIG. 5B, a first intermediate layer 8a having a thermogravimetric change of 5% or less at 260° C. is formed on this peeling layer 6, and an insecure adhesion layer 9a is formed thereon by sputtering. A seed layer 11 is formed of a laminated film of a conductive layer 13a or a single layer of the conductive layer 13a.

Next, as shown in FIG. 5C, openings corresponding to copper posts and openings serving as alignment marks are formed on the seed layer 11, thereby forming the second intermediate layer 8b. Furthermore, after forming electrolytic copper plating 10 in the opening of second intermediate layer 8b on seed layer 11, the surfaces of second intermediate layer 8b and electrolytic copper plating 10 are removed by mechanical polishing or cutting to the cutting line. . Thereby, as shown in FIG. 5D, a copper post 14 for connection with a semiconductor chip can be formed.

Next, as shown in FIG. 5E, an insulating resin 15 is formed on the intermediate layer 8b and the copper post 14. In this embodiment, the insulating resin 15 may be formed by a spin coating method using a coating liquid containing a photosensitive insulating resin, or may be formed by a spin coating method. It is also possible to form the insulating resin 15 by compressing and curing an insulating resin film using a vacuum laminator. In this case, an insulating film with good flatness can be formed. As the photosensitive insulating resin, in addition to phenolic resins, epoxy resins, acrylic resins, mixtures thereof, polyimide resins, etc. can be used. Further, either a positive type resist or a negative type resist may be used.

In addition, if the chemical bond between the intermediate layer 8b and the insulating resin 15 is high and inhibits the releasability of the intermediate layer 8b, the adhesiveness of both the intermediate layer 8b and the insulating resin 15 is high on the intermediate layer 8b. It is also possible to form an airtight adhesion layer 9a (see FIG. 4B). The non-secret adhesive layer 9a formed here may be mounted on the FCBGA wiring board 1 as the multilayer wiring layer 25a of the second wiring board 3, and then the intermediate layer 8b and the non-secret adhesive layer 9a may be removed.

Next, as shown in FIG. 5F, a seed layer 18 is formed on the insulating resin 15, and the trench 12 which becomes the fine pattern 7 formed on the upper surface of the insulating resin is electrically connected to the copper wiring in the lower layer. The opening that will become the via 17 is covered with electrolytic copper plating 10b. Next, the surfaces of the insulating resin 15 and the electrolytic copper plating 10b are removed by mechanical polishing or cutting to the cutting line so that they are almost flush with the upper surface of the insulating resin 15, thereby forming the fine pattern 7 and the conductive via 17. (See the lower diagram in Figure 5F).

The process of laminating the insulating resin 15 and the fine pattern 7 on the conductive via 17 and the intermediate layer 8b is performed by repeating the same process (wiring creation process) as shown in FIGS. 5E to 5F as many times as necessary. It is possible to form a build-up layer having a desired number of fine patterns 7 therein. According to this embodiment, since the wiring layers of the build-up layer are sequentially formed on the carrier substrate 5, one wiring layer in the multilayer wiring layer 25a is close to the FCBGA wiring board 1 to be combined, due to the manufacturing process. As the diameter increases, the cross-sectional shape becomes larger; for example, the conductive via has a tapered shape.
Next, the outermost insulating resin layer, pad surface treatment, and solder bumps may be formed through steps similar to those shown in FIGS. 4G to 4J.

Next, through steps similar to those shown in FIG. 3A to FIG. The carrier substrate 5 is removed by irradiating the peeling layer 6 formed at the interface with the carrier substrate 5.

Next, after peeling off the carrier substrate 5, the intermediate layer 8 made of a photosensitive resist is removed using a developing solution or stripping solution for the photosensitive resist.

Next, the seed layer 18 formed between the intermediate layer 8 and the insulating resin 15 is removed by wet etching or dry etching using a reactive gas to expose the copper post 14 connected to the semiconductor chip 4. As a result, the semiconductor package wiring board 100 (see FIG. 3E) with the very thin multilayer wiring layer 25a (interposer 25) of the second wiring board 3 is completed.

In this embodiment, a solder paste layer is formed on the surface of the copper post 14, and the semiconductor chip 4 is mounted on the multilayer wiring layer 25a side of the second wiring board 3 of the semiconductor package wiring board 100 via the solder paste. By filling the underfill 32 between the multilayer wiring layer 25a of the second wiring board 3 and the semiconductor chip 4, a semiconductor package 30 as shown in FIG. 1 can be manufactured.

(Effects of wiring board 100 for semiconductor package)
As described above, according to the present embodiment, the FCBGA wiring board (first wiring board) 1 and the multilayer wiring layer 25a of the second wiring board 3 formed on the carrier board 5, which becomes the second wiring board 3, , and then bonded together, it is possible to manufacture the semiconductor package wiring board 100 (FIG. 3E) with the interposer 25 (that is, the multilayer wiring layer 25a of the second wiring board 3). When bonding the FCBGA wiring board 1 and the multilayer wiring layer 25a of the second wiring board 3 including the carrier board 5, only good products are selected and the non-defective products are bonded together to form the semiconductor package wiring board 100. By forming this, a decrease in yield can be prevented.

Further, since a glass substrate can be used as the carrier substrate 5 instead of a silicon substrate, highly efficient substrate manufacturing is possible, and costs can be reduced.

In addition, by forming the copper posts 14 on the carrier board 5 which becomes the second wiring board 3, it becomes possible to arrange bumps with a narrow pitch and to form the heights of the copper posts 14 uniformly. Electrical short-circuits and disconnections due to solder protrusion and insufficient solder at the connecting portion between the semiconductor chip 14 and the semiconductor chip 4 can be suppressed, and mounting with high connection reliability can be achieved.

Furthermore, by forming the intermediate layer 8 between the release layer 6 and the insulating resin 15, when the release layer 6 is irradiated with laser light, the laser light that has passed through the release layer 6 is attenuated up to the intermediate layer 8. Thereby, damage to the insulating resin 15 and the fine pattern 7 can be avoided.

Furthermore, since the FCBGA wiring board 1 and the multilayer wiring layer 25a of the second wiring board 3 equipped with the carrier board 5 are bonded and bonded together after their respective manufacturing processes are completed, It is possible to avoid warping of the semiconductor package wiring board 100 due to differences in wiring density, number of layers, and structure.

Furthermore, by using a high-rigidity, low-CTE, low-distortion carrier as the carrier substrate 5, the surface of the wiring layer after the carrier is removed is flat and the pad placement accuracy is high, making chip mounting easy. Become.

Further, especially when the second wiring board 3 is a thin film-like board, it is difficult to bond it to the FCBGA wiring board 1 via solder bumps. However, in this embodiment, as described above, the multilayer wiring layer 25a of the second wiring board 3 is formed on the carrier board 5, and the multilayer wiring layer 25a of the second wiring board 3 provided with the carrier board 5 is formed on the carrier board 5. After bonding to the FCBGA wiring board 1 via the solder bumps 24 and filling the underfill 32 to bond the multilayer wiring layer 25a side of the second wiring board 3 to the FCBGA wiring board 1, the carrier board 5 is removed. By doing this, the semiconductor package wiring board 100 in which the interposer 25 is bonded to the FCBGA wiring board 1 is realized, so even if the interposer 25 is a thin board, it can be easily connected to the FCBGA wiring board 1 via solder bumps. It can be joined by

Furthermore, if there is a CTE difference between the FCBGA wiring board 1 and the semiconductor chip 4, the bonding is likely to be destroyed, but by joining the FCBGA wiring board 1 and the semiconductor chip 4 via the interposer 25, the mutual distance can be reduced. Therefore, the influence of the CTE difference can be alleviated. Even if the interposer 25 has a small thickness, even if there is a difference in CTE, the stress caused by the difference is small, so the influence is small, and the reduction in the influence due to the difference in CTE between the FCBGA wiring board 1 and the semiconductor chip 4 is not hindered. Therefore, connection reliability and smoothness of the surface of the interposer 25 due to warpage can be improved.

In other words, even if the interposer 25 is thin, it is possible to realize the wiring board 100 for a semiconductor package, and if the thickness is 100 μm or less, the effect of the wiring board 100 for a semiconductor package according to the present embodiment can be sufficiently obtained. The effect is particularly effective when the thickness is 10 μm to 20 μm.

According to the wiring board for a semiconductor package of this embodiment, only good products of the FCBGA wiring board (first wiring board) and the interposer (second wiring board) manufactured in separate processes are used to form the first wiring board. This is a wiring board for a semiconductor package in which a second wiring board is flip-chip mounted, and an underfill is filled in the gap formed between the two and solidified. Therefore, it is possible to suppress a decrease in yield in the flip-chip mounting process and increase production efficiency. Furthermore, since the thickness of the interposer is as thin as 10 μm to 100 μm, deformation such as warping of the wiring board for a semiconductor package is suppressed. Therefore, mounting of the semiconductor chip becomes easy.

Further, according to the semiconductor package using the semiconductor package wiring board of this embodiment, since the thickness of the interposer is thin, deformation such as warping is suppressed. Since the underfill is also filled and fixed in the space between the semiconductor chip and the wiring board, the reliability of the connection between the semiconductor chip and the wiring board can be increased.

Although the present invention has been described above with reference to specific embodiments, the invention is not limited by these descriptions. Various modifications of the disclosed embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art from reading the description of the invention. Therefore, the claims should be understood to cover those modifications or embodiments that fall within the scope and spirit of the invention.

INDUSTRIAL APPLICABILITY The present invention can be applied to a semiconductor device including a wiring board for FCBGA and a wiring board such as an interposer interposed between an IC chip.

1... FCBGA wiring board (first wiring board); 2, 32... Underfill; 3... Second wiring board; 4... Semiconductor chip; 5... Carrier board; 6... Peeling layer; 7... Fine pattern; 8, 8a , 8b... intermediate layer; 9, 9a, 9b... non-containing adhesion layer; 10, 10a, 10b... electrolytic copper plating; 11... seed layer; 12... trench (groove); 13... opening; 13a, 13b... conductive layer; 14... Copper post; 15... Insulating resin; 16... UV exposure; 17... Conductive via; 18, 18a... Seed layer; 19... Photosensitive resist; 19a... Opening; 20... Pad electrode; 21, 21a... Insulating resin layer ;22...UV exposure;23...Pad surface treatment layer (Ni/Pd/Au);24,33...Solder bump;25...Multilayer wiring layer (interposer) of second wiring board;30...Semiconductor package;31...Cu pillar Or gold bump; 100...wiring board for semiconductor package

Claims (4)

a first wiring board on which a semiconductor chip is mounted;
a second wiring board, which is disposed on the surface of the first wiring board on which the semiconductor chip is mounted, and includes a build-up layer formed with an insulating resin layer and a wiring layer;
The first wiring board and the second wiring board are electrically connected via protruding electrodes on pad electrodes provided on their surfaces, and the first wiring board and the second wiring board A wiring board for a semiconductor package, which is provided with an underfill in between,
The thickness of the second wiring board is 10 μm to 100 μm,
A copper post is provided on the surface of the second wiring board on which a semiconductor chip is mounted, the first wiring board is a wiring board for FCBGA, and the second wiring board is a wiring board for a semiconductor package, which is an interposer. A manufacturing method,
The method includes a step of manufacturing the interposer, and a step of connecting the interposer to the FCBGA wiring board,
The manufacturing process of the interposer is as follows:
forming a release layer and an intermediate layer made of a photosensitive resin on the surface of a carrier substrate made of glass as a support;
a step of patterning the intermediate layer by a photolithography process;
After forming a seed layer consisting of an insecure adhesive layer and a conductive layer laminated in this order on the surface of the patterned intermediate layer and exposed release layer, electrolytic copper plating is formed on the seed layer to a thickness equal to or greater than that of the intermediate layer. The process of
A step of forming an intermediate layer of the same height as the copper post by cutting the electrolytic copper plating and the intermediate layer so as to leave the electrolytic copper plating with the same thickness as the intermediate layer;
Form an insulating resin pattern with an opening above the copper post or conductive via, form a trench that will serve as a wiring pattern at the top of the insulating resin pattern, and apply an insulating adhesive layer over the copper post or conductive via and the insulating resin pattern. After forming a conductive layer, electrolytic copper plating is applied thicker than the insulating resin pattern, and by cutting the electrolytic copper plating so that the top of the insulating resin pattern is exposed, electrolytic copper is applied to the trench on the top of the insulating resin pattern. a wiring creation step of forming a conductive via on a wiring pattern filled with copper plating and a copper post or conductive via;
repeating the wiring creation step according to the required number of layers of the wiring pattern to form a multilayer wiring layer with pad electrodes exposed on the top layer;
After forming a photosensitive insulating resin layer on the top layer of the multilayer wiring layer, using a photolithography process to form an insulating resin pattern having an opening for forming a conductive via on the pad electrode;
forming a pad surface treatment layer on the pad electrode;
forming a protruding electrode on the pad surface treatment layer,
The step of connecting the interposer to the FCBGA wiring board includes:
After aligning the FCBGA wiring board and the interposer attached with the carrier board, performing flip-chip mounting;
A step of making the carrier substrate peelable by irradiating the peeling layer with laser light from the carrier substrate side of the interposer;
a step of peeling and removing the carrier substrate from the interposer;
removing the intermediate layer exposed by peeling off the carrier substrate;
A method for manufacturing a wiring board for a semiconductor package, comprising the steps of: removing an insecure adhesion layer and a conductive layer on the surface of the copper post exposed by removing the intermediate layer to expose the copper post. a first wiring board on which a semiconductor chip is mounted;
a second wiring board, which is disposed on the surface of the first wiring board on which the semiconductor chip is mounted, and includes a build-up layer formed with an insulating resin layer and a wiring layer;
The first wiring board and the second wiring board are electrically connected via protruding electrodes on pad electrodes provided on their surfaces, and the first wiring board and the second wiring board A wiring board for a semiconductor package, which is provided with an underfill in between,
The thickness of the second wiring board is 10 μm to 100 μm,
A copper post is provided on the surface of the second wiring board on which a semiconductor chip is mounted, the first wiring board is a wiring board for FCBGA, and the second wiring board is a wiring board for a semiconductor package, which is an interposer. A manufacturing method,
The method includes a step of manufacturing the interposer, and a step of connecting the interposer to the FCBGA wiring board,
The manufacturing process of the interposer is as follows:
A release layer, a first intermediate layer made of a photosensitive resin, and a seed layer in which an insecure adhesive layer and a conductive layer are laminated in this order are formed in this order on the surface of a carrier substrate made of glass as a support. process and
After forming a second intermediate layer made of a photosensitive resin on the seed layer, patterning the second intermediate layer by a photolithography process;
A process of electrolytic copper plating using the patterned second intermediate layer as a plating mask,
A process of forming an intermediate layer of the same height as the copper post by cutting the electrolytic copper plating and the intermediate layer so as to leave a preset thickness of the electrolytic copper plating;
Form an insulating resin pattern with the upper part of the copper post or conductive via as an opening, form a trench that will serve as a wiring pattern at the top of the insulating resin pattern, and apply an insulating adhesive layer over the copper post or conductive via and the insulating resin pattern. After forming a conductive layer, electrolytic copper plating is applied thicker than the insulating resin pattern, and by cutting the electrolytic copper plating so that the top of the insulating resin pattern is exposed, electrolytic copper is applied to the trench on the top of the insulating resin pattern. a wiring creation step of forming a conductive via on a wiring pattern filled with copper plating and a copper post or conductive via;
repeating the wiring creation step according to the number of required wiring layers to form a multilayer wiring layer with pad electrodes exposed on the top layer;
After forming a photosensitive insulating resin layer on the top layer of the multilayer wiring layer, using a photolithography process to form an insulating resin pattern having an opening for forming a conductive via on the pad electrode;
forming a pad surface treatment layer on the pad electrode;
forming a protruding electrode on the pad surface treatment layer,
The step of connecting the interposer to the FCBGA wiring board includes:
After aligning the FCBGA wiring board and the interposer attached with the carrier board, performing flip-chip mounting;
A step of making the carrier substrate peelable by irradiating the peeling layer with laser light from the carrier substrate side of the interposer;
a step of peeling and removing the carrier substrate from the interposer;
removing the intermediate layer exposed by peeling off the carrier substrate;
A method for manufacturing a wiring board for a semiconductor package, comprising the steps of: removing an insecure adhesion layer and a conductive layer on the surface of the copper post exposed by removing the intermediate layer to expose the copper post. 3. The method of manufacturing a wiring board for a semiconductor package according to claim 1, wherein the protruding electrode is a solder bump, a copper post, or a gold bump. 4. The wiring board for a semiconductor package according to claim 1, wherein the wiring layer of the second wiring board has a cross-sectional shape that becomes larger as it approaches the first wiring board. manufacturing method .

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