JP2004063808A - Package structure of semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package structure of a semiconductor device and its manufacturing method capable of simply manufacturing a package as well as reducing disconnection of a wiring. <P>SOLUTION: The package structure of the semiconductor device comprises a semiconductor chip 1 having a semiconductor element and an electrode pad 2, and a protection layer 3 having a wiring 5 structuring an electric circuit on one surface and a plurality of interlayer connection bodies 4 penetrated from the specific position to the other surface. The protection layers 3 are laminated on the semiconductor chip 1 to cover an electrode pad 2, a top of the interlayer connection body 4 is connected to the electrode pad 2, and the wiring 5 is arranged on a surface opposite to a surface covering the electrode pad 2 of the protection layer 3. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a package structure of a semiconductor device and a method of manufacturing the same, and more particularly to a package structure of a semiconductor device called a wafer level CSP and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, as a semiconductor device packaging process, a wafer level chip size package (WLCSP) technology for packaging a plurality of semiconductor devices at a wafer level has been proposed. FIG. 4 shows a package proposed in Japanese Patent No. 3137322 (Japanese Patent Laid-Open No. 10-079362) as a package that can be formed at the wafer level.
[0003]
In FIG. 4, a semiconductor chip (not shown) and an electrode pad 102 electrically connected thereto are formed on a surface of a semiconductor substrate made of silicon to form a semiconductor chip 101. A wiring 104 made of, for example, aluminum (Al) is formed on the electrode pad 102 via an insulating layer 103 formed on the semiconductor chip 101, and one end of the wiring 104 is formed on the electrode pad 102. The other end is connected to a substantially cylindrical interlayer connector 105 in which a resin having elasticity such as polyimide is coated with a metal having some elasticity and low electric resistance such as Al, for example. Is formed. Further, a plurality of the interlayer connectors 105 are provided on the semiconductor chip 101, and a protective layer 106 having insulating properties is provided between the interlayer connectors 105. Then, a bump 107 made of, for example, a solder ball is formed on the upper surface of the interlayer connector 105 (upward in FIG. 4) to provide a connection terminal with the outside (for example, a circuit board).
[0004]
This is manufactured as follows.
[0005]
First, an insulating layer 103 is formed on a protective film (not shown) formed on a surface of a semiconductor chip 101 having a semiconductor element, and the insulating layer 103 on the electrode pad 102 is removed by lithography. Next, a plurality of wirings 104 and interlayer connectors 105 are formed by plating. Next, a protective layer 106 is formed between the interlayer connectors 105 using, for example, lithography. Then, bumps 107 are formed on the upper surface of the interlayer connector 105, and finally, the package is completed by cutting each chip.
[0006]
According to this package, the bump 107 is rearranged from the electrode pad 102 on the semiconductor chip 101 to the protective layer 106 via the wiring 104 as a new electrode pad, so that the package 107 is compared with the conventional chip level CSP. The size can be reduced. Also, unlike the conventional packaging method, it is not necessary to cut out the semiconductor chip 101 from the semiconductor substrate and individually package the semiconductor chip 101. The semiconductor device can be completed by forming the bumps 107 in units of the semiconductor substrate and then cutting them out individually. Therefore, the manufacturing process can be simplified.
[0007]
[Problems to be solved by the invention]
By the way, according to the above-mentioned package, the wiring 104 is formed on the element forming surface side of the semiconductor chip 101. On the element forming surface side, wiring (not shown) between elements having a predetermined shape necessary for forming a semiconductor element (not shown), an interlayer insulating film (not shown), and a protective film (not shown) Are formed, and as a result, the thickness of the film is partially changed, so that not less than a level difference is generated on the surface thereof. The step increases as the films are stacked, and gradually deteriorates the coverage (step coverage) at the step. If the wiring 104 is formed in this state, the wiring at the step may be deteriorated in the worst case. There is a possibility that disconnection of the wiring 104 or short-circuiting between wiring layers may occur when a multilayer structure is formed.
[0008]
In the manufacturing method, a lithography step and an etching step are repeatedly required to form the wiring 104, the interlayer connector 105, and the protective layer. This lithography process is a process in which a target material is formed on the entire surface of the target object, and then, for example, a photosensitive resin is applied, and after the pattern is transferred, unnecessary photosensitive resin is removed. The step is a step of removing an exposed portion of the target material by removing the photosensitive resin. As described above, when the target materials to be formed are different, it is necessary to repeat the lithography process and the etching process substantially equivalent to the number of materials. In addition, the steps of forming the wiring 104, the interlayer connector 105, and the protective layer 106 are chronological, and it is relatively difficult to perform different film formations at once, and there is a possibility that a time constraint may occur.
[0009]
The present invention has been made in view of the above points, and an object of the present invention is to provide a package structure of a semiconductor device and a method of manufacturing the same, which can reduce disconnection of wiring and can easily manufacture a package. Is to do.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a package structure of a semiconductor device according to the first aspect of the present invention includes a semiconductor chip having a semiconductor element and an electrode pad electrically connected thereto, and a wiring forming an electric circuit on one surface. A semiconductor device package structure comprising a protective layer having a plurality of interlayer connectors penetrating from a predetermined position of the wiring to the other surface thereof, wherein the protective layer is laminated on a semiconductor chip and has electrode pads. And an end of the interlayer connector is connected to the electrode pad, and the wiring is disposed on a surface of the protective layer opposite to the surface covering the electrode pad.
[0011]
In this way, the wiring can be formed on a comparatively smooth protective layer, so that the step of the wiring due to unevenness caused when the wiring is formed on the semiconductor chip can be reduced, and the stress of the wiring due to the step can be reduced. Can be reduced to reduce disconnection, and a highly reliable semiconductor device can be provided.
[0012]
According to a second aspect of the present invention, in the package structure of the semiconductor device according to the second aspect, the wiring is multi-layered by stacking a plurality of the protective layers.
[0013]
By doing so, a package can be formed without making wiring fine even in a semiconductor chip having relatively many electrode pads, so that a more reliable semiconductor device can be provided.
[0014]
According to a third aspect of the present invention, there is provided a method for manufacturing a package of a semiconductor device, comprising: a semiconductor chip having a semiconductor element and an electrode pad electrically connected thereto; and a wiring having an electric circuit on one surface. And a protective layer having a plurality of interlayer connectors penetrating from the predetermined position to the other surface of the semiconductor chip, wherein the protective layer is formed on at least a surface of the semiconductor chip on which electrode pads are formed. A first step of: and mounting a sheet having the interlayer connector and the wiring and releasably providing the wiring on the protective layer such that the tip of the interlayer connector faces a predetermined electrode pad of the semiconductor chip. A second step of placing and pressing, bonding the wiring on the protective layer and connecting the tip of the interlayer connector and the electrode pad, and peeling the sheet to transfer the wiring on the protective layer. It is characterized by having a third step.
[0015]
By doing so, the predetermined wiring and interlayer connection body can be formed in advance on the sheet separately from the semiconductor chip formation step, so that the wiring and interlayer connection body formation step is the same as the semiconductor chip formation step. Independent manufacture is possible, and the time restriction on layer formation is relatively small. Further, since the sheet is placed at a predetermined position on the semiconductor chip and pressed, the connection between the electrode pad and the interlayer connector and the formation of an electric circuit by wiring can be relatively easily performed. Can be reduced, and the package can be manufactured relatively easily.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
1A and 1B show a package structure of a semiconductor device according to the present embodiment, wherein FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view taken along line AA.
[0018]
The package structure of the semiconductor device of this embodiment includes a semiconductor chip 1 on which a semiconductor element (not shown) and an electrode pad 2 are formed, a protective layer 3, an interlayer connector 4, and a wiring 5 as main components. I have.
[0019]
The semiconductor chip 1 is formed on a semiconductor substrate made of, for example, silicon. On the surface of the semiconductor chip 1, for example, a semiconductor element such as a transistor and an electrode pad 2 electrically connected to the semiconductor element are formed.
[0020]
Further, a protective layer 3 is provided on the surface of the semiconductor chip 1 on which the electrode pads 2 are formed. This serves as a base for providing the wiring 5 described later and electrically insulates the semiconductor chip 1 from the wiring 5, and is formed of, for example, a prepreg in which epoxy resin is semi-cured. ing. The protective layer 3 is a thermosetting film, and has elasticity when laminated on the semiconductor chip 1. Furthermore, since it has a property of shrinking after heat curing, its thickness is set to a thickness such that an interlayer connector 4 described later can penetrate at least the cured protective layer 3. In this embodiment, the thickness is about 100 μm.
[0021]
The wiring 5 serves as an electric path for rearranging the electrode pad 2 on the protective layer 3 and is made of, for example, Cu, and its surface is plated with nickel (Ni) -gold (Au). ing. This is provided on the upper surface of the protective layer 3 (upward in FIG. 1A), and is fixed in a state of being embedded in the upper surface of the protective layer 3. Further, for example, a solder bump 6 for connection to a circuit board (not shown) is formed at one end of the wiring 5, and the wiring 5 and the electrode pad 2 are formed at the other end. Are formed electrically.
[0022]
The interlayer connector 4 is formed of, for example, a stud bump made of Au, has a two-step projection shape composed of a ball portion 41 and a lead portion 42, and has a thickness direction of the protective layer 3 (FIG. ) Is provided so as to pass through. In addition, this is Au-Au bonded to the wiring 5 and is in pressure contact with the electrode pad 2 by utilizing shrinkage of the protective layer 3 after thermosetting. In this embodiment, the height of the interlayer connector 4 is set to about 100 μm.
[0023]
Next, the manufacturing method will be described.
[0024]
The method of manufacturing the package of the semiconductor device according to this embodiment is basically divided into two steps of a manufacturing step of the semiconductor chip 1 and a manufacturing step of the wiring 5. However, the manufacturing process of the semiconductor chip 1 is substantially the same as a general manufacturing process, and a description thereof will be omitted.
[0025]
Next, in the method of manufacturing the wiring 5, first, a mask having a predetermined pattern is formed on the sheet 7 made of a stainless steel thin film. Then, after applying Cu plating on the mask side to form a Cu thin film, the mask is removed, and the wiring 5 constituting a predetermined circuit is formed. At this time, the wiring 5 is not chemically bonded to the sheet 7 and is maintained in a peelable state (FIG. 2A).
[0026]
Next, the surface of the wiring 5 is plated with Ni and Au, and the ball portion 41 of the interlayer connector 4 composed of Au stud bumps is bonded to one end of the wiring 5 by ultrasonic bonding (FIG. 2B).
[0027]
Subsequently, a protective layer 3 is formed on at least the surface of the semiconductor chip 1 on which the electrode pads 2 are formed (first step), and the sheet 7 is connected to the predetermined electrode pads 2 of the semiconductor chip 1 by the lead portions 42 of the interlayer connector 4. It is mounted on the protective layer 3 so as to face each other (FIG. 2C).
[0028]
Then, in this state, the semiconductor chip 1 and the sheet 7 are heated to about 200 ° C., and the sheet is pressed for about 3 to 10 seconds so that a pressure of about 100 g per one interlayer connection body 4 is applied to the tip of the lead portion 42 and the electrode. The pad 2 is connected (second step) (FIG. 2D).
[0029]
Finally, the sheet 7 is peeled off, and the wiring 5 is transferred onto the protective layer 3 (third step) (FIG. 2E).
[0030]
When the above-described manufacturing method is performed for each semiconductor substrate and the semiconductor chip 1 is cut, a semiconductor device package is completed. Further, as shown in FIG. 3, by repeating this manufacturing process, it is possible to make the wiring 5 multilayer.
[0031]
According to the method for manufacturing a package of a semiconductor device of the embodiment described above, the protective layer 3 is formed on the surface of the semiconductor chip 1 on which the electrode pads 2 are formed, and the wiring 5 having the interlayer connector 4 is provided so as to be peelable. The sheet 7 is placed on the protective layer 3 and pressed, and the sheet 7 is peeled off and the wiring 5 is transferred onto the protective layer 3, thereby connecting the electrode pad 2 and the interlayer connector 4 and forming an electric circuit by the wiring. Can be performed relatively easily, the number of lithography steps and etching steps can be reduced, and the package can be easily manufactured. In addition, since the predetermined wiring 5 and the interlayer connection body 4 can be formed in advance on the sheet 7 separately from the formation step of the semiconductor chip 1, the formation step of the wiring 5 and the interlayer connection body 4 is omitted. Manufacturing can be performed independently of the process, and there is relatively less time restriction on the formation of the wiring 5.
[0032]
Further, in the package structure of the semiconductor device manufactured as described above, the protective layer 3 is laminated on the semiconductor chip 1 to cover the electrode pad 2, and the tip of the interlayer connector 4 is connected to the electrode pad 2, and Since the wiring 5 is disposed on the surface of the protective layer 3 opposite to the surface covering the electrode pads 2, the wiring 5 can be formed on the relatively smooth protective layer 3 rather than on the semiconductor chip 1 having relatively severe irregularities. In addition, it is possible to reduce the level difference of the wiring due to the unevenness, to reduce the stress of the wiring 5 at the level difference, and to suppress the disconnection. As a result, a highly reliable semiconductor device can be provided.
[0033]
In addition, the material of the protective layer 3 is not limited to an epoxy resin. For example, the same effect can be obtained by using a polyimide resin. Alternatively, a film or paste in which fine particles having conductivity are mixed in the protective layer 3 may be used. By doing so, the fine particles are sandwiched between the contact surfaces between the electrode pads 2 and the interlayer connector 4, and the reliability of the electrical contact between them can be further improved.
[0034]
【The invention's effect】
In the semiconductor device package structure according to the first aspect of the present invention, the protective layer is laminated on the semiconductor chip to cover the electrode pad, the tip of the interlayer connector is connected to the electrode pad, and the wiring is formed by the electrode pad of the protective layer. By arranging the wiring on the surface opposite to the surface that covers the surface, the wiring can be formed on a relatively smooth protective layer rather than on a semiconductor chip with severe unevenness, so that the wiring steps due to the unevenness can be reduced, and as a result, the step portion In this case, the stress of the wiring can be reduced to suppress the disconnection, and a highly reliable semiconductor device can be provided.
[0035]
According to the package structure of the semiconductor device of the second aspect, in addition to the effect of the second aspect, the wiring is multi-layered by laminating a plurality of protective layers, so that the semiconductor device has a relatively large number of electrode pads. Since a package can be formed without making wiring fine, a more reliable semiconductor device can be provided.
[0036]
According to a third aspect of the present invention, there is provided a method of manufacturing a package of a semiconductor device, comprising: a first step of forming a protective layer on at least a surface of a semiconductor chip on which electrode pads are formed; The peelably provided sheet is placed on the protective layer and pressed so that the tip of the interlayer connector faces the predetermined electrode pad of the semiconductor chip, and the wiring is adhered to the protective layer and the interlayer connector is By providing a second step of connecting the tip and the electrode pad and a third step of peeling the sheet and transferring the wiring onto the protective layer, a predetermined wiring is formed on the sheet separately from the step of forming the semiconductor chip. In addition, since the interlayer connector can be formed in advance, the process of forming the wiring and the interlayer connector can be manufactured independently of the process of forming the semiconductor chip. There is relatively less. Further, since the sheet is placed at a predetermined position on the semiconductor chip and pressed, the connection between the electrode pad and the interlayer connector and the formation of an electric circuit by wiring can be relatively easily performed. And the package can be easily manufactured.
[Brief description of the drawings]
1A and 1B show a package structure of a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional view taken along line AA. It is.
FIG. 2 is a process cross-sectional view showing a semiconductor device packaging method according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a package structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a package structure of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Electrode pad 3 Protective layer 4 Interlayer connector 5 Wiring

Claims (3)

A semiconductor chip having a semiconductor element and an electrode pad electrically connected thereto, and a plurality of interlayer connectors having a wiring forming an electric circuit on one surface and penetrating from a predetermined position of the wiring to the other surface A semiconductor device package structure comprising a protective layer having
The protective layer is stacked on the semiconductor chip to cover the electrode pad, and the interlayer connector has a tip connected to the electrode pad, and the wiring is on the side opposite to the surface of the protective layer covering the electrode pad. A package structure for a semiconductor device, wherein the package structure is provided on a surface of a semiconductor device. 2. The package structure of a semiconductor device according to claim 1, wherein the wiring is multilayered by laminating a plurality of the protective layers. A semiconductor chip having a semiconductor element and an electrode pad electrically connected to the semiconductor element, and a plurality of interlayer connectors having a wiring forming an electric circuit on one surface and penetrating from a predetermined position of the wiring to the other surface A method for manufacturing a package of a semiconductor device comprising a protective layer having:
A first step of forming the protective layer on at least a surface of the semiconductor chip on which electrode pads are formed;
A sheet having the interlayer connector and the wiring and provided with the wiring releasable is placed and pressed on the protective layer so that the tip of the interlayer connector faces a predetermined electrode pad of the semiconductor chip, A second step of bonding the wiring on the protective layer and connecting the tip of the interlayer connector and the electrode pad;
A third step of peeling off the sheet and transferring the wiring onto the protective layer.

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