JP2009252942A - Component built-in wiring board, and method of manufacturing component built-in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a component built-in wiring board which is manufactured inexpensively while soundness as a wiring board is maintained, and to provide a method of manufacturing the same. <P>SOLUTION: The component built-in wiring board includes: a semiconductor element 41 having a first insulating layer 11, second insulating layers 12, 13, 14, and 15 disposed in a stack on the first insulating layer, a semiconductor chip buried in the second insulating layers and having a terminal pad, and surface mounting terminals in a grid array electrically connected to the terminal pad; a wiring pattern provided while sandwiched between the first insulating layer and second insulating layers and including a mounting land for the semiconductor element; a connection member electrically and mechanically connecting the surface mounting terminals of the semiconductor element to the mounting land; and a resin provided between the semiconductor element and first insulating layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate, and more particularly to a component built-in wiring board in which semiconductor elements are embedded and mounted and a method for manufacturing the same.

  An example of a component built-in wiring board in which a semiconductor chip is embedded and mounted by flip connection is disclosed in Japanese Unexamined Patent Application Publication No. 2003-197849. If a semiconductor chip (bare chip) is flip-connected, the thickness generated by the mounting is saved to a minimum. Therefore, the flip connection is an effective method for incorporating a semiconductor element in a wiring board.

  In the flip connection, for example, an Au bump is further formed on a terminal pad formed on a semiconductor chip, and this is press-contacted to a wiring pattern formed on a wiring board via an adhesive (underfill resin). Can be made. The consideration here is the low resistance connection between the Au bump and the wiring pattern and the securing of the connection reliability. Therefore, a high degree of cleaning is required on the surface of the wiring pattern, and as a common method, an Au plating layer is also formed on the surface layer of the wiring pattern.

  Generally, when flip-connecting a semiconductor chip on the main surface of a wiring board, a protective layer such as a solder resist is formed, leaving only a portion of the wiring pattern to be connected, and then a portion to be connected An Au plating layer is formed on the substrate. As a result, Au plating, which is not inexpensive, can be applied with a minimum area.

  In the case of embedding a semiconductor chip in a wiring board and flip-connecting it, there are some differences from the flip-connection of the semiconductor chip on the main surface as described above. First, there is an influence of the solder resist becoming a part of the inner insulating layer. Generally, the adhesion between the solder resist and the insulating plate material used in the wiring board is not so strong between the insulating plate materials. Therefore, when a configuration in which the solder resist as the inner layer is omitted is adopted, it is necessary to perform Au plating over a wide area, which affects the manufacturing cost. It cannot be said that the adhesion between the Au plating layer and the insulating plate material is strong, and a problem remains in this respect.

Further, the flip connection includes a technique for aligning a fine pitch connection pad formed on a semiconductor chip with respect to a land made of a wiring pattern, and has a wiring pattern for ensuring positional accuracy. The size of the workpiece cannot be increased too much. Therefore, the cost is increased due to the disadvantage of productivity. The same is true in that a device for flip connection must be prepared.
JP 2003-197849 A

  The present invention has been made in consideration of the above-described circumstances, and is manufactured at a low cost while maintaining soundness as a wiring board in a component built-in wiring board in which a semiconductor element is embedded and mounted in an insulating board. An object of the present invention is to provide a component built-in wiring board and a method of manufacturing the same.

  In order to solve the above-described problem, a component built-in wiring board according to the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, and the second insulating layer. A semiconductor element embedded in an insulating layer and having a terminal pad; and a semiconductor element comprising a grid-arranged surface mounting terminal electrically connected to the terminal pad; the first insulating layer; A wiring pattern including the mounting lands for the semiconductor element provided between the second insulating layers, and the surface mounting terminals and the mounting lands of the semiconductor element electrically and mechanically. It comprises a connecting member to be connected and a resin provided between the semiconductor element and the first insulating layer.

  That is, the semiconductor element incorporated in the component built-in wiring board has a semiconductor chip and a grid-mounted surface mounting terminal, and the semiconductor chip has a terminal pad. The terminal pads of the semiconductor chip and the surface mounting terminals are electrically connected. In other words, the semiconductor element is built in and mounted on the wiring board by the surface mounting terminals arranged in a grid pattern. Further, a resin is provided between the semiconductor element and the first insulating layer, and the reliability of electrical and mechanical connection between them is enhanced.

  Since the semiconductor element has a surface mounting terminal, surface mounting technology can be used to mount the semiconductor element in the wiring board. Therefore, it is not necessary to prepare a device for flip connection. Further, unlike the case of flip connection, the size of the work having the wiring pattern cannot be increased so much in order to ensure the alignment accuracy of the semiconductor chip with respect to the land. Furthermore, since the surface mounting terminals are arranged in a grid pattern, that is, in a plane arrangement, it is possible to reduce the plane area as a semiconductor element as much as possible, and the built-in area is the same as that of a semiconductor chip. Easy to manage. The wiring pattern for the built-in component does not require special formation of Au plating or solder resist.

  As described above, the wiring board with a built-in component that can be manufactured at low cost while removing the cause of the deterioration of the adhesion of the insulating material and maintaining the soundness of the wiring board.

  In addition, in the method for manufacturing a component built-in wiring board according to one embodiment of the present invention, the metal foil laminated on the first insulating plate is patterned, and the semiconductor chip having the terminal pads is electrically connected to the terminal pads. A step of forming a wiring pattern so as to include a land for mounting a semiconductor element having a grid-arranged surface mounting terminal; and the surface mounting terminal of the semiconductor element on the land of the wiring pattern. Electrically and mechanically connecting the second insulating layer to the first insulating plate so that the semiconductor element is embedded in a second insulating plate different from the first insulating plate. And a step of integrating the insulating plates.

  That is, the semiconductor element incorporated in this method of manufacturing a component built-in wiring board has a semiconductor chip and a grid-arranged surface mounting terminal, and the semiconductor chip has a terminal pad. The terminal pads of the semiconductor chip and the surface mounting terminals are electrically connected. Thereby, the semiconductor element is built-in and mounted by the surface mounting terminals arranged in a grid pattern.

  That is, since the semiconductor element has the surface mounting terminal, the surface mounting technique can be used to mount the semiconductor element internally, and thus it is not necessary to prepare an apparatus for flip connection. Further, unlike the case of flip connection, the size of the work having the wiring pattern cannot be increased so much in order to ensure the alignment accuracy of the semiconductor chip with respect to the land. Furthermore, since the surface mounting terminals are arranged in a grid pattern, that is, in a plane arrangement, it is possible to reduce the plane area as a semiconductor element as much as possible, and the built-in area is the same as that of a semiconductor chip. Easy to manage. The wiring pattern for component mounting does not require special formation of Au plating or solder resist.

  As described above, it is possible to provide a method of manufacturing a component built-in wiring board that can be manufactured at low cost while eliminating the cause of deterioration in adhesion of the insulating material and maintaining soundness as a wiring board.

  According to the present invention, in a component built-in wiring board in which a semiconductor element is embedded and mounted in an insulating plate, the component built-in wiring board that can be manufactured at low cost while maintaining soundness as a wiring board, and its manufacture A method can be provided.

  As an embodiment of the present invention, the wiring pattern may be a wiring pattern in which the surface on the second insulating layer side excluding the mounting land is roughened. According to this, the adhesiveness of the resin provided between the semiconductor element and the first insulating layer to the wiring pattern under the semiconductor element is improved, and the connection reliability between the semiconductor element and the wiring pattern is improved. Increased further.

  As an embodiment, the second insulating layer is a laminate of at least two insulating layers, and a second wiring pattern provided between the at least two insulating layers, and the second wiring layer An insulating layer that penetrates a part in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, is made of a conductive composition, and has an axis that matches the stacking direction. And an interlayer connection body having a shape whose diameter changes in the direction of the axis.

  This interlayer connection body is an example of an interlayer connection body that penetrates a part in the stacking direction of the second insulating layer in which the semiconductor element is embedded. For example, the interlayer connection body is derived from conductive bumps formed by screen printing of a conductive composition. It is an interlayer connection body. The interlayer connection body is sandwiched between the second wiring pattern and the wiring pattern. However, since the surface of the wiring pattern can be roughened, the connection reliability between the wiring pattern and the interlayer connection body can be improved. Can be provided and is preferred.

  As an embodiment, the resin may contain an insulating filler. By using a resin containing an insulating filler as the resin, the physical characteristics of the resin filling the space between the semiconductor element and the wiring pattern can be improved, and the reliability of the connection between the semiconductor element and the wiring pattern can be further improved. it can.

  As an embodiment, the resin may be a portion of the second insulating layer extending between the semiconductor element and the first insulating layer. According to this, since it is not necessary to provide a step of filling the resin between the semiconductor element and the first insulating layer independently during the manufacturing process, it is preferable in terms of production efficiency.

  Further, as an embodiment as a manufacturing method, the second insulating plate is laminated on the first insulating plate after the surface mounting terminals of the semiconductor element are connected to the lands of the wiring pattern. Before the integration, the method may further include a step of filling a resin between the semiconductor element, the first insulating plate, and the wiring pattern. By providing a step of filling a resin between the semiconductor element, the first insulating plate, and the wiring pattern, a resin having appropriate physical properties can be selected as a resin filling the gap. For example, even when the area of the semiconductor element is large, the resin can be filled without a gap. This can further contribute to the improvement of reliability.

  As an embodiment, a resin is filled between the semiconductor element and the first insulating plate and the wiring pattern after the surface mounting terminals of the semiconductor element are connected to the lands of the wiring pattern. Before performing, the method may further comprise a step of roughening the surface of the wiring pattern except for the land to which the surface mounting terminal of the semiconductor element is connected. According to this, the adhesiveness of the resin provided between the semiconductor element and the first insulating layer to the wiring pattern under the semiconductor element is improved, and the connection reliability between the semiconductor element and the wiring pattern is improved. Increased further.

  As an embodiment, the second insulating plate is a laminate of at least two insulating layers, and a second wiring pattern provided between the at least two insulating layers, 2 is in contact with the surface of the wiring pattern 2 and penetrates a part of the second insulating plate in the stacking direction to expose the head, and is made of a conductive composition and has an axis that matches the stacking direction. The step of integrating the second insulating plate into the first insulating plate in a laminated manner, the interlayer connecting body having a shape whose diameter changes in the axial direction. The head part of the interlayer connection body of the board may be brought into contact with the wiring pattern.

  The interlayer connection here is an example of an interlayer connection that penetrates a part in the stacking direction of the second insulating plate in which the semiconductor chip is embedded. For example, conductive bumps formed by screen printing of a conductive composition Is an interlayer connection body derived from The interlayer connection body is sandwiched between the second wiring pattern and the wiring pattern. However, since the surface of the wiring pattern can be roughened, the connection reliability between the wiring pattern and the interlayer connection body can be improved. Can be provided and is preferred.

  As an embodiment, the metal foil may have Cu as a material thereof, and the roughening may be performed by blackening and reducing Cu. The metal foil may have Cu as a material thereof, and the roughening may be performed by micro-etching Cu. These roughening methods are examples of roughening methods that can be generally employed when the metal foil is Cu.

  As an embodiment, the resin may be a resin containing an insulating filler. By using a resin containing an insulating filler as the resin, the physical characteristics of the resin filling the space between the semiconductor element and the wiring pattern can be improved, and the reliability of the connection between the semiconductor element and the wiring pattern can be further improved. .

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer 21, 22 (wiring pattern), 23 (second wiring pattern), 24, 25, 26 (= total 6 layers wiring), interlayer connector 31, 32, 34, 35, through-hole conductor 33, semiconductor element (by wafer level / chip scale package) 41, solder (connection member) 51, and solder resists 61 and 62.

  This wiring board has a semiconductor element 41 as a built-in component. The semiconductor element 41 is an element based on a wafer level chip scale package, and includes at least a semiconductor chip and a grid-shaped array of surface mounting terminals 41a formed on the semiconductor chip. Details of the structural example and the manufacturing process example will be described later (FIGS. 2 and 3). The surface mounting terminal 41a is a terminal provided by rearranging its position while electrically conducting from the terminal pad that the semiconductor chip originally has via the rewiring layer. The arrangement density is coarser than that of the terminal pads on the semiconductor chip. Thereby, the semiconductor element 41 can be mounted on the mounting land by the wiring layer 22 via the solder 51 by the surface mounting technique.

  Describing another structure as a component built-in wiring board, the wiring layers 21 and 26 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. Solder resist 61 is provided on both main surfaces except for the land portions of the wiring layers 21 and 26 on which solder (not shown) is to be mounted in mounting, so that the solder melted at the time of solder connection is held on the land portions and thereafter functions as a protective layer. , 62 (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is insulated between the wiring layer 21 and the wiring layer 22, and the wiring layer 22 and the wiring layer 23 are insulated in this order. The insulating layer 13 is provided between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is provided between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is provided between the wiring layer 25 and the wiring layer 26. However, the wiring layers 21 to 26 are separated from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, each having a thickness of 100 μm, for example, only the insulating layer 13 has a thickness of, for example, 300 μm, excluding the insulating layer 13. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in semiconductor element 41, and provides a space for embedding the semiconductor element 41. The insulating layers 12, 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in semiconductor element 41 and the space inside the through-hole conductor 33 of the insulating layer 13. Furthermore, the insulating layer 12 also deforms and enters between the semiconductor element 41 and the insulating layer 11 to fill the space therebetween. Thus, there is no space that becomes a void inside.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  The structure of the component built-in wiring board according to this embodiment has been described above. Next, the configuration of the semiconductor element 41 used for this component built-in wiring board will be described in some detail with reference to FIG. FIG. 2 is a bottom view (FIG. 2 (a)) and a cross-sectional view (FIG. 2 (b)) schematically showing the semiconductor element 41 used in the component built-in wiring board shown in FIG. FIG. 2B is a cross-sectional view in the arrow direction at the position A-Aa in FIG. In FIG. 2, the same components as those shown in FIG.

  As shown in FIG. 2A, the semiconductor element 41 has surface mounting terminals 41a arranged in a grid. The arrangement pitch of the terminals 41a is, for example, 0.2 mm to 1.0 mm. If the number of terminals necessary for the semiconductor element 41 is small near the center of the surface on which the terminal 41a is disposed, the terminal 41a may not be disposed.

  This semiconductor element 41 is in the form of a so-called LGA (land grid array) in which there is no solder ball on the terminal 41a as a form before being mounted because it is built in the wiring board. By adopting such a configuration without solder balls, the mounting size in the height direction is suppressed and the suitability for incorporation is further improved. If the thickness of the built-in wiring board permits, a so-called BGA (ball grid array) form in which solder balls are mounted on the terminals 41a can also be used.

  In the cross-sectional direction of the semiconductor element 41, as shown in FIG. 2B, the surface mounting terminal 41a is in contact with the rewiring layer 41b on the insulating layer 41e and through a portion penetrating the insulating layer 41e. It is formed to do. Furthermore, the rewiring layer 41b is in contact with the terminal pad 41c on the semiconductor chip on the insulating layer 41d provided between the insulating layer 41e and the semiconductor chip and through a portion penetrating the insulating layer 41d. Is formed.

  Since the terminal pads 41c are usually arranged in a line along each side of the semiconductor chip, the arrangement pitch is relatively narrow. That is, the rewiring layer 41b is provided to mediate conduction between the arrangement pitch and the arrangement pitch of the surface mounting terminals 41a that are arranged in a grid and have a relatively large arrangement pitch. With such a configuration, the semiconductor element 41 has a surface area that is the same as that of the semiconductor chip in spite of being capable of being surface-mounted, and is slightly thicker than the semiconductor chip itself in the thickness direction. It has become. In order to make the semiconductor element 41 thinner, the back surface of the semiconductor chip may be ground by providing a grinding step. For example, the total thickness can be about 0.3 mm or less.

  Next, an example of a manufacturing process of such a semiconductor element 41 will be described with reference to FIG. FIG. 3 is a process diagram schematically showing a manufacturing process example of the semiconductor element 41 used in the component built-in wiring board shown in FIG. In FIG. 3, the same reference numerals are given to the same components as those already shown in the drawings.

  First, as shown in FIG. 3A, a semiconductor wafer 41w having a plurality of semiconductor devices already formed on its surface is prepared. On the surface of the semiconductor wafer 41w, terminal pads 41c are formed as external connection portions of the respective semiconductor devices. The terminal pads 41c are usually provided along the four sides of each semiconductor device having an area necessary for wire bonding and having an arrangement pitch that does not hinder wire bonding. ing. This arrangement pitch is narrower than the arrangement pitch of terminals for general surface mounting.

  Next, as shown in FIG. 3B, an insulating layer 41d is formed on the entire surface of the semiconductor wafer 41w so as to cover the pad 41c. As a forming method, a known method may be used. For example, a polyimide which is an insulating material is dropped on the semiconductor wafer 41w and spin-coated, and the thickness can be formed to about 1 μm, for example.

  Next, as shown in FIG. 3C, the insulating layer 41d on the pad 41c is selectively removed by etching to form an opening 71 leading to the pad 41c in the insulating layer 41d. For selective etching, a known method such as photolithography can be applied. Instead of the method shown in FIGS. 3B and 3C, a method of selectively forming the insulating layer 41d except on the pad 41c may be used. The insulating layer 41d can be selectively formed by a well-known method.

  After the opening 71 is formed, next, as shown in FIG. 3D, a rewiring layer 41b is formed on the insulating layer 41d with a conductive material so as to fill the opening 71 and have a necessary pattern. . For example, Al, Au, Cu, or the like can be used for the rewiring layer 41b. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. For patterning, in consideration of the material to be used, unnecessary portions are etched away after being formed on the entire surface of the insulating layer 41d, or a resist mask having a predetermined pattern is formed on the insulating layer 41d. This can be done by forming a layer to be the wiring layer 41b. The thickness of the rewiring layer 41b can be set to about 1 μm, for example.

  After the rewiring layer 41b is formed, next, as shown in FIG. 3E, an insulating layer 41e is formed so as to cover the rewiring layer 41b, and the insulating layer 41e is selectively removed by etching. An opening 72 leading to the rewiring layer 41b is formed in 41e. The step shown in FIG. 3 (e) can be performed in the same manner as in FIG. 3 (b) and FIG. 3 (c), which are steps for forming and processing the insulating layer 41d. The same applies when a method for selectively forming the insulating layer 41e is selected.

  After the opening 72 is formed, next, as shown in FIG. 3F, the surface mounting terminal 41a is made of a conductive material so as to fill the opening 72 and occupy a predetermined arrangement position on the insulating layer 41e. Form. For example, Al, Au, Cu, or the like can be used as the conductive material. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. In order to form it selectively, in consideration of the material to be used, unnecessary portions are etched away after being formed on the entire surface of the insulating layer 41e, or a resist mask having a predetermined pattern is formed on the insulating layer 41d. This can be done by forming a layer to be the surface mounting terminal 41a. The layer of the surface mounting terminal 41a can have a thickness of about 1 μm, for example.

  If the conductive material is Cu or Al, the surface mounting terminal 41a may be further processed so that its surface layer is covered with a Ni / Au plating layer or a Sn (tin) plating layer. For example, an electroless plating process can be used to perform such plating. By having a plating layer of a predetermined material, it is possible to obtain good soldering and connection reliability in surface mounting for incorporation in a wiring board.

  When the surface mounting terminals 41a are formed, finally, as shown in FIG. 3G, the semiconductor wafer 41w is diced to obtain individual semiconductor elements 41. The semiconductor element 41 thus obtained can be subjected to the same surface mounting process as that of the chip component by the surface mounting terminal 41a.

  In FIG. 3, the method of forming the surface mounting terminals 41a using the wafer 41w before dicing has been described. However, this is an example of forming with higher productivity. However, the surface mounting terminals 41a can be formed by the same method on the individual semiconductor chips after dicing.

  As a modification of the semiconductor element 41 shown in FIG. 3, an example in which the rewiring layer 41b and the surface mounting terminal 41a are formed as the same layer can be given. In this case, a layer of a conductive material is formed on the insulating layer 41d so as to have a pattern necessary for rewiring and to have a pattern of the surface mounting terminals 41a in contact with this pattern. This layer of conductive material fills the opening 71 formed in the insulating layer 41d. Then, the conductive material layer is formed so as to cover the entire surface with the insulating layer 41e except for the portion of the surface mounting terminal 41a. This also makes it possible to obtain a semiconductor element having the surface mounting terminals 41a in which the terminal pads 41c of the semiconductor device are rearranged.

  As described above, in the component built-in wiring board according to this embodiment, the built-in / embedded semiconductor element 41 has the semiconductor chip and the surface mounting terminals 41a arranged in a grid. Therefore, since the semiconductor element 41 is built in the wiring board, the same surface mounting technology as that of the chip component can be applied when mounting. Therefore, it is possible to use a surface mounting technique for mounting a plurality of types of components at the same time, and it is possible to use a relatively large workpiece in consideration of productivity. Further, since the surface mounting terminals 41a are particularly in a grid arrangement, that is, in a plane arrangement, the planar area as the semiconductor element 41 can be reduced as much as possible, and the area as in the semiconductor chip can be reduced. The built-in ease is secured.

  Further, the insulating layer 12 is deformed and filled in the space between the semiconductor element 41 and the insulating layer 11, which contributes to ensuring the reliability of the connection portion between the semiconductor element 41 and the wiring layer 22. . That is, the reliability of electrical and mechanical connection between them is enhanced. In addition, it is not necessary to form Au plating or solder resist in the wiring layer 22 for incorporating components. As described above, a component-embedded wiring board that can be manufactured at a low cost while removing the cause of the deterioration of the adhesion of the insulating material and maintaining the soundness of the wiring board.

  The semiconductor element 41 to be embedded or buried is not a wafer level chip scale package as described above, but another package product (for example, an interpose substrate is provided between the semiconductor chip and the surface mounting element 41a). Form). In this case, the area and thickness of the element are inevitably larger than those of the wafer level / chip scale package, but this can be dealt with depending on the specifications of the board side used for component incorporation. Also in this case, the advantage that the same surface mounting technology as that applied to the chip component can be applied to the semiconductor element 41 is maintained.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 4 to 6 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 4 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 4A, a paste-like conductive composition to be the interlayer connection body 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing, for example, in a substantially conical shape. It is formed in a bump shape (bottom diameter, eg, 200 μm, height, eg, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 4B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31 so that the head is exposed. To do. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction). Subsequently, as shown in FIG. 4C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 4D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into a wiring layer 22 including mounting lands. And as shown in FIG.4 (e), the cream solder 51A is printed and applied on the mounting land obtained by processing, for example by screen printing. The cream solder 51A can be easily printed in a predetermined pattern by using screen printing. A dispenser can be used instead of screen printing.

  For the cream solder 51A, a conductive composition before curing may be used instead. When the conductive composition is used, heat resistance after curing is high, and it is possible to effectively prevent poor connection due to heat applied during component mounting as a wiring board after completion.

  Next, the semiconductor element 41 is mounted on the mounting land through the cream solder 51A, for example, with a mounter, and then heated to reflow the cream solder 51A. As a result, as shown in FIG. 4 (f), the wiring board material 1 in a state where the semiconductor element 41 is connected to the mounting land of the wiring layer 22 through the solder 51 is obtained. A subsequent process using the wiring board material 1 will be described with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 5 shows a manufacturing process of a part centering on the insulating layers 13 and 12 in each configuration shown in FIG. First, as shown in FIG. 5A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through hole 82 for forming a through-hole conductor is formed at a predetermined position, and a component opening 81 is formed in a portion corresponding to the built-in semiconductor element 41.

  Next, electroless plating and electrolytic plating are performed to form the through-hole conductor 33 on the inner wall of the through hole 82 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 81. Further, as shown in FIG. 5C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form the wiring layers 23 and 24. By the patterning formation of the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 81 is also removed.

  Next, as shown in FIG. 5 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that become interlayer connectors 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 5E, the FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. In the prepreg 12A, an opening corresponding to the built-in semiconductor element 41, similar to the insulating layer 13, is provided in advance.

  In the stacking step of FIG. 5 (e), the head of the interlayer connector 32 is made to penetrate the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG.5 (e) shows that there are both the case where the head part is plastically deformed and crushed at this stage, and the case where it is not plastically deformed. The wiring board material obtained as described above is referred to as a wiring board material 2.

  The process shown in FIG. 5 can be performed as follows. In the stage of FIG. 5A, only the through hole 82 is formed and the subsequent steps from FIG. 5B to FIG. 5D are performed without forming the opening 81 for the built-in component. Next, as a step corresponding to FIG. 5E, prepreg 12A (without opening) is laminated. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 6 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked. Here, the upper wiring board material 3 shown in the figure applies the same process as that of the lower wiring board material 1, and thereafter, the interlayer connector 34 and the prepreg 14A are connected to the interlayer connector in the intermediate wiring board material 2 shown in the figure. 32 and the prepreg 12A.

  However, the wiring board material 3 is configured without a component (semiconductor element 41) and a portion (mounting land) for connecting the component (semiconductor element 41), and further, no opening is provided in the prepreg 14A. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Here, the wiring board material 1 includes a first insulating plate, and the wiring board materials 2 and 3 correspond to a second insulating plate. The prepregs 12A and 14A are completely cured by pressurization and heating in the press machine, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the semiconductor element 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively.

  After the laminating process shown in FIG. 6, the metal foils 26A and 21A on the upper and lower surfaces are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. Further, for the interlayer connectors 31, 32, 34, and 35, in addition to those derived from the conductive bumps printed by the conductive composition described above, for example, metal bumps formed by metal plate etching, conductive composition filling It is also possible to appropriately select and employ a connection body obtained from the above, a conductor bump formed by plating, or the like. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 4D) other than patterning after the final lamination process. May be.

  In the laminating process shown in FIG. 6, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating layer 11) of the wiring board material 1. In this case, the mounted semiconductor element 41 seems to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance. However, in the case of a sufficiently thin component as the semiconductor element 41, what is actually an interference factor? Don't be. In the step of laminating the prepreg 12A, the prepreg 12A can be uniformly laminated in the in-plane direction by pressing and heating with a cushioning material capable of absorbing the thickness of the semiconductor element 41 interposed.

  Next, another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to another embodiment of the present invention. In FIG. 7, the same or equivalent parts as those already described are denoted by the same reference numerals, and the description thereof is omitted. In this embodiment, as compared with that shown in FIG. 1, the wiring layer 22 is a wiring layer 22 having a roughened surface 22a on the surface on the insulating layer 12 side excluding the mounting land of the semiconductor element 41. The difference is that a resin 52 (underfill resin) different from that of the insulating layer 12 is provided between the semiconductor element 41 and the insulating layer 11.

  The intention of the roughened surface 22a is mainly the wiring layer 22 under the semiconductor element 41 (the “wiring layer 22 under the semiconductor element 41 excluding the land for mounting the semiconductor element 41” is not shown in the figure. The adhesion of the resin 52 to the semiconductor element 41 and the wiring layer 22 is further improved. The intent of the resin 52 is that a resin having appropriate physical properties is selected as a resin that fills the gap between the semiconductor element 41 and the wiring layer 22. Thereby, the reliability of the connection between the semiconductor element 41 and the wiring layer 22 is further improved.

  With reference to FIG. 8, the manufacturing method of the component built-in wiring board of this embodiment is demonstrated. FIG. 8 is a process diagram schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In FIG. 8, parts that are the same as or equivalent to those already described are given the same reference numerals. More specifically, FIG. 8 shows a process of further processing the wiring board material 1 shown in FIG. 4 (f) and changing it to a new wiring board material 1 A that replaces the wiring board material 1. .

  First, FIG. 8A is exactly the same as FIG. 4F. Next, as shown in FIG. 8B, the remaining surface of the wiring layer 22 to which the semiconductor element 41 is connected by the solder 51 is roughened to be modified to a roughened surface 22a. Specifically, for example, a blackening reduction process or a microetching process can be employed. Examples of the micro-etching process include CZ processing (MEC product name) and bond film processing (Atotech product name).

  In addition, since the process which roughens the surface of copper foil is generally performed in order to improve adhesiveness with the insulating resin laminated | stacked on copper foil, the said roughening is carried out as a process simultaneously with this process. Processing may be performed. According to this, it is not necessary to perform the roughening process as a new process, and it is possible to manufacture efficiently. However, the degree of roughening is preferably directed to an appropriate degree in consideration of the adhesion with the resin 52.

  Following the roughening treatment, as shown in FIG. 8C, an underfill resin 52 is filled between the semiconductor element 41 and the insulating layer 11. Specifically, for example, a liquid thermosetting resin is injected with a dispenser. Since it is liquid, even when the area of the semiconductor element 41 is considerably large, the liquid resin 52 spreads into the gap due to the capillary phenomenon and the filling is completed. After filling, the underfill resin 52 is cured by heating.

  The wiring board material 1A having the form shown in FIG. 8C is used instead of the wiring board material 1 in the laminating process shown in FIG. In this lamination process, since the surface of the wiring layer 22 is the roughened surface 22a, the connection reliability between the wiring layer 22 and the interlayer connector 32 is also improved. Thereafter, the steps as already described are performed. Thereby, the component built-in wiring board having the configuration shown in FIG. 7 is obtained.

  In addition, as the underfill resin 52, in order to further improve the connection reliability between the semiconductor element 41 and the wiring layer 22, it is conceivable to employ an insulating filler. Ensuring the reliability of the connection between the semiconductor element 41 and the wiring layer 22 is a major matter for the component built-in wiring board. Therefore, if a resin containing an insulating filler of an inorganic material is employed as the underfill resin 52, the coefficient of thermal expansion is smaller than that of the organic material, and the stress generated at the boundary with the semiconductor element 41 can be suppressed. As a result, reliability can be improved.

  Further, in this embodiment, the formation of the roughened surface 22a and the use of the underfill resin 52 different from the insulating layer 12 may be considered as only one depending on the required reliability specifications.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. The bottom view and sectional drawing which show the semiconductor element 41 used for the component built-in wiring board shown in FIG. 1 typically in some detail. Process drawing which shows the example of a manufacture process in the cross section about the semiconductor element 41 used for the component built-in wiring board shown in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on another embodiment of this invention. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1A ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 13A ... Prepreg, 14 ... Insulation 14A ... prepreg, 15 ... insulating layer, 21 ... wiring layer (wiring pattern), 21A ... metal foil (copper foil), 22 ... wiring layer (wiring pattern), 22a ... roughened surface, 22A ... metal foil (copper) Foil), 23 ... Wiring layer (wiring pattern), 23A ... Metal foil (copper foil), 24 ... Wiring layer (wiring pattern), 24A ... Metal foil (copper foil), 25 ... Distribution layer (wiring pattern), 26 ... Wiring layer (wiring pattern), 26A... Metal foil (copper foil), 31, 32, 34, 35... Interlayer connection body (conductive bump by conductive composition printing), 33... Through-hole conductor, 41. (Wafer level / chip scale 41a ... terminal for surface mounting, 41b ... redistribution layer, 41c ... terminal pad, 41d, 41e ... insulating layer, 41w ... semiconductor wafer, 51 ... connecting member (solder or conductive composition), 51A ... cream Solder or pre-curing conductive composition, 52... Underfill resin, 61, 62... Solder resist, 71, 72... Opening, 81.

Claims (12)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A semiconductor element comprising a semiconductor chip embedded in the second insulating layer and having a terminal pad; and a grid-arranged surface mounting terminal electrically connected to the terminal pad;
A wiring pattern including a mounting land for the semiconductor element, which is provided between the first insulating layer and the second insulating layer;
A connection member for electrically and mechanically connecting the surface mounting terminal of the semiconductor element and the mounting land;
A component built-in wiring board, comprising: a resin provided between the semiconductor element and the first insulating layer.   2. The component built-in wiring board according to claim 1, wherein the wiring pattern is a wiring pattern having a roughened surface on the second insulating layer side excluding the mounting land. The second insulating layer is a stack of at least two insulating layers;
A second wiring pattern provided between the at least two insulating layers;
The second insulating layer penetrates a part in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and coincides with the stacking direction. 3. The component built-in wiring board according to claim 1, further comprising: an interlayer connection body having an axis that has a shape that has a diameter that changes in a direction of the axis.   The component built-in wiring board according to claim 1, wherein the resin contains an insulating filler.   The component built-in wiring board according to claim 1, wherein the resin is a portion of the second insulating layer extending between the semiconductor element and the first insulating layer. A metal element laminated on a first insulating plate is patterned, and a semiconductor element having a semiconductor chip having terminal pads and grid-mounting surface mounting terminals electrically connected to the terminal pads is mounted. Forming a wiring pattern so as to include a land for performing,
Electrically and mechanically connecting the surface mounting terminals of the semiconductor element to the lands of the wiring pattern;
Integrating the second insulating plate in a stacked manner on the first insulating plate so as to embed the semiconductor element in a second insulating plate different from the first insulating plate. A method of manufacturing a component built-in wiring board.   After connecting the surface mounting terminals of the semiconductor element to the lands of the wiring pattern and before integrating the second insulating plate in a stacked manner on the first insulating plate, The method of manufacturing a component built-in wiring board according to claim 6, further comprising a step of filling a resin between the first insulating board and the wiring pattern.   After connecting the surface mounting terminal of the semiconductor element to the land of the wiring pattern, and before filling the resin between the semiconductor element, the first insulating plate, and the wiring pattern, the wiring 8. The component built-in wiring board according to claim 7, further comprising a step of roughening a surface of the wiring pattern except for the land of the pattern to which the surface mounting terminal of the semiconductor element is connected. Production method. The second insulating plate is a laminate of at least two insulating layers, and a second wiring pattern sandwiched between the at least two insulating layers, and a surface of the second wiring pattern The head is exposed through a part of the second insulating plate in the laminating direction and is made of a conductive composition and has an axis that coincides with the laminating direction and has a diameter in the direction of the axis. An interlayer connection body having a changing shape,
The step of integrating the second insulating plate in a stacked manner on the first insulating plate is performed such that the head of the interlayer connection body of the second insulating plate is in contact with the wiring pattern. The method for manufacturing a component built-in wiring board according to any one of claims 6 to 8, wherein: The metal foil has Cu as its material,
The method of manufacturing a component built-in wiring board according to claim 8, wherein the roughening is performed by blackening and reducing Cu. The metal foil has Cu as its material,
The method of manufacturing a component built-in wiring board according to claim 8, wherein the roughening is performed by microetching Cu.   9. The method for manufacturing a component built-in wiring board according to claim 7, wherein the resin is a resin containing an insulating filler.

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