JP5649771B2 - Component built-in wiring board - Google Patents

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate, and more particularly to a component built-in wiring board in which semiconductor elements are embedded and mounted.

  An example of a component built-in wiring board in which a semiconductor chip as a semiconductor element is embedded and mounted by flip connection is disclosed in Japanese Patent Application Laid-Open No. 2003-197849. If a semiconductor chip (bare chip) is flip-connected, the thickness generated by the mounting is saved to a minimum, which is an effective method for incorporating a semiconductor element in a wiring board.

  In the flip connection, for example, an Au bump is further formed on a terminal pad formed on a semiconductor chip, and this is press-contacted to a wiring pattern formed on a wiring board via an adhesive (underfill resin). (ACF [anisotropic conductive film] or ACP [anisotropic conductive paste] may be sandwiched between them). The consideration here is the low resistance connection between the Au bump and the wiring pattern and the securing of the connection reliability. Therefore, a high degree of cleaning is required on the surface of the wiring pattern, and as a common method, an Au plating layer is also formed on the surface layer of the wiring pattern.

  Generally, when flip-connecting a semiconductor chip on the main surface of a wiring board, a protective layer such as a solder resist is formed, leaving only a portion of the wiring pattern to be connected, and then a portion to be connected An Au plating layer is formed on the substrate. As a result, Au plating, which is not inexpensive, can be applied with a minimum area.

  In the case of embedding a semiconductor chip in a wiring board and flip-connecting it, there are some differences from the flip-connection of the semiconductor chip on the main surface as described above. First, there is an influence of the solder resist becoming a part of the inner insulating layer. Generally, the adhesion between the solder resist and the insulating plate material used in the wiring board is not so strong between the insulating plate materials. Therefore, if a configuration in which the solder resist as the inner layer is omitted is adopted, Au plating is performed over a large area, which affects the manufacturing cost. It cannot be said that the adhesion between the Au plating layer and the insulating plate material is strong, and a problem remains in this respect. Further, even if the Au plating layer is formed in a limited region, the steps such as mask formation and removal increase and the cost increases.

In addition, the flip connection includes a technique for aligning a fine pitch connection pad formed on a semiconductor chip with respect to a land made of the wiring pattern. It is not possible to make the size of the workpiece to be too large. Therefore, the cost is increased due to the disadvantage of productivity. The cost is also high in that a device for flip connection must be prepared.
JP 2003-197849 A

  The present invention has been made in consideration of the above-mentioned circumstances, and in a component built-in wiring board in which a semiconductor element is embedded and mounted in an insulating plate, the soundness as the wiring board and the electrical reliability built in the component are maintained. Then, it aims at providing the component built-in wiring board which can be manufactured at low cost.

In order to solve the above-described problems, a component built-in wiring board according to one aspect of the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, A semiconductor element including a semiconductor chip embedded in a second insulating layer and having a terminal pad; and a grid-arranged surface mounting terminal electrically connected to the terminal pad; and the first insulation A pattern which is sandwiched between a layer and the second insulating layer and faces each of the surface mounting terminals of the semiconductor element, and each has a similar or congruent shape to the planar shape of each of the surface mounting terminals Are interconnected with each of the surface mounting terminals of the semiconductor element and each of the mounting lands of the first wiring pattern. , Comprises is provided in contact to contact with and said actual wear land terminal surface mounting, a solder portion which is reflowed, the, of said mounting lands of said first wiring pattern A second wiring pattern provided on the opposite side of the first insulating layer from the side where the first wiring pattern is present, at least a part of which is an island-shaped pattern without wiring drawing as a pattern. And a conductive composition sandwiched between the surface of the at least part of the mounting land and the surface of the second wiring pattern through the first insulating layer, and laminated And an interlayer connector having a shape that has an axis that coincides with the direction and has a diameter that changes in the direction of the axis.

  That is, the semiconductor element incorporated in the component built-in wiring board has a semiconductor chip and a grid-mounted surface mounting terminal, and the semiconductor chip has a terminal pad. The terminal pads of the semiconductor chip and the surface mounting terminals are electrically connected. In other words, the semiconductor element is built in and mounted on the wiring board by the surface mounting terminals arranged in a grid pattern. Further, here, for this built-in mounting, a wiring pattern including a pattern that is similar or congruent to the planar shape of each of the surface mounting terminals of the semiconductor element is provided as a mounting land.

  Since the semiconductor element has a surface mounting terminal, surface mounting technology can be used to mount the semiconductor element in the wiring board. Therefore, it is not necessary to prepare a device for flip connection. Further, unlike the case of flip connection, the size of the work having the wiring pattern cannot be increased so much in order to ensure the alignment accuracy of the semiconductor chip with respect to the land. Furthermore, since the surface mounting terminals are arranged in a grid pattern, that is, in a plane arrangement, it is possible to reduce the plane area as a semiconductor element as much as possible, and the built-in area is the same as that of a semiconductor chip. Easy to manage. The wiring pattern for the built-in component does not require special formation of Au plating or solder resist.

In particular, solder is used as a connecting member for mounting a semiconductor element, and furthermore, the mounting land is a pattern similar to or congruent with the planar shape of each surface mounting terminal of the semiconductor element. The controllability of the shape of the connecting member that interconnects the surface mounting terminals is very high. That is, it is possible to suppress the spreading of the connection member, and furthermore, since the connection member can be formed in a uniform shape between the terminals, the reliability of electrical connection can be further improved. For electrical connection of the mounting lands that are not drawn out as pattern wiring, an interlayer connection body provided on the side opposite to the side where the semiconductor elements are mounted is used. By making the land into an island pattern, it is possible to further improve the controllability of the shape of the connecting member that interconnects the land and the surface mounting terminal. That is, since there is no lead portion for the pattern wiring, the connection member does not spread over this. The interlayer connection body is an interlayer connection body derived from conductive bumps formed by screen printing of a conductive composition, for example.

  As described above, the component built-in wiring board that can be manufactured at low cost while removing the cause of the deterioration of the adhesion of the insulating material and maintaining the soundness as the wiring board and the electrical reliability of the built-in component.

  According to the present invention, a component built-in wiring board in which a semiconductor element is embedded and mounted in an insulating plate can be manufactured at low cost while maintaining soundness as the wiring board and electrical reliability of the built-in component. become.

As an embodiment of the present invention, the second insulating layer is a laminate of at least two insulating layers, and a third wiring pattern provided between the at least two insulating layers, and the second The insulating layer is formed of a conductive composition that penetrates a part of the insulating layer in the stacking direction and is sandwiched between the surface of the first wiring pattern and the surface of the third wiring pattern, and in the stacking direction. further comprising radial direction of the shaft has a matching shaft and a second interlayer connector having a shape has changed, it is possible to. This interlayer connection body is an example of an interlayer connection body that penetrates a part in the stacking direction of the second insulating layer in which the semiconductor element is embedded. For example, the interlayer connection body is derived from conductive bumps formed by screen printing of a conductive composition. It is an interlayer connection body.

  As an embodiment, the surface mounting terminal of the semiconductor element can be an LGA terminal. In surface mounting using LGA, it is possible to mount on a wiring board without using bumps such as solder balls, and the size in the height direction can be suppressed.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer 21 (second wiring pattern), 22 (wiring pattern), 23 (third wiring pattern), 24, 25, and 26 (= 6 wirings in total), interlayer connector 31 , 31a, 32, 34, 35, through-hole conductor 33, semiconductor element (by wafer level / chip scale package) 41, solder (connection member) 51, and solder resists 61, 62. The wiring layer 22 includes a mounting land 22a.

  This wiring board has a semiconductor element 41 as a built-in component. The semiconductor element 41 is an element based on a wafer level chip scale package, and includes at least a semiconductor chip and a grid-shaped array of surface mounting terminals 41a formed on the semiconductor chip. Details of the structural example and the manufacturing process example will be described later (FIGS. 2 and 4). The surface mounting terminal 41a is a terminal provided by rearranging its position while electrically conducting from the terminal pad that the semiconductor chip originally has via the rewiring layer. The arrangement density is coarser than that of the terminal pads on the semiconductor chip. Thereby, the semiconductor element 41 can be mounted on the mounting land 22a of the wiring layer 22 via the solder 51 by the surface mounting technique.

Further, the mounting lands 22a for mounting the semiconductor element 41 via the solder 51 are provided corresponding to the surface mounting terminals 41a of the semiconductor element 41, as will be described later (FIG. 3). Each of the planar shapes has a pattern similar to or congruent with the surface mounting terminals 41a. For this reason, the controllability of the shape of the solder 51 that interconnects the mounting lands 22a and the surface mounting terminals 41a is very high. That is, it is possible to suppress the spread of the connection member 51, and the solder 51 can be formed in a uniform shape between the terminals 41a, so that stress generation is not biased and the reliability of electrical connection is improved. It can be improved further.

  Describing another structure as a component built-in wiring board, the wiring layers 21 and 26 are wiring layers on both main surfaces as a wiring board, and various components (not shown) can be mounted thereon. Solder resist 61 is provided on both main surfaces except for the land portions of the wiring layers 21 and 26 on which solder (not shown) is to be mounted in mounting, so that the solder melted at the time of solder connection is held on the land portions and thereafter functions as a protective layer. , 62 (thickness is about 20 μm, for example). An Ni / Au plating layer (not shown) with high corrosion resistance may be formed on the surface layer of the land portion.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is insulated between the wiring layer 21 and the wiring layer 22, and the wiring layer 22 and the wiring layer 23 are insulated in this order. The insulating layer 13 is provided between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is provided between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is provided between the wiring layer 25 and the wiring layer 26. However, the wiring layers 21 to 26 are separated from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, each having a thickness of 100 μm, for example, only the insulating layer 13 has a thickness of, for example, 300 μm, excluding the insulating layer 13. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in semiconductor element 41, and provides a space for embedding the semiconductor element 41. The insulating layers 12 and 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in semiconductor element 41 and the space inside the through-hole conductor 33 of the insulating layer 13 and become voids inside. There is no space.

  The wiring layer 21 and the wiring layer 22 can be electrically connected by interlayer connectors 31 and 31 a that are sandwiched between the surfaces of the patterns and penetrate the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 31a, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, and depend on the manufacturing process in the axial direction (FIG. 1). The diameter changes in the upper and lower stacking directions in FIG. The diameter is, for example, 200 μm on the thick side. Among these, in particular, the interlayer connection body 31a is provided directly below the pattern (that is, the island-like pattern) in the mounting land 22a that does not lead to wiring, so that the mounting land 22a is connected to the wiring layer 21. Can be electrically connected.

  By making the mounting land 22a into an island pattern, the controllability of the shape of the solder 51 that interconnects the land 22a and the surface mounting terminal 41a can be further enhanced. That is, since there is no lead portion for pattern wiring, the solder 51 does not spread.

  The structure of the component built-in wiring board according to this embodiment has been described above. Next, the configuration of the semiconductor element 41 used for this component built-in wiring board will be described in some detail with reference to FIG. FIG. 2 is a bottom view (FIG. 2 (a)) and a cross-sectional view (FIG. 2 (b)) schematically showing the semiconductor element 41 used in the component built-in wiring board shown in FIG. FIG. 2B is a cross-sectional view in the arrow direction at the position A-Aa in FIG. In FIG. 2, the same components as those shown in FIG. The arrangement of the terminals 41a is different from that of the semiconductor element 41 shown in FIG. 1, because FIG. 1 includes omissions for convenience of explanation.

  As shown in FIG. 2A, the semiconductor element 41 has surface mounting terminals 41a arranged in a grid. The arrangement pitch of the terminals 41a is, for example, 0.3 mm to 1.0 mm. If the number of terminals necessary for the semiconductor element 41 is small near the center of the surface on which the terminal 41a is disposed, the terminal 41a may not be disposed.

  This semiconductor element 41 is in the form of a so-called LGA (land grid array) in which there is no solder ball on the terminal 41a as a form before being mounted because it is built in the wiring board. By adopting such a configuration without solder balls, the mounting size in the height direction is suppressed and the suitability for incorporation is further improved. If the thickness of the built-in wiring board permits, a so-called BGA (ball grid array) form in which solder balls are mounted on the terminals 41a can also be used.

  In the cross-sectional direction of the semiconductor element 41, as shown in FIG. 2B, the surface mounting terminal 41a is in contact with the rewiring layer 41b on the insulating layer 41e and through a portion penetrating the insulating layer 41e. It is formed to do. Furthermore, the rewiring layer 41b is in contact with the terminal pad 41c on the semiconductor chip on the insulating layer 41d provided between the insulating layer 41e and the semiconductor chip and through a portion penetrating the insulating layer 41d. Is formed.

  Since the terminal pads 41c are usually arranged in a line along each side of the semiconductor chip, the arrangement pitch is relatively narrow. That is, the rewiring layer 41b is provided to mediate conduction between the arrangement pitch and the arrangement pitch of the surface mounting terminals 41a that are arranged in a grid and have a relatively large arrangement pitch. With such a configuration, the semiconductor element 41 has a surface area that is the same as that of the semiconductor chip in spite of being capable of being surface-mounted, and is slightly thicker than the semiconductor chip itself in the thickness direction. It has become. In order to make the semiconductor element 41 thinner, the back surface of the semiconductor chip may be ground by providing a grinding step. For example, the total thickness can be about 0.3 mm or less.

  Next, FIG. 3 is a plan view schematically showing a partial configuration of the wiring layer 22 shown in FIG. More specifically, the pattern of the wiring layer 22 including the land 22a for mounting the semiconductor element 41 described above is shown in a plan view. In FIG. 3, the same reference numerals are given to the same components as those shown in the already described drawings.

As shown in FIG. 3, the mounting land 22a included in the wiring layer 22 is provided corresponding to each of the surface mounting terminals 41a of the semiconductor element 41 described above, and each of the planar lands is a surface mounting terminal. The pattern is similar to or congruent to 41a (in this example, a circle). For this reason, as already described, the controllability of the shape of the solder 51 that interconnects the mounting lands 22a and the surface mounting terminals 41a can be kept high. In order to obtain such controllability, it is not necessary to form a solder resist that is normally used. Therefore, the problem of adhesion between the materials to be laminated does not occur.

  The wiring pattern drawn out from the mounting land 22a is preferably as thin as possible. Such a lead-out portion is a disturbance factor for the purpose of giving controllability to the shape of the solder 51, and affects the spread of the solder 51. Further, depending on the thickness difference of the lead portions, the effect of making the shape of the solder 51 uniform between the terminals 41a is reduced. A better mode is to utilize the interlayer connector 31a immediately below the pattern so that the land 22a has an island pattern as much as possible.

  Next, an example of a manufacturing process of the semiconductor element 41 described above will be described with reference to FIG. FIG. 4 is a process diagram schematically showing a manufacturing process example of the semiconductor element 41 used in the component built-in wiring board shown in FIG. In FIG. 4, the same reference numerals are given to the same components as those already shown in the drawings.

  First, as shown in FIG. 4A, a semiconductor wafer 41w having a plurality of semiconductor devices already formed on its surface is prepared. On the surface of the semiconductor wafer 41w, terminal pads 41c are formed as external connection portions of the respective semiconductor devices. The terminal pads 41c are usually provided along the four sides of each semiconductor device having an area necessary for wire bonding and having an arrangement pitch that does not hinder wire bonding. ing. This arrangement pitch is narrower than the arrangement pitch of terminals for general surface mounting.

  Next, as shown in FIG. 4B, an insulating layer 41d is formed on the entire surface of the semiconductor wafer 41w so as to cover the pad 41c. As a forming method, a known method may be used. For example, a polyimide which is an insulating material is dropped on the semiconductor wafer 41w and spin-coated, and the thickness can be formed to about 1 μm, for example.

  Next, as shown in FIG. 4C, the insulating layer 41d on the pad 41c is selectively removed by etching to form an opening 71 leading to the pad 41c in the insulating layer 41d. For selective etching, a known method such as photolithography can be applied. Instead of the method shown in FIGS. 4B and 4C, a method of selectively forming the insulating layer 41d except on the pad 41c may be used. The insulating layer 41d can be selectively formed by a well-known method.

  After the opening 71 is formed, next, as shown in FIG. 4D, a rewiring layer 41b is formed on the insulating layer 41d with a conductive material so as to fill the opening 71 and have a necessary pattern. . For example, Al, Au, Cu, or the like can be used for the rewiring layer 41b. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. For patterning, in consideration of the material to be used, unnecessary portions are etched away after being formed on the entire surface of the insulating layer 41d, or a resist mask having a predetermined pattern is formed on the insulating layer 41d. This can be done by forming a layer to be the wiring layer 41b. The thickness of the rewiring layer 41b can be set to about 1 μm, for example.

  After the rewiring layer 41b is formed, next, as shown in FIG. 4E, an insulating layer 41e is formed so as to cover the rewiring layer 41b, and the insulating layer 41e is selectively removed by etching. An opening 72 leading to the rewiring layer 41b is formed in 41e. The process shown in FIG. 4 (e) can be performed in the same manner as in FIG. 4 (b) and FIG. 4 (c), which are processes for forming and processing the insulating layer 41d. The same applies when a method for selectively forming the insulating layer 41e is selected.

  After the opening 72 is formed, next, as shown in FIG. 4F, the surface mounting terminal 41a is made of a conductive material so as to fill the opening 72 and occupy a predetermined arrangement position on the insulating layer 41e. Form. For example, Al, Au, Cu, or the like can be used as the conductive material. As a formation method, an appropriate one can be selected in consideration of a material to be used among sputtering, vapor deposition, plating, and the like. In order to form it selectively, in consideration of the material to be used, unnecessary portions are etched away after being formed on the entire surface of the insulating layer 41e, or a resist mask having a predetermined pattern is formed on the insulating layer 41d. This can be done by forming a layer to be the surface mounting terminal 41a. The layer of the surface mounting terminal 41a can have a thickness of about 1 μm, for example.

  If the conductive material is Cu or Al, the surface mounting terminal 41a may be further processed so that its surface layer is covered with a Ni / Au plating layer or a Sn (tin) plating layer. For example, an electroless plating process can be used to perform such plating. By having a plating layer of a predetermined material, it is possible to obtain good soldering and connection reliability in surface mounting for incorporation in a wiring board.

  When the surface mounting terminals 41a are formed, finally, as shown in FIG. 4G, the semiconductor wafer 41w is diced to obtain individual semiconductor elements 41. The semiconductor element 41 thus obtained can be subjected to the same surface mounting process as that of the chip component by the surface mounting terminal 41a.

  In FIG. 4, the method of forming the surface mounting terminals 41a using the wafer 41w before dicing has been described. However, this shows an example of forming with higher productivity. However, the surface mounting terminals 41a can be formed by the same method on the individual semiconductor chips after dicing.

  As a modification of the semiconductor element 41 shown in FIG. 4, an example in which the rewiring layer 41b and the surface mounting terminal 41a are formed as the same layer can be given. In this case, a layer of a conductive material is formed on the insulating layer 41d so as to have a pattern necessary for rewiring and to have a pattern of the surface mounting terminals 41a in contact with this pattern. This layer of conductive material fills the opening 71 formed in the insulating layer 41d. Then, the conductive material layer is formed so as to cover the entire surface with the insulating layer 41e except for the portion of the surface mounting terminal 41a. This also makes it possible to obtain a semiconductor element having the surface mounting terminals 41a in which the terminal pads 41c of the semiconductor device are rearranged.

  As described above, in the component built-in wiring board according to this embodiment, the built-in / embedded semiconductor element 41 has a semiconductor chip and a surface-mounting terminal 41a arranged in a grid pattern. Has terminal pads. The terminal pads of the semiconductor chip and the surface mounting terminals 41a are electrically connected. That is, the semiconductor element 41 is built in and mounted on the wiring board by the surface mounting terminals 41a arranged in a grid. Further, here, for this built-in mounting, the wiring layer 22 is provided with a pattern which is similar or congruent to the planar shape of each of the surface mounting terminals 41a of the semiconductor element 41 as the mounting land 22a.

  Since the semiconductor element 41 has the surface mounting terminals 41a, the surface mounting technology can be used to mount this on the wiring board. Therefore, it is not necessary to prepare a device for flip connection. Further, unlike the case of flip connection, the size of the work having the wiring pattern cannot be increased so much in order to ensure the alignment accuracy of the semiconductor chip with respect to the land. Furthermore, since the surface mounting terminals 41a are particularly in a grid arrangement, that is, in a plane arrangement, the planar area as the semiconductor element 41 can be reduced as much as possible, and the area as in the semiconductor chip can be reduced. The built-in ease is secured. The land 22a for the built-in component does not require the formation of Au plating, and does not require the formation of a solder resist around it.

  In particular, since the mounting land 22a has a similar or congruent pattern to the planar shape of each of the surface mounting terminals 41a of the semiconductor element 41, the shape of the solder 51 that interconnects the mounting land 22a and the surface mounting terminals 41a. The controllability is very high. That is, the spread of the solder 51 can be suppressed, and the solder 51 can be formed in a uniform shape between the terminals 41a, so that the reliability of electrical connection can be further improved.

  It should be noted that the relationship between the size of the planar shape of the mounting land 22a and the surface mounting terminal 41a may be appropriately determined as to which is larger. When the lands 22a are made smaller, there is a possibility that more wiring patterns can be passed between the lands 22a. When the terminal 41a is made smaller, the degree of freedom in pattern formation of the rewiring layer 41b may be further increased.

  In the present embodiment, a component built-in wiring board that can be manufactured at a low cost can be obtained while removing the cause of the deterioration of the adhesion of the insulating material and maintaining the soundness as the wiring board and the electrical reliability of the built-in component.

  The semiconductor element 41 to be embedded or buried is not a wafer level chip scale package as described above, but another package product (for example, an interpose substrate is provided between the semiconductor chip and the surface mounting element 41a). Form). In this case, the area and thickness of the element are inevitably larger than those of the wafer level / chip scale package, but this can be dealt with depending on the specifications of the board side used for component incorporation. Also in this case, the advantage that the same surface mounting technology as that applied to the chip component can be applied to the semiconductor element 41 is maintained.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 5 to 7 are process diagrams schematically showing a part of a manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 5 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 5 (a), a paste-like conductive composition that becomes the interlayer connection bodies 31 and 31a is substantially cone-shaped by, for example, screen printing on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example. It is formed in a bump shape (bottom diameter, eg, 200 μm, height, eg, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connectors 31, 31a are printed, they are dried and cured.

  Next, as shown in FIG. 5B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connectors 31, 31a, and the head is exposed. Like that. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection bodies 31 and 31a has an axis coinciding with the stacking direction, and the diameter changes in the axial direction). . Subsequently, as shown in FIG. 5C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connectors 31, 31a, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 5D, patterning by, for example, well-known photolithography is performed on the metal foil 22A on one side, and this is processed into the wiring layer 22 including the mounting land 22a. Then, as shown in FIG. 5E, cream solder 51A is printed and applied on the mounting land 22a obtained by the processing, for example, by screen printing. The cream solder 51A can be easily printed in a predetermined pattern by using screen printing. A dispenser can be used instead of screen printing.

  For the cream solder 51A, a conductive composition before curing may be used instead. When the conductive composition is used, heat resistance after curing is high, and it is possible to effectively prevent poor connection due to heat applied during component mounting as a wiring board after completion.

  Next, the semiconductor element 41 is mounted on the mounting land through the cream solder 51A, for example, with a mounter, and then heated to reflow the cream solder 51A. As described above, the wiring board material 1 in a state where the semiconductor element 41 is connected to the mounting land 22a of the wiring layer 22 through the solder 51 as shown in FIG. A subsequent process using the wiring board material 1 will be described with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 6 shows a manufacturing process of a portion centering on the insulating layer 13 and the same 12 in each configuration shown in FIG. First, as shown in FIG. 6A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through hole 82 for forming a through-hole conductor is formed at a predetermined position, and a component opening 81 is formed in a portion corresponding to the built-in semiconductor element 41.

  Next, electroless plating and electrolytic plating are performed to form the through-hole conductor 33 on the inner wall of the through hole 82 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 81. Further, as shown in FIG. 6C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 81 is also removed.

  Next, as shown in FIG. 6 (d), conductive bumps (bottom diameter: 200 μm, height: 160 μm, for example) that will become the interlayer connector 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 6E, an FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. In the prepreg 12A, an opening corresponding to the built-in semiconductor element 41, similar to the insulating layer 13, is provided in advance.

  In the stacking step of FIG. 6E, the head of the interlayer connector 32 is made to penetrate the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 6 (e) indicates that there are both cases where the head part is plastically deformed and crushed at this stage, and when it is not plastically deformed. The wiring board material obtained as described above is referred to as a wiring board material 2.

  The steps shown in FIG. 6 can be performed as follows. In the stage of FIG. 6A, only the through hole 82 is formed and the subsequent steps from FIG. 6B to FIG. 6D are performed without forming the opening 81 for the built-in component. Next, as a step corresponding to FIG. 6E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 7 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked. Here, the upper wiring board material 3 shown in the figure applies the same process as that of the lower wiring board material 1, and thereafter, the interlayer connector 34 and the prepreg 14A are connected to the interlayer connector in the intermediate wiring board material 2 shown in the figure. 32 and the prepreg 12A.

  However, the wiring board material 3 is configured without a component (semiconductor element 41) and a portion (mounting land) for connecting the component (semiconductor element 41), and further, no opening is provided in the prepreg 14A. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. The prepregs 12A and 14A are completely cured by pressurization and heating in the press machine, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the semiconductor element 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively.

  After the laminating process shown in FIG. 7, the upper and lower metal foils 26A and 21A are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. Further, for the interlayer connectors 31, 31a, 32, 34, 35, in addition to those derived from the conductive bumps obtained by printing the conductive composition described above, for example, metal bumps formed by metal plate etching, conductive compositions It is possible to appropriately select and employ a connection body by filling an object, a conductor bump formed by plating, or the like. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 5D) other than patterning after the last lamination step. May be.

  Further, in the laminating process shown in FIG. 7, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating layer 11) of the wiring board material 1. In this case, the mounted semiconductor element 41 seems to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance. However, in the case of a sufficiently thin component as the semiconductor element 41, what is actually an interference factor? Don't be. In the step of laminating the prepreg 12A, the prepreg 12A can be uniformly laminated in the in-plane direction by pressing and heating with a cushioning material capable of absorbing the thickness of the semiconductor element 41 interposed.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. The bottom view and sectional drawing which show the semiconductor element 41 used for the component built-in wiring board shown in FIG. 1 typically in some detail. FIG. 2 is a plan view schematically showing a partial configuration of a wiring layer 22 shown in FIG. 1. Process drawing which shows the example of a manufacture process in the cross section about the semiconductor element 41 used for the component built-in wiring board shown in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Wiring board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 13A ... Prepreg, 14 ... Insulating layer, 14A ... Prepreg, 15 ... Insulating layer, 21 ... Wiring layer (wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (wiring pattern), 22a ... Land for mounting, 22A ... Metal foil (copper foil) , 23 ... wiring layer (wiring pattern), 23A ... metal foil (copper foil), 24 ... wiring layer (wiring pattern), 24A ... metal foil (copper foil), 25 ... wiring layer (wiring pattern), 26 ... wiring layer (Wiring pattern), 26A ... metal foil (copper foil), 31, 31a, 32, 34, 35 ... interlayer connection (conductive bump by conductive composition printing), 33 ... through-hole conductor, 41 ... semiconductor element (Wafer level chip 41a ... surface mounting terminals, 41b ... redistribution layer, 41c ... terminal pads, 41d, 41e ... insulating layer, 41w ... semiconductor wafer, 51 ... connecting member (solder or conductive composition), 51A ... Cream solder or conductive composition before curing, 61, 62 ... solder resist, 71, 72 ... opening, 81 ... opening for parts, 82 ... through hole.

Claims (3)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A semiconductor element comprising a semiconductor chip embedded in the second insulating layer and having a terminal pad; and a grid-arranged surface mounting terminal electrically connected to the terminal pad;
It is provided between the first insulating layer and the second insulating layer, and faces each of the surface mounting terminals of the semiconductor element, and each is similar to the planar shape of each of the surface mounting terminals, or A first wiring pattern having a pattern of a congruent figure as a mounting land for the semiconductor element;
Contact the surface mounting terminals and contact the mounting lands so as to interconnect each of the surface mounting terminals of the semiconductor element and each of the mounting lands of the first wiring pattern. Provided with a reflowed solder part,
At least a part of the mounting lands of the first wiring pattern is an island pattern, and there is no wiring drawing as a pattern,
A second wiring pattern provided on the side of the first insulating layer opposite to the side on which the first wiring pattern is located;
The conductive composition is interposed between the surface of the mounting land and the surface of the second wiring pattern through the first insulating layer and in the stacking direction. A component built-in wiring board, further comprising: an interlayer connector having a shape having a matching axis and a diameter changing in the direction of the axis. The second insulating layer is a stack of at least two insulating layers;
A third wiring pattern provided between the at least two insulating layers;
A conductive composition comprising a portion of the second insulating layer in the stacking direction and sandwiched between the surface of the first wiring pattern and the surface of the third wiring pattern; 2. The component built-in wiring board according to claim 1, further comprising: a second interlayer connection body having an axis that coincides with the direction and having a shape that changes in diameter in the direction of the axis.   The component built-in wiring board according to claim 1, wherein the surface mounting terminal of the semiconductor element is an LGA terminal.

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