JP2007335487A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2007335487A
JP2007335487A JP2006163137A JP2006163137A JP2007335487A JP 2007335487 A JP2007335487 A JP 2007335487A JP 2006163137 A JP2006163137 A JP 2006163137A JP 2006163137 A JP2006163137 A JP 2006163137A JP 2007335487 A JP2007335487 A JP 2007335487A
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Prior art keywords
electrically insulating
insulating substrate
semiconductor element
semiconductor device
wiring
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JP2006163137A
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JP2007335487A5 (en
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Tomoe Sasaki
智江 佐々木
Toshiyuki Asahi
俊行 朝日
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2006163137A priority Critical patent/JP2007335487A/en
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Publication of JP2007335487A5 publication Critical patent/JP2007335487A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can establish electrical connection stable to thermal stress and wherein semiconductor elements can be arranged in three-dimensional manner. <P>SOLUTION: The semiconductor device is provided with: a semiconductor element 7 provided with a plurality of external terminals 8; a wiring substrate 4 formed of a first electrically insulating base 1 and a wiring pattern 10 that is provided with a connection pad 2 formed in the first electrically insulating base 1; and a second electrically insulating base 5 to adhere the semiconductor element 7 to the wiring substrate 4. In this case, the external terminal 8 and the connection pad 2 are electrically connected with each other through a via 6 formed in the second electrically insulating base 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子を配線基板に実装した半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device in which a semiconductor element is mounted on a wiring board, and a manufacturing method thereof.

近年、電子機器には高性能化および小型化の要求が高まっており、これらの電子機器に組み込まれる電子部品の高密度実装化と機能ごとにモジュール化する動きが急速に進んでいる。   In recent years, demands for high performance and miniaturization of electronic devices have been increasing, and the movement of high density mounting of electronic components incorporated in these electronic devices and modularization for each function is rapidly progressing.

高密度実装の手法として、半田ボールを有する半導体素子を回路基板にフェースダウン実装する方法がある。   As a high-density mounting method, there is a method in which a semiconductor element having solder balls is mounted face-down on a circuit board.

フェースダウン実装においては、マトリクス状に配置された複数の半田ボールを有する半導体素子を、マトリクス状に配置された複数の接続パッドを有する配線基板上に、それぞれ対応する接続パッドに接合させてフェースダウン実装し、配線基板とこれに搭載された半導体素子の隙間に対してアンダーフィル剤が充填される。これは、アンダーフィル剤が充填されない状態では、配線基板および半導体素子における面内方向の熱膨張率の差に起因した応力・歪が、電気接続部に集中し、信頼性が低くなるからである。   In face-down mounting, a semiconductor element having a plurality of solder balls arranged in a matrix is bonded to a corresponding connection pad on a wiring board having a plurality of connection pads arranged in a matrix. The underfill agent is filled in the gap between the wiring board and the semiconductor element mounted thereon. This is because in a state where the underfill agent is not filled, stress and strain due to the difference in the thermal expansion coefficient in the in-plane direction between the wiring board and the semiconductor element are concentrated on the electrical connection portion, and the reliability is lowered. .

また、近年では、更なる小型化・高機能化の手法として、半導体素子や電子部品を基板に内蔵した三次元実装形態の部品内蔵基板も実現されている。半導体素子を収納する凹部をセラミック基板内に設け、三次元的に配置した構造のものも出願されている。   In recent years, as a technique for further miniaturization and higher functionality, a component-embedded substrate having a three-dimensional mounting form in which a semiconductor element and an electronic component are embedded in the substrate has been realized. An application has also been filed in which a concave portion for housing a semiconductor element is provided in a ceramic substrate and arranged three-dimensionally.

なお、この出願の発明に関する先行技術文献として、例えば特許文献１〜３が知られている。
特開２０００−２９４５１９号公報 特開２００５−３４７３６２号公報 特開平５−８２７１０号公報 For example, Patent Documents 1 to 3 are known as prior art documents relating to the invention of this application.
JP 2000-294519 A JP 2005-347362 A JP-A-5-82710

しかしながら、アンダーフィルを採用した従来の技術においては、マザー基板上にモジュール化された半導体装置を実装する際、リフロー工程で半導体素子を実装している半田が再溶融し半田どうしがショートしたり、アンダーフィルと半田の接着力が低下する。そのため、再溶融した半田が再度固体化した後にアンダーフィルとの間に隙間が生じ、水分を吸収する要因となる。水分を吸収してしまうと、再度熱が加わる工程がある場合に水分に起因して、電気的接続がとれなくなるなど信頼性が低下するという課題がある。   However, in the conventional technology adopting underfill, when mounting a semiconductor device modularized on a mother board, the solder mounting the semiconductor element in the reflow process is remelted and the solders are short-circuited, The adhesive force between the underfill and solder is reduced. For this reason, after the remelted solder is solidified again, a gap is formed between the remelted solder and the underfill, which causes moisture absorption. If moisture is absorbed, there is a problem that reliability is lowered such that electrical connection is lost due to moisture when there is a process in which heat is applied again.

本発明は、このような課題のもとで考えだされたものであって、熱に対し安定な電気的接続を実現し、モジュール化に適した半導体装置を提供することを目的とする。   The present invention has been conceived under such a problem, and an object of the present invention is to provide a semiconductor device that realizes a stable electrical connection against heat and is suitable for modularization.

上記目的を達成するために、本発明は、複数の外部端子を有した半導体素子と、第一の電気絶縁性基材と、前記第一の電気絶縁性基材に形成された接続パッドを有する配線パターンからなる配線基板と、前記半導体素子と前記配線基板を接着する第二の電気絶縁性基材で構成され、前記外部端子と前記接続パッドを前記第二の電気絶縁性基材に形成されたビアにより電気的に接続することを特徴とする半導体装置であり、半田を用いずに再溶融しないビアにより接続することにより信頼性の高い半導体装置を提供することができる。また、第二の電気絶縁性基材がアンダーフィルとして半導体素子と基板の間を接着することで信頼性が向上する。   In order to achieve the above object, the present invention includes a semiconductor element having a plurality of external terminals, a first electrically insulating substrate, and a connection pad formed on the first electrically insulating substrate. The wiring board is composed of a wiring pattern and a second electrically insulating base material for bonding the semiconductor element and the wiring board, and the external terminals and the connection pads are formed on the second electrically insulating base material. The semiconductor device is characterized in that it is electrically connected by a via, and a highly reliable semiconductor device can be provided by connecting by a via that does not remelt without using solder. Further, the reliability is improved by bonding the second electrically insulating base material between the semiconductor element and the substrate as an underfill.

以上のように、本発明の半導体装置は、電気絶縁性基材に形成されたビアを用いて半導体素子と配線基板の接続を行い、信頼性の高い半導体装置が得られるという効果を奏するものである。   As described above, the semiconductor device of the present invention has an effect of obtaining a highly reliable semiconductor device by connecting a semiconductor element and a wiring board using vias formed in an electrically insulating base material. is there.

（実施の形態１）
以下、実施の形態１を用いて、本発明の特に請求項１，３〜７に記載の発明について図面を参照しながら説明する。 (Embodiment 1)
Hereinafter, the first and third aspects of the present invention will be described with reference to the drawings, using the first embodiment.

図１は、本実施の形態１における半導体装置の断面図である。図１において、半導体素子７は、外部端子８を有しており、配線基板４は、第一の電気絶縁性基材１と、第一の電気絶縁性基材１に形成された接続パッド２および配線パターン１０と、両面の配線パターン間を電気的に接続するスルーホール３からなる。第二の電気絶縁性基材５は半導体素子７と配線基板４を接着し、外部端子８と接続パッド２を接続する第一のビア６を有している。   FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. In FIG. 1, a semiconductor element 7 has an external terminal 8, and a wiring board 4 includes a first electrically insulating substrate 1 and connection pads 2 formed on the first electrically insulating substrate 1. And the wiring pattern 10 and the through hole 3 for electrically connecting the wiring patterns on both sides. The second electrically insulating substrate 5 has a first via 6 that bonds the semiconductor element 7 and the wiring substrate 4 and connects the external terminal 8 and the connection pad 2.

本発明において半導体素子７は外部端子８を再配線し、図７，８に示すようにマトリクス状に配置してもよい。マトリクス状に配置することで、ビアや配線パターンの形成が容易となる。また、外部端子を銅ポストとすることで、ビアとの接続信頼性を高めることができる。なお、図７の底面図に示すように複数の外部端子８は、例えば１１行×１１列すべて形成されているものでも、図８の底面図に示すような周辺部のみに形成されているものを用いてもよく、特に限定するものではない。また、外部端子に使用する金属は、金、銀、パラジウムなどの導電性の高い金属であってもよい。   In the present invention, the semiconductor elements 7 may be arranged in a matrix as shown in FIGS. By arranging in a matrix, vias and wiring patterns can be easily formed. Further, the reliability of connection with the via can be enhanced by using a copper post as the external terminal. As shown in the bottom view of FIG. 7, the plurality of external terminals 8 are formed only in the peripheral portion as shown in the bottom view of FIG. There is no particular limitation. The metal used for the external terminal may be a highly conductive metal such as gold, silver, or palladium.

さらに銅ポストからなる外部端子８が、エポキシ樹脂やポリイミド樹脂などからなる封止膜１１の下面と平滑になるように設けられているものを用いることにより、第二の電気絶縁性基材５と隙間なく接着することができる。   Further, by using the external terminal 8 made of a copper post so as to be smooth with the lower surface of the sealing film 11 made of an epoxy resin, a polyimide resin or the like, the second electrically insulating substrate 5 and Can be bonded without gaps.

配線基板４は、ガラス織布にエポキシ樹脂を含浸させた基板（ガラス−エポキシ基板）、アラミド繊維不織布にエポキシ樹脂を含浸させた基板（アラミド−エポキシ基板）、紙にフェノール樹脂を含浸させた基板（紙−フェノール基板）、多孔質のフィルム基材に未硬化のエポキシ樹脂を空孔が残るように含浸させたフィルム基材を使ったフレキシブル基板、セラミックス基板、樹脂（例えば熱硬化性樹脂および／または熱可塑性樹脂）と無機フィラーとを含むコンポジット材料からなる基板など任意の基板から目的に応じて選択し使用できる。   The wiring board 4 includes a substrate in which a glass woven fabric is impregnated with an epoxy resin (glass-epoxy substrate), a substrate in which an aramid fiber nonwoven fabric is impregnated with an epoxy resin (aramid-epoxy substrate), and a substrate in which paper is impregnated with a phenol resin. (Paper-phenol substrate), a flexible substrate, a ceramic substrate, a resin (for example, a thermosetting resin and / or a film substrate in which a porous film substrate is impregnated with an uncured epoxy resin so that pores remain. Alternatively, any substrate such as a substrate made of a composite material containing a thermoplastic resin and an inorganic filler can be selected and used according to the purpose.

配線基板４にコンポジット材料を用いた場合、熱膨張差に起因する接続部の接続信頼性を損なうことなく半導体素子を実装することができる。   When a composite material is used for the wiring substrate 4, a semiconductor element can be mounted without impairing the connection reliability of the connection portion due to the difference in thermal expansion.

スルーホール３は、両面の配線パターン間を接続する機能を有し、ビアホール形成後、めっきすることによって形成できる。めっきは金、銀、銅またはニッケルなどを用いることができる。また、本実施の形態においてはスルーホールを例に挙げているが、インナービアによって層間接続を行ってもよい。たとえば、導電性の粒子と熱硬化性の樹脂からなる導電性ペーストを用いたインナービアでもよい。   The through hole 3 has a function of connecting the wiring patterns on both sides, and can be formed by plating after forming the via hole. For the plating, gold, silver, copper, nickel, or the like can be used. In the present embodiment, a through hole is taken as an example, but interlayer connection may be performed by an inner via. For example, an inner via using a conductive paste made of conductive particles and a thermosetting resin may be used.

配線基板４のスルーホール３と、第二の電気絶縁性基材に形成されている第一、第二のビア６，９のビアホールの形成は、レーザ加工によって形成する。レーザ加工の光源には、炭酸ガスレーザやＹＡＧレーザ、エキシマレーザが用いられる。レーザ加工では、小径の貫通穴を短時間で形成することができ、生産性に優れた加工を実現できる。また、スルーホール３は、パンチ加工、ドリル加工を用いてもよく、ドリル加工やパンチング加工を用いる場合、汎用性のある既存の設備でビアホールの形成が可能である。   The through holes 3 of the wiring board 4 and the via holes of the first and second vias 6 and 9 formed in the second electrically insulating base material are formed by laser processing. A carbon dioxide laser, YAG laser, or excimer laser is used as a light source for laser processing. In laser processing, a small-diameter through hole can be formed in a short time, and processing with excellent productivity can be realized. The through hole 3 may be punched or drilled. When drilling or punching is used, a via hole can be formed with existing versatile equipment.

接続パッド２および配線パターン１０は、電気伝導性を有する物質からなり、例えば金属箔や導電性樹脂組成物、金属板を加工したリードフレームを用いることができる。金属箔やリードフレームを用いることにより、エッチング等により微細な配線パターンの作成が容易となる。また、金属箔においては、離型フィルムを用いた転写等による配線パターンの形成も可能となる。特に銅箔はコストも安く、電気伝導性も高いため好ましい。また、これらの接続パッド２および配線パターン１０は表面にメッキ処理をすることにより、耐食性や電気伝導性を向上させることができる。また、接続パッド２および配線パターン１０の第二の電気絶縁性基材５との接触面を粗化することで、第二の電気絶縁性基材５との接着性を向上させることができる。粗化の処理は、反応性ガスを用いたドライエッチング加工、サンドブラストによる機械加工、および電解エッチング加工が挙げられる。   The connection pad 2 and the wiring pattern 10 are made of a material having electrical conductivity. For example, a metal foil, a conductive resin composition, or a lead frame processed from a metal plate can be used. By using a metal foil or a lead frame, a fine wiring pattern can be easily created by etching or the like. In addition, in the metal foil, a wiring pattern can be formed by transfer using a release film. In particular, copper foil is preferable because it is inexpensive and has high electrical conductivity. Further, the connection pad 2 and the wiring pattern 10 can be improved in corrosion resistance and electrical conductivity by plating the surface. Moreover, the adhesiveness with the 2nd electrical insulation base material 5 can be improved by roughening the contact surface with the 2nd electrical insulation base material 5 of the connection pad 2 and the wiring pattern 10. FIG. Examples of the roughening treatment include dry etching using a reactive gas, machining by sandblasting, and electrolytic etching.

第二の電気絶縁性基材５は、樹脂（例えば熱硬化性樹脂および／または熱可塑性樹脂）と無機フィラーとを含むコンポジット材料から形成されており、樹脂として熱硬化性樹脂を用いるのが好ましい。尚、無機フィラーを実質的に用いずに、熱硬化性樹脂のみから第二の電気絶縁性基材５を構成することも可能である。熱硬化性樹脂は、例えばエポキシ樹脂等であり、無機フィラーを添加する場合、例えばＡｌ2Ｏ3、ＳｉＯ2、ＭｇＯ、ＢＮ、ＡｌＮ等のフィラーを使用できる。無機フィラーの添加により、第二の電気絶縁性基材５の種々の物性を制御することができるので、無機フィラーを含むコンポジット材料から第二の電気絶縁性基材を形成することが好適である。 The second electrically insulating substrate 5 is formed of a composite material containing a resin (for example, a thermosetting resin and / or a thermoplastic resin) and an inorganic filler, and it is preferable to use a thermosetting resin as the resin. . In addition, it is also possible to comprise the 2nd electrically insulating base material 5 only from a thermosetting resin, without using an inorganic filler substantially. The thermosetting resin is, for example, an epoxy resin. When an inorganic filler is added, for example, a filler such as Al 2 O 3 , SiO 2 , MgO, BN, and AlN can be used. Since various physical properties of the second electrically insulating substrate 5 can be controlled by adding the inorganic filler, it is preferable to form the second electrically insulating substrate from the composite material containing the inorganic filler. .

第一のビア６は導電性の粒子と非導電性の樹脂とを含有した導電性ペーストを用いることができる。導電性の粒子としては、金、銀、銅又はニッケルなどを用いることができる。金、銀、銅又はニッケルは導電性が高いため好ましく、銅は導電性が高くマイグレーションも少ないため特に好ましい。銅を銀で被覆した導電性の粒子を用いても、マイグレーションの少なさと導電性の高さ、両方の特性を満たすことができる。非導電性の樹脂としては、熱硬化性樹脂を用いることが好ましく、たとえば、エポキシ樹脂、フェノール樹脂又はイソシアネート樹脂を用いることができる。エポキシ樹脂は、耐熱性が高いため特に好ましい。   For the first via 6, a conductive paste containing conductive particles and a non-conductive resin can be used. Gold, silver, copper, nickel, or the like can be used as the conductive particles. Gold, silver, copper, or nickel is preferable because of its high conductivity, and copper is particularly preferable because of its high conductivity and low migration. Even when conductive particles in which copper is coated with silver are used, the characteristics of both low migration and high conductivity can be satisfied. As the non-conductive resin, a thermosetting resin is preferably used, and for example, an epoxy resin, a phenol resin, or an isocyanate resin can be used. Epoxy resins are particularly preferred because of their high heat resistance.

また、第二の電気絶縁性基材に形成されている第一のビア６は、半導体素子７の外部端子８と接続するようにマトリクス状に形成されており、図３に示すように外部端子８よりも小さいことが好ましい。これにより、半導体素子７が押圧された時に導電性ペーストのはみ出しや広がりを抑えることができ、より信頼性を高めることができる。また、半導体素子７を実装する時、第一のビア６と外部端子８の位置ズレを防止し、半導体素子の外部端子８と電気絶縁性基材が接触することで、より強固に接着することができる。   Further, the first vias 6 formed in the second electrically insulating substrate are formed in a matrix so as to be connected to the external terminals 8 of the semiconductor element 7, and as shown in FIG. Preferably it is less than 8. Thereby, when the semiconductor element 7 is pressed, the protrusion and spread of the conductive paste can be suppressed, and the reliability can be further improved. In addition, when mounting the semiconductor element 7, the first via 6 and the external terminal 8 are prevented from being misaligned, and the external terminal 8 of the semiconductor element and the electrically insulating base material are in contact with each other to be more firmly bonded. Can do.

以上のように、本実施の形態によれば、半田を用いずに再溶融しないビアにより接続することができ、熱に対して安定した電気的接続を実現し、ショートや吸湿がしにくい信頼性の高い半導体装置を提供することができる。   As described above, according to the present embodiment, it is possible to connect via vias that do not remelt without using solder, realize stable electrical connection against heat, and are less likely to cause short circuit or moisture absorption. A semiconductor device with a high level can be provided.

（実施の形態２）
以下、実施の形態２を用いて、本発明の特に請求項２に記載の発明について図面を参照ながら説明する。なお、実施の形態１と同一の構造については、同一番号を付与してその説明を省略する。 (Embodiment 2)
Hereinafter, the second aspect of the present invention will be described with reference to the drawings. In addition, about the structure same as Embodiment 1, the same number is provided and the description is abbreviate | omitted.

図２は、本実施の形態２における半導体装置の断面図である。図２において、半導体素子７は、外部端子８を有しており、配線基板４は、第一の電気絶縁性基材１と、第一の電気絶縁性基材１に形成された接続パッド２および配線パターン１０と、両面の配線パターン間を電気的に接続するスルーホール３からなる。第二の電気絶縁性基材５は半導体素子７を内蔵し、複数の配線基板４を厚さ方向に積層している。第二の電気絶縁性基材５には、外部端子８と接続パッド２を接続する第一のビア６と、厚さ方向に積層された配線基板４の対向するパターンを電気的に接続する第二のビア９を有している。   FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment. In FIG. 2, the semiconductor element 7 has an external terminal 8, and the wiring board 4 includes a first electrically insulating substrate 1 and connection pads 2 formed on the first electrically insulating substrate 1. And the wiring pattern 10 and the through hole 3 for electrically connecting the wiring patterns on both sides. The second electrically insulating substrate 5 contains a semiconductor element 7, and a plurality of wiring boards 4 are laminated in the thickness direction. The second electrically insulating base 5 is electrically connected to the first via 6 for connecting the external terminal 8 and the connection pad 2 and the opposing pattern of the wiring board 4 laminated in the thickness direction. It has two vias 9.

本発明において、第一の電気絶縁性基材１は、第二の電気絶縁性基材５と同様の樹脂と無機フィラーとを含むコンポジット材料を用いることもできる。これにより、熱膨張差に起因する接続部の接続信頼性を損なうことなく半導体素子を内蔵することができる。また、製造コストも抑えることができる。   In the present invention, the first electrically insulating substrate 1 may be a composite material containing the same resin and inorganic filler as the second electrically insulating substrate 5. Thereby, a semiconductor element can be built in without impairing the connection reliability of the connection part resulting from a thermal expansion difference. Further, the manufacturing cost can be suppressed.

図２において、第二のビア９は、第一のビア６と同様のものを用いることもできる。また、図２において、インナービアの例を示しているが、第二のビア９においては、スルーホールにより層間接続を行ってもよい。   In FIG. 2, the second via 9 can be the same as the first via 6. Further, in FIG. 2, an example of the inner via is shown, but in the second via 9, interlayer connection may be performed by a through hole.

以上のように、本実施の形態によれば、半導体素子の周囲を同じ熱膨張係数の電気絶縁性基材で囲むことで、熱膨張係数に起因する接続部の接続信頼性を損なうことなく半導体素子を内蔵することができ、高密度な半導体装置をモジュールとして提供できる。   As described above, according to the present embodiment, the semiconductor element is surrounded by the electrically insulating base material having the same thermal expansion coefficient, so that the connection reliability of the connection portion due to the thermal expansion coefficient is not impaired. An element can be incorporated and a high-density semiconductor device can be provided as a module.

（実施の形態３）
以下、実施の形態３を用いて、本発明の特に請求項８に記載の発明について図面を参照しながら説明する。なお、実施の形態１と同一の構造については、同一番号を付与してその説明を省略する。 (Embodiment 3)
The third embodiment of the present invention will be described below with reference to the drawings. In addition, about the structure same as Embodiment 1, the same number is provided and the description is abbreviate | omitted.

図４（ａ）〜（ｃ）は、本実施の形態３における半導体装置の製造工程を示す断面図である。   4A to 4C are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the third embodiment.

図４（ａ）は、第一のビア６が形成された第二の電気絶縁性基材５を示している。次に、図４（ｂ）に示すように、第一のビア６と接続パッド２が接触するように第二の電気絶縁性基材５を配線基板４に積層する。   FIG. 4A shows the second electrically insulating substrate 5 on which the first via 6 is formed. Next, as shown in FIG. 4B, the second electrically insulating base material 5 is laminated on the wiring board 4 so that the first via 6 and the connection pad 2 are in contact with each other.

次に図４（ｃ）に示すように、外部端子８とビア６が接触するように半導体素子７を第二の電気絶縁性基材５に実装する。この時、ビアをアライメントマークとして使用することもできる。その後、外部から熱を加えて第二の電気絶縁性基材５と第一のビア６を硬化する。この時、半導体素子７の上面からヒートツールにより加熱・加圧により硬化を行っても良い。また、オーブン、真空ラミネータ、真空熱プレスを用いて硬化を行ってもよい。   Next, as shown in FIG. 4C, the semiconductor element 7 is mounted on the second electrically insulating substrate 5 so that the external terminals 8 and the vias 6 are in contact with each other. At this time, a via can also be used as an alignment mark. Thereafter, heat is applied from the outside to cure the second electrically insulating substrate 5 and the first via 6. At this time, curing may be performed from the upper surface of the semiconductor element 7 by heating and pressing with a heat tool. Further, curing may be performed using an oven, a vacuum laminator, or a vacuum hot press.

硬化する前には電気的導通検査を行ってもよい。これにより、半導体素子７や第一のビア６が不良であった場合に、容易にリペアすることができる。   An electrical continuity test may be performed before curing. Thereby, when the semiconductor element 7 or the first via 6 is defective, it can be easily repaired.

以上のように、本実施の形態によれば、半田を用いずに再溶融しないビアにより接続することができ、熱に対して安定した電気的接続を実現し、ショートや吸湿がしにくい信頼性の高い半導体装置を提供することができる。   As described above, according to the present embodiment, it is possible to connect via vias that do not remelt without using solder, realize stable electrical connection against heat, and are less likely to cause short circuit or moisture absorption. A semiconductor device with a high level can be provided.

（実施の形態４）
以下、実施の形態４を用いて、本発明の特に請求項９に記載の発明について図面を参照しながら説明する。なお、実施の形態１と同一の構造については、同一番号を付与してその説明を省略する。 (Embodiment 4)
Hereinafter, the fourth aspect of the present invention will be described with reference to the drawings. In addition, about the structure same as Embodiment 1, the same number is provided and the description is abbreviate | omitted.

図５（ａ）〜（ｇ）は、本実施の形態４における半導体装置の製造工程を示す断面図である。   5A to 5G are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fourth embodiment.

図５（ａ）は、第一のビア６が形成された第二の電気絶縁性基材５を示している。次に、図５（ｂ）に示すように、第一のビア６と接続パッド２が接触するように第二の電気絶縁性基材５を配線基板４に積層する。   FIG. 5A shows the second electrically insulating substrate 5 on which the first via 6 is formed. Next, as shown in FIG. 5B, the second electrically insulating base material 5 is laminated on the wiring board 4 so that the first via 6 and the connection pad 2 are in contact with each other.

次に、図５（ｃ）に示すように、外部端子８と第一のビア６が接触するように半導体素子７を第二の電気絶縁性基材５に実装する。   Next, as shown in FIG. 5C, the semiconductor element 7 is mounted on the second electrically insulating substrate 5 so that the external terminal 8 and the first via 6 are in contact with each other.

次に、図５（ｄ）に示すように、別の第二の電気絶縁性基材１３にキャビティ１２を形成する。   Next, as shown in FIG. 5D, the cavity 12 is formed in another second electrically insulating base material 13.

次に、図５（ｅ）に示すように、キャビティ１２に半導体素子７を収納するように第二の電気絶縁性基材１３を積層する。   Next, as shown in FIG. 5E, a second electrically insulating base material 13 is laminated so that the semiconductor element 7 is accommodated in the cavity 12.

次に、図５（ｆ）に示すように、キャビティ１２が形成された第二の電気絶縁性基材１３上にさらに別の第二の電気絶縁性基材１４及び配線基板１５を積層する。   Next, as shown in FIG. 5F, another second electrically insulating base material 14 and a wiring board 15 are laminated on the second electrically insulating base material 13 in which the cavity 12 is formed.

次に、図５（ｇ）に示すように、第二の電気絶縁性基材５，１３，１４と第一、第二のビア６，９を硬化し、半導体素子７を埋設する。その後、外部から熱を加えて第二の電気絶縁性基材５，１３，１４と第一、第二のビア６，９を硬化する。この時、半導体素子の上面からヒートツールにより加熱・加圧により硬化を行っても良い。また、オーブン、真空ラミネータ、真空熱プレスを用いて硬化を行ってもよい。   Next, as shown in FIG. 5G, the second electrically insulating base materials 5, 13, 14 and the first and second vias 6, 9 are cured, and the semiconductor element 7 is embedded. Thereafter, heat is applied from the outside to cure the second electrically insulating base materials 5, 13, 14 and the first and second vias 6, 9. At this time, curing may be performed by heating and pressing with a heat tool from the upper surface of the semiconductor element. Further, curing may be performed using an oven, a vacuum laminator, or a vacuum hot press.

キャビティ１２の形成は、たとえば打ち抜き加工やパンチ加工、レーザ加工によって行う。打ち抜き加工やパンチング加工の場合、汎用性のある既存の設備でキャビティの形成が可能である。   The cavity 12 is formed by, for example, punching, punching, or laser processing. In the case of punching or punching, a cavity can be formed with existing versatile equipment.

以上のように、本実施の形態によれば、半導体素子の周囲を同じ熱膨張係数の電気絶縁性基材で囲むことで、熱膨張係数に起因する接続部の接続信頼性を損なうことなく半導体素子を内蔵することができ、高密度な半導体装置をモジュールとして提供できる。   As described above, according to the present embodiment, the semiconductor element is surrounded by the electrically insulating base material having the same thermal expansion coefficient, so that the connection reliability of the connection portion due to the thermal expansion coefficient is not impaired. An element can be incorporated and a high-density semiconductor device can be provided as a module.

（実施の形態５）
以下、実施の形態５を用いて、本発明の特に請求項１０に記載の発明について図面を参照しながら説明する。なお、実施の形態１および４と同一の構造については、同一番号を付与してその説明を省略する。 (Embodiment 5)
The fifth embodiment of the present invention will be described below with reference to the drawings. In addition, about the same structure as Embodiment 1 and 4, the same number is provided and the description is abbreviate | omitted.

図６（ａ）〜（ｇ）は、本実施の形態５における半導体装置の製造工程を示す断面図である。   6A to 6G are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fifth embodiment.

図６（ａ）は、第一のビア６が形成された第二の電気絶縁性基材５を示している。次に、図６（ｂ）に示すように、第一のビア６と接続パッド２が接触するように第二の電気絶縁性基材５を配線基板４に積層する。   FIG. 6A shows the second electrically insulating substrate 5 on which the first via 6 is formed. Next, as shown in FIG. 6B, the second electrically insulating base material 5 is laminated on the wiring board 4 so that the first via 6 and the connection pad 2 are in contact with each other.

次に、図６（ｃ）に示すように、別の第二の電気絶縁性基材１３にキャビティ１２を形成する。   Next, as shown in FIG. 6C, the cavity 12 is formed in another second electrically insulating substrate 13.

次に、図６（ｄ）に示すように、配線基板４に積層された第二の電気絶縁性基材５とキャビティ１２が形成された第二の電気絶縁性基材１３を積層する。   Next, as shown in FIG. 6D, the second electrically insulating substrate 5 laminated on the wiring board 4 and the second electrically insulating substrate 13 formed with the cavity 12 are laminated.

次に、図６（ｅ）に示すように、キャビティ１２に半導体素子７を収納し、外部端子８と第一のビア６が接触するように半導体素子７を第二の電気絶縁性基材５に実装する。   Next, as shown in FIG. 6 (e), the semiconductor element 7 is accommodated in the cavity 12, and the semiconductor element 7 is placed in the second electrically insulating base 5 so that the external terminal 8 and the first via 6 are in contact with each other. To implement.

次に、図６（ｆ）に示すように、キャビティ１２が形成された第二の電気絶縁性基材１３上にさらに別の第二の電気絶縁性基材１４及び配線基板１５を積層する。   Next, as shown in FIG. 6F, another second electrically insulating base material 14 and wiring board 15 are laminated on the second electrically insulating base material 13 in which the cavity 12 is formed.

次に、図６（ｇ）に示すように、第二の電気絶縁性基材５，１３，１４と第一、第二のビア６，９を硬化し、半導体素子７を埋設する。その後、外部から熱を加えて第二の電気絶縁性基材５，１３，１４と第一、第二のビア６，９を硬化する。この時、半導体素子の上面からヒートツールにより加熱・加圧により硬化を行っても良い。また、オーブン、真空ラミネータ、真空熱プレスを用いて硬化を行ってもよい。   Next, as shown in FIG. 6G, the second electrically insulating base materials 5, 13, 14 and the first and second vias 6, 9 are cured, and the semiconductor element 7 is embedded. Thereafter, heat is applied from the outside to cure the second electrically insulating base materials 5, 13, 14 and the first and second vias 6, 9. At this time, curing may be performed by heating and pressing with a heat tool from the upper surface of the semiconductor element. Further, curing may be performed using an oven, a vacuum laminator, or a vacuum hot press.

以上のように、本実施の形態によれば、半導体素子の周囲を同じ熱膨張係数の電気絶縁性基材で囲むことで、熱膨張係数に起因する接続部の接続信頼性を損なうことなく半導体素子を内蔵することができ、高密度な半導体装置をモジュールとして提供できる。   As described above, according to the present embodiment, the semiconductor element is surrounded by the electrically insulating base material having the same thermal expansion coefficient, so that the connection reliability of the connection portion due to the thermal expansion coefficient is not impaired. An element can be incorporated and a high-density semiconductor device can be provided as a module.

本発明の半導体装置は、電気絶縁性基材に形成されたビアを用いて半導体素子と配線基板の接続を行うことで、半田を用いない半導体装置を提供することができ、熱に対して安定な電気的接続を実現する信頼性の高い半導体装置として有用である。   The semiconductor device of the present invention can provide a semiconductor device that does not use solder by connecting a semiconductor element and a wiring board using a via formed in an electrically insulating base material, and is stable against heat. It is useful as a highly reliable semiconductor device that realizes an electrical connection.

本発明の実施の形態１における半導体装置を示す断面図Sectional drawing which shows the semiconductor device in Embodiment 1 of this invention 本発明の実施の形態２における半導体装置を示す断面図Sectional drawing which shows the semiconductor device in Embodiment 2 of this invention 本発明の外部端子とビアの接続部の一例を示す拡大断面図The expanded sectional view which shows an example of the connection part of the external terminal and via | veer of this invention 本発明の実施の形態３における半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 3 of this invention 本発明の実施の形態４における半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 4 of this invention 本発明の実施の形態５における半導体装置の製造方法を示す工程断面図Process sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 5 of this invention 本発明の外部端子の配置の一例を示す平面図The top view which shows an example of arrangement | positioning of the external terminal of this invention 本発明の外部端子の配置の一例を示す平面図The top view which shows an example of arrangement | positioning of the external terminal of this invention

符号の説明Explanation of symbols

１ 第一の電気絶縁性基材
２ 接続パッド
３ スルーホール
４，１５ 配線基板
５，１３，１４ 第二の電気絶縁性基材
６ 第一のビア
７ 半導体素子
８ 外部端子
９ 第二のビア
１０ 配線パターン
１１ 封止膜
１２ キャビティ DESCRIPTION OF SYMBOLS 1 1st electric insulation base material 2 Connection pad 3 Through hole 4,15 Wiring board 5,13,14 2nd electric insulation base material 6 1st via 7 Semiconductor element 8 External terminal 9 2nd via 10 Wiring pattern 11 Sealing film 12 Cavity

Claims (10)

複数の外部端子を有した半導体素子と、
第一の電気絶縁性基材と、前記第一の電気絶縁性基材に形成された接続パッドを有する配線パターンからなる配線基板と、
前記半導体素子と前記配線基板を接着する第二の電気絶縁性基材で構成され、
前記外部端子と前記接続パッドを前記第二の電気絶縁性基材に形成されたビアにより電気的に接続することを特徴とする半導体装置。 A semiconductor element having a plurality of external terminals;
A wiring board comprising a first electrically insulating substrate and a wiring pattern having connection pads formed on the first electrically insulating substrate;
Consists of a second electrically insulating substrate that bonds the semiconductor element and the wiring board,
The semiconductor device, wherein the external terminal and the connection pad are electrically connected by a via formed in the second electrically insulating substrate. 複数の外部端子を有した半導体素子と、
第一の電気絶縁性基材と、前記第一の電気絶縁性基材に形成された接続パッドを有する配線パターンからなる複数の配線基板と、
前記半導体素子を内蔵し、前記複数の配線基板を厚さ方向に積層する第二の電気絶縁性基材とで構成され、
前記第二の電気絶縁性基材に形成され、前記外部端子と前記接続パッドを電気的に接続する第一のビアと、前記対向する配線パターン間を電気的に接続する第二のビアを有することを特徴とする半導体装置。 A semiconductor element having a plurality of external terminals;
A plurality of wiring boards comprising a first electrically insulating substrate and a wiring pattern having connection pads formed on the first electrically insulating substrate;
The semiconductor element is built in, and is constituted by a second electrically insulating base material that laminates the plurality of wiring boards in the thickness direction,
A first via formed on the second electrically insulating substrate and electrically connecting the external terminal and the connection pad; and a second via electrically connecting the opposing wiring patterns. A semiconductor device. 前記半導体素子がマトリクス状に再配線された外部端子を有することを特徴とする請求項１，２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor element has external terminals rewired in a matrix. 前記外部端子が銅ポストであることを特徴とする請求項１，２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the external terminal is a copper post. 前記ビアの面方向の大きさが、前記外部端子の面方向の大きさよりも小さいことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein a size of the via in the surface direction is smaller than a size of the external terminal in the surface direction. 前記ビアは、導電性の粒子と非導電性の樹脂とを含有した導電性ペーストから構成されていることを特徴とする請求項１，２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the via is made of a conductive paste containing conductive particles and a nonconductive resin. 第二の電気絶縁性基材は、無機フィラーと熱硬化性樹脂を含む混合物である請求項１，２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second electrically insulating substrate is a mixture containing an inorganic filler and a thermosetting resin. 第二の電気絶縁性基材にビアを形成する工程と、
前記ビアと接続パッドが接触するように前記第二の電気絶縁性基材を第一の電気絶縁性基材に形成された接続パッドを有する配線パターンからなる配線基板に積層する工程と、
外部端子と前記ビアが接触するように半導体素子を前記第二の電気絶縁性基材に実装する工程と、
前記第二の電気絶縁性基材と前記ビアを硬化する工程と、
を備えた半導体装置の製造方法。 Forming a via in the second electrically insulating substrate;
Laminating the second electrically insulating substrate on a wiring substrate having a wiring pattern having a connection pad formed on the first electrically insulating substrate so that the via and the connection pad are in contact with each other;
Mounting the semiconductor element on the second electrically insulating base so that the external terminal and the via are in contact with each other;
Curing the second electrically insulating substrate and the via;
A method for manufacturing a semiconductor device comprising: 第二の電気絶縁性基材にビアを形成する工程と、
前記ビアと接続パッドが接触するように前記第二の電気絶縁性基材を第一の電気絶縁性基材に形成された接続パッドを有する配線パターンからなる配線基板に積層する工程と、
外部端子と前記ビアが接触するように半導体素子を前記第二の電気絶縁性基材に実装する工程と、
別の第二の電気絶縁性基材にキャビティを形成する工程と、
この第二の電気絶縁性基材を前記キャビティ内に前記半導体素子を収納するように積層する工程と、
前記キャビティが形成された第二の電気絶縁性基材上にさらに別の第二の電気絶縁性基材及び別の配線基板を積層する工程と、
積層された前記第二の電気絶縁性基材と前記ビアをそれぞれ硬化し、前記半導体素子を埋設する工程と、
を備えた半導体装置の製造方法。 Forming a via in the second electrically insulating substrate;
Laminating the second electrically insulating substrate on a wiring substrate having a wiring pattern having a connection pad formed on the first electrically insulating substrate so that the via and the connection pad are in contact with each other;
Mounting the semiconductor element on the second electrically insulating base so that the external terminal and the via are in contact with each other;
Forming a cavity in another second electrically insulating substrate;
Laminating the second electrically insulating substrate so as to accommodate the semiconductor element in the cavity;
Laminating another second electrically insulating substrate and another wiring substrate on the second electrically insulating substrate in which the cavity is formed;
Curing the laminated second electrical insulating substrate and the via, respectively, and embedding the semiconductor element;
A method for manufacturing a semiconductor device comprising: 第二の電気絶縁性基材にビアを形成する工程と、
前記ビアと接続パッドが接触するように第二の電気絶縁性基材を第一の電気絶縁性基材に形成された接続パッドを有する配線パターンからなる配線基板に積層する工程と、
別の第二の電気絶縁性基材にキャビティを形成する工程と、
このキャビティを形成した第二の電気絶縁性基材を前記配線基板に積層された別の第二の電気絶縁性基材に積層する工程と、
前記キャビティに半導体素子を収納し、外部端子とビアが接触するように前記半導体素子を前記第二の電気絶縁性基材に実装する工程と、
前記キャビティが形成された第二の電気絶縁性基材上にさらに別の第二の電気絶縁性基材及び別の配線基板を積層する工程と、
積層された前記第二の電気絶縁性基材と前記ビアをそれぞれ硬化し、前記半導体素子を埋設する工程と、
を備えた半導体装置の製造方法。 Forming a via in the second electrically insulating substrate;
Laminating a second electrically insulating base material on a wiring board having a wiring pattern having a connection pad formed on the first electrically insulating base material so that the via and the connecting pad are in contact with each other;
Forming a cavity in another second electrically insulating substrate;
Laminating the second electrically insulating base material forming the cavity on another second electrically insulating base material laminated on the wiring board;
Storing the semiconductor element in the cavity, and mounting the semiconductor element on the second electrically insulating substrate so that the external terminal and the via are in contact with each other;
Laminating another second electrically insulating substrate and another wiring substrate on the second electrically insulating substrate in which the cavity is formed;
Curing the laminated second electrically insulating substrate and the via, respectively, and embedding the semiconductor element;
A method for manufacturing a semiconductor device comprising:
JP2006163137A 2006-06-13 2006-06-13 Semiconductor device and its manufacturing method Pending JP2007335487A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260084A (en) * 2008-04-17 2009-11-05 Dainippon Printing Co Ltd Wiring board with built-in component
KR101551177B1 (en) 2009-04-21 2015-09-09 엘지이노텍 주식회사 Imbedded printed circuit board within wire redistribution layer and Method of fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058592A (en) * 1998-06-04 2000-02-25 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2001144212A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Semiconductor chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058592A (en) * 1998-06-04 2000-02-25 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
JP2001144212A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Semiconductor chip

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009260084A (en) * 2008-04-17 2009-11-05 Dainippon Printing Co Ltd Wiring board with built-in component
KR101551177B1 (en) 2009-04-21 2015-09-09 엘지이노텍 주식회사 Imbedded printed circuit board within wire redistribution layer and Method of fabricating the same

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