JP2001144212A - Semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip which can be mounted at a wider bump pitch by decreasing the number of bumps. SOLUTION: A plane layer 46 for connecting a plurality of vias 42 formed in a first insulation layer 36 with copper plating posts 50 formed on the surface of a second insulation layer 36 is formed on the surface of the first insulation layer 36. Since wiring is integrated through the plane layer 46, wiring density can be increased and the number of bumps 56 can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a method of manufacturing the same, and more particularly to a conductor chip that can be mounted on a substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor chip is mounted on a package substrate and mounted on an external substrate such as a motherboard. Currently, bumps for direct connection are formed on electrode pads of the semiconductor chip, or re-formed on the chip. A mounting mode in which the semiconductor chip is directly mounted on an external substrate after wiring and widening the bump pitch has been studied.

[0003]

However, in the semiconductor chip of such a mounting form, since connection bumps are provided one-to-one with respect to each of the electrode pads of the semiconductor chip, the number of electrode pads per unit area is increased. When the number increases, the bump pitch must be narrowed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor chip which can reduce the number of bumps and can be mounted at a wider bump pitch. .

[0005]

According to a first aspect of the present invention, there is provided a semiconductor chip having an insulating layer formed on an electrode pad side of a semiconductor chip and connected to the electrode pad formed on the insulating layer. A via, a plane layer connected to the two or more electrode pads via the via, and a conductor circuit connected to the one electrode pad via the via;
Is a technical feature.

According to a second aspect of the present invention, there is provided a semiconductor chip according to the first aspect, wherein the via is filled with an elastic resin.

A semiconductor chip according to a third aspect of the present invention is a semiconductor chip to which an external connection substrate is pasted via an adhesive, wherein the external connection substrate has a via hole and two or more via holes. A technical feature is that a plane layer connected to the electrode pad and a conductor circuit connected to the one electrode pad via the via hole are formed.

According to a fourth aspect of the present invention, there is provided a semiconductor chip to which an external connection substrate is pasted via an adhesive, wherein the semiconductor chip has an insulating layer on an electrode pad side and an insulating layer formed on the insulating layer. A via hole, a via layer, a plane layer connected to two or more of the electrode pads through the via hole, and a via layer formed in the external connection substrate through the via hole. A conductor circuit connected to the first electrode pad, a protruding conductor connected to the via hole and connected to the via side, and a bump connected to the plane layer or the conductor circuit. Is a technical feature.

According to a fifth aspect of the present invention, there is provided a semiconductor chip.
In the above, the technical feature is that the electrode pad is a zincate-treated aluminum electrode pad, and the via made of copper plating is formed on the electrode pad via a composite plating layer of nickel and copper. And

In the semiconductor chip of the first aspect, since the plane layer connected to the two or more electrode pads is provided, the wiring can be integrated, and the number of bumps for connecting to the external substrate can be reduced.

In the semiconductor chip of the present invention, the via is filled with an elastic resin, and the via absorbs a stress generated due to a difference in thermal expansion between the semiconductor chip and the substrate, so that the semiconductor chip is firmly connected to the substrate. The connection reliability of the semiconductor chip can be improved.

In the semiconductor chip of the third and fourth aspects, since the plane layer connected to the two or more electrode pads is provided, the wiring can be integrated, and the number of bumps for connecting to the external substrate can be reduced. Here, by using the plane layer as a power supply layer or a ground layer, power can be supplied or shielded closer to the semiconductor chip, and electric performance is improved. Further, since the external connection substrate provided with the plane layer is attached to the semiconductor chip with an adhesive, the semiconductor chip does not warp during the attachment.

In the fifth aspect, it is difficult to perform copper plating on the surface of the aluminum electrode pad of the semiconductor chip. However, in the present invention, after performing zincate treatment on the surface of the aluminum electrode pad, nickel and copper are removed. In order to form a composite plating layer with, a via can be formed on the composite plating layer by copper plating.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip and a method for manufacturing a semiconductor chip according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1A shows a cross section of a semiconductor chip according to the first embodiment of the present invention. Semiconductor chip 3
An aluminum electrode pad 32 is formed on the lower surface of the substrate 0 by zincating the opening of the passivation film 34. In the present embodiment, a first insulating layer 36 is provided on the lower surface of the passivation film 34, and the first insulating layer 36 is formed with a non-through hole 36 a that extends in a tapered shape to reach the aluminum electrode pad 32. I have. The aluminum electrode pad 32 at the bottom of the non-through hole 36a has a nickel plating layer 38, a composite plating layer 40 of nickel and copper interposed therebetween, and a via 4 filled with copper plating.
2 are formed. A conductive circuit 44 and a plane layer 46 are connected to the via 42.

On the first insulating layer 36, a second insulating layer 48 having a copper plating post (via) 50 formed thereon is formed. A protruding conductor (bump) 56 made of a low melting point metal such as solder is provided on the copper plating post 50.
The semiconductor chip 30 is connected to a pad 92 on the substrate 90 via a protruding conductor (bump) 56.

FIG. 1B is a plan view of the semiconductor chip shown in FIG. 1A, taken across the line BB, that is, the conductor circuit 44 and the plane layer 46 formed on the surface of the first insulating layer 36. ing. The conductor circuit 44 is provided for connecting one via 42 formed in the first insulating layer 36 and one copper plating post 50 formed in the second insulating layer 48. That is, one electrode pad 32 of the semiconductor chip 30 is connected to the bump 56 via the via 42, the conductor circuit 44, and the copper plating post 50. On the other hand, the plane layer 46 is provided to connect the plurality of vias 42 formed in the first insulating layer 36 to the copper plating posts 50 formed in the second insulating layer 48. That is, two or more electrode pads of the semiconductor chip 30 (here, electrode pads for grounding or power supply)
32 is a via 42, a plane layer 46, and a copper plating post 5
0 is connected to one or more bumps 56.

In this embodiment, since the wiring is integrated via the plane layer 46, the wiring density can be increased and the number of the bumps 56 can be reduced.

Here, the thickness of the second insulating layer 48 and the height of the copper plating post 50 are formed to be 25 to 250 μm. On the other hand, the diameter of the copper plating post 50 is 20 μm or more.
It is formed to a thickness of 300 μm. Here, the semiconductor chip 3
0 and the substrate 90 have different coefficients of thermal expansion, and the heat generated during operation of the semiconductor chip 30 causes the semiconductor chip 30 and the substrate 9 to have different thermal expansion coefficients.
However, since stress can be absorbed by the second insulating layer 48 having flexibility and the copper plating post 50 having elasticity, a crack is not generated in an electrical connection portion, and a semiconductor is not generated. High connection reliability is provided between the chip 30 and the substrate 90.

The thickness of the second insulating layer 48 is preferably 25 μm or more. This is because when the thickness is 25 μm or less, the stress cannot be sufficiently absorbed. On the other hand, the thickness is 250
It is desirable that it is not more than μm. This is because if the thickness is larger than 250 μm, the connection reliability between the semiconductor chip 30 and the substrate 90 is reduced.

Subsequently, a method of manufacturing the semiconductor chip 30 according to the present embodiment will be described with reference to FIGS. Here, copper plating posts and bumps are formed on the semiconductor chip 30 in which the aluminum electrode pads 32 are formed in the openings of the passivation film 34 shown in the step (A) of FIG. First, as shown in step (B) of FIG.
The zinc electrode treatment is performed on the aluminum electrode pad 32 by immersing it in a mixture of zinc oxide as a metal salt and sodium hydroxide as a reducing agent for 0 second. This facilitates the deposition of the nickel plating layer or the composite plating layer.

Subsequently, as shown in step (C) of FIG. 2, the semiconductor chip 30 is immersed in a nickel electroless plating solution to deposit a nickel plating layer 38 on the surface of the aluminum electrode pad 32. Note that, even if the step of forming the nickel plating layer is omitted, a composite plating layer described later can be directly formed on the aluminum electrode pad 32.

Then, as shown in step (D) of FIG.
The semiconductor chip 30 is immersed in a nickel-copper composite plating solution, and is placed on the nickel plating layer 38 by 0.01 to 5 μm.
The nickel-copper composite plating layer 40 is formed. By making this composite plating layer 1-60% by weight of nickel and the remainder mainly copper, in addition to being able to form the composite plating layer on the aluminum electrode pad, it is possible to easily form copper plating on the surface. To Further, by setting the thickness of the composite plating layer to 0.01 μm or more, it becomes possible to form copper plating on the surface. On the other hand, when the thickness is 5 μm or less, precipitation can be performed in a short time.

Next, as shown in step (E) of FIG. 3, an insulating resin is applied. In this embodiment, a thermosetting epoxy resin or a polyimide resin is used as the insulating resin in order to form a non-through hole by laser processing. When a non-through hole is formed by a chemical treatment, a photosensitive epoxy resin or a polyimide resin can be used.
Next, after performing a drying process as shown in step (F) of FIG. 3, the first non-through hole 36a is formed by laser. Further, a first insulating layer 36 having a non-through hole 36a reaching the aluminum electrode pad 32 is formed by heat treatment.

Next, as shown in the step (G) of FIG. 3, the first non-through hole 36a is filled with copper plating to form the via 42, and the above is described with reference to FIG. 1 (B). The conductor circuit 44 and the plane layer 46 are formed on the first insulating layer 36 as described above. These are formed by electroless plating.

Next, as shown in the step (H) of FIG. 4, a thermosetting epoxy resin or a polyimide resin is applied, followed by a drying treatment. Then, as shown in the step (I) of FIG. A non-through hole reaching the conductive circuit 44 and the plane layer 46 is formed by a laser, and after roughening the surface, the second insulating layer 4 having the second non-through hole 48a is heated.
8 is formed.

Next, after the semiconductor chip 30 is immersed in the pretreatment liquid and a palladium catalyst is applied, an electroless copper plating film 49 is uniformly formed on the surface of the second insulating layer 48 and the wall of the non-through hole 48a. Then, a PET (polyethylene terephthalate) film is stuck on the electroless plating film 49. Then, an opening for opening the second non-through hole 48a is provided in the PET film by laser, and a resist having the opening is formed. Thereafter, the semiconductor chip 30 is immersed in an electrolytic plating solution, and a current is passed through the electroless copper plating film 49, thereby filling the second non-through hole 48a with copper as shown in the step (J) of FIG. Then, a copper plating post 50 is formed, and the PET film is peeled off. Since this copper plating post is formed by filling the second non-through-hole 48a with copper by electrolytic plating, a tall copper plating post can be formed at low cost. In addition, since the electrolytic plating is used, the time for immersing the semiconductor chip in a strong alkaline electroless plating solution is shorter than that of the electroless plating, and the risk of damaging the circuit on the semiconductor chip is reduced.

Next, as shown in a step (K) of FIG. 5, the electroless plating film 49 on the copper plating post 50 is etched to form a bump land 52. Thereafter, a solder resist composition is applied to form an opening reaching the metal film 52, and then heated to form an opening 54a as shown in the step (L).
Is formed. And
Solder is printed in the opening 54a, and reflow is performed as shown in a step (M) to form a solder bump 56. The height of the bump is desirably 3 to 60 μm.
The reason is that if the thickness is less than 3 μm, variations in the height of the bump cannot be tolerated due to the deformation of the bump.
If it exceeds 60 μm, when the bump is melted, it spreads in the horizontal direction and causes a short circuit.

The bumps 44 of the semiconductor chip 30 and the substrate 90
The semiconductor chip 30 is placed so that the pads 92 correspond to each other, and the semiconductor chip 30 is attached to the substrate 90 as shown in FIG. 1A by reflow.

FIG. 6 shows a semiconductor chip according to a modification of the first embodiment. In the semiconductor chip described above with reference to FIG. 1, the via 50 formed in the second insulating layer 48
It was a copper plating post filled with copper plating. On the other hand, in a modified example, the via 50 is composed of the copper plating film 51 formed on the surface of the second non-through hole 48a and the elastic resin 53 filled in the copper plating film 51. The elastic resin 53 is made of a thermosetting epoxy resin or a polyimide resin. A metal film 52 is formed on the surface of the elastic resin 53.

In the semiconductor chip 30 according to the modification, the inside of the via 50 is filled with the elastic resin 53, and the via 50 absorbs the stress generated due to the difference in thermal expansion between the semiconductor chip 30 and the substrate. Connection reliability can be improved. In the first embodiment described above, two layers of the first insulating layer 36 and the second insulating layer 48 are formed on the semiconductor chip 30. However, three or more insulating layers are formed, and a capacitor is formed by a plane layer. It is also possible.

Next, a semiconductor chip according to a second embodiment of the present invention will be described with reference to FIGS.
In the first embodiment described above, by stacking the insulating layers,
Wiring was formed. On the other hand, the second embodiment employs a configuration in which the substrate on which the wiring is formed is attached to the semiconductor chip.

FIG. 7A shows a cross section of a semiconductor chip according to the first embodiment of the present invention. On the lower surface of the semiconductor chip 30, an aluminum electrode pad 32 is formed in which an opening of the passivation film 34 is zincated. In the present embodiment, a first insulating layer 36 is provided on the lower surface of the passivation film 34, and the first insulating layer 36 is formed with a non-through hole 36 a that extends in a tapered shape to reach the aluminum electrode pad 32. I have. A nickel plating layer 38 and a composite plating layer 40 of nickel and copper are provided on the aluminum electrode pad 32 at the bottom of the non-through hole 36a.
A via 42 and a conductor circuit 44, which are filled with copper plating, are formed with the interposition therebetween.

An external connection substrate 60 is attached to the lower surface of the semiconductor chip 30. The external connection substrate 60 includes three first substrates 60A, second substrates 60B, and third substrates 60C in which via holes 62A, 62B, and 62C are formed. Via hole 62A of first substrate 60A
Is connected to the conductor circuit 44 on the semiconductor chip side via the protruding conductor 68A. On the lower surface of the via hole 62C of the third substrate 60C, a solder bump 56 for connection to an external substrate is formed.

FIG. 7B is a plan view of the semiconductor chip shown in FIG. 7A crossing the line BB, that is, the conductor circuit 64 and the plane layer 66 formed on the lower surface of the first substrate 60A. I have. The conductor circuit 64 is provided for connecting one through hole 62A formed on the first substrate 60A and one through hole 62B formed on the second substrate 60B. That is, one electrode pad 3 of the semiconductor chip 30
2 is a via 42, a conductor circuit 44, a through hole 62A of the first substrate, a conductor circuit 64, a through hole 62 of the second substrate.
B, connected to the bump 56 via the through hole 62C of the third substrate 60C. On the other hand, the plane layer 66 is provided to connect the plurality of through holes 62A formed in the first substrate 60A and the through holes 62B formed in the second substrate 60B. That is, the semiconductor chip 30
The two or more electrode pads 32 (here, electrode pads for grounding or power supply) 32 include vias 42, conductor circuits 44, through holes 62A of first substrate 30A, plane layer 66, through holes 62B of second substrate 30B, The third substrate 60C is connected to one or more bumps 56 through through holes 62C.

The plane layer 66C of the first substrate 30A
1 and the plane layer 66C2 of the second substrate 60B
The capacitors are opposed to each other with the substrate 60B interposed therebetween to form a capacitor. In the present embodiment, the substrate 60 is
Since A, 60B, and 60C are stacked, a substrate 60B made of a material having a high dielectric constant can be used unlike the first embodiment. Therefore, a high-capacity capacitor can be formed. Further, in the present embodiment, since the wiring is integrated via the plane layer 66, the wiring density can be increased and the number of the bumps 56 can be reduced. Also,
Since the first, second, and third substrates on which the conductor circuits are formed are used, the dimensional accuracy of the substrate and the wiring, such as the thickness and width, is excellent, and the electrical characteristics can be improved, as compared with the first embodiment.

Here, the thickness of the external connection substrate 60 formed by laminating the substrates 60A, 60B and 60C is 75 to 750.
μm. Here, the thermal expansion coefficients of the semiconductor chip 30 and the substrate 90 (see FIG. 1) are different, and the heat generated during the operation of the semiconductor chip 30 causes the semiconductor chip 30
Stress is generated between the substrate and the substrate 90 (see FIG. 1), but the stress can be absorbed by the flexible external connection substrate 60 made of resin, so that cracks are not generated in the electrical connection portion. Thus, high connection reliability is provided between the semiconductor chip 30 and the substrate 90. In the second embodiment, a resin is used as the base material of the second substrate 60B. However, instead of this, a ceramic plate or the like having a high dielectric constant can be used to increase the capacitance of the capacitor. .

Next, a method of manufacturing the semiconductor chip 30 according to the second embodiment will be described with reference to FIGS. Here, first, the first insulating layer 3 on the semiconductor chip side
Since the formation of the vias 6 and the vias 42 are the same as in the first embodiment described above with reference to FIGS. 2 and 3, a method of forming the first substrate 60A will be described with reference to FIG.
As shown in step (A) of FIG. 8, an adhesive layer 74 and a PET are placed on an insulating substrate 70 having a metal layer 72 formed on one surface.
(Polyethylene terephthalate) A film 76 is attached. Here, as the insulating base material 70, any organic insulating base material can be used.
A rigid (hard) laminated substrate selected from an epoxy resin substrate, a glass cloth epoxy resin substrate, an aramid nonwoven-polyimide substrate, a bismaleimide triazine resin substrate, or a polyphenylene ether (PPE) film;
It is desirably one type selected from a flexible base material made of a film such as polyimide (PI).

The insulating substrate 70 is preferably a rigid laminated substrate, and a single-sided copper-clad laminate is particularly preferred. This is because the positions of the wiring patterns and the via holes do not shift during handling after the metal layer 72 is etched, and the positional accuracy is excellent.

The metal layer 72 formed on the insulating base material 70 can use a copper foil. Copper foil is used to improve adhesion.
Matting treatment may be performed. Here, a single-sided copper-clad laminate is used. A single-sided copper-clad laminate is obtained by impregnating a glass cloth with a thermosetting resin such as an epoxy resin, a phenol resin, and a bismaleimide-triazine resin, laminating a prepreg having a B stage and a copper foil, and hot pressing the laminate. It is a substrate. The single-sided copper-clad laminate is a rigid substrate, is easy to handle, and is most advantageous in terms of cost. Alternatively, after depositing a metal on the surface of the insulating substrate 70, a metal layer can be formed by electrolytic plating.

The thickness of the insulating substrate 70 is 25 to 250 μm.
m, preferably 50 to 100 μm. This is to ensure insulation. If the thickness is smaller than these ranges, the strength is reduced and handling becomes difficult, and it is difficult to provide sufficient flexibility. Conversely, if the thickness is too large, it becomes difficult to form fine via holes and fill with a conductive material. . On the other hand, the thickness of the metal layer 72 is 5 to 35 μm, preferably 8 μm.
To 30 μm, and preferably 12 to 25 μm. This is because, as will be described later, when the hole is formed by laser processing, if the hole is too thin, it penetrates, and if it is too thick, etching is difficult.

The adhesive layer 74 is preferably made of an organic adhesive. As the organic adhesive, epoxy resin,
Polyimide resin, thermosetting polyphenolene ether (P
It is desirable that the resin be at least one resin selected from PE (Polyphenyl ether), a composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and BT resin.

As a method of applying the uncured resin as an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen printing, or the like can be used. Further, the formation of the adhesive layer can also be performed by laminating an adhesive sheet. The thickness of the adhesive layer is 5-50μ
m is desirable. The adhesive layer is preferably pre-cured (pre-cured) for easy handling.

Next, the insulating base material 7 is formed by laser processing.
A non-through hole 70a is opened at 0 (step (B)). As the laser beam machine, a carbon dioxide laser beam machine, a UV laser beam machine, an excimer laser beam machine or the like can be used. The pore size is preferably 20 to 300 μm. The carbon dioxide laser processing machine is most suitable for industrial use because it can be processed at a high processing speed and at low cost, and is the most desirable laser processing machine for the present invention. Here, when a carbon dioxide laser beam machine is used, a small amount of molten resin is likely to remain on the surface of the metal layer 72 in the hole 70a, so that desmear treatment ensures connection reliability. Desirable.

Subsequently, the non-through hole 7 opened by laser processing
0a is filled with electrolytic plating to form a through hole 62A (step (E)). As electrolytic plating, for example, copper,
Gold, nickel, or solder plating can be used, but electrolytic copper plating is particularly suitable. In this case, bumps can be formed simultaneously.

In the electroplating, the metal layer 72 formed on the insulating substrate 70 is used as a plating lead. The metal layer 7
2 is formed on the entire surface of the insulating base material 70,
The current density becomes uniform, and the non-through holes can be filled at a uniform height by electrolytic plating. Here, before the electrolytic plating, the surface of the metal layer 72 in the non-through hole 70a may be activated with an acid or the like. When plating is performed, a mask (not shown) is placed on the metal layer 72 side so that electrolytic plating does not deposit on the surface side of the metal layer 72 formed on the insulating base material 70, or the same insulating property is used. Two substrates 70,
Electroplating is preferably performed so that the metal layers 72 are in close contact with each other so as not to come into contact with the plating solution.

Next, in the step (D), the conductive paste 68 is filled in the remaining space in the non-through hole 70a. In the second embodiment, variations in the height of the electrolytic plating can be corrected by the conductive paste 68 so that the heights of the bumps can be made uniform. In this case, a low melting point metal can be filled instead of the conductive paste.

As the conductive paste, a conductive paste comprising at least one kind of metal particles selected from silver, copper, gold, nickel and solder can be used. Further, as the metal particles, those obtained by coating the surface of metal particles with a dissimilar metal can also be used. Specifically, gold,
Metal particles coated with a noble metal selected from silver can be used.

As the conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a phenol resin or a thermoplastic resin such as polyphenylene sulfide (PPS) to metal particles is desirable.

The filling rate of non-through holes in electrolytic plating (height of electrolytic plating × 100 / depth of non-through holes) is 50% on average.
Or more, less than 100%, more preferably 55% to 95%
And 60% to 90% is optimal.

Next, as shown in step (E), the metal film 7
2 is subjected to pattern etching to form a conductor circuit 64 and a plane layer 66.

In step (F), the film 76 is removed.
The conductive paste 68 is exposed from the adhesive layer 74 to form bumps 68A, thereby completing the first substrate 60A.

Subsequently, the semiconductor chip 30 and the first substrate 6
OA, the second substrate 60B, and the third substrate 60C are bonded by heating using a hot press and pressing under pressure. Here, first, the substrates 60A, 60B,
The bumps 68A, 68B, and 68C of 60C extrude the uncured adhesive (insulating resin) 74 to the surroundings, and the conductive circuit 4
4, the plane layer 46, the conductor circuit 64, and the plane layer 66 are brought into contact with each other to establish connection therebetween. Further, the adhesive layer 74 is cured by being heated at the same time as the pressurization, and strong bonding is performed between the semiconductor chip 30 and the substrates 60A, 60B, and 60C. It is preferable to use a vacuum hot press as the hot press. In the first embodiment, the insulating layers 36, 4
When hardening 8, the semiconductor chip may be warped. On the other hand, in the second embodiment, since the substrate provided with the plane layer is attached to the semiconductor chip with an adhesive, the semiconductor chip does not warp during the attachment.

Finally, as shown in FIG. 7A, the bump 5 is formed on the surface of the through hole 62C opposite to the semiconductor chip.
6 is formed. The bumps 56 may be formed, for example, by screen printing a conductive paste using a metal mask provided with openings at predetermined positions, printing a solder paste that is a low-melting metal, performing a solder plating, or using a solder melt. It can be formed by a method of immersion in the glass. Pb-Sn solder, Ag-Sn solder, indium solder, or the like can be used as the low melting point metal.

In the above-described embodiment, the holes for forming the via holes are formed by using the laser processing. However, the holes may be formed by a mechanical method such as drilling and punching.

In the second embodiment, the base material 70
After applying an adhesive layer 74 to the side, the through-hole 62 and the protruding conductor 68A were formed. Thereby, the protruding conductor 68A is exposed from the adhesive layer 74, and the electrical connection reliability is improved. Instead, the adhesive layer 74 may be applied after forming the protruding conductor, and the adhesive layer 74 may not be exposed to a chemical solution or the like, so that the reliability of the adhesion may be improved.

[Brief description of the drawings]

FIG. 1A is a sectional view of a semiconductor chip according to a first embodiment of the present invention, and FIG. 1B is a sectional view of FIG.
FIG. 6 is a cross-sectional view taken along line BB of FIG.

FIG. 2 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 3 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 4 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 5 is a manufacturing process diagram of the semiconductor chip according to the first embodiment.

FIG. 6 is a cross-sectional view of a semiconductor chip according to a modification of the first embodiment of the present invention.

FIG. 7A is a sectional view of a semiconductor chip according to a second embodiment of the present invention, and FIG. 7B is a sectional view of FIG.
FIG. 6 is a cross-sectional view taken along line BB of FIG.

FIG. 8 is a manufacturing process diagram of the semiconductor chip according to the second embodiment.

FIG. 9 is a manufacturing process diagram of the semiconductor chip according to the second embodiment.

[Explanation of symbols]

 Reference Signs List 30 semiconductor chip 32 aluminum electrode pad 34 passivation film 38 nickel plating layer 40 composite plating layer 42 via 44 conductive circuit 46 plane layer 56 bump 60 external connection substrate 60A first substrate 60B second substrate 60C third substrate 62A, 62B, 62C Through hole 68A, 68B, 68C Projecting conductor 74 Adhesive layer

Claims (5)

[Claims] 1. An insulating layer formed on an electrode pad side of a semiconductor chip, a via formed on the insulating layer and connected to the electrode pad, and a plane connected to two or more of the electrode pads via the via A semiconductor chip comprising: a layer; and a conductor circuit connected to one of the electrode pads via the via. 2. The semiconductor chip according to claim 1, wherein said via is filled with an elastic resin. 3. A semiconductor chip to which an external connection substrate is pasted via an adhesive, wherein the external connection substrate is connected to a via hole and the two or more electrode pads via the via hole. And a conductor circuit connected to one of the electrode pads via the via hole. 4. A semiconductor chip to which an external connection substrate is pasted via an adhesive, wherein the semiconductor chip is connected to an insulating layer on an electrode pad side and the electrode pad formed on the insulating layer. A via hole, a plane layer connected to two or more of the electrode pads via the via hole, and one of the electrode pads via the via hole. A conductive circuit connected to the via hole, a protruding conductor connected to the via hole and connected to the via side, and a bump connected to the plane layer or the conductive circuit. Semiconductor chip. 5. The method according to claim 1, wherein the electrode pad is an aluminum electrode pad subjected to zincate treatment, and the via made of copper plating is formed on the electrode pad via a composite plating layer of nickel and copper. Claim 1.
Or the semiconductor chip according to 4.