JP2003100787A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device

Info

Publication number
JP2003100787A
JP2003100787A JP2001298564A JP2001298564A JP2003100787A JP 2003100787 A JP2003100787 A JP 2003100787A JP 2001298564 A JP2001298564 A JP 2001298564A JP 2001298564 A JP2001298564 A JP 2001298564A JP 2003100787 A JP2003100787 A JP 2003100787A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
manufacturing
copper foil
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001298564A
Other languages
Japanese (ja)
Inventor
Hitoshi Kawaguchi
均 川口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2001298564A priority Critical patent/JP2003100787A/en
Publication of JP2003100787A publication Critical patent/JP2003100787A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method which can realize miniaturization and cost reduction of a semiconductor device, and to provide the semiconductor device using the same. SOLUTION: In the method for manufacturing a semiconductor device comprising, correspondingly to each chip on the wafer, pads for mounting each solder ball, bond fingers for connecting with each chip, and circuits for connecting both (re-wiring circuits) on an insulative resin layer formed over the surface of a semiconductor wafer being an aggregate of semiconductor elements, the semiconductor wafer is arranged in a metal mold, and the insulation resin layer is formed by compression molding, transfer molding, or injection molding.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法及び半導体装置に関するものである。更に詳しく
は、ウェハーレベルのパッケージの製造方法、及びその
製造方法から得られる半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device. More specifically, the present invention relates to a wafer level package manufacturing method and a semiconductor device obtained by the manufacturing method.

【0002】[0002]

【従来の技術】近年の電子機器の高機能化並びに軽薄短
小化の要求に伴い、電子部品の高密度集積化、さらには
高密度実装化が進んできている。これらの電子機器に使
用される半導体パッケージは、小型化かつ多ピン化して
きており、また、半導体パッケージを含めた電子部品を
実装する、実装用基板も小型化してきている。さらには
電子機器への収納性を高めるため、リジット基板とフレ
キシブル基板を積層し一体化して、折り曲げを可能とし
たリジットフレックス基板が、実装用基板として使われ
るようになってきている。
2. Description of the Related Art With the recent demand for higher functionality, lightness, thinness, shortness, and miniaturization of electronic equipment, high-density integration and further high-density packaging of electronic parts have been advanced. Semiconductor packages used in these electronic devices have been downsized and have a large number of pins, and mounting substrates for mounting electronic components including semiconductor packages have also been downsized. Furthermore, in order to enhance the storage property in electronic equipment, a rigid flex substrate, which is made by stacking and integrating a rigid substrate and a flexible substrate and is bendable, has come to be used as a mounting substrate.

【0003】半導体パッケージはその小型化に伴って、
従来のようなリードフレームを使用した形態のパッケー
ジでは、小型化に限界がきているため、最近では回路基
板上にチップを実装したものとして、BGA(Ball
Grid Array)や、CSP(Chip Sc
ale Package)と言った、エリア実装型の新
しいパッケージ方式が提案されている。これらの半導体
パッケージにおいて、半導体チップの電極と従来型半導
体パッケージのリードフレームの機能を有する、半導体
パッケージ用基板と呼ばれる、プラスチックやセラミッ
クス等各種材料を使って構成される、サブストレートの
端子との電気的接続方法として、ワイヤーボンディング
方式やTAB(Tape Automated Bon
ding)方式、さらにはFC(Frip Chip)
方式などが知られているが、最近では、半導体パッケー
ジの小型化に有利なFC接続方式を用いた、BGAやC
SPの構造が盛んに提案されている。しかし、これらの
パッケージは半導体チップを個片化した後に、1つ1つ
パッケージング及びテストを実施しなくてはならず、コ
ストを押し上げる要因となっていた。
As semiconductor packages have become smaller,
In a package using a lead frame as in the past, miniaturization has reached its limit, so recently, a BGA (Ball) has been used as a chip mounted on a circuit board.
Grid Array) and CSP (Chip Sc)
A new package method of area mounting type called "ale Package" has been proposed. In these semiconductor packages, the electrical connection between the electrodes of the semiconductor chip and the terminals of the substrate, which is composed of various materials such as plastics and ceramics, called the semiconductor package substrate, which has the function of the lead frame of the conventional semiconductor package. As a dynamic connection method, a wire bonding method or TAB (Tape Automated Bonn)
ing) method, and further FC (Flip Chip)
Although the method is known, recently, BGA and C using the FC connection method, which is advantageous for miniaturization of semiconductor packages.
The structure of SP is actively proposed. However, these packages have to be individually packaged and tested after the semiconductor chips have been separated into individual pieces, which has been a factor of increasing costs.

【0004】このため、半導体チップを個片化する前
に、一括してパッケージング及びテストする方法が各社
より提案されている。その中でも、ウェハー上に応力緩
和機能を持つ絶縁層を樹脂により形成し、その上にサブ
トラクティブ法もしくはセミアディティブ法といった従
来よりある、導体回路形成法により再配線用回路を形成
する方法が、高い次元で信頼性とコストを両立させ得る
手法であるとして注目を集めている。
Therefore, various companies have proposed a method of collectively packaging and testing semiconductor chips before dividing them into individual pieces. Among them, the method of forming a rewiring circuit by a conventional conductive circuit forming method such as a subtractive method or a semi-additive method, in which an insulating layer having a stress relaxation function is formed on a wafer by resin, is high. It is attracting attention as a method that can achieve both reliability and cost in terms of dimensions.

【0005】[0005]

【発明が解決しようとする課題】従来より提案されてい
る様な、接着剤付き樹脂フィルム上に、半田ボールを搭
載するためのパッド、チップとの接続のためのボンドフ
ィンガー、および両者をつなぐための回路を、ウェハー
上の各チップに対応して反復して形成し、チップと該回
路との接続のためのワイヤーボンディング用の開口部を
形成し、これをウェハーに貼り付ける方法では、上記構
造を有する半導体装置を作ることは可能であるが、コス
トダウンのために有用なウェハーの大径化には、貼り付
け位置精度の要求が高く、歩留まり低下が一つの問題と
してある。
In order to connect a pad for mounting a solder ball, a bond finger for connecting with a chip, and a bond finger on a resin film with an adhesive, which has been conventionally proposed. Circuit is repeatedly formed corresponding to each chip on the wafer, an opening for wire bonding for connecting the chip and the circuit is formed, and this is attached to the wafer by the method described above. Although it is possible to manufacture a semiconductor device having the above-mentioned requirements, the increase in the diameter of a wafer, which is useful for cost reduction, requires a high degree of accuracy in the attachment position, and a decrease in yield is one of the problems.

【0006】また、ルーター加工は加工コストが高く、
プレス加工の場合は、チップデザインによりワイヤボン
ディングパッドの配置が変更された場合、その度に開口
部形成用の打ち抜き金型を新調する必要があり、コスト
を押し上げる要因になる。
[0006] Further, the processing cost of the router is high,
In the case of press working, when the arrangement of the wire bonding pads is changed by the chip design, it is necessary to newly prepare a punching die for forming the opening, which causes a cost increase.

【0007】本発明は、前記従来の問題点に鑑みなされ
たものであって、半導体装置の小型化及び低コスト化を
可能とする、半導体装置の製造方法及びその製造方法に
より得られる半導体装置を提供する。
The present invention has been made in view of the above-mentioned conventional problems, and provides a method of manufacturing a semiconductor device and a semiconductor device obtained by the manufacturing method, which enables miniaturization and cost reduction of the semiconductor device. provide.

【0008】[0008]

【課題を解決するための手段】即ち本発明は、次の半導
体装置の製造方法及び半導体装置を提供する。 (1)半導体素子の集合体である半導体ウェハー表面全
体に形成された、絶縁樹脂層上に、半田ボールを搭載す
るためのパッド、チップとの接続のためのボンドフィン
ガー、および両者をつなぐための回路(再配線用回路)
が、ウェハー上の各チップに対応して形成されてなる半
導体装置の製造方法において、半導体ウェハーを成形用
金型内に配置し、圧縮成形、移送成形又は射出成形によ
り、絶縁樹脂層を成形して形成することを特徴とする、
半導体装置の製造方法。 (2)半導体ウェハーを成形用金型内に配置する際に、
半導体ウェハー上に絶縁樹脂層を形成する間隙を設け
て、再配線回路形成用銅箔が配置される、前記第(1)
項記載の半導体装置の製造方法。 (3)該再配線回路形成用銅箔が、絶縁樹脂層形成面と
反対側に補強材を配置される、前記第(2)項記載の半
導体装置の製造方法。 (4)再配線回路が、再配線回路形成用銅箔を用いてサ
ブトラクティブもしくはセミアディティブ法により形成
される、前記第(1)項、第(2)項又は第(3)項記
載の半導体装置の製造方法。 (5)半導体素子入出力端子上の絶縁樹脂層をレーザー
により除去することにより前記入出力端子を露出させ、
その開口部を介して、入出力端子と再配線用回路が銅メ
ッキにより接続される、前記第(1)項、第(2)項、
第(3)項又は第(4)記載の半導体装置の製造方法。 (6)前記第(1)項ないし第(5)項のいずれかに記
載された製造方法によって、製造されたものであること
を特徴とする半導体装置。
That is, the present invention provides the following semiconductor device manufacturing method and semiconductor device. (1) A pad for mounting a solder ball, a bond finger for connecting with a chip, and a bond finger for connecting both, on an insulating resin layer formed on the entire surface of a semiconductor wafer which is an assembly of semiconductor elements Circuit (rewiring circuit)
In the method of manufacturing a semiconductor device formed corresponding to each chip on a wafer, the semiconductor wafer is placed in a molding die, and an insulating resin layer is molded by compression molding, transfer molding or injection molding. Characterized by forming
Manufacturing method of semiconductor device. (2) When placing the semiconductor wafer in the molding die,
The copper foil for forming a rewiring circuit is arranged on the semiconductor wafer with a gap for forming an insulating resin layer, and the (1)
A method of manufacturing a semiconductor device according to the item. (3) The method for manufacturing a semiconductor device according to the item (2), wherein the copper foil for forming a rewiring circuit is provided with a reinforcing material on the side opposite to the surface on which the insulating resin layer is formed. (4) The semiconductor according to (1), (2) or (3) above, wherein the rewiring circuit is formed by a subtractive or semi-additive method using a rewiring circuit forming copper foil. Device manufacturing method. (5) Exposing the input / output terminals by removing the insulating resin layer on the input / output terminals of the semiconductor element with a laser,
The input / output terminal and the rewiring circuit are connected by copper plating through the opening, and the above (1), (2),
A method of manufacturing a semiconductor device according to item (3) or (4). (6) A semiconductor device manufactured by the manufacturing method described in any one of (1) to (5) above.

【0009】[0009]

【発明の実施の形態】本発明の半導体装置の製造方法の
例を、以下に説明するが、本発明はこれらに限定されな
い。まず、半導体素子の集合体である半導体ウェハーを
成形用金型内に、半導体素子の入出力端子を上にして配
置する。次いで、再配線回路形成用銅箔を、半導体ウェ
ハー上に絶縁樹脂層を形成するための、間隙を設けて、
半導体ウェハーが配置された金型と相対する金型に配置
して、成形の準備をする。
BEST MODE FOR CARRYING OUT THE INVENTION An example of a method for manufacturing a semiconductor device of the present invention will be described below, but the present invention is not limited to these. First, a semiconductor wafer, which is an assembly of semiconductor elements, is placed in a molding die with the input / output terminals of the semiconductor elements facing upward. Next, a copper foil for forming a rewiring circuit is provided with a gap for forming an insulating resin layer on the semiconductor wafer,
The semiconductor wafer is arranged in a mold opposite to the mold in which the semiconductor wafer is arranged, and preparation for molding is performed.

【0010】再配線回路形成用銅箔は、電解銅箔が用い
られるが、再配線用回路の精細度を確保するため、例え
ば、厚み1μm以上15μm以下のものを用いることが
できるが、2μm以上7μm以下のものを用いること
が、より望ましい。また、成形時の銅箔の破れやシワ防
止として、絶縁樹脂層形成面と反対側の面に、補強材を
設けることが、より好ましい。補強材としては、成形時
の熱に耐えることができるものであれば良く、ポリエス
テル、ポリエーテルサルフォン、ポリイミド等のプラス
チックシートを用いることができる。また、銅箔と補強
材シートの間に、約20〜50μm程度の裏打ち銅箔を
貼り付けておくと、更に好ましい。
As the copper foil for forming the rewiring circuit, an electrolytic copper foil is used. To secure the fineness of the rewiring circuit, for example, a foil having a thickness of 1 μm or more and 15 μm or less can be used, but 2 μm or more. It is more desirable to use the one having a thickness of 7 μm or less. Further, it is more preferable to provide a reinforcing material on the surface opposite to the surface on which the insulating resin layer is formed, in order to prevent the copper foil from breaking and wrinkling during molding. Any reinforcing material can be used as long as it can withstand heat during molding, and a plastic sheet such as polyester, polyether sulfone, or polyimide can be used. Further, it is more preferable to attach a backing copper foil of about 20 to 50 μm between the copper foil and the reinforcing material sheet.

【0011】次いで、絶縁樹脂を金型内の絶縁樹脂層形
成部に注入して成形することにより、半導体ウェハー、
絶縁樹脂層及び再配線回路形成用銅箔、更には補強材か
らなる成形物が得られる。この後、補強材は、除去す
る。
Next, by injecting an insulating resin into the insulating resin layer forming portion in the mold to form a semiconductor wafer,
A molded product including an insulating resin layer, a copper foil for forming a rewiring circuit, and a reinforcing material is obtained. After this, the reinforcing material is removed.

【0012】成形方法としては、圧縮成形、移送成形、
射出成形を用いることができる。絶縁樹脂層に成形時の
発生するガス等により生じるボイドを防止するために、
真空吸引成形を行うと良い。圧縮成形の場合は、絶縁樹
脂を秤量して、タブレット形状に成形しておくと好まし
い。また、圧縮成形の絶縁樹脂の金型内投入は、前記成
形の準備において、金型内に配置された半導体ウェハー
の上に置いて、加熱加圧することで成形できる。
As the molding method, compression molding, transfer molding,
Injection molding can be used. In order to prevent voids generated in the insulating resin layer due to gas generated during molding,
Vacuum suction molding is recommended. In the case of compression molding, it is preferable to weigh the insulating resin and mold it into a tablet shape. Further, the injection of the insulating resin for compression molding into the mold can be carried out by placing it on the semiconductor wafer arranged in the mold and applying heat and pressure in the preparation for the molding.

【0013】絶縁樹脂としては、熱硬化性樹脂、熱可塑
性樹脂を問わないが、本発明の製造方法に適するもので
あれば良い。例えば、半導体装置の絶縁樹脂として用い
られる、エポキシ樹脂やポリイミド樹脂等が、好まし
い。
The insulating resin may be a thermosetting resin or a thermoplastic resin as long as it is suitable for the manufacturing method of the present invention. For example, an epoxy resin or a polyimide resin used as an insulating resin of a semiconductor device is preferable.

【0014】本発明の製造方法において、再配線回路用
銅箔を配置せずに、成形しても良い。この場合は、成形
により、絶縁樹脂層を形成した後、金型より、成形物を
取り出し、絶縁樹脂層表面に、電解により、再配線回路
用銅箔層を形成することもできる。製造工程簡略化から
して、成形時に再配線回路用銅箔を配置することが好ま
しい。
In the manufacturing method of the present invention, the copper foil for the rewiring circuit may be formed without disposing it. In this case, after forming the insulating resin layer by molding, the molded product can be taken out from the mold, and the copper foil layer for the rewiring circuit can be formed on the surface of the insulating resin layer by electrolysis. From the viewpoint of simplifying the manufacturing process, it is preferable to arrange the copper foil for rewiring circuit at the time of molding.

【0015】このようにして得られた、表面が銅箔に覆
われた絶縁樹脂付ウェハーは、半導体素子入出力端子上
の絶縁樹脂層をレーザー加工機により除去して開口部を
形成するが、レーザーエネルギーが集中するよう、銅箔
表面を薬液により粗化した後、レーザー加工機により銅
箔ごと絶縁樹脂層を除去する。
In the thus obtained wafer with insulating resin whose surface is covered with copper foil, the insulating resin layer on the input / output terminals of the semiconductor element is removed by a laser processing machine to form an opening. The surface of the copper foil is roughened with a chemical solution so that the laser energy is concentrated, and then the insulating resin layer is removed together with the copper foil by a laser processing machine.

【0016】上記開口部は、無電解メッキが施され、絶
縁樹脂層表面を覆う銅箔と半導体素子入出力端子が電気
的に接続される。さらに、電解銅箔からなる再配線回路
形成用銅箔及び無電解メッキ層を給電層として、銅箔上
に電解メッキを行うが、この際のメッキ厚は、給電層と
して用いた再配線回路形成用銅箔の厚みとあわせて25
μm以下となるよう制御する。
The opening is electroless plated to electrically connect the copper foil covering the surface of the insulating resin layer to the semiconductor element input / output terminal. Further, electrolytic copper plating is performed on the copper foil using the copper foil for rewiring circuit formation made of electrolytic copper foil and the electroless plating layer as the power feeding layer. The plating thickness at this time is the rewiring circuit formation used as the power feeding layer. 25 together with the thickness of copper foil
The control is performed so that it is less than or equal to μm.

【0017】更に、電解メッキ層の上にエッチングレジ
スト層を再配線用回路を形成したい部位のみに形成し、
エッチング液により不要な部分の電解メッキ層、無電解
メッキ層および再配線回路形成用銅箔を除去することに
より、半導体素子入出力端子と電気的に接続された再配
線用回路を得る。
Further, an etching resist layer is formed on the electroplating layer only at a portion where a rewiring circuit is to be formed,
By removing unnecessary portions of the electrolytic plating layer, the electroless plating layer and the rewiring circuit forming copper foil with an etching solution, a rewiring circuit electrically connected to the semiconductor element input / output terminals is obtained.

【0018】また電解銅箔からなる再配線回路形成用銅
箔の厚みが3μm以下である場合は、上記無電解メッキ
工程の後、メッキレジスト層を再配線用回路を形成した
い部位以外を被覆するよう形成し、電解銅箔を給電層と
して、該銅箔に上に電解銅箔層を形成する。次にメッキ
レジストを除去した後、電解銅箔及び無電解メッキ層を
過水硫酸で除去することにより所定の位置に、半導体素
子入出力端子と電気的に接続された再配線用回路を得る
事も可能である。
When the thickness of the rewiring circuit forming copper foil made of the electrolytic copper foil is 3 μm or less, after the electroless plating step, the plating resist layer is coated on portions other than the portion where the rewiring circuit is to be formed. Thus, the electrolytic copper foil is used as a power feeding layer, and the electrolytic copper foil layer is formed on the copper foil. Next, after removing the plating resist, the electrolytic copper foil and the electroless plating layer are removed with perhydrosulfuric acid to obtain a rewiring circuit electrically connected to the semiconductor element input / output terminals at predetermined positions. Is also possible.

【0019】次に、半田バンプを形成する部位以外の絶
縁樹脂層及び再配線用回路を覆うようにソルダーレジス
ト層を形成し、半田バンプを形成する所定の位置に、半
田ボールを配置後、リフロー炉投入もしくは半田ペース
トをステンシル印刷した後、リフロー炉投入することに
より、半田バンプを形成する。
Next, a solder resist layer is formed so as to cover the insulating resin layer and the rewiring circuit other than the portion where the solder bumps are formed, and the solder balls are arranged at predetermined positions where the solder bumps are to be formed, and then reflow is performed. Solder bumps are formed by charging in a furnace or stencil printing a solder paste and then charging in a reflow furnace.

【0020】最後に、半導体ウェハーを各半導体素子に
個片化することにより、半導体素子と全く同一面積の半
導体装置を得る。
Finally, the semiconductor wafer is divided into individual semiconductor elements to obtain a semiconductor device having the same area as the semiconductor element.

【0021】[0021]

【実施例】以下、実施例により本発明を具体的に説明す
るが、本発明はこれによって何ら限定されるものではな
い。
EXAMPLES The present invention will be described in detail below with reference to examples, but the present invention is not limited thereto.

【0022】(実施例1)175℃に昇温させた金型内
にウェハを置き、その上にタブレット状に成形されたエ
ポキシ封止材料(住友ベークライト製:品番EME−7
880)を配置し、厚み35μmの電解銅箔で裏打ちさ
れた厚み3μmの電解銅箔の裏打ち箔側に、粘着材付PE
Tフィルムを貼り付けたものを、ウェハーが配置された
金型と正対する金型近くに配置する。 この際、上記PE
Tフィルム付銅箔は金型外周部に設けられた吸気口によ
り、吸引固定される。この後、型締力120tで上型と
下型を閉じて、ウェハを搭載した金型により圧力を掛
け、実効圧9.8MPaで、120秒間、加圧、加熱し
た後、金型から取り出し、PETフィルムとともに裏打
ち銅箔を除去することにより、ウェハー全面に厚さ10
5μmの絶縁樹脂を介して厚み3μmの銅箔が貼り付け
られた構造物を得た。上記構造物の銅箔を粗化液(三菱
瓦斯化学製CPE900)により粗化した後、UVレー
ザー加工機(三菱重工製:機種605LDX)により、
半導体素子入出力端子直上部の樹脂及び銅箔を直径75
μmの円状に除去する。次に、無電解メッキにより、樹
脂開口部及び銅箔表面に厚さ0.5μmの銅層を形成し
た後、更に電解メッキにより厚さ15μmの銅層を形成
する。次に、銅層上にエッチングレジスト層(旭化成
製:品番AQ2558)を形成し、開口部と所定の半田
ボール配置部を接続するための再配線回路以外の部位の
銅箔を、アルカリエッチング液により除去した。この
後、ウェハー全面を覆うように感光性ソルダーレジスト
(住友ベークライト製:CFP−1123)層を形成し
半田ボール配置部のを開口する。この後、フラックスと
ともに、半田ボールをソルダーレジスト開口部に配置
し、リフロー工程に投入、ダイシングマシンにより各半
導体素子を個片化することにより、独立して機能する半
導体装置を得た。このようにして得られた半導体装置は
半導体装置としての作動に問題がないことが確認され
た。
Example 1 A wafer was placed in a mold heated to 175 ° C., and an epoxy encapsulating material formed into a tablet shape (manufactured by Sumitomo Bakelite: product number EME-7) was formed on the wafer.
880) is placed on the backing foil side of the electrolytic copper foil with a thickness of 3 μm, which is lined with an electrolytic copper foil with a thickness of 35 μm.
The one to which the T film is attached is placed near the die that directly faces the die on which the wafer is placed. At this time, the PE
The copper foil with the T film is suctioned and fixed by the intake port provided on the outer periphery of the mold. After that, the upper mold and the lower mold are closed with a mold clamping force of 120 t, pressure is applied by the mold on which the wafer is mounted, and pressure and heat are applied for 120 seconds at an effective pressure of 9.8 MPa, and then the mold is taken out from the mold. By removing the backing copper foil together with the PET film, a thickness of 10
A structure was obtained in which a copper foil having a thickness of 3 μm was attached via an insulating resin having a thickness of 5 μm. After roughening the copper foil of the above structure with a roughening liquid (CPE900 manufactured by Mitsubishi Gas Chemical Co., Ltd.), using a UV laser processing machine (Mitsubishi Heavy Industries: Model 605LDX),
The diameter of resin and copper foil right above the semiconductor device input / output terminals is 75
Remove in a circle of μm. Next, a copper layer having a thickness of 0.5 μm is formed on the resin opening and the surface of the copper foil by electroless plating, and then a copper layer having a thickness of 15 μm is further formed by electrolytic plating. Next, an etching resist layer (manufactured by Asahi Kasei: product number AQ2558) is formed on the copper layer, and the copper foil other than the rewiring circuit for connecting the opening portion and the predetermined solder ball arrangement portion is treated with an alkali etching solution. Removed. After that, a photosensitive solder resist (CFP-1123 made by Sumitomo Bakelite) layer is formed so as to cover the entire surface of the wafer, and a solder ball arrangement portion is opened. Thereafter, together with the flux, solder balls were placed in the solder resist openings, put into a reflow step, and each semiconductor element was diced into individual pieces by a dicing machine to obtain a semiconductor device that independently functions. It was confirmed that the semiconductor device thus obtained has no problem in its operation as a semiconductor device.

【0023】[0023]

【発明の効果】本発明によれば、半導体装置の小型化及
び低コスト化を可能とする、半導体装置の製造方法が適
用でき、また、その製造方法により得られる半導体装置
は、品質信頼性に優れる。
According to the present invention, a method of manufacturing a semiconductor device, which enables downsizing and cost reduction of the semiconductor device, can be applied, and the semiconductor device obtained by the manufacturing method has high quality reliability. Excel.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子の集合体である半導体ウェハ
ー表面全体に形成された、絶縁樹脂層上に、半田ボール
を搭載するためのパッド、チップとの接続のためのボン
ドフィンガー、および両者をつなぐための回路(再配線
用回路)が、ウェハー上の各チップに対応して形成され
てなる半導体装置の製造方法において、半導体ウェハー
を成形用金型内に配置し、圧縮成形、移送成形又は射出
成形により、絶縁樹脂層を成形して形成することを特徴
とする、半導体装置の製造方法。
1. A pad for mounting a solder ball, a bond finger for connecting to a chip, and a bond between the two are formed on an insulating resin layer formed on the entire surface of a semiconductor wafer which is an assembly of semiconductor elements. In the method of manufacturing a semiconductor device in which a circuit for rewiring (circuit for rewiring) is formed corresponding to each chip on the wafer, the semiconductor wafer is placed in a molding die, and compression molding, transfer molding or injection molding is performed. A method for manufacturing a semiconductor device, comprising forming an insulating resin layer by molding.
【請求項2】 半導体ウェハーを成形用金型内に配置す
る際に、半導体ウェハー上に絶縁樹脂層を形成する間隙
を設けて、再配線回路形成用銅箔が配置される、請求項
1記載の半導体装置の製造方法。
2. The copper foil for forming a rewiring circuit is arranged with a gap for forming an insulating resin layer on the semiconductor wafer when the semiconductor wafer is arranged in a molding die. Of manufacturing a semiconductor device of.
【請求項3】 再配線回路形成用銅箔が、絶縁樹脂層形
成面と反対側に補強材を有する請求項2記載の半導体装
置の製造方法。
3. The method for manufacturing a semiconductor device according to claim 2, wherein the rewiring circuit forming copper foil has a reinforcing material on the side opposite to the surface on which the insulating resin layer is formed.
【請求項4】 再配線回路が、再配線回路形成用銅箔を
用いてサブトラクティブもしくはセミアディティブ法に
より形成される、請求項1、2又は3記載の半導体装置
の製造方法。
4. The method of manufacturing a semiconductor device according to claim 1, wherein the redistribution circuit is formed by a subtractive or semi-additive method using a redistribution circuit forming copper foil.
【請求項5】 半導体素子入出力端子上の絶縁樹脂層を
レーザーにより除去することにより前記入出力端子を露
出させ、その開口部を介して、入出力端子と再配線用回
路が銅メッキにより接続される、請求項1、2、3又は
4記載の半導体装置の製造方法。
5. The input / output terminal is exposed by removing the insulating resin layer on the input / output terminal of the semiconductor element with a laser, and the input / output terminal and the rewiring circuit are connected by copper plating through the opening. The method for manufacturing a semiconductor device according to claim 1, 2, 3, or 4.
【請求項6】 請求項1ないし請求項5のいずれかに記
載された製造方法によって、製造されたものであること
を特徴とする半導体装置。
6. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 5.
JP2001298564A 2001-09-27 2001-09-27 Semiconductor device manufacturing method and semiconductor device Pending JP2003100787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001298564A JP2003100787A (en) 2001-09-27 2001-09-27 Semiconductor device manufacturing method and semiconductor device

Publications (1)

Publication Number Publication Date
JP2003100787A true JP2003100787A (en) 2003-04-04

Family

ID=19119450

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2003100787A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817855A (en) * 1994-06-29 1996-01-19 Nitto Denko Corp Manufacture of semiconductor device and laminate used therefor
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof
JP2001127095A (en) * 1999-10-29 2001-05-11 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2001144212A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Semiconductor chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817855A (en) * 1994-06-29 1996-01-19 Nitto Denko Corp Manufacture of semiconductor device and laminate used therefor
JPH1079362A (en) * 1996-07-12 1998-03-24 Fujitsu Ltd Manufacture of semiconductor device, mold for manufacturing semiconductor device, semiconductor device and mounting method thereof
JP2001127095A (en) * 1999-10-29 2001-05-11 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2001144212A (en) * 1999-11-16 2001-05-25 Ibiden Co Ltd Semiconductor chip

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