WO2013061500A1 - Flexible wiring board and method for manufacturing same - Google Patents

Flexible wiring board and method for manufacturing same Download PDF

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Publication number
WO2013061500A1
WO2013061500A1 PCT/JP2012/005238 JP2012005238W WO2013061500A1 WO 2013061500 A1 WO2013061500 A1 WO 2013061500A1 JP 2012005238 W JP2012005238 W JP 2012005238W WO 2013061500 A1 WO2013061500 A1 WO 2013061500A1
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WO
WIPO (PCT)
Prior art keywords
conductor
wiring board
bump
conductive
flexible wiring
Prior art date
Application number
PCT/JP2012/005238
Other languages
French (fr)
Japanese (ja)
Inventor
典昭 関根
Original Assignee
山一電機株式会社
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Filing date
Publication date
Application filed by 山一電機株式会社 filed Critical 山一電機株式会社
Publication of WO2013061500A1 publication Critical patent/WO2013061500A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985Flexible insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/06772High frequency probes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/286External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189Pressing leads, bumps or a die through an insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Definitions

  • the present invention relates to a flexible wiring board used as a substrate for semiconductor packages, transmission wiring, circuit wiring, and the like, and a method for manufacturing the same.
  • flexible wiring boards used in electronic devices such as network devices, servers, and testers require high-speed transmission without impairing their high-frequency characteristics when using high-speed digital signals in the range of several GHz to several tens of GHz.
  • mobile electronic devices such as portable devices
  • the flexible wiring board is being made to have high density wiring and light weight.
  • the wiring patterns that become transmission wirings or circuit wirings are miniaturized and the wiring density is increased by multilayering.
  • conductive members for electrically connecting the wiring pattern layers are formed by plating in via holes, through holes, etc. provided in the interlayer insulator layer.
  • conductive bumps are embedded in interlayer insulating layers and applied to conductive members (for example, see Patent Document 1).
  • the semiconductor devices mounted on the flexible wiring board are made finer, higher-integrated, faster, or multi-functional (hereinafter referred to as higher performance of semiconductor devices). Say) is remarkable.
  • the number of external connection terminals in the semiconductor chip has increased, and for example, BGA (Ball Grid Array) package, LGA (Land Grid Array) package, CSP (Chip Size Package) and the like have been frequently used.
  • BGA Ball Grid Array
  • LGA Land Grid Array
  • CSP Chip Size Package
  • various attempts have been made to increase the density of conductor patterns (see, for example, Patent Documents 2 and 3).
  • Patent Document 1 Japanese Patent No. 3816038 Patent Document 2: Japanese Patent No. 3378171 Patent Document 3: Japanese Patent Application Laid-Open No. 2005-26491
  • the interlayer insulator layer and the wiring layer are thinned with the increase in wiring density, and the flexibility of the base material is increased.
  • this high flexibility leads to a decrease in productivity in the process of laminating and integrating the interlayer insulator layer and the wiring layer or in the process of forming conductive bumps due to the poor handling properties.
  • the manufacturing cost of the flexible wiring board may increase.
  • SiP System-in-Package
  • MCM Multi-Chip Module
  • the present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a flexible wiring board and a method for manufacturing the same that enable high-density wiring with high productivity. And the flexible wiring board which can respond easily to the high performance of a semiconductor device and enables the high-density mounting is provided.
  • a flexible wiring board according to the present invention is a flexible wiring board in which a plurality of layers of conductor patterns are laminated in multiple layers, and two or more layers of conductor patterns are integrally laminated on a conductor plate with an interlayer insulator layer interposed therebetween.
  • conductive paste bumps penetrating the interlayer insulating layer
  • conductive bumps are formed which are electrically connected to the conductor pattern by etching the conductor plate in contact with the conductor pattern, The conductor bump protrudes from the main surface of the interlayer insulator layer on which the conductor pattern is disposed.
  • a method for manufacturing a flexible wiring board includes a step of electrically contacting a layer of a first conductor pattern on a surface of a conductor plate, and a conductive paste bump in a predetermined region of the first conductor pattern.
  • a step of forming, and a resin film to be an interlayer insulating layer and a metal foil to be the second conductor pattern are laminated in this order on the conductive paste bump, and heated and pressed to electrically connect the conductive paste bump and the metal foil.
  • the present invention it is possible to provide a flexible wiring board and a method for manufacturing the same that enable high density wiring with high productivity.
  • a flexible wiring board that can easily cope with high performance of semiconductor devices and enables high-density mounting.
  • FIG. 1 is a partially enlarged cross-sectional view illustrating an example of a flexible wiring board according to a first embodiment of the present invention.
  • Sectional drawing according to manufacturing process which shows the manufacturing method of an example of the flexible wiring board concerning the 1st Embodiment of this invention.
  • Sectional drawing according to the manufacturing process following the process of FIG. 2A and 2B show specific examples of the flexible wiring board according to the first embodiment of the present invention, in which FIG. 1A is a plan view of a semiconductor package substrate, and FIG. 2B is an enlarged cross-sectional view taken along line XX in FIG.
  • the partial expanded sectional view which shows an example of the flexible wiring board concerning the 2nd Embodiment of this invention.
  • Sectional drawing according to manufacturing process which shows the manufacturing method of an example of the flexible wiring board concerning the 2nd Embodiment of this invention.
  • the flexible wiring board has a conductor bump protruding from its main surface.
  • This embodiment uses both conductive paste bumps and conductor bumps.
  • the conductor bumps are formed from a metal conductor plate that makes a fragile flexible laminate board rigid and easy to process in the manufacturing process of the flexible wiring board.
  • a conductor plate bump is formed by etching from this conductor plate. That is, the conductor plate functions as a substrate support, as will be described later, and is formed on the conductor bumps to function as connection bumps for connection lands and interlayer insulators.
  • the 1st conductor pattern 12 and the 2nd conductor pattern 13 are laminated
  • the predetermined first conductor pattern 12 and the second conductor pattern 13 are electrically connected through the conductive paste bumps 14.
  • the conductive paste bump 14 provided by this printing is formed so as to penetrate the interlayer insulator layer 11.
  • the conductor bumps 15 are electrically connected to the predetermined first conductor pattern 12.
  • the conductor bump 15 protrudes from the main surface 11 a of the interlayer insulator layer 11 on which the first conductor pattern 12 is arranged, that is, the main surface of the flexible wiring board 10.
  • the conductor bump 15 is formed by etching a conductive plate, as will be described later in the description of the method for manufacturing the flexible wiring board 10. In the example shown in FIG. 1, the conductive bumps 15 formed by etching are shown to overlap with the conductive paste bumps 14 via the first conductive pattern 12, but in the region where the conductive paste bumps 14 are not provided.
  • One conductor pattern 12 may be connected and protruded.
  • the conductor bumps 15 are preferably electrically connected to the first conductor pattern 12 via the metal barrier 16, but may be directly connected to the first conductor pattern 12.
  • a solder resist 17 is formed between the patterns of the second conductor pattern 13.
  • a plating layer 18 is preferably formed on the surfaces of the first conductor pattern 12, the second conductor pattern 13, and the conductor bump 15.
  • a thermoplastic resin or a thermosetting resin is used as the interlayer insulator layer 11.
  • a liquid crystal polymer is particularly preferable because it exhibits excellent high-frequency transmission characteristics and flexibility.
  • the liquid crystal polymer is, for example, a multiaxially oriented thermoplastic polymer represented by xidar (trade name, manufactured by Dartco) or Vectra (trade name, manufactured by Clanese). Further, it may be modified by adding and blending another insulating resin. Examples thereof include Bexter FA type, Bexter CT type, and BIAC film.
  • the first conductor pattern 12 and the second conductor pattern 13 are made of normal copper (Cu) or a copper alloy.
  • the conductive paste bump 14 includes a granular metal material such as silver (Ag), Cu, gold (Au), solder, or the like using a resin as a binder.
  • the conductor bump 15 is made of a metal material such as Cu or Cu alloy.
  • the metal barrier 16 is made of a metal material such as nickel (Ni) or tin (Sn), and the plating layer 18 is a single layer of Au, Ag, or nickel (Ni), or Ni / Au, Ni / Ag, or the like. It consists of a composite layer.
  • a clad material having a three-layer structure of a first metal foil (for example, Cu foil) 23 having a thickness of 10 mm is prepared.
  • the conductive plate 21 is preferably thicker than the wiring layer (first conductive pattern) in order to increase the rigidity of the flexible laminate during the manufacturing process.
  • the first metal foil 23 is in electrical contact with the conductor plate 21 by adopting a clad structure.
  • an etching resist 24 having a predetermined pattern is formed on the surface, and an etching resist 25 that covers the entire back side of the conductor plate 21 is formed.
  • these etching resists are formed, for example, by photolithography using a known photosensitive dry film.
  • the first metal foil 23 is selectively etched using the etching resists 24 and 25 as an etching mask by immersing in an etching solution of a chemical solution such as an ammonia-based alkaline etching solution that selectively dissolves Cu.
  • the metal barrier layer 22 functions as an etching stopper.
  • the etching resists 24 and 25 are removed or dissolved with an alkaline aqueous solution and removed. In this way, the first conductor pattern 12 is formed on the metal barrier layer 22 as shown in FIG.
  • the conical conductive paste 26 is obtained by repeating screen printing and drying of the conductive paste using, for example, a stainless steel screen plate on the predetermined first conductive pattern 12. Make a bump.
  • the conductive paste is, for example, a mixture of metal particles such as Ag, Au, Cu, Sn, lead (Pb), and carbon and an epoxy resin, a phenol resin, an acrylic resin, or the like.
  • a resin film 11 having a thickness of about 15 ⁇ m to 50 ⁇ m and a second metal foil 27 made of, for example, Cu having a thickness of about 10 ⁇ m to 50 ⁇ m are stacked from above.
  • heat and pressure treatment heat press
  • the conical conductive paste 26 undergoes a composition change along with plastic deformation in which the head is crushed, and the conductive paste bump 14 become.
  • the conductive paste bump 14 is inserted through the interlayer insulator layer 11 and connected to the second metal foil 27.
  • the interlayer insulator layer 11 is made of a thermoplastic resin film such as a liquid crystal polymer, and is bonded to the first conductor pattern 12 and the metal barrier layer 22 by thermocompression bonding.
  • the atmospheric gas is, for example, in a reduced pressure state, and the heating temperature at that time is a temperature at which the thermoplastic resin film is heat-softened, and in the case of a thermosetting resin film, the temperature is the temperature at which thermosetting is performed.
  • the temperature is set to about 180 ° C. to 230 ° C.
  • the pressurization is, for example, about 30 to 100 kgf / cm 2 .
  • the productivity is improved particularly in the process of forming the conical conductive paste 26 shown in FIGS. 2D and 2E or laminating and integrating by hot pressing.
  • an etching resist is applied on both sides to form an etching mask (not shown), and the second metal foil 27 is selectively etched with the same chemical solution as described above. .
  • a second conductor pattern 13 having a required pattern is formed.
  • a solder resist 17 is formed between the patterns of the second conductor patterns 13.
  • an etching resist 28 having a predetermined pattern is formed on the surface of the conductor plate 21, and an etching resist 29 covering the entire surface of the first conductor pattern 13, the solder resist 17, and the like is formed.
  • etching resists are formed by, for example, photolithography using a known photosensitive dry film, as described with reference to FIG.
  • the conductive plate 21 is immersed in a chemical solution for etching, and the conductive plate 21 is selectively wet etched using the etching resists 28 and 29 as an etching mask. Also in this case, the metal barrier layer 22 functions as an etching stopper. This prevents the first conductive pattern from being etched. Thereafter, the etching resists 28 and 29 are removed or dissolved and removed with an alkaline aqueous solution. In this way, a conductor bump 15 as shown in FIG. 3D is formed.
  • the conductor bump 15 has a trapezoidal shape whose cross section is a forward tapered shape.
  • the exposed metal barrier layer 22 is selectively removed by etching using, for example, a chemical solution that selectively dissolves Ni. Thereafter, a plating layer 18 is formed on the surface of the conductor bump 15, the surface of the first conductor pattern 12, and the surface of the second conductor pattern 13 as shown in FIG. In this way, the flexible wiring board 10 is manufactured.
  • a flexible wiring substrate 10a as shown in FIG. 4A is an example of a package substrate on which a plurality of semiconductor chips can be mounted, and is used for a BGA package or an LGA package that can easily be multi-pinned.
  • a predetermined number of die lands 31 are arranged as second conductor patterns on the upper surface thereof.
  • a required number of wire connection lands 32 are formed as second conductor patterns so as to surround each die land 31.
  • connection lands 32 are formed on one main surface 11a of the flexible wiring board 10a, that is, the lower surface shown in the figure, through the conductive paste bumps 14 penetrating the interlayer insulator layer 11 as shown in FIG. 4B.
  • the conductor bumps 15 are electrically connected.
  • solder resists 17 and 33 are respectively formed between the die land 31 and the connection land 32 on the upper surface of the flexible wiring board 10a and between the conductor bumps 15 on the lower surface thereof.
  • the semiconductor chip is attached to the die land 31 with, for example, a conductive paste or an insulating paste.
  • the electrode pads of the respective semiconductor chips are connected to the connection lands 32 by bonding wires. In this manner, these semiconductor chips and bonding wires are resin-sealed, and a plurality of semiconductor chips are mounted on the flexible wiring board 10a with high density.
  • a flexible wiring board on which a semiconductor chip is flip-chip mounted there is a flexible wiring board on which a semiconductor chip is flip-chip mounted.
  • a flexible wiring board 10 having a structure as described in FIG. 1 can be applied. That is, in the flexible wiring board 10 of FIG. 1, the conductor bumps 15 on the lower surface 11a are formed as described with reference to FIG. Then, second conductor patterns 13 (including connection lands) connected to these conductor bumps 15 through the conductive paste bumps 14 are disposed on the upper surface of the flexible wiring board 10. These second conductor patterns 13 have a structure in which they are flip-chip connected to external connection terminals such as electrode pads or solder ball bumps on a semiconductor chip.
  • the conductor bump 15 becomes an external connection bump of the semiconductor package substrate, and is used for electrical connection with a mother board such as a printed circuit wiring board.
  • a mother board such as a printed circuit wiring board.
  • this flexible wiring board it is possible to increase the density of the conductor pattern to be the wiring and to make the conductor bump finer and more accurate. For this reason, it becomes easy to cope with miniaturization and high integration of semiconductor devices. Further, high-density mounting of, for example, SiP on a semiconductor device with high performance such as multi-function becomes easy.
  • a probe board for conducting an electric current inspection of an electronic device such as a semiconductor device or a display device such as an FPD.
  • This flexible wiring board as a probe board is attached to the tip of a probe head attached to a probe card in an energization inspection apparatus (hereinafter also referred to as a prober) for energizing an electronic device.
  • the conductor bump 15 on the lower surface of the flexible wiring board 10 described in FIG. 1 is a probe (contactor) that comes into contact with an external connection terminal of a device under test (hereinafter also referred to as Device under Test; DUT). Function as.
  • the second conductor pattern 13 on the upper surface of the flexible wiring board 10 is appropriately connected to the circuit wiring of the probe card via the probe head.
  • the conventional needle-shaped contact attached to the probe head has a limit in processing accuracy, and it is difficult to cope with a large number of pins and a narrow pitch.
  • the flexible wiring board according to the present embodiment is remarkably improved in dimensional accuracy including the height of the protruding conductor bumps, so that it is very easy to cope with a large number of pins and a narrow pitch. To do. In addition, its reliability is increased. For this reason, the flexible wiring board of the present embodiment is extremely useful as a probe board for electronic devices in which the number of external connection terminals is increased and the pitch is reduced. This energization inspection includes a burn-in test.
  • the flexible wiring board of the above embodiment can be variously multilayered by build-up.
  • an uncured thermosetting resin is sandwiched between the substrate in the state shown in FIG. 3A described in the method for manufacturing the flexible wiring board 10 and another prepared substrate in FIG. 3E is heated. Laminated and integrated by pressing.
  • the conductor bump 15 becomes a conductive member that penetrates the thermosetting resin and connects to the second conductor pattern 13.
  • a flexible wiring board having a wiring layer composed of four layers of conductor patterns and a conductor bump protruding from the main surface of the board is formed.
  • a conical conductive paste is formed on the predetermined second conductor pattern 13 of the substrate without the solder resist 17, and the substrate in the state of FIG. Laminated and integrated by hot pressing with curable resin in between. Thereafter, the conductor plate 21 in the state of FIG. 3A is processed into a conductor bump. In this way, a flexible wiring board having four-layer wirings that electrically connect the conductive bumps protruding from the main surfaces of the upper and lower surfaces of the substrate and the two-layer conductive paste bumps as conductive members is formed.
  • the flexible wiring board of the present embodiment two or more conductor pattern layers are laminated and integrated with an interlayer insulator layer interposed therebetween, and these conductor pattern layers are electrically connected by conductive paste bumps.
  • a conductor bump connected to the outermost layer of the conductor pattern or the conductive paste bump is formed by etching the conductor plate, and the conductor bump protrudes from the main surface of the flexible wiring board. For this reason, the flexible wiring board according to the present embodiment facilitates miniaturization and high-density mounting of the semiconductor package as described above.
  • the flexible wiring board of this embodiment can easily cope with external connection terminals that are multi-terminal and narrow pitched as the performance of a semiconductor device increases or the definition of a display device increases. And in the energization test
  • the interlayer insulator layer 11 is made of a liquid crystal polymer
  • the relative dielectric constant is 3 or less
  • the electrostatic tangent is 0.003 or less.
  • the wiring on the flexible wiring board 10 exhibits extremely excellent transmission / conduction characteristics of high-speed digital signals in the range of several GHz to several tens of GHz. For this reason, high-speed mounting and accurate energization inspection that do not degrade the performance of semiconductor devices at high speeds are possible.
  • a conductor plate that finally becomes a conductor bump of the flexible wiring board is used by etching.
  • a very thin resin sheet can be used for processing on the basis of a conductor plate, and even if the base material becomes more flexible as the conductor pattern of the flexible wiring board becomes denser and thinner, its high flexibility It is possible to prevent a decrease in handling property due to the property.
  • the combination of the printed bumps made of conductive paste bumps and the etching bumps on the conductive plate can give the element mounting elasticity even on a thin board such as a flexible circuit board, thereby improving the connection reliability. Further, the productivity in the process of laminating and integrating the interlayer insulator layer and the wiring layer or the process of forming the conductive paste bump is improved, and the cost of the flexible wiring board can be reduced.
  • the conductor bump is a conductive member that electrically connects the conductor pattern layers together with the conductive paste bump.
  • the flexible wiring board 20 of the example has four conductor pattern layers.
  • the first conductor pattern 42 is disposed on the lower surface 41a and the second conductor pattern 43 is disposed on the upper surface 41b with the first insulator layer 41 interposed therebetween, and the predetermined first conductor pattern 42 and second conductor pattern 43 are disposed.
  • a conductive paste bump 54 is connected by a conductive paste bump 54.
  • the conductive paste bump 54 penetrates the first insulator layer 41.
  • the third conductor pattern 45 is disposed on the lower surface with the second insulator layer 44 interposed therebetween, and the fourth conductor pattern 47 is disposed on the upper surface with the third insulator layer 46 interposed therebetween.
  • the predetermined third conductor pattern 45 is connected to the predetermined first conductor pattern 42 through the first conductor bump 48, and the predetermined fourth conductor pattern 47 is connected to the predetermined second conductor pattern 43 through the second conductor bump 49. is doing.
  • the first conductor bump 48 and the second conductor bump 49 are formed by etching a conductor plate, as will be described later in the description of the method for manufacturing the flexible wiring board 20.
  • the part 42 a of the predetermined first conductor pattern 42 is electrically connected to the part 47 a of the predetermined fourth conductor pattern 47 through the conductive paste bump 54, the second conductor pattern 43, and the second conductor bump 49.
  • a portion 43 a of the predetermined second conductor pattern 43 is electrically connected to a portion 45 a of the predetermined third conductor pattern 45 through the conductive paste bump 54, the first conductor pattern 42, and the first conductor bump 48. Therefore, the predetermined third conductor pattern 45a and the predetermined fourth conductor pattern 47a are arranged via the first conductor bump 48, the first conductor pattern 42, the conductive paste bump 54, the second conductor pattern 43a, and the second conductor bump 49. Can be connected electrically.
  • through holes 50 are provided in the first insulator layer 41, the second insulator layer 44, and the third insulator layer 46 as necessary. Then, the inside of the through hole 50 may be made conductive by the conductive body 50a, and the predetermined third conductor pattern 45 and the predetermined fourth conductor pattern 47 may be directly electrically connected. In the example shown in FIG. 5, the conductive body 50 a is formed integrally with the third conductor pattern 45 and the fourth conductor pattern 47.
  • a plating resist 52 having a required pattern is formed on a first conductor plate (eg, Cu plate) 51 having a thickness of 25 ⁇ m to 200 ⁇ m, for example. Then, for example, the metal barrier 53 and the first conductor pattern 42 are laminated and formed in an area where the first conductor plate 51 is exposed by electrolytic plating.
  • a first conductor plate eg, Cu plate
  • the metal barrier 53 and the first conductor pattern 42 are laminated and formed in an area where the first conductor plate 51 is exposed by electrolytic plating.
  • the metal barrier 53 is made of, for example, a Ni layer or a Sn layer having a thickness of about 0.5 ⁇ m to 1 ⁇ m
  • the first conductor pattern 42 is made of, for example, a Cu layer having a thickness of about 10 ⁇ m to 50 ⁇ m. Then, the plating resist 52 is stripped or dissolved and removed by an alkaline aqueous solution, and the first conductor pattern 42 is a predetermined region on the main surface of the first conductor plate 51 through the metal barrier 53 as shown in FIG. Formed.
  • the conical conductive paste 54 is bumped onto the predetermined first conductor pattern 42 in the same manner as described in the first embodiment.
  • the second conductor pattern 43 is formed in a predetermined region of the main surface of the second conductor plate 55 via the metal barrier 53. Then, as shown in FIG. 6D, the second conductor plate 55 is turned over, and set up and positioned together with a first resin film 56 made of, for example, a liquid crystal polymer having a thickness of about 15 ⁇ m to 50 ⁇ m.
  • the conical conductive paste 54 changes its composition along with the plastic deformation that crushes its head, and becomes a conductive paste bump.
  • the first resin film 56 becomes the first insulator layer 41 in which the first conductor pattern 42 and the second conductor pattern 43 are bonded to the both surfaces together with the metal barrier 53 and the conductive paste bumps 54 are inserted therethrough.
  • the predetermined first conductor pattern 42 and the predetermined second conductor pattern 43 are electrically connected through the conductive paste bumps 54.
  • the required hardness can be imparted by the first conductor plate 51, so that the base material of the flexible wiring board can be handled. Sexuality can be increased. For this reason, as described in the first embodiment, in particular, in the step of forming the conical conductive paste 54 shown in FIGS. 6C, 6D, and 6E or laminating and integrating by hot pressing, Its productivity is improved.
  • the first conductor plate 51 and the second conductor plate 55 are selectively etched by photolithography and wet etching.
  • a first conductor bump 48 and a second conductor bump 49 projecting from the lower surface and the upper surface of the first insulator layer 41 are formed.
  • These conductor bumps have trapezoidal cross sections, and are electrically connected to predetermined first conductor patterns 42 and second conductor patterns 43 through metal barriers 53, respectively.
  • the first conductor pattern 42 or the second conductor pattern 43 in the region where the first conductor bump 48 or the second conductor bump 49 is not formed is protected by the metal barrier 53 as an etching stopper.
  • thermosetting second resin film 57 and the second resin film 58 in an uncured state are shown in FIG. 7A by a known vacuum laminating method.
  • the first insulator layer 41 is laminated and integrated with each other.
  • a sheet-like support member (not shown) may be used to press the film from both sides.
  • the temperature in this laminate is a predetermined temperature at which the second resin film 57 and the third resin film 58 in an uncured state are cured, and is a temperature lower than the glass transition point or the melting point of the first insulator layer 41.
  • the second resin film 57 and the third resin film 58 are thermosetting resins such as ABFGX-13 (trade name) manufactured by Ajinomoto Fine Techno Co., Ltd. The thickness of these films is about 15 ⁇ m to 100 ⁇ m.
  • the second resin film 57 has the first conductor pattern 42 having the first insulator layer 41 and the metal barrier 53 bonded to the upper surface thereof, and the first conductor bumps 48 penetrated.
  • the inserted second insulator layer 44 is obtained.
  • the third resin film 58 is joined to the first conductor layer 41 and the second conductor pattern 43 having the metal barrier 53 on the lower surface thereof to become the third insulator layer 46 through which the second conductor bumps 49 are inserted. .
  • the surfaces of the second insulator layer 44, the third insulator layer 46, etc. are cleaned.
  • mechanical polishing, degreasing, pickling, etc. are performed on the surfaces of the first conductor bump 48 and the second conductor bump 49.
  • a through hole 50 penetrating the first insulator layer 41, the second insulator layer 44, and the third insulator layer 46 in a predetermined region is formed by laser processing, for example.
  • a desmear process is performed to clean the exposed surfaces of the first conductor bump 48 and the second conductor bump 49 and the inner wall of the through hole 50.
  • a metal outer layer 59 that adheres to the surface of the second insulator layer 44, the third insulator layer 46, and the inner wall of the through hole 50, for example, by electroless plating or the like.
  • the thickness of the metal outer layer 59 is set to about 10 ⁇ m to 50 ⁇ m.
  • the third conductor pattern 45 and the fourth conductor pattern 47 which are the outer layers described in FIG.
  • a plating layer (not shown) is formed on the surface of these outer layers by electroless plating such as Au. In this way, the flexible wiring board 20 as shown in FIG. 5 is manufactured.
  • the clad having a three-layer structure as described in the first embodiment Materials can be used. Also in this case, selective etching using photolithography is performed on the metal foil of the clad material.
  • first conductor pattern 42 and the first conductor plate 51 may be made of different metal materials.
  • second conductor pattern 43 and the second conductor plate 55 may be made of different metal materials.
  • the metal barrier 53 as an etching stopper can be eliminated in the wet etching of the first conductor plate 51 or the second conductor plate 55.
  • a resin film and a metal foil are laminated in this order from the first conductor bump 48 or the second conductor bump 49 on the substrate in the state of FIG.
  • the laminated metal foil corresponding to the position of the upper side (bump top) of the conductor bumps 48 and 49 is removed by etching, and then the above-described bump top surface is cleaned.
  • the third conductor pattern 45 and the fourth conductor pattern 47 can be formed by patterning the metal foil and the copper plating film. The cleaning and copper plating after the removal of the metal foil on the bump top may be combined with the mechanical polishing and the desmear process after the through-hole drilling.
  • the flexible wiring board of the second embodiment can be variously multilayered by build-up, as described in the first embodiment.
  • the base material in the state of FIG. 6C is laminated and integrated by hot pressing, for example, with an uncured thermosetting resin sandwiched from the lower surface or the upper surface of the flexible wiring board 20 described in FIG.
  • the first conductor plate 51 is processed into a conductor bump.
  • a multilayer flexible wiring board is formed.
  • a high-density wiring flexible wiring board is manufactured with high reliability of the wiring layers. be able to.
  • the conductive paste bump acts as a buffer for thermal stress caused by thermal expansion or contraction in the manufacturing process of a base material such as an insulator layer, and the conductor bump works to prevent thermal deformation of the material. It is.
  • the one having the structure of FIG. 7A can be used in the second embodiment.
  • the first conductor bump 48 and the second conductor bump 49 protruding from the lower surface and the upper surface of the first insulator layer 41 are exposed to cover the first conductor pattern 42 and the second conductor pattern 43.
  • the solder resist is deposited.
  • the conductive paste bump may be one in which a via hole or a through hole formed in the base material of the flexible wiring board is filled with a conductive paste such as Cu paste.
  • upper surface and “lower surface”.
  • the “upper surface” and the “lower surface” mean that they are in a relationship of front and back, and do not mean spatial top and bottom.

Abstract

In order to provide a flexible wiring board, which makes it possible to have high-density wiring with high productivity, and a method for manufacturing the flexible wiring board, a flexible wiring board (10) is formed, said flexible wiring board having a plurality of layers of conductor patterns (12, 13) laminated in layers. The first conductor pattern (12) and the second conductor pattern (13) are integrally laminated on a conductor board with an interlayer insulating layer (11) between the first and the second conductor patterns, the layers of the conductor patterns (12, 13) are electrically connected to each other by means of a conductive paste bump (14) that penetrates the interlayer insulating layer (11), and a conductor bump (15) electrically connected to the first conductor pattern (12) is formed by etching the conductor board in contact with the first conductor pattern (12) on the conductor board side, thereby forming the flexible wiring board having the conductor bump (15) protruding from the main surface of the interlayer insulating layer (11), said main surface having the first conductor pattern (12) disposed thereon.

Description

フレキシブル配線基板およびその製造方法Flexible wiring board and manufacturing method thereof
 本発明は、半導体パッケージや、伝送配線、回路配線等の基板として用いられるフレキシブル配線基板およびその製造方法に関する。 The present invention relates to a flexible wiring board used as a substrate for semiconductor packages, transmission wiring, circuit wiring, and the like, and a method for manufacturing the same.
 例えばネットワーク機器、サーバー、テスターのような電子機器に使用されるフレキシブル配線基板では、数GHz~数十GHz帯の高速デジタル信号の使用においてその高周波特性を損なうことなく高速伝送することが要求されている。また、例えば携帯機器類のようなモバイル電子機器では、その小型化あるいは薄型化に伴って、フレキシブル配線基板の高密度配線化および軽薄化が種々に進められている。そして、伝送配線あるいは回路配線等となる配線パターンの微細化および多層化による配線の高密度化が行われている。 For example, flexible wiring boards used in electronic devices such as network devices, servers, and testers require high-speed transmission without impairing their high-frequency characteristics when using high-speed digital signals in the range of several GHz to several tens of GHz. Yes. In mobile electronic devices such as portable devices, for example, as the size and thickness of the mobile electronic devices are reduced, the flexible wiring board is being made to have high density wiring and light weight. In addition, the wiring patterns that become transmission wirings or circuit wirings are miniaturized and the wiring density is increased by multilayering.
 上記多層化するフレキシブル配線基板では、配線パターン層間を電気接続する導通部材が、その層間絶縁体層に設けられたビアホール、スルーホール等にメッキ形成される。あるいは、導電性バンプが層間絶縁体層に埋め込まれて導通部材に適用されるようになってきている(例えば、特許文献1参照)。 In the multi-layer flexible wiring board, conductive members for electrically connecting the wiring pattern layers are formed by plating in via holes, through holes, etc. provided in the interlayer insulator layer. Alternatively, conductive bumps are embedded in interlayer insulating layers and applied to conductive members (for example, see Patent Document 1).
 また、電子機器の小型化および高機能化を可能にするため、上記フレキシブル配線基板に実装される半導体デバイスの微細・高集積化、高速化あるいは多機能化(以下、半導体デバイスの高性能化ともいう)は著しい。それと共に半導体チップにおける外部接続用端子の数は増大し、例えばBGA(Ball Grid Array)パッケージ、LGA(Land Grid Array)パッケージ、CSP(Chip Size Package)等が多用されるようになってきている。そして、これ等のパッケージ基板であるインターポーザあるいはフィルム状基板等のフレキシブル配線基板において、配設される導体パターンの高密度化が種々に検討されている(例えば、特許文献2,3参照)。 In addition, in order to enable downsizing and higher functionality of electronic equipment, the semiconductor devices mounted on the flexible wiring board are made finer, higher-integrated, faster, or multi-functional (hereinafter referred to as higher performance of semiconductor devices). Say) is remarkable. At the same time, the number of external connection terminals in the semiconductor chip has increased, and for example, BGA (Ball Grid Array) package, LGA (Land Grid Array) package, CSP (Chip Size Package) and the like have been frequently used. In addition, in a flexible wiring board such as an interposer or a film-like board as these package boards, various attempts have been made to increase the density of conductor patterns (see, for example, Patent Documents 2 and 3).
 特許文献1: 特許第3816038号公報
 特許文献2: 特許第3378171号公報
 特許文献3: 特開2005-26491号公報
Patent Document 1: Japanese Patent No. 3816038 Patent Document 2: Japanese Patent No. 3378171 Patent Document 3: Japanese Patent Application Laid-Open No. 2005-26491
 上記軽薄化するフレキシブル配線基板では、配線の高密度化と共に層間絶縁体層および配線層が薄層化して、その基材の柔軟性は高くなる。フレキシブル配線基板の製造工程において、この高い柔軟性は、そのハンドリング性の悪さから、層間絶縁体層および配線層の積層・一体化の工程あるいは導電性バンプの形成工程での生産性の低下につながる。ここで、高柔軟性の基材を高精度に取り扱うことができるハンドリング技術を採り入れることもできる。しかし、いずれにしてもフレキシブル配線基板の製造コストが上昇する虞がある。 In the flexible wiring board that is lightened and thinned, the interlayer insulator layer and the wiring layer are thinned with the increase in wiring density, and the flexibility of the base material is increased. In the manufacturing process of flexible wiring boards, this high flexibility leads to a decrease in productivity in the process of laminating and integrating the interlayer insulator layer and the wiring layer or in the process of forming conductive bumps due to the poor handling properties. . Here, it is possible to adopt a handling technique that can handle a highly flexible base material with high accuracy. However, in any case, the manufacturing cost of the flexible wiring board may increase.
 また、例えばSiP(System in Package)あるいはMCM(Multi-Chip Module)にみられるように、半導体デバイスの更なる高密度実装を可能にする半導体パッケージに対する要求は強い。しかし、そのような半導体パッケージに用いられるインターポーザ基板等のフレキシブル配線基板においても、その軽薄化あるいは配線の高密度化に伴う製造コストの上昇の虞が生じる。そして、この半導体パッケージの場合には、半導体デバイスの高性能化に対応できてその高密度実装を可能にする新技術も望まれている。 Also, as seen in, for example, SiP (System-in-Package) or MCM (Multi-Chip Module), there is a strong demand for a semiconductor package that enables higher-density mounting of semiconductor devices. However, even in a flexible wiring board such as an interposer board used in such a semiconductor package, there is a risk of an increase in manufacturing cost due to the lighter thickness or higher wiring density. In the case of this semiconductor package, a new technology that can cope with high performance of semiconductor devices and enables high-density mounting is also desired.
 本発明は、上述の事情等に鑑みてなされたもので、配線の高密度化を高い生産性のもとに可能にするフレキシブル配線基板およびその製造方法を提供することを目的とする。そして、半導体デバイスの高性能化に容易に対応でき、その高密度実装を可能にするフレキシブル配線基板を提供する。 The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a flexible wiring board and a method for manufacturing the same that enable high-density wiring with high productivity. And the flexible wiring board which can respond easily to the high performance of a semiconductor device and enables the high-density mounting is provided.
 本発明にかかるフレキシブル配線基板は、複数層の導体パターンを多層に積層したフレキシブル配線基板において、導体板上に層間絶縁体層を挟んで2層以上の導体パターンが一体に積層され、前記導体パターンの層間が前記層間絶縁層を貫通する導電性ペーストバンプにより電気的に接続され、前記導体パターンに接触する前記導体板のエッチング加工により前記導体パターンに電気的に接続される導体バンプが形成され、前記導体バンプが前記導体パターンを配置した前記層間絶縁体層の主面から突き出している。 A flexible wiring board according to the present invention is a flexible wiring board in which a plurality of layers of conductor patterns are laminated in multiple layers, and two or more layers of conductor patterns are integrally laminated on a conductor plate with an interlayer insulator layer interposed therebetween. Are electrically connected by conductive paste bumps penetrating the interlayer insulating layer, conductive bumps are formed which are electrically connected to the conductor pattern by etching the conductor plate in contact with the conductor pattern, The conductor bump protrudes from the main surface of the interlayer insulator layer on which the conductor pattern is disposed.
 本発明にかかるフレキシブル配線基板の製造方法は、導体板の表面に第1導体パターンの層を電気的に接触させて形成する工程と、前記第1導体パターンの所定の領域に導電性ペーストバンプを形成する工程と、前記導電性ペーストバンプ上から、層間絶縁層となる樹脂フィルムと第2導体パターンとなる金属箔をこの順に積層し加熱加圧して前記導電性ペーストバンプと前記金属箔を電気的に接続する工程と、前記金属箔をパターニングして第2導体パターンを形成する工程と、前記導体板をエッチング加工して前記第1導電パターンに電気的に接続する導体バンプにする工程とを有する。 A method for manufacturing a flexible wiring board according to the present invention includes a step of electrically contacting a layer of a first conductor pattern on a surface of a conductor plate, and a conductive paste bump in a predetermined region of the first conductor pattern. A step of forming, and a resin film to be an interlayer insulating layer and a metal foil to be the second conductor pattern are laminated in this order on the conductive paste bump, and heated and pressed to electrically connect the conductive paste bump and the metal foil. A step of patterning the metal foil to form a second conductor pattern, and a step of etching the conductor plate to form a conductor bump electrically connected to the first conductive pattern. .
 本発明により、配線の高密度化を高い生産性のもとに可能にするフレキシブル配線基板およびその製造方法を提供することができる。また、半導体デバイスの高性能化に容易に対応でき、その高密度実装を可能にするフレキシブル配線基板を提供することができる。 According to the present invention, it is possible to provide a flexible wiring board and a method for manufacturing the same that enable high density wiring with high productivity. In addition, it is possible to provide a flexible wiring board that can easily cope with high performance of semiconductor devices and enables high-density mounting.
本発明の第1の実施形態にかかるフレキシブル配線基板の一例を示す一部拡大断面図。1 is a partially enlarged cross-sectional view illustrating an example of a flexible wiring board according to a first embodiment of the present invention. 本発明の第1の実施形態にかかるフレキシブル配線基板の一例の製造方法を示す製造工程別断面図。Sectional drawing according to manufacturing process which shows the manufacturing method of an example of the flexible wiring board concerning the 1st Embodiment of this invention. 図2の工程に続く製造工程別断面図。Sectional drawing according to the manufacturing process following the process of FIG. 本発明の第1の実施形態にかかるフレキシブル配線基板の具体例を示し、(a)は半導体パッケージ基板の平面図、(b)は(a)のX-X矢視の拡大断面図。2A and 2B show specific examples of the flexible wiring board according to the first embodiment of the present invention, in which FIG. 1A is a plan view of a semiconductor package substrate, and FIG. 2B is an enlarged cross-sectional view taken along line XX in FIG. 本発明の第2の実施形態にかかるフレキシブル配線基板の一例を示す一部拡大断面図。The partial expanded sectional view which shows an example of the flexible wiring board concerning the 2nd Embodiment of this invention. 本発明の第2の実施形態にかかるフレキシブル配線基板の一例の製造方法を示す製造工程別断面図。Sectional drawing according to manufacturing process which shows the manufacturing method of an example of the flexible wiring board concerning the 2nd Embodiment of this invention. 図6の工程に続く製造工程別断面図。Sectional drawing according to manufacturing process following the process of FIG.
 以下に本発明の好適な実施形態のいくつかについて図面を参照して説明する。ここで、図面は模式的なものであり、各寸法の比率等は現実のものとは異なる。 Hereinafter, some preferred embodiments of the present invention will be described with reference to the drawings. Here, the drawings are schematic, and ratios of dimensions and the like are different from actual ones.
(第1の実施形態)
 本発明の第1の実施形態にかかるフレキシブル配線基板について図1ないし図4を参照して説明する。この実施形態ではフレキシブル配線基板がその主面から突出する導体バンプを有する構造になっている。
(First embodiment)
A flexible wiring board according to a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, the flexible wiring board has a conductor bump protruding from its main surface.
 本実施形態は導電性ペーストバンプと導体バンプの両者を用いる。導体バンプはフレキシブル配線基板の製造工程で、脆弱なフレキシブル積層板に剛性を持たせて加工を容易にする金属導体板から形成される。この導体板から導体板バンプがエッチングにより形成される。すなわち導体板は後述するように基板支持体として機能し、導体バンプに形成されて接続ランドや層間絶縁体の接続バンプとして機能する。 This embodiment uses both conductive paste bumps and conductor bumps. The conductor bumps are formed from a metal conductor plate that makes a fragile flexible laminate board rigid and easy to process in the manufacturing process of the flexible wiring board. A conductor plate bump is formed by etching from this conductor plate. That is, the conductor plate functions as a substrate support, as will be described later, and is formed on the conductor bumps to function as connection bumps for connection lands and interlayer insulators.
 図1に示すように、その一例のフレキシブル配線基板10では、層間絶縁体層11を挟んで両面に第1導体パターン12および第2導体パターン13が積層して一体に配設されている。そして、所定の第1導体パターン12と第2導体パターン13とが導電性ペーストバンプ14を通して電気接続される。この印刷により設けられる導電性ペーストバンプ14は層間絶縁体層11を貫通するように形成されている。 As shown in FIG. 1, in the flexible wiring board 10 of the example, the 1st conductor pattern 12 and the 2nd conductor pattern 13 are laminated | stacked and arrange | positioned integrally on both surfaces on both sides of the interlayer insulator layer 11. As shown in FIG. Then, the predetermined first conductor pattern 12 and the second conductor pattern 13 are electrically connected through the conductive paste bumps 14. The conductive paste bump 14 provided by this printing is formed so as to penetrate the interlayer insulator layer 11.
 また、所定の第1導体パターン12に導体バンプ15が電気的に接続されている。この導体バンプ15は第1導体パターン12を配置した層間絶縁体層11の主面11aすなわちフレキシブル配線基板10の主面から突き出して突設している。この導体バンプ15は、フレキシブル配線基板10の製造方法の説明において後述するように、導体板のエッチング加工により形成される。図1に示す例では、エッチングによる導体バンプ15は第1導体パターン12を介して導電性ペーストバンプ14と重層するように示されているが、導電性ペーストバンプ14が設けられていない領域で第1導体パターン12に接続し突き出させてもよい。 Further, the conductor bumps 15 are electrically connected to the predetermined first conductor pattern 12. The conductor bump 15 protrudes from the main surface 11 a of the interlayer insulator layer 11 on which the first conductor pattern 12 is arranged, that is, the main surface of the flexible wiring board 10. The conductor bump 15 is formed by etching a conductive plate, as will be described later in the description of the method for manufacturing the flexible wiring board 10. In the example shown in FIG. 1, the conductive bumps 15 formed by etching are shown to overlap with the conductive paste bumps 14 via the first conductive pattern 12, but in the region where the conductive paste bumps 14 are not provided. One conductor pattern 12 may be connected and protruded.
 上記フレキシブル配線基板10において、導体バンプ15は金属バリア16を介して第1導体パターン12に電気接続するのが好ましいが、直接に第1導体パターン12に接続しても構わない。また、第2導体パターン13のパターン間にはソルダーレジスト17が形成されると好適である。そして、第1導体パターン12、第2導体パターン13および導体バンプ15の表面にはメッキ層18が形成されるとよい。 In the flexible wiring board 10, the conductor bumps 15 are preferably electrically connected to the first conductor pattern 12 via the metal barrier 16, but may be directly connected to the first conductor pattern 12. In addition, it is preferable that a solder resist 17 is formed between the patterns of the second conductor pattern 13. A plating layer 18 is preferably formed on the surfaces of the first conductor pattern 12, the second conductor pattern 13, and the conductor bump 15.
 上記フレキシブル配線基板10において、層間絶縁体層11としては、熱可塑性樹脂あるいは熱硬化性樹脂が使用される。その中でも特に、液晶ポリマーは、優れた高周波伝送特性及びフレキシブル性を奏すること等から好ましい。ここで、液晶ポリマーとしては、例えばキシダール(商品名.Dartco社製)、ベクトラ(商品名.Clanese社製)で代表される多軸配向の熱可塑性ポリマーである。また、他の絶縁性樹脂を添加・配合し変性したものであってもよい。そして、ベクスターFAタイプ、ベクスターCTタイプ、BIACフィルムなどが例示される。 In the flexible wiring board 10, a thermoplastic resin or a thermosetting resin is used as the interlayer insulator layer 11. Among these, a liquid crystal polymer is particularly preferable because it exhibits excellent high-frequency transmission characteristics and flexibility. Here, the liquid crystal polymer is, for example, a multiaxially oriented thermoplastic polymer represented by xidar (trade name, manufactured by Dartco) or Vectra (trade name, manufactured by Clanese). Further, it may be modified by adding and blending another insulating resin. Examples thereof include Bexter FA type, Bexter CT type, and BIAC film.
 第1導体パターン12、第2導体パターン13は通常の銅(Cu)あるいは銅合金からなる。そして、導電性ペーストバンプ14は、樹脂を結着材として例えば銀(Ag)、Cu、金(Au)、ハンダ等の粒状金属材料を含んでいる。 The first conductor pattern 12 and the second conductor pattern 13 are made of normal copper (Cu) or a copper alloy. The conductive paste bump 14 includes a granular metal material such as silver (Ag), Cu, gold (Au), solder, or the like using a resin as a binder.
 導体バンプ15は例えばCu、Cu合金等の金属材料からなる。そして、金属バリア16は例えばニッケル(Ni)、錫(Sn)等の金属材料からなり、メッキ層18は、Au、Ag、ニッケル(Ni)の単層、あるいはNi/Au、Ni/Ag等の複合層からなる。 The conductor bump 15 is made of a metal material such as Cu or Cu alloy. The metal barrier 16 is made of a metal material such as nickel (Ni) or tin (Sn), and the plating layer 18 is a single layer of Au, Ag, or nickel (Ni), or Ni / Au, Ni / Ag, or the like. It consists of a composite layer.
 次に、本発明の第1の実施形態にかかるフレキシブル配線基板の製造方法の一例について説明する。図2(a)に示すように、例えば25μm~200μm厚さの導体板(例えばCu板)21、0.5μm~1μm程度の厚さの金属バリア層(例えばNi層)22および10μm~50μm程度の厚さの第1金属箔(例えばCu箔)23の3層構造のクラッド材を用意する。ここで導体板21は製造工程中のフレキシブル積層体の剛性を高めるために、配線層(第1導電パターン)よりも厚いことが好ましい。 Next, an example of a method for manufacturing the flexible wiring board according to the first embodiment of the present invention will be described. As shown in FIG. 2A, for example, a conductor plate (eg, Cu plate) 21 having a thickness of 25 μm to 200 μm, a metal barrier layer (eg, Ni layer) 22 having a thickness of about 0.5 μm to 1 μm, and about 10 μm to 50 μm. A clad material having a three-layer structure of a first metal foil (for example, Cu foil) 23 having a thickness of 10 mm is prepared. Here, the conductive plate 21 is preferably thicker than the wiring layer (first conductive pattern) in order to increase the rigidity of the flexible laminate during the manufacturing process.
 図2(b)に示すように、クラッド構造にすることで第1金属箔23は導体板21に電気的に接触している。第1金属箔23を第1導体パターン12の層に形成するために、表面に所定パターンを有するエッチングレジスト24を形成し、更に導体板21の裏側の全面を被覆するエッチングレジスト25を形成する。ここで、これ等のエッチングレジストは、例えば公知の感光性ドライフィルムを用いたフォトリソグラフィにより形成される。 As shown in FIG. 2B, the first metal foil 23 is in electrical contact with the conductor plate 21 by adopting a clad structure. In order to form the first metal foil 23 in the layer of the first conductor pattern 12, an etching resist 24 having a predetermined pattern is formed on the surface, and an etching resist 25 that covers the entire back side of the conductor plate 21 is formed. Here, these etching resists are formed, for example, by photolithography using a known photosensitive dry film.
 次に、Cuを選択的に溶解する例えばアンモニア系アルカリエッチング液等の化学薬液のエッチング液に浸漬し、エッチングレジスト24,25をエッチングマスクにして、第1金属箔23を選択エッチングする。ここで、金属バリア層22がエッチングストッパーとして機能する。そして、エッチングレジスト24,25をアルカリ水溶液により剥離ないし溶解し除去する。このようにして、図2(c)に示すように、第1導体パターン12が金属バリア層22上に形成される。 Next, the first metal foil 23 is selectively etched using the etching resists 24 and 25 as an etching mask by immersing in an etching solution of a chemical solution such as an ammonia-based alkaline etching solution that selectively dissolves Cu. Here, the metal barrier layer 22 functions as an etching stopper. Then, the etching resists 24 and 25 are removed or dissolved with an alkaline aqueous solution and removed. In this way, the first conductor pattern 12 is formed on the metal barrier layer 22 as shown in FIG.
 次に、図2(d)に示すように、所定の第1導体パターン12上に例えばステンレス鋼製のスクリーン板などを使用した導電性ペーストのスクリーン印刷・乾燥の繰り返しにより、円錐導電性ペースト26のバンプ付けをする。ここで、導電性ペーストは、例えばAg、Au、Cu、Sn、鉛(Pb)、カーボン等の金属粒子とエポキシ樹脂、フェノール樹脂、アクリル樹脂等とを混合したものである。 Next, as shown in FIG. 2D, the conical conductive paste 26 is obtained by repeating screen printing and drying of the conductive paste using, for example, a stainless steel screen plate on the predetermined first conductive pattern 12. Make a bump. Here, the conductive paste is, for example, a mixture of metal particles such as Ag, Au, Cu, Sn, lead (Pb), and carbon and an epoxy resin, a phenol resin, an acrylic resin, or the like.
 次に、例えば厚さが15μm~50μm程度の樹脂フィルム11と10μm~50μm程度の厚さの例えばCuからできた第2金属箔27とを上方から重ねる。その後に加熱加圧処理(熱プレス)して、図2(e)に示すように、円錐導電性ペースト26は、その頭部が圧潰する塑性変形と共にその組成変化が生じて導電性ペーストバンプ14になる。そして、導電性ペーストバンプ14は層間絶縁体層11を貫挿して第2金属箔27に接続する。この層間絶縁体層11は例えば液晶ポリマーのような熱可塑性の樹脂フィルムからなり、第1導体パターン12および金属バリア層22に熱圧着し接合する。 Next, for example, a resin film 11 having a thickness of about 15 μm to 50 μm and a second metal foil 27 made of, for example, Cu having a thickness of about 10 μm to 50 μm are stacked from above. Thereafter, heat and pressure treatment (heat press) is performed, and as shown in FIG. 2 (e), the conical conductive paste 26 undergoes a composition change along with plastic deformation in which the head is crushed, and the conductive paste bump 14 become. Then, the conductive paste bump 14 is inserted through the interlayer insulator layer 11 and connected to the second metal foil 27. The interlayer insulator layer 11 is made of a thermoplastic resin film such as a liquid crystal polymer, and is bonded to the first conductor pattern 12 and the metal barrier layer 22 by thermocompression bonding.
 上記熱プレスでは、雰囲気ガスは例えば減圧状態でありその時の加熱温度は、熱可塑性の樹脂フィルムが熱軟化する温度であり、熱硬化性の樹脂フィルムの場合には熱硬化する温度である。例えば180℃~230℃程度の温度に設定される。また、加圧は例えば30~100kgf/cm程度である。 In the hot press, the atmospheric gas is, for example, in a reduced pressure state, and the heating temperature at that time is a temperature at which the thermoplastic resin film is heat-softened, and in the case of a thermosetting resin film, the temperature is the temperature at which thermosetting is performed. For example, the temperature is set to about 180 ° C. to 230 ° C. The pressurization is, for example, about 30 to 100 kgf / cm 2 .
 ここで、層間絶縁体層11および第1導体パターン12が薄層化しても、導体板21により所要の剛性、強度を付与できることから、フレキシブル配線基板の製造工程における基材のハンドリング性を高くすることができる。このため、特に図2(d)、(e)で示した円錐導電性ペースト26の形成あるいは熱プレスによる積層・一体化の工程において、その生産性は向上する。 Here, even if the interlayer insulator layer 11 and the first conductor pattern 12 are thinned, the required rigidity and strength can be imparted by the conductor plate 21, so that the handling property of the base material in the manufacturing process of the flexible wiring board is increased. be able to. Therefore, the productivity is improved particularly in the process of forming the conical conductive paste 26 shown in FIGS. 2D and 2E or laminating and integrating by hot pressing.
 次に、図2(b)において説明したのと同様にして、エッチングレジストを両面に塗布してエッチングマスク(図省略)にし、上記と同様の化学薬液により、第2金属箔27を選択エッチングする。そして、図3(a)に示すように、所要のパターンを有する第2導体パターン13を形成する。更に、図3(b)に示すように、これ等の第2導体パターン13のパターン間にソルダーレジスト17を形成する。 Next, in the same manner as described in FIG. 2B, an etching resist is applied on both sides to form an etching mask (not shown), and the second metal foil 27 is selectively etched with the same chemical solution as described above. . Then, as shown in FIG. 3A, a second conductor pattern 13 having a required pattern is formed. Further, as shown in FIG. 3B, a solder resist 17 is formed between the patterns of the second conductor patterns 13.
 次に、図3(c)に示すように、導体板21の表面に所定パターンを有するエッチングレジスト28を形成し、第1導体パターン13、ソルダーレジスト17等の全面を被覆するエッチングレジスト29を形成する。これ等のエッチングレジストは、図2(b)で説明したのと同様に、例えば公知の感光性ドライフィルムを用いたフォトリソグラフィにより形成される。 Next, as shown in FIG. 3C, an etching resist 28 having a predetermined pattern is formed on the surface of the conductor plate 21, and an etching resist 29 covering the entire surface of the first conductor pattern 13, the solder resist 17, and the like is formed. To do. These etching resists are formed by, for example, photolithography using a known photosensitive dry film, as described with reference to FIG.
 そして、導体板21をエッチングする化学薬液に浸漬し、エッチングレジスト28,29をエッチングマスクにして、導体板21を選択的にウエットエッチングする。この場合においても、金属バリア層22がエッチングストッパーとして機能する。これにより第1導電パターンがエッチングされるのを防止する。その後に、エッチングレジスト28,29をアルカリ水溶液により剥離ないし溶解し除去する。このようにして、図3(d)に示すような導体バンプ15が形成される。この導体バンプ15は、その断面が順テーパー形状の台形になる。 Then, the conductive plate 21 is immersed in a chemical solution for etching, and the conductive plate 21 is selectively wet etched using the etching resists 28 and 29 as an etching mask. Also in this case, the metal barrier layer 22 functions as an etching stopper. This prevents the first conductive pattern from being etched. Thereafter, the etching resists 28 and 29 are removed or dissolved and removed with an alkaline aqueous solution. In this way, a conductor bump 15 as shown in FIG. 3D is formed. The conductor bump 15 has a trapezoidal shape whose cross section is a forward tapered shape.
 次に、図3(e)に示すように、露出する金属バリア層22を例えばNiを選択的に溶解する化学薬液により選択的にエッチング除去する。その後は、例えばAu等の無電解メッキにより、図1で示したような導体バンプ15の表面、第1導体パターン12および第2導体パターン13の表面にメッキ層18を形成する。このようにして、フレキシブル配線基板10が作製される。 Next, as shown in FIG. 3E, the exposed metal barrier layer 22 is selectively removed by etching using, for example, a chemical solution that selectively dissolves Ni. Thereafter, a plating layer 18 is formed on the surface of the conductor bump 15, the surface of the first conductor pattern 12, and the surface of the second conductor pattern 13 as shown in FIG. In this way, the flexible wiring board 10 is manufactured.
 次に、上述したように基板主面から突出する導体バンプを有している構造の具体的なフレキシブル配線基板について説明する。例えば図4(a)に示すようなフレキシブル配線基板10aは、複数の半導体チップを実装できるパッケージ基板の例であり、多ピン化が容易なBGAパッケージもしくはLGAパッケージ等に用いられる。図4に示すフレキシブル配線基板10aでは、その上面に所定数のダイランド31が第2導体パターンとして配設されている。そして、それぞれのダイランド31を囲うように所要数のワイヤー接続用の接続ランド32が第2導体パターンとして形成されている。これ等の接続ランド32は、図4(b)のようにそれぞれ層間絶縁体層11を貫挿する導電性ペーストバンプ14を通してフレキシブル配線基板10aの一主面11aすなわち図示の下面に形設されている導体バンプ15に電気接続されている。 Next, a specific flexible wiring board having a structure having conductor bumps protruding from the main surface of the board as described above will be described. For example, a flexible wiring substrate 10a as shown in FIG. 4A is an example of a package substrate on which a plurality of semiconductor chips can be mounted, and is used for a BGA package or an LGA package that can easily be multi-pinned. In the flexible wiring board 10a shown in FIG. 4, a predetermined number of die lands 31 are arranged as second conductor patterns on the upper surface thereof. A required number of wire connection lands 32 are formed as second conductor patterns so as to surround each die land 31. These connection lands 32 are formed on one main surface 11a of the flexible wiring board 10a, that is, the lower surface shown in the figure, through the conductive paste bumps 14 penetrating the interlayer insulator layer 11 as shown in FIG. 4B. The conductor bumps 15 are electrically connected.
 なお、フレキシブル配線基板10aの上面におけるダイランド31、接続ランド32の間、およびその下面における導体バンプ15の間にはそれぞれソルダーレジスト17,33が形成されている。 Note that solder resists 17 and 33 are respectively formed between the die land 31 and the connection land 32 on the upper surface of the flexible wiring board 10a and between the conductor bumps 15 on the lower surface thereof.
 上記フレキシブル配線基板10aでは、図示しないが、半導体チップがダイランド31に例えば導電性ペーストあるいは絶縁性ペーストにより貼着される。そして、それぞれの半導体チップの電極パッドがボンディングワイヤーにより接続ランド32に接続される。このようにして、これ等の半導体チップおよびボンディングワイヤーは樹脂封止され、フレキシブル配線基板10aに複数の半導体チップが高密度実装される。 In the flexible wiring board 10a, although not shown, the semiconductor chip is attached to the die land 31 with, for example, a conductive paste or an insulating paste. The electrode pads of the respective semiconductor chips are connected to the connection lands 32 by bonding wires. In this manner, these semiconductor chips and bonding wires are resin-sealed, and a plurality of semiconductor chips are mounted on the flexible wiring board 10a with high density.
 その他に、多ピン化が容易なBGAパッケージもしくはLGAパッケージの例として、半導体チップをフリップチップ実装するフレキシブル配線基板がある。このようなフレキシブル配線基板として、図示しないが、図1で説明したような構造のフレキシブル配線基板10を少し変形したものが適用できる。すなわち、図1のフレキシブル配線基板10において、その下面11aの導体バンプ15は図4(b)で説明したように形設される。そして、これ等の導体バンプ15にそれぞれ導電性ペーストバンプ14を通して接続する第2導体パターン13(接続ランドを含む)がフレキシブル配線基板10の上面に配設される。そして、これ等の第2導体パターン13は半導体チップ上の電極パッドあるいは半田ボールバンプのような外部接続用端子にフリップチップ接続する構造を有している。 In addition, as an example of a BGA package or an LGA package that can be easily multi-pinned, there is a flexible wiring board on which a semiconductor chip is flip-chip mounted. As such a flexible wiring board, although not shown, a flexible wiring board 10 having a structure as described in FIG. 1 can be applied. That is, in the flexible wiring board 10 of FIG. 1, the conductor bumps 15 on the lower surface 11a are formed as described with reference to FIG. Then, second conductor patterns 13 (including connection lands) connected to these conductor bumps 15 through the conductive paste bumps 14 are disposed on the upper surface of the flexible wiring board 10. These second conductor patterns 13 have a structure in which they are flip-chip connected to external connection terminals such as electrode pads or solder ball bumps on a semiconductor chip.
 上記ボンディングワイヤー接続あるいはフリップチップ接続のいずれであっても、導体バンプ15は半導体パッケージ基板の外部接続用バンプとなり、例えばプリント回路配線板のようなマザーボードとの電気接続に用いられる。そして、このフレキシブル配線基板では、その配線となる導体パターンの高密度化と共に導体バンプの微細化および高精度化が可能になる。このために、半導体デバイスの微細化および高集積化への対応が容易になる。そして、多機能化等の高性能化する半導体デバイスの例えばSiPにおける高密度実装が容易になる。 In either the bonding wire connection or the flip chip connection, the conductor bump 15 becomes an external connection bump of the semiconductor package substrate, and is used for electrical connection with a mother board such as a printed circuit wiring board. In this flexible wiring board, it is possible to increase the density of the conductor pattern to be the wiring and to make the conductor bump finer and more accurate. For this reason, it becomes easy to cope with miniaturization and high integration of semiconductor devices. Further, high-density mounting of, for example, SiP on a semiconductor device with high performance such as multi-function becomes easy.
 更に、基板主面から突出する導体バンプを有する構造の具体的なフレキシブル配線基板として、半導体デバイス、FPDのような表示デバイス等の電子デバイスを通電検査するためのプローブ用基板がある。このプローブ用基板としてのフレキシブル配線基板は、電子デバイスを通電検査する通電検査装置(以下、プローバともいう)において、プローブカードに装着されるプローブヘッドの先端部に取り付けられる。そして、図1に説明したフレキシブル配線基板10の下面の導体バンプ15は、被検体である被測定デバイス(以下、Device under Test;DUTともいう)の外部接続用端子に接触するプローブ(接触子)として機能する。また、フレキシブル配線基板10の上面の第2導体パターン13はプローブヘッドを介してプローブカードの回路配線に適宜に接続する。 Furthermore, as a specific flexible wiring board having a structure having a conductor bump protruding from the main surface of the board, there is a probe board for conducting an electric current inspection of an electronic device such as a semiconductor device or a display device such as an FPD. This flexible wiring board as a probe board is attached to the tip of a probe head attached to a probe card in an energization inspection apparatus (hereinafter also referred to as a prober) for energizing an electronic device. The conductor bump 15 on the lower surface of the flexible wiring board 10 described in FIG. 1 is a probe (contactor) that comes into contact with an external connection terminal of a device under test (hereinafter also referred to as Device under Test; DUT). Function as. Further, the second conductor pattern 13 on the upper surface of the flexible wiring board 10 is appropriately connected to the circuit wiring of the probe card via the probe head.
 近年、半導体デバイスの高性能化あるいは表示デバイスの高精細化に伴い、それ等の表面に形成される外部接続用端子は多端子化、狭ピッチ化している。そして、電子デバイスの通電検査が高速化し複数DUTを同時に通電検査することが行われるようになってきている。あるいは、ウェーハレベルパッケージにみられるように多数の外部接続用端子を同時に通電検査するようになってきている。 In recent years, with the improvement in performance of semiconductor devices or the increase in definition of display devices, the terminals for external connection formed on the surface of these devices have become multiterminal and narrow pitched. And the energization inspection of an electronic device is speeded up, and a plurality of DUTs are being inspected simultaneously. Alternatively, as seen in wafer level packages, a large number of external connection terminals are inspected at the same time.
 従来のプローブヘッドに取り付けられる針状の接触子では、その加工精度に限界があり、多ピン化、狭ピッチ化対応が困難であった。これに対して、本実施形態のフレキシブル配線基板は、その突設する導体バンプの高さを含めた寸法精度が格段に向上することから、多ピン化、狭ピッチ化への対応を極めて容易にする。また、その信頼性も高くなる。このために、本実施形態のフレキシブル配線基板は、特に外部接続用端子が多端子化、狭ピッチ化する電子デバイスのプローブ用基板として極めて有用になる。なお、この通電検査はバーンインテストも含む。 The conventional needle-shaped contact attached to the probe head has a limit in processing accuracy, and it is difficult to cope with a large number of pins and a narrow pitch. On the other hand, the flexible wiring board according to the present embodiment is remarkably improved in dimensional accuracy including the height of the protruding conductor bumps, so that it is very easy to cope with a large number of pins and a narrow pitch. To do. In addition, its reliability is increased. For this reason, the flexible wiring board of the present embodiment is extremely useful as a probe board for electronic devices in which the number of external connection terminals is increased and the pitch is reduced. This energization inspection includes a burn-in test.
 上記実施形態のフレキシブル配線基板はそのビルドアップによる多層化が種々に可能である。例えば、フレキシブル配線基板10の製造方法で説明した図3(a)の状態の基板上に、例えば未硬化の熱硬化性樹脂を挟んで、ほかに用意した図3(e)状態の基板を熱プレスにより積層・一体化する。このようにして、導体バンプ15は上記熱硬化性樹脂を貫挿して第2導体パターン13に接続する導通部材になる。そして、図3(a)の状態の導体板21を導体バンプに加工することにより、4層の導体パターンからなる配線層および基板主面から突出する導体バンプを有するフレキシブル配線基板が形成される。 The flexible wiring board of the above embodiment can be variously multilayered by build-up. For example, an uncured thermosetting resin is sandwiched between the substrate in the state shown in FIG. 3A described in the method for manufacturing the flexible wiring board 10 and another prepared substrate in FIG. 3E is heated. Laminated and integrated by pressing. In this way, the conductor bump 15 becomes a conductive member that penetrates the thermosetting resin and connects to the second conductor pattern 13. Then, by processing the conductor plate 21 in the state of FIG. 3A into a conductor bump, a flexible wiring board having a wiring layer composed of four layers of conductor patterns and a conductor bump protruding from the main surface of the board is formed.
 あるいは、図3(e)においてソルダーレジスト17の無い基板の所定の第2導体パターン13上に円錐導電性ペーストを形成し、図3(a)の状態の基板を裏返しにして、未硬化の熱硬化性樹脂を挟んで熱プレスにより積層・一体化する。その後、図3(a)の状態の導体板21を導体バンプに加工する。このようにすると、基板の上面および下面の主面から突出する導体バンプ、および2層の導電性ペーストバンプを導通部材として電気接続する4層配線を有するフレキシブル配線基板が形成される。 Alternatively, in FIG. 3E, a conical conductive paste is formed on the predetermined second conductor pattern 13 of the substrate without the solder resist 17, and the substrate in the state of FIG. Laminated and integrated by hot pressing with curable resin in between. Thereafter, the conductor plate 21 in the state of FIG. 3A is processed into a conductor bump. In this way, a flexible wiring board having four-layer wirings that electrically connect the conductive bumps protruding from the main surfaces of the upper and lower surfaces of the substrate and the two-layer conductive paste bumps as conductive members is formed.
 本実施形態のフレキシブル配線基板では、層間絶縁体層を挟んで2層以上の導体パターン層が積層・一体化され、これ等の導体パターン層間が導電性ペーストバンプにより電気的に接続される。また、導体パターンの最外層あるいは上記導電性ペーストバンプに接続する導体バンプが導体板のエッチング加工により形成され、この導体バンプはフレキシブル配線基板の主面から突出するようになっている。このために、本実施形態のフレキシブル配線基板は、上述したように半導体パッケージの微細化、高密度実装化等を容易にする。 In the flexible wiring board of the present embodiment, two or more conductor pattern layers are laminated and integrated with an interlayer insulator layer interposed therebetween, and these conductor pattern layers are electrically connected by conductive paste bumps. A conductor bump connected to the outermost layer of the conductor pattern or the conductive paste bump is formed by etching the conductor plate, and the conductor bump protrudes from the main surface of the flexible wiring board. For this reason, the flexible wiring board according to the present embodiment facilitates miniaturization and high-density mounting of the semiconductor package as described above.
 また、本実施形態のフレキシブル配線基板は、半導体デバイスの高性能化あるいは表示デバイスの高精細化に伴い多端子化、狭ピッチ化する外部接続用端子に容易に対応できる。そして、これ等の電子デバイスの通電検査において、そのプローブ用基板として極めて有用になる。 In addition, the flexible wiring board of this embodiment can easily cope with external connection terminals that are multi-terminal and narrow pitched as the performance of a semiconductor device increases or the definition of a display device increases. And in the energization test | inspection of these electronic devices, it becomes very useful as the board | substrate for probes.
 また、層間絶縁体層11が液晶ポリマーからなると、その比誘電率は3以下になり、静電正接は0.003以下になる。そして、フレキシブル配線基板10における配線は、数GHz~数十GHz帯の高速デジタル信号の極めて優れた伝達・伝導特性を示す。このために、半導体デバイスの高速化にあって、その性能を低下させない高密度実装、正確な通電検査が可能になる。 Further, when the interlayer insulator layer 11 is made of a liquid crystal polymer, the relative dielectric constant is 3 or less, and the electrostatic tangent is 0.003 or less. The wiring on the flexible wiring board 10 exhibits extremely excellent transmission / conduction characteristics of high-speed digital signals in the range of several GHz to several tens of GHz. For this reason, high-speed mounting and accurate energization inspection that do not degrade the performance of semiconductor devices at high speeds are possible.
 本実施形態のフレキシブル配線基板の製造方法では、エッチング加工により最終的にフレキシブル配線基板の導体バンプとなる導体板が使用される。導体板をベースにして加工するために、非常に薄い樹脂シートが使用でき、フレキシブル配線基板における導体パターンの高密度化および薄層化と共にその基材の柔軟性が高くなっても、その高柔軟性に伴うハンドリング性の低下は防止される。さらに導電性ペーストバンプによる印刷バンプと、導体板のエッチングバンプの組み合わせによって、フレキシブル回路基板のような薄い基板でも素子のマウントに弾力性をもたせることができ、接続の信頼性を高めることができる。また、層間絶縁体層および配線層の積層・一体化の工程あるいは導電性ペーストバンプの形成工程での生産性は向上し、フレキシブル配線基板の低コスト化が可能になる。 In the method for manufacturing a flexible wiring board according to the present embodiment, a conductor plate that finally becomes a conductor bump of the flexible wiring board is used by etching. A very thin resin sheet can be used for processing on the basis of a conductor plate, and even if the base material becomes more flexible as the conductor pattern of the flexible wiring board becomes denser and thinner, its high flexibility It is possible to prevent a decrease in handling property due to the property. Furthermore, the combination of the printed bumps made of conductive paste bumps and the etching bumps on the conductive plate can give the element mounting elasticity even on a thin board such as a flexible circuit board, thereby improving the connection reliability. Further, the productivity in the process of laminating and integrating the interlayer insulator layer and the wiring layer or the process of forming the conductive paste bump is improved, and the cost of the flexible wiring board can be reduced.
(第2の実施形態)
 次に、本発明の第2の実施形態にかかるフレキシブル配線基板について図5ないし図7を参照して説明する。この実施形態は、導体バンプが導電性ペーストバンプと共に導体パターン層間を電気接続する導通部材となる場合である。
(Second Embodiment)
Next, a flexible wiring board according to a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, the conductor bump is a conductive member that electrically connects the conductor pattern layers together with the conductive paste bump.
 図5に示すように、その一例のフレキシブル配線基板20は4層の導体パターン層を有する。その内層では、第1絶縁体層41を挟んで下面41aに第1導体パターン42が、および上面41bに第2導体パターン43が配設され、所定の第1導体パターン42と第2導体パターン43とが導電性ペーストバンプ54で接続している。この導電性ペーストバンプ54は第1絶縁体層41を貫挿している。 As shown in FIG. 5, the flexible wiring board 20 of the example has four conductor pattern layers. In the inner layer, the first conductor pattern 42 is disposed on the lower surface 41a and the second conductor pattern 43 is disposed on the upper surface 41b with the first insulator layer 41 interposed therebetween, and the predetermined first conductor pattern 42 and second conductor pattern 43 are disposed. Are connected by a conductive paste bump 54. The conductive paste bump 54 penetrates the first insulator layer 41.
 そして、フレキシブル配線基板20の外層では、第2絶縁体層44を挟んで下面に第3導体パターン45が配設され、第3絶縁体層46を挟んで上面に第4導体パターン47が配設されている。そして、所定の第3導体パターン45は第1導体バンプ48を通して所定の第1導体パターン42に接続し、所定の第4導体パターン47は第2導体バンプ49を通して所定の第2導体パターン43に接続している。第1導体バンプ48および第2導体バンプ49は、フレキシブル配線基板20の製造方法の説明において後述するように、導体板のエッチング加工により形成される。 In the outer layer of the flexible wiring board 20, the third conductor pattern 45 is disposed on the lower surface with the second insulator layer 44 interposed therebetween, and the fourth conductor pattern 47 is disposed on the upper surface with the third insulator layer 46 interposed therebetween. Has been. The predetermined third conductor pattern 45 is connected to the predetermined first conductor pattern 42 through the first conductor bump 48, and the predetermined fourth conductor pattern 47 is connected to the predetermined second conductor pattern 43 through the second conductor bump 49. is doing. The first conductor bump 48 and the second conductor bump 49 are formed by etching a conductor plate, as will be described later in the description of the method for manufacturing the flexible wiring board 20.
 ここで、所定の第1導体パターン42の一部42aは、導電性ペーストバンプ54および第2導体パターン43および第2導体バンプ49を介して所定の第4導体パターン47の一部47aに電気接続する。所定の第2導体パターン43の一部43aは、導電性ペーストバンプ54および第1導体パターン42および第1導体バンプ48を介して所定の第3導体パターン45の一部45aに電気接続する。したがって、所定の第3導体パターン45aおよび所定の第4導体パターン47aは、第1導体バンプ48、第1導体パターン42、導電性ペーストバンプ54、第2導体パターン43aおよび第2導体バンプ49を介して電気接続することができる。 Here, the part 42 a of the predetermined first conductor pattern 42 is electrically connected to the part 47 a of the predetermined fourth conductor pattern 47 through the conductive paste bump 54, the second conductor pattern 43, and the second conductor bump 49. To do. A portion 43 a of the predetermined second conductor pattern 43 is electrically connected to a portion 45 a of the predetermined third conductor pattern 45 through the conductive paste bump 54, the first conductor pattern 42, and the first conductor bump 48. Therefore, the predetermined third conductor pattern 45a and the predetermined fourth conductor pattern 47a are arranged via the first conductor bump 48, the first conductor pattern 42, the conductive paste bump 54, the second conductor pattern 43a, and the second conductor bump 49. Can be connected electrically.
 なお、上記フレキシブル配線基板20において、必要に応じて第1絶縁体層41、第2絶縁体層44および第3絶縁体層46にスルーホール50が設けられる。そして、スルーホール50内が導通体50aにより導電化し、所定の第3導体パターン45および所定の第4導体パターン47が直接に電気接続されてもよい。図5に示す例では、導通体50aは第3導体パターン45および第4導体パターン47と一体に形成されている。 In the flexible wiring board 20, through holes 50 are provided in the first insulator layer 41, the second insulator layer 44, and the third insulator layer 46 as necessary. Then, the inside of the through hole 50 may be made conductive by the conductive body 50a, and the predetermined third conductor pattern 45 and the predetermined fourth conductor pattern 47 may be directly electrically connected. In the example shown in FIG. 5, the conductive body 50 a is formed integrally with the third conductor pattern 45 and the fourth conductor pattern 47.
 次に、本発明の第2の実施形態にかかるフレキシブル配線基板の製造方法の一例について説明する。図6(a)に示すように、例えば25μm~200μm厚さの第1導体板(例えばCu板)51上に所要のパターンを有するメッキレジスト52を形成する。そして、例えば電解メッキにより第1導体板51の露出する領域に金属バリア53および第1導体パターン42を積層して形成する。ここで、金属バリア53は厚さが0.5μm~1μm程度の例えばNi層、Sn層からなり、第1導体パターン42は10μm~50μm程度の厚さの例えばCu層からなる。そして、メッキレジスト52をアルカリ水溶液により剥離ないし溶解し除去して、図6(b)に示すように、第1導体パターン42が金属バリア53を介して第1導体板51主面の所定の領域に形成される。 Next, an example of a method for manufacturing a flexible wiring board according to the second embodiment of the present invention will be described. As shown in FIG. 6A, a plating resist 52 having a required pattern is formed on a first conductor plate (eg, Cu plate) 51 having a thickness of 25 μm to 200 μm, for example. Then, for example, the metal barrier 53 and the first conductor pattern 42 are laminated and formed in an area where the first conductor plate 51 is exposed by electrolytic plating. Here, the metal barrier 53 is made of, for example, a Ni layer or a Sn layer having a thickness of about 0.5 μm to 1 μm, and the first conductor pattern 42 is made of, for example, a Cu layer having a thickness of about 10 μm to 50 μm. Then, the plating resist 52 is stripped or dissolved and removed by an alkaline aqueous solution, and the first conductor pattern 42 is a predetermined region on the main surface of the first conductor plate 51 through the metal barrier 53 as shown in FIG. Formed.
 次に、図6(c)に示すように、所定の第1導体パターン42上に第1の実施形態で説明したのと同様に円錐導電性ペースト54のバンプ付けをする。 Next, as shown in FIG. 6C, the conical conductive paste 54 is bumped onto the predetermined first conductor pattern 42 in the same manner as described in the first embodiment.
 また、図6(a)、(b)で説明したのと同様にして、第2導体板55の主面の所定の領域に金属バリア53を介して第2導体パターン43を形成する。そして、図6(d)に示すように、第2導体板55を裏返しにし、例えば厚さが15μm~50μm程度の例えば液晶ポリマーからなる第1樹脂フィルム56と共にセットアップして位置決めする。 Further, in the same manner as described with reference to FIGS. 6A and 6B, the second conductor pattern 43 is formed in a predetermined region of the main surface of the second conductor plate 55 via the metal barrier 53. Then, as shown in FIG. 6D, the second conductor plate 55 is turned over, and set up and positioned together with a first resin film 56 made of, for example, a liquid crystal polymer having a thickness of about 15 μm to 50 μm.
 つぎに、上記第1導体板51、第1樹脂フィルム56および第2導体板55を第1の実施形態で説明したのと同様に熱プレスで熱圧着して接合一体化する。これにより、図6(e)に示すように、円錐導電性ペースト54は、その頭部が圧潰する塑性変形と共にその組成変化が生じて導電性ペーストバンプになる。また、第1樹脂フィルム56は、その両面にそれぞれ第1導体パターン42および第2導体パターン43が金属バリア53と共に接合し、導電性ペーストバンプ54が貫挿した第1絶縁体層41となる。ここで、所定の第1導体パターン42と所定の第2導体パターン43は導電性ペーストバンプ54を通して電気接続する。 Next, the first conductor plate 51, the first resin film 56, and the second conductor plate 55 are joined together by thermocompression using a hot press in the same manner as described in the first embodiment. As a result, as shown in FIG. 6E, the conical conductive paste 54 changes its composition along with the plastic deformation that crushes its head, and becomes a conductive paste bump. Further, the first resin film 56 becomes the first insulator layer 41 in which the first conductor pattern 42 and the second conductor pattern 43 are bonded to the both surfaces together with the metal barrier 53 and the conductive paste bumps 54 are inserted therethrough. Here, the predetermined first conductor pattern 42 and the predetermined second conductor pattern 43 are electrically connected through the conductive paste bumps 54.
 ここで、第1絶縁体層41、第1導体パターン42および第2導体パターン43が薄層化しても、第1導体板51により所要の硬度を付与できることから、フレキシブル配線基板の基材のハンドリング性を高くすることができる。このため、第1の実施形態で説明したように、特に図6(c)、(d)、(e)で示した円錐導電性ペースト54の形成あるいは熱プレスによる積層・一体化の工程において、その生産性は向上する。 Here, even if the first insulator layer 41, the first conductor pattern 42, and the second conductor pattern 43 are thinned, the required hardness can be imparted by the first conductor plate 51, so that the base material of the flexible wiring board can be handled. Sexuality can be increased. For this reason, as described in the first embodiment, in particular, in the step of forming the conical conductive paste 54 shown in FIGS. 6C, 6D, and 6E or laminating and integrating by hot pressing, Its productivity is improved.
 次に、第1の実施形態で説明したのと同様にフォトリソグラフィとウェットエッチングにより第1導体板51と第2導体板55を選択エッチングする。そして、図7(a)に示すように、第1絶縁体層41の下面および上面にそれぞれに突出する第1導体バンプ48および第2導体バンプ49を形成する。これ等の導体バンプは、その断面が順テーパー形状の台形になり、それぞれ所定の第1導体パターン42および第2導体パターン43に金属バリア53を介して電気接続する。上記エッチングでは、第1導体バンプ48あるいは第2導体バンプ49が形成されない領域の第1導体パターン42あるいは第2導体パターン43は金属バリア53がエッチングストッパーとなり保護される。 Next, as described in the first embodiment, the first conductor plate 51 and the second conductor plate 55 are selectively etched by photolithography and wet etching. Then, as shown in FIG. 7A, a first conductor bump 48 and a second conductor bump 49 projecting from the lower surface and the upper surface of the first insulator layer 41 are formed. These conductor bumps have trapezoidal cross sections, and are electrically connected to predetermined first conductor patterns 42 and second conductor patterns 43 through metal barriers 53, respectively. In the etching, the first conductor pattern 42 or the second conductor pattern 43 in the region where the first conductor bump 48 or the second conductor bump 49 is not formed is protected by the metal barrier 53 as an etching stopper.
 次に、図7(b)に示すように、公知の真空ラミネート法により、未硬化状態にある熱硬化性の第2樹脂フィルム57および第2樹脂フィルム58を図7(a)に示した状態の第1絶縁体層41にそれぞれ積層・一体化する。この積層・一体化では、フィルムを両面からプレスするためにそれぞれシート状支持部材(図示せず)を用いるとよい。このラミネートにおける温度は、未硬化状態にある第2樹脂フィルム57および第3樹脂フィルム58が硬化する所定の温度であり、第1絶縁体層41のガラス転移点あるいは融点より低い温度である。第2樹脂フィルム57および第3樹脂フィルム58は例えば味の素ファインテクノ社製のABFGX-13(商品名)のような熱硬化性樹脂である。そして、これ等のフィルムの厚さは15μm~100μm程度である。 Next, as shown in FIG. 7B, the thermosetting second resin film 57 and the second resin film 58 in an uncured state are shown in FIG. 7A by a known vacuum laminating method. The first insulator layer 41 is laminated and integrated with each other. In this lamination / integration, a sheet-like support member (not shown) may be used to press the film from both sides. The temperature in this laminate is a predetermined temperature at which the second resin film 57 and the third resin film 58 in an uncured state are cured, and is a temperature lower than the glass transition point or the melting point of the first insulator layer 41. The second resin film 57 and the third resin film 58 are thermosetting resins such as ABFGX-13 (trade name) manufactured by Ajinomoto Fine Techno Co., Ltd. The thickness of these films is about 15 μm to 100 μm.
 そして、図7(c)に示すように、第2樹脂フィルム57は、その上面に第1絶縁体層41、金属バリア53をもつ第1導体パターン42が接合し、第1導体バンプ48が貫挿した第2絶縁体層44になる。また、第3樹脂フィルム58は、その下面に第1絶縁体層41、金属バリア53をもつ第2導体パターン43が接合し、第2導体バンプ49が貫挿した第3絶縁体層46になる。 As shown in FIG. 7C, the second resin film 57 has the first conductor pattern 42 having the first insulator layer 41 and the metal barrier 53 bonded to the upper surface thereof, and the first conductor bumps 48 penetrated. The inserted second insulator layer 44 is obtained. Further, the third resin film 58 is joined to the first conductor layer 41 and the second conductor pattern 43 having the metal barrier 53 on the lower surface thereof to become the third insulator layer 46 through which the second conductor bumps 49 are inserted. .
 次に、図7(c)に示す状態において、第2絶縁体層44、第3絶縁体層46等の表面を清浄化する。ここで、第1導体バンプ48および第2導体バンプ49の表面の機械研磨、脱脂、酸洗等を行う。そして、必要に応じて、所定の領域において第1絶縁体層41、第2絶縁体層44および第3絶縁体層46を貫通するスルーホール50を例えばレーザ加工により形成する。その後にデスミア処理を施して、第1導体バンプ48および第2導体バンプ49の露出面およびスルーホール50の内壁を清浄にする。 Next, in the state shown in FIG. 7C, the surfaces of the second insulator layer 44, the third insulator layer 46, etc. are cleaned. Here, mechanical polishing, degreasing, pickling, etc. are performed on the surfaces of the first conductor bump 48 and the second conductor bump 49. Then, if necessary, a through hole 50 penetrating the first insulator layer 41, the second insulator layer 44, and the third insulator layer 46 in a predetermined region is formed by laser processing, for example. Thereafter, a desmear process is performed to clean the exposed surfaces of the first conductor bump 48 and the second conductor bump 49 and the inner wall of the through hole 50.
 次に、図7(d)に示すように、例えば無電解メッキ等により、第2絶縁体層44、第3絶縁体層46の表面、およびスルーホール50の内壁に被着する金属外層59を形成する。ここで、金属外層59の膜厚は10μ~50μm程度に設定される。そして、フォトリソグラフィを用いた金属外層59の選択エッチングにより、図5で説明した外層となる第3導体パターン45、第4導体パターン47と、スルーホール50の内壁の導通体50aを形成する。その後は、第1の実施形態で説明したのと同様に、例えばAu等の無電解メッキにより、これ等の外層表面にメッキ層(図示せず)を形成する。このようにして、図5で示したようなフレキシブル配線基板20が作製される。 Next, as shown in FIG. 7D, a metal outer layer 59 that adheres to the surface of the second insulator layer 44, the third insulator layer 46, and the inner wall of the through hole 50, for example, by electroless plating or the like. Form. Here, the thickness of the metal outer layer 59 is set to about 10 μm to 50 μm. Then, by the selective etching of the metal outer layer 59 using photolithography, the third conductor pattern 45 and the fourth conductor pattern 47, which are the outer layers described in FIG. Thereafter, as described in the first embodiment, a plating layer (not shown) is formed on the surface of these outer layers by electroless plating such as Au. In this way, the flexible wiring board 20 as shown in FIG. 5 is manufactured.
 なお、第1導体板51上への第1導体パターン42の形成あるいは第2導体板55上への第2導体パターン43の形成では、第1の実施形態で説明したように3層構造のクラッド材を用いることができる。この場合もクラッド材の金属箔に対してフォトリソグラフィを用いた選択エッチングを行う。 In the formation of the first conductor pattern 42 on the first conductor plate 51 or the formation of the second conductor pattern 43 on the second conductor plate 55, the clad having a three-layer structure as described in the first embodiment. Materials can be used. Also in this case, selective etching using photolithography is performed on the metal foil of the clad material.
 また、第1導体パターン42と第1導体板51は互いに異なる金属材料であってもよい。同様に、第2導体パターン43と第2導体板55も互いに異なる金属材料であってよい。これ等の場合には、第1導体板51あるいは第2導体板55のウェットエッチングにおいてエッチングストッパーとしての金属バリア53は不要にすることができる。 Further, the first conductor pattern 42 and the first conductor plate 51 may be made of different metal materials. Similarly, the second conductor pattern 43 and the second conductor plate 55 may be made of different metal materials. In these cases, the metal barrier 53 as an etching stopper can be eliminated in the wet etching of the first conductor plate 51 or the second conductor plate 55.
 図7(a)の状態にある基板において、第1導体バンプ48あるいは第2導体バンプ49上から樹脂フィルムと金属箔(銅箔)をこの順に積層し、熱プレスして積層・一体化する。ここで導体バンプの表面の酸化物などの付着を取り除くために、導体バンプ48,49の上辺(バンプトップ)の位置に当たる積層された金属箔をエッチングにて除去後、前述のバンプトップ表面の清浄化を実施する。その後のパネル銅めっきによりバンプトップとの接続を実現する。これ等の金属箔および銅めっき皮膜をパターニングして第3導体パターン45および第4導体パターン47を形成することができる。このバンプトップの金属箔の除去後の清浄化と銅めっきはスルーホール穴あけ後の機械研磨、デスミアー工程と兼用されても良い。 7A, a resin film and a metal foil (copper foil) are laminated in this order from the first conductor bump 48 or the second conductor bump 49 on the substrate in the state of FIG. Here, in order to remove adhesion of oxides and the like on the surface of the conductor bump, the laminated metal foil corresponding to the position of the upper side (bump top) of the conductor bumps 48 and 49 is removed by etching, and then the above-described bump top surface is cleaned. To implement. Subsequent panel copper plating realizes connection with the bump top. The third conductor pattern 45 and the fourth conductor pattern 47 can be formed by patterning the metal foil and the copper plating film. The cleaning and copper plating after the removal of the metal foil on the bump top may be combined with the mechanical polishing and the desmear process after the through-hole drilling.
 第2の実施形態のフレキシブル配線基板は、第1の実施形態で説明したのと同様に、そのビルドアップによる多層化が種々に可能である。例えば、図5に説明したフレキシブル配線基板20の下面あるいは上面から図6(c)の状態の基材を例えば未硬化の熱硬化性樹脂を挟んで熱プレスにより積層・一体化する。そして、第1導体板51を導体バンプに加工する。その後、例えば図7(b)、(c)、(d)の工程を経て、多層のフレキシブル配線基板が形成される。 The flexible wiring board of the second embodiment can be variously multilayered by build-up, as described in the first embodiment. For example, the base material in the state of FIG. 6C is laminated and integrated by hot pressing, for example, with an uncured thermosetting resin sandwiched from the lower surface or the upper surface of the flexible wiring board 20 described in FIG. Then, the first conductor plate 51 is processed into a conductor bump. Thereafter, for example, through the steps of FIGS. 7B, 7C, and 7D, a multilayer flexible wiring board is formed.
 第2の実施形態では、第1の実施形態で説明したのと同様に、フレキシブル配線基板の製造工程において、導体板によって積層体に対して所要の強度を付与することができ、フレキシブル配線基板の生産性等が向上し、その低コスト化が可能になる。 In the second embodiment, as described in the first embodiment, in the manufacturing process of the flexible wiring board, a required strength can be imparted to the laminated body by the conductor plate. Productivity etc. improve and the cost reduction is attained.
 また、導体パターンからなる複数の配線層間は、導電性ペーストバンプと導体バンプとにより交互に電気接続されるために、配線層の高い信頼性のもとに高密度配線のフレキシブル配線基板を製造することができる。これは、導電性ペーストバンプが絶縁体層のような基材の製造工程における熱膨張あるいは熱収縮から生じる熱応力の緩衝材として作用し、導体バンプが素材の熱変形を防止するように働くからである。 In addition, since a plurality of wiring layers made of conductive patterns are alternately electrically connected by conductive paste bumps and conductive bumps, a high-density wiring flexible wiring board is manufactured with high reliability of the wiring layers. be able to. This is because the conductive paste bump acts as a buffer for thermal stress caused by thermal expansion or contraction in the manufacturing process of a base material such as an insulator layer, and the conductor bump works to prevent thermal deformation of the material. It is.
 また、層間絶縁体層および配線層の薄層化と共に配線層の高密度化が容易になる。そして、例えばコンピューターのCPUクロックのようにGHz帯に達する高周波数化に対応した配線回路を有するフレキシブル配線基板が容易に提供できるようになる。 Also, it is easy to increase the density of the wiring layer as the interlayer insulating layer and the wiring layer are made thinner. Then, for example, a flexible wiring board having a wiring circuit corresponding to a high frequency reaching the GHz band like a CPU clock of a computer can be easily provided.
 第1の実施形態で説明した半導体パッケージ基板あるいはプローブ用基板に適用されるフレキシブル配線基板としては、第2の実施形態において図7(a)の構造のものを使用することができる。そして、最終の構造においては、第1絶縁体層41の下面と上面に突設する第1導体バンプ48および第2導体バンプ49を露出させ、第1導体パターン42および第2導体パターン43を覆うようにソルダーレジストが被着する。 As the flexible wiring substrate applied to the semiconductor package substrate or the probe substrate described in the first embodiment, the one having the structure of FIG. 7A can be used in the second embodiment. In the final structure, the first conductor bump 48 and the second conductor bump 49 protruding from the lower surface and the upper surface of the first insulator layer 41 are exposed to cover the first conductor pattern 42 and the second conductor pattern 43. The solder resist is deposited.
 また、導電性ペーストバンプとしては、フレキシブル配線基板の基材に形成されるビアホールあるいはスルーホールを例えばCuペーストのような導電性ペーストで充填したものであっても構わない。 Also, the conductive paste bump may be one in which a via hole or a through hole formed in the base material of the flexible wiring board is filled with a conductive paste such as Cu paste.
 なお、便宜上、明細書においては「上面」および「下面」という文言を用いて説明した。「上面」と「下面」とは、互いに表裏の関係にあることを意味し、空間的な上下を意味するものではない。 For convenience, the description uses the terms “upper surface” and “lower surface”. The “upper surface” and the “lower surface” mean that they are in a relationship of front and back, and do not mean spatial top and bottom.
 以上、本発明の好適な実施形態について説明したが、上述した実施形態は本発明を限定するものでない。当業者にあっては、具体的な実施態様において本発明の技術思想および技術範囲から逸脱せずに種々の変形・変更を加えることが可能である。 The preferred embodiments of the present invention have been described above, but the above-described embodiments do not limit the present invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and technical scope of the present invention.
 10,10a,20…フレキシブル配線基板、11…層間絶縁体層、11a…主面、12,42…第1導体パターン、13,43…第2導体パターン、14,54…導電性ペーストバンプ、15…導体バンプ、16,53…金属バリア、17,33…ソルダーレジスト、18…メッキ層、21…導体板、22…金属バリア層、23…第1金属箔,24,25,28,29…エッチングレジスト、26,54…円錐導電性ペースト、27…第2金属箔、31…ダイランド(導体パターン)、32…接続ランド(導体パターン)、41…第1絶縁体層(層間絶縁体層)、41a…下面(主面)、41b…上面(主面)、44…第2絶縁体層(層間絶縁体層)、45…第3導体パターン、46…第3絶縁体層、47…第4導体パターン、48…第1導体バンプ、49…第2導体バンプ、50…スルーホール、50a…導通体、51…第1導体板、52…メッキレジスト、55…第2導体板、56…第1樹脂フィルム、57…第2樹脂フィルム、58…第3樹脂フィルム、59…金属外層 DESCRIPTION OF SYMBOLS 10, 10a, 20 ... Flexible wiring board, 11 ... Interlayer insulator layer, 11a ... Main surface, 12, 42 ... First conductor pattern, 13, 43 ... Second conductor pattern, 14, 54 ... Conductive paste bump, 15 ... Conductor bump, 16, 53 ... Metal barrier, 17, 33 ... Solder resist, 18 ... Plating layer, 21 ... Conductor plate, 22 ... Metal barrier layer, 23 ... First metal foil, 24, 25, 28, 29 ... Etching Resist, 26, 54 ... conical conductive paste, 27 ... second metal foil, 31 ... die land (conductor pattern), 32 ... connection land (conductor pattern), 41 ... first insulator layer (interlayer insulator layer), 41a ... lower surface (main surface), 41b ... upper surface (main surface), 44 ... second insulator layer (interlayer insulator layer), 45 ... third conductor pattern, 46 ... third insulator layer, 47 ... fourth conductor pattern 48th Conductor bump, 49 ... second conductor bump, 50 ... through hole, 50a ... conductor, 51 ... first conductor plate, 52 ... plating resist, 55 ... second conductor plate, 56 ... first resin film, 57 ... second Resin film, 58 ... third resin film, 59 ... metal outer layer

Claims (10)

  1.  複数層の導体パターンを多層に積層したフレキシブル配線基板において、導体板上に層間絶縁体層を挟んで2層以上の導体パターンが一体に積層され、前記導体パターンの層間が前記層間絶縁層を貫通する導電性ペーストバンプにより電気的に接続され、前記導体パターンに接触する前記導体板のエッチング加工により前記導体パターンに電気的に接続される導体バンプが形成され、前記導体バンプが前記導体パターンを配置した前記層間絶縁体層の主面から突き出していることを特徴とするフレキシブル配線基板。 In a flexible wiring board in which a plurality of layers of conductor patterns are laminated, two or more layers of conductor patterns are laminated on a conductor plate with an interlayer insulator layer in between, and the layers of the conductor patterns penetrate the interlayer insulation layer Conductive bumps that are electrically connected by conductive paste bumps that are electrically connected to the conductive patterns are formed by etching the conductive plate in contact with the conductive patterns, and the conductive bumps arrange the conductive patterns. A flexible wiring board protruding from the main surface of the interlayer insulator layer.
  2.  前記導体板が前記導体パターン層よりも層厚であることを特徴とする請求項1記載のフレキシブル配線基板。 The flexible wiring board according to claim 1, wherein the conductor plate has a layer thickness greater than that of the conductor pattern layer.
  3.  半導体パッケージの基板であって、前記導体バンプが前記半導体パッケージ基板の外部接続用バンプとなることを特徴とする請求項1に記載のフレキシブル配線基板。 The flexible wiring board according to claim 1, wherein the conductive bump is a bump for external connection of the semiconductor package substrate.
  4.  電子デバイスの通電検査に用いるプローブ用基板であって、前記導体バンプが被検体の外部接続用端子に接触するプローブバンプになることを特徴とする請求項1に記載のフレキシブル配線基板。 2. The flexible printed circuit board according to claim 1, wherein the flexible printed circuit board is a probe board used for an energization inspection of an electronic device, wherein the conductor bump is a probe bump that contacts an external connection terminal of a subject.
  5.  複数層の導体パターンを多層に積層したフレキシブル配線基板において、導体板上に層間絶縁体層を挟んで2層以上の導体パターンが一体に積層され、前記導体パターンの層間が前記層間絶縁層を貫通する導電性ペーストバンプと導体板のエッチング加工により形成された導体バンプとにより電気的に接続されていることを特徴とするフレキシブル配線基板。 In a flexible wiring board in which a plurality of layers of conductor patterns are laminated, two or more layers of conductor patterns are laminated on a conductor plate with an interlayer insulator layer in between, and the layers of the conductor patterns penetrate the interlayer insulation layer A flexible wiring board characterized in that the conductive paste bump is electrically connected to a conductive bump formed by etching a conductive plate.
  6.  前記導体パターンの層間は、前記導電性ペーストバンプと導体板のエッチング加工により形成された前記導体バンプとにより交互に電気的に接続されていることを特徴とする請求項5に記載のフレキシブル配線基板。 6. The flexible wiring board according to claim 5, wherein the layers of the conductive patterns are alternately electrically connected by the conductive paste bumps and the conductive bumps formed by etching a conductive plate. .
  7.  導体板の表面に第1導体パターンの層を電気的に接触させて形成する工程と、
     前記第1導体パターンの所定の領域に導電性ペーストバンプを形成する工程と、
     前記導電性ペーストバンプ上から、層間絶縁層となる樹脂フィルムと第2導体パターンとなる金属箔をこの順に積層し加熱加圧して前記導電性ペーストバンプと前記金属箔を電気的に接続する工程と、
     前記金属箔をパターニングして第2導体パターンを形成する工程と、
     前記導体板をエッチング加工して前記第1導電パターンに電気的に接続する導体バンプにする工程と、
     を有することを特徴とするフレキシブル配線基板の製造方法。
    Forming a first conductive pattern layer in electrical contact with the surface of the conductive plate;
    Forming a conductive paste bump in a predetermined region of the first conductor pattern;
    A step of laminating a resin film to be an interlayer insulating layer and a metal foil to be a second conductor pattern in this order from above the conductive paste bump and electrically connecting the conductive paste bump and the metal foil by heating and pressing; ,
    Patterning the metal foil to form a second conductor pattern;
    Etching the conductive plate to form a conductive bump electrically connected to the first conductive pattern;
    The manufacturing method of the flexible wiring board characterized by having.
  8.  第1導体板の表面に第1導体パターンを電気的に接触させて形成する工程と、
     前記第1導体パターンの所定の領域に導電性ペーストバンプを形成する工程と、
     第2導体板の表面に第2導体パターンを形成する工程と、
     前記導電性ペーストバンプ上から樹脂フィルムと前記第2導体板をこの順に積層し加熱加圧して、前記導電性ペーストバンプと前記第2導体パターンを接続する工程と、
     前記第1導体板および前記第2導体板をそれぞれにエッチング加工して第1導体バンプおよび第2導体バンプにする工程と、
     を有することを特徴とするフレキシブル配線基板の製造方法。
    Forming the first conductor pattern in electrical contact with the surface of the first conductor plate;
    Forming a conductive paste bump in a predetermined region of the first conductor pattern;
    Forming a second conductor pattern on the surface of the second conductor plate;
    Laminating the resin film and the second conductor plate in this order on the conductive paste bump and heating and pressing to connect the conductive paste bump and the second conductor pattern;
    Etching the first conductor plate and the second conductor plate into a first conductor bump and a second conductor bump, respectively;
    The manufacturing method of the flexible wiring board characterized by having.
  9.  前記導体板と前記第1導体パターン層が同種の金属でなり、前記導体板と前記第1導体パターン層の間にエッチング特性の異なる異種金属の金属バリア層が形成されてなることを特徴とする請求項7記載のフレキシブル配線基板の製造方法。 The conductor plate and the first conductor pattern layer are made of the same kind of metal, and a metal barrier layer of different metals having different etching characteristics is formed between the conductor plate and the first conductor pattern layer. The manufacturing method of the flexible wiring board of Claim 7.
  10.  前記第1導体板と前記第1導体パターン層が同種の金属でなり、前記第1導体板と前記第1導体パターン層の間にエッチング特性の異なる異種金属の金属バリア層が形成されて、
     前記第2導体板と前記第2導体パターン層が同種の金属でなり、前記第2導体板と前記第2導体パターン層の間にエッチング特性の異なる異種金属の金属バリア層が形成されて、なることを特徴とする請求項8記載のフレキシブル配線基板の製造方法。
     
    The first conductor plate and the first conductor pattern layer are made of the same kind of metal, and a metal barrier layer of a different metal having different etching characteristics is formed between the first conductor plate and the first conductor pattern layer,
    The second conductor plate and the second conductor pattern layer are made of the same kind of metal, and a metal barrier layer made of a different kind of metal having different etching characteristics is formed between the second conductor plate and the second conductor pattern layer. The method for producing a flexible wiring board according to claim 8.
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