JPH10335528A - Semiconductor package and manufacture thereof - Google Patents

Semiconductor package and manufacture thereof

Info

Publication number
JPH10335528A
JPH10335528A JP14387397A JP14387397A JPH10335528A JP H10335528 A JPH10335528 A JP H10335528A JP 14387397 A JP14387397 A JP 14387397A JP 14387397 A JP14387397 A JP 14387397A JP H10335528 A JPH10335528 A JP H10335528A
Authority
JP
Japan
Prior art keywords
external connection
semiconductor package
conductive
connection terminal
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14387397A
Other languages
Japanese (ja)
Other versions
JP3378171B2 (en
Inventor
Nobushi Suzuki
悦四 鈴木
Hiroshi Ohira
洋 大平
Eiji Imamura
英治 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaichi Electronics Co Ltd
Original Assignee
Yamaichi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaichi Electronics Co Ltd filed Critical Yamaichi Electronics Co Ltd
Priority to JP14387397A priority Critical patent/JP3378171B2/en
Publication of JPH10335528A publication Critical patent/JPH10335528A/en
Application granted granted Critical
Publication of JP3378171B2 publication Critical patent/JP3378171B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package having a highly reliable through hole type connection part, and to provide the manufacturing method of the above-mentioned semiconductor package. SOLUTION: This semiconductor package has a substrate 6 wherein the liquid crystal polymer, on which external connection terminals are arranged on one main surface, is used as an insulator, a conductive bump group 6b, one end of which is electrically connected to each external connection terminal 6a which is inserted to the thickness direction of a substrate 6, and a semiconductor chip 7 on which the other end of each conductive bump 6b is connected to the surface of an electrode 7a, Also, a conductive bump 6b is provided on the surface of the electrode 7a of a semiconductor chip 7, and a conductive metal layer 6a is superposingly arranged on the surface of the semiconductor chip 7 through a liquid crystal sheet 6 in this manufacturing method. Then, the tip side of the conductive bump 6b, which penetrates the liquid crystal polymer sheet 6, is connected to the surface of the conductive metal layer 6a, the conductive metal layer 6a is patterned, and an external connection terminal part 6a is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に係り、さらに詳しくは基板面にベアチップ
をフェースダウンに搭載した半導体モジュールおよびそ
の製造方法に関する。
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor module having a bare chip mounted face down on a substrate surface and a method of manufacturing the same.

【0002】[0002]

【従来の技術】電子機器類の小型化などに伴って、半導
体チップの外部接続電極数が数 100と増大し、半導体パ
ッケージの裏面にマトリックス状の半田ボール付き外部
接続端子を有する BGA (Ball Grid Arrey)パッケージや
CSP (Chip Sise Package)が急速に普及しつつある。こ
れらパッケージは、一般的に、ガラス・エポキシ樹脂や
各種樹脂フィルム(シート)の銅箔張り板を基材とし、
これにエッチング加工を施してパターニングした後、Au
メッキなどを施して成るインターポーザ基板面に、ICチ
ップなどを搭載し、前記基板電極とICチップの電極との
間を電気的に接続した半導体パッケージである。
2. Description of the Related Art With the miniaturization of electronic devices, the number of external connection electrodes of a semiconductor chip has increased to several hundreds, and a BGA (Ball Grid) having external connection terminals with solder balls in a matrix on the back surface of a semiconductor package. Arrey) packages and
CSP (Chip Sise Package) is rapidly spreading. These packages are generally based on copper-clad boards made of glass epoxy resin or various resin films (sheets).
After etching and patterning this, Au
A semiconductor package in which an IC chip or the like is mounted on an interposer substrate surface subjected to plating or the like, and the substrate electrodes and the electrodes of the IC chip are electrically connected.

【0003】ところで、半導体チップの搭載・実装技術
としては、一般的に、ワイヤボンディング方式、TAB(Ta
pe Automated Bonding) 方式、フリッブチップ方式、CO
G(Chip on Glass)方式が広く利用されている。中でも、
フリッブチップ方式や COG方式、いわゆるフェースダウ
ン実装方式は、一層の高密度実装や低コスト化が可能な
ことから関心が寄せられている。
[0003] By the way, as a semiconductor chip mounting / mounting technique, generally, a wire bonding method, a TAB (TaB) method is used.
pe Automated Bonding) method, flip chip method, CO
The G (Chip on Glass) method is widely used. Among them,
Flip-chip and COG methods, or so-called face-down mounting methods, have attracted attention because they can achieve higher density mounting and lower costs.

【0004】そして、このフェースダウン実装方式にお
ける半導体チップの接続は、 (a)半田バンプを使用する
フリップチップ、 (b)導電性粒子を含む樹脂フィルム
(異方導電性フィルム)を使用するボンディングなどで
行われている(たとえば特開平4-323841号公報)。
[0004] The connection of the semiconductor chip in this face-down mounting method includes (a) a flip chip using solder bumps, and (b) a bonding using a resin film containing conductive particles (anisotropic conductive film). (For example, JP-A-4-323841).

【0005】図4は、上記フェースダウン実装方式によ
る CSP半導体パッケージの一構成例を示す断面図であ
る。図4において、1は主面に接続端子1aを含む配線パ
ターンを有する基板、2は前記基板1に実装された半導
体チップであり、この半導体チップ2のAl製電極2aは、
Auボールバンプもしくは導体バンプ3を介して、対応す
る接続端子1aに電気的に接合している。また、4は前記
電気的な接合を確保するため、基板1を厚さ方向に貫挿
導出させた外部接続端子であり、5はAuポールバンプも
しくは導体バンプ3を含む接続部を封止・接合する封止
樹脂層である。
FIG. 4 is a sectional view showing an example of a configuration of the CSP semiconductor package using the face-down mounting method. In FIG. 4, 1 is a substrate having a wiring pattern including a connection terminal 1a on a main surface, 2 is a semiconductor chip mounted on the substrate 1, and an Al electrode 2a of the semiconductor chip 2
It is electrically connected to the corresponding connection terminal 1a via the Au ball bump or the conductor bump 3. Reference numeral 4 denotes an external connection terminal through which the substrate 1 is inserted and led out in the thickness direction in order to secure the electrical connection. Reference numeral 5 denotes a connection portion including the Au pole bump or the conductor bump 3 for sealing and bonding. Is a sealing resin layer to be formed.

【0006】そして、このような半導体パッケージは、
インターポーザ基板とICチップとを別々に作成し、ICチ
ップをインターポーザ基板に搭載実装し、さらに、イン
ターポーザ基板を適正なサイズに切断して得られてい
る。
[0006] Such a semiconductor package is
It is obtained by separately producing an interposer substrate and an IC chip, mounting and mounting the IC chip on the interposer substrate, and cutting the interposer substrate to an appropriate size.

【0007】[0007]

【発明が解決しようとする課題】上記実装方式は、ワイ
ヤボンディングの回避や外部接続端子の裏面側への導出
配置により、実装密度の向上ないし半導体モジュールの
コンパクト化などの点ですくれているが、さらなる高密
度化、信頼性などの点で、なお改善が望まれる。すなわ
ち、基板1の厚さ方向に、外部接続端子4群を貫挿導出
させる構成は、一般的に、基板の所定位置に貫通孔を穿
設し、この孔内もしくは孔内壁面を導電性化(スルホー
ル接続部)する必要がある。
[Problems to be Solved by the Invention] The above-mentioned mounting method is intended to improve the mounting density or make the semiconductor module more compact by avoiding wire bonding and arranging the external connection terminals on the back side. Further improvements are desired in terms of higher density, reliability, and the like. That is, a configuration in which the external connection terminals 4 are inserted and led out in the thickness direction of the substrate 1 is generally such that a through hole is formed at a predetermined position of the substrate, and the inside of the hole or the inner wall surface of the hole is made conductive. (Through hole connection).

【0008】しかし、貫通孔の径が穿設加工の点で限界
があるし、また、導電性化にも限界があるため、外部接
続端子4の多数化ないし高密度配置が制約される。つま
り、半導体モジュールの多端子化や高機能化、あるいは
コンパクト化などに、十分対応することができない。
However, the diameter of the through-hole is limited in terms of drilling and the conductivity is also limited, so that the number of the external connection terminals 4 or the high density arrangement is restricted. That is, it is not possible to sufficiently cope with the increase in the number of terminals, the enhancement of functions, and the reduction in size of the semiconductor module.

【0009】こうした状況に対して、微小な導電性バン
プを植設した銅箔面に、たとえばガラス・エポキシ樹脂
系プリプレグシート(絶縁体層)を配置・積層し、この
積層体の加圧によって、導電性バンプの先端側を絶縁体
層を貫挿させ、スルホール型接続部を形成する手段が開
発されている。この方式の場合は、穿設加工を省略でき
るし、また、スルホール接続部の配置の高密度化などを
図れる可能性がある。つまり、この手段は、多層配線板
の製造工程などを大幅に改善できるが、さらなる半導体
モジュールの多端子化や高機能化、あるいはコンパクト
化などに、十分対応し得ない。
To cope with such a situation, for example, a glass-epoxy resin prepreg sheet (insulator layer) is arranged and laminated on a copper foil surface on which minute conductive bumps are implanted, and the laminated body is pressed by pressure. Means for forming the through-hole type connection portion by penetrating the insulating layer through the tip side of the conductive bump has been developed. In the case of this method, the boring process can be omitted, and there is a possibility that the arrangement of the through-hole connection portions can be increased. In other words, this means can greatly improve the manufacturing process of the multilayer wiring board, but cannot sufficiently cope with further increase in the number of terminals of the semiconductor module, higher functionality, or downsizing.

【0010】また、前記半導体パッケージの製造法で
は、各インタポーザ基板ごとに1個の半導体チップ実装
するため、コストアップとなる問題もある。
In the method of manufacturing a semiconductor package, since one semiconductor chip is mounted for each interposer substrate, there is a problem that the cost is increased.

【0011】本発明者らは、上記事情に対処して、鋭意
検討を進めた結果、液晶ポリマーなどを絶縁体とした場
合、微小な導電性バンプ先端側が絶縁体層によって損傷
されず、また、導電性バンプと当接する導体層との電気
的な接続、すなわち層間接続を熱圧着のみで行うことが
できると同時に、所定の位置を容易に貫挿し、高精度
に、かつ信頼性の高いスルホール型接続部が形成されて
いることを見出した。また、液晶ポリマーがほとんど吸
湿性を有しないこと、半導体チップ面および導体層に対
する密着性よいこと、熱膨脹係数をSiとほぼ同じにでき
ることなどに伴って、より信頼性の高い接続を形成でき
ることを見出した。
The inventors of the present invention have made intensive studies in consideration of the above circumstances, and as a result, when a liquid crystal polymer or the like is used as an insulator, the tip of the minute conductive bump is not damaged by the insulator layer. The electrical connection between the conductive bumps and the conductor layer in contact with the conductive layer, that is, the interlayer connection can be performed only by thermocompression bonding. At the same time, the through hole is easily inserted into a predetermined position, and the through hole type is highly accurate and highly reliable. It has been found that a connecting portion is formed. They also found that liquid crystal polymers have little hygroscopicity, good adhesion to semiconductor chip surfaces and conductor layers, and that the thermal expansion coefficient can be made almost the same as that of Si, making it possible to form more reliable connections. Was.

【0012】特に、Si並の熱膨脹係数を有する液晶ポリ
マーを絶縁体とした回路基板の場合は、半導体パッケー
ジに対する温度サイクルや使用環境においても、半導体
チップの電極と導電バンプとの接合面にストレスが発生
せずに、高い信頼性の接続が実現される。
In particular, in the case of a circuit board using a liquid crystal polymer having a thermal expansion coefficient equivalent to that of Si as an insulator, stress is applied to the bonding surface between the electrodes of the semiconductor chip and the conductive bumps even in a temperature cycle with respect to the semiconductor package and in a use environment. A reliable connection is realized without any occurrence.

【0013】本発明は、上記知見に基づいてなされたも
ので、信頼性の高いスルホール型接続部を有する半導体
パッケージ、およびその製造方法の提供を目的とする。
The present invention has been made based on the above findings, and has as its object to provide a semiconductor package having a highly reliable through-hole type connection portion and a method of manufacturing the same.

【0014】[0014]

【課題を解決するための手段】請求項1の発明は、一主
面に外部接続端子群が配設された回路基板と、前記基板
を厚さ方向に貫挿して各外部接続端子に一端が電気的に
接続する導電性バンプ群と、前記基板の他主面にフェー
スダウンに配設され、各導電性バンプの他端が電極面に
接続された半導体チップとを有することを特徴とする半
導体パッケージである。
According to a first aspect of the present invention, there is provided a circuit board having an external connection terminal group disposed on one main surface thereof, and one end connected to each external connection terminal by penetrating the substrate in a thickness direction. A semiconductor, comprising: a conductive bump group to be electrically connected; and a semiconductor chip disposed face-down on the other main surface of the substrate and having the other end of each conductive bump connected to an electrode surface. Package.

【0015】請求項2の発明は、請求項1記載の半導体
パッケージにおいて、一主面の外部接続端子群が、配線
によって分散的に配設されていることを特徴とする。
According to a second aspect of the present invention, in the semiconductor package of the first aspect, the external connection terminal group on one main surface is dispersedly arranged by wiring.

【0016】請求項3の発明は、請求項1もしくは請求
項2記載の半導体パッケージにおいて、一主面の各外部
接続端子面に、導電性バンプが設けられていることを特
徴とする。
According to a third aspect of the present invention, in the semiconductor package of the first or second aspect, a conductive bump is provided on each of the external connection terminal surfaces on one main surface.

【0017】請求項4の発明は、請求項1ないし請求項
3いずれか一記載の半導体パッケージにおいて、回路基
板が液晶ポリマーを絶縁体として形成されていることを
特徴とする。
According to a fourth aspect of the present invention, in the semiconductor package according to any one of the first to third aspects, the circuit board is formed using a liquid crystal polymer as an insulator.

【0018】請求項5の発明は、半導体チップの電極面
に導電性バンプを設ける工程と、前記導電性バンプを設
けた半導体チップ面に絶縁性シートを介して導電性金属
層を重ね合わせ配置する工程と、前記重ね合わせ体を加
圧して、絶縁性シートを貫挿する導電性バンプ先端側を
導電性金属層面に対接・接続する工程と、前記導電性金
属層をパターンニングし、外部接続端子部を形成する工
程とを有することを特徴とする半導体パッケージの製造
方法である。
According to a fifth aspect of the present invention, there is provided a step of providing a conductive bump on an electrode surface of a semiconductor chip, and arranging a conductive metal layer on the semiconductor chip surface on which the conductive bump is provided via an insulating sheet. Pressurizing the superimposed body, contacting and connecting the front end side of the conductive bump penetrating the insulating sheet to the surface of the conductive metal layer, and patterning the conductive metal layer for external connection Forming a terminal portion.

【0019】請求項6の発明は、半導体ウエハーの各半
導体素子電極面に導電性バンプを設ける工程と、前記導
電性バンプを設けた半導体チップ面に絶縁性シートを介
して導電性金属層を重ね合わせ配置する工程と、前記重
ね合わせ体を加圧して、絶縁性シートを貫挿する導電性
バンプ先端側を導電性金属層面に対接・接続する工程
と、前記導電性金属層をパターンニングし、外部接続端
子部を形成する工程と、前記外部部接続端子部を形成し
た積層体をカッティング加工する工程とを有することを
特徴とする半導体パッケージの製造方法である。
According to a sixth aspect of the present invention, there is provided a semiconductor wafer comprising: a step of providing conductive bumps on each semiconductor element electrode surface of a semiconductor wafer; and a step of laminating a conductive metal layer via an insulating sheet on the semiconductor chip surface provided with the conductive bumps. A step of aligning and arranging, and a step of pressing the overlapped body to contact and connect a tip end of a conductive bump penetrating an insulating sheet to a conductive metal layer surface, and patterning the conductive metal layer. A method of manufacturing a semiconductor package, comprising: a step of forming an external connection terminal portion; and a step of cutting the laminated body having the external portion connection terminal portion formed therein.

【0020】請求項7の発明は、請求項5もしくは請求
項6記載の半導体パッケージの製造方法において、外部
接続端子部面に、さらに導電性バンプを設けることを特
徴とする。
According to a seventh aspect of the present invention, in the method for manufacturing a semiconductor package according to the fifth or sixth aspect, a conductive bump is further provided on the surface of the external connection terminal portion.

【0021】請求項8の発明は、請求項5ないし請求項
7いずれか一記載の半導体パッケージの製造方法におい
て、絶縁性シートが液晶ポリマーシートであることを特
徴とする。
According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor package according to any one of the fifth to seventh aspects, the insulating sheet is a liquid crystal polymer sheet.

【0022】本発明において、回路基板の絶縁体は、各
種の熱可塑性樹脂や熱硬化性樹脂などでもよいが、たと
えば、次のような構造式、
In the present invention, the insulator of the circuit board may be made of various thermoplastic resins or thermosetting resins.

【化1】 で示される芳香族ポリエステル系液晶ポリマーが好まし
く、この種の芳香族ポリエステル系液晶ポリマーは、
“ベクトラ”もしくは LCP-A, LCP-Cなどの商品名で市
販されている。ここで、絶縁体の選択は、半導体パッケ
ージの使用環境が厳しくない場合、換言すると、それほ
どの高信頼性が要求されない場合は、たとえばビスマレ
イミドトリアジン樹脂、ポリフェニールエーテル樹脂な
ど液晶ポリマーに類似した樹脂類であってもよい。
Embedded image Aromatic polyester-based liquid crystal polymer represented by is preferred, this kind of aromatic polyester-based liquid crystal polymer,
It is marketed under the trade name "VECTRA" or LCP-A, LCP-C. Here, the choice of the insulator is made when the use environment of the semiconductor package is not severe, in other words, when not so high reliability is required, for example, a resin similar to a liquid crystal polymer such as a bismaleimide triazine resin and a polyphenyl ether resin. Kind.

【0023】また、回路基板の厚さは、一般的に、20〜
80μm 程度であり、また、幅や長さなどは、半導体装置
の用途や製造条件などに応じて選択する。さらに、回路
基板ないし絶縁体は、半導体パッケージ化工程などの熱
処理で、その熱膨脹係数が−7〜60ppm/℃( TMA法によ
る測定値)程度変化できるので、このような性状を考慮
する。
The thickness of the circuit board is generally 20 to
It is about 80 μm, and the width and length are selected according to the use of the semiconductor device and manufacturing conditions. Further, since the thermal expansion coefficient of a circuit board or an insulator can be changed by about -7 to 60 ppm / ° C. (measured by the TMA method) by a heat treatment such as a semiconductor packaging process, such properties are taken into consideration.

【0024】本発明において、液晶ポリマーシートなど
絶縁性シートを貫挿し、スルホール型接続部を形成する
導電性バンプは、たとえば導電性カーボン粉末、Au粒
子、Ni粒子、Ag粒子、Pb粒子、Sn粒子、Cu粒子、半田粒
子などの導電性粒子と、たとえばエポキシ樹脂、フェノ
ール樹脂、アクリル樹脂などとの混合・分散系(導電性
ペースト)の印刷・乾燥、あるいは導電性金属のメッキ
などによって形成される。 すなわち、ステンレス鋼製
のスクリーン版などを使用したスクリーン印刷と乾燥の
繰り返し、あるいは化学メッキなどによる選択的な導電
性金属の成長などで形成される。そして、この導電性バ
ンプの形設は、一般的には、半導体チップの電極面であ
るが、外部接続端子を形成する銅箔面側であってもよ
い。なお、半導体チップはICチップなどで、通常、一主
面にたとえばAl製の電極端子群(入出力端子)を有する
ものである。
In the present invention, conductive bumps formed by penetrating an insulating sheet such as a liquid crystal polymer sheet to form a through-hole type connection portion include, for example, conductive carbon powder, Au particles, Ni particles, Ag particles, Pb particles, Sn particles. It is formed by printing and drying a mixed / dispersed system (conductive paste) of conductive particles such as Cu, Cu and solder particles with epoxy resin, phenol resin, acrylic resin, etc., or by plating conductive metal. . That is, it is formed by repeating screen printing and drying using a stainless steel screen plate or the like, or by selectively growing a conductive metal by chemical plating or the like. The conductive bumps are generally formed on the electrode surface of the semiconductor chip, but may be formed on the copper foil surface on which external connection terminals are formed. The semiconductor chip is an IC chip or the like, and usually has an electrode terminal group (input / output terminal) made of, for example, Al on one main surface.

【0025】本発明において、要すれば、基板の外部接
続端子面面に配置する導電性バンプは、たとえばAu線な
どの局部的な溶融によるボールバンプ形成方式、Cuメッ
キ法やNiメッキ法などによって形成することができる。
In the present invention, if necessary, the conductive bumps disposed on the surface of the external connection terminal of the substrate may be formed by a method of forming a ball bump by local melting of Au wire or the like, a Cu plating method, a Ni plating method, or the like. Can be formed.

【0026】請求項1〜4の発明では、基板の外部接続
端子に対して、半導体チップの電極面が、この電極面に
一端が接合し、かつ絶縁体層を貫挿した導電性バンプで
電気的に接続している。この構成においては、絶縁体層
を形成する液晶ポリマーなどが、すぐれた耐湿性、小さ
い誘電率、良好なバンプ突き抜き性を有することに伴っ
て、微細な外部接続端子配置で、かつ電気的特性なども
良好など、半導体パッケージの信頼性向上が図られる。
According to the first to fourth aspects of the present invention, the electrode surface of the semiconductor chip is electrically connected to the external connection terminal of the substrate by a conductive bump having one end joined to the electrode surface and an insulator layer penetrating therethrough. Connected. In this configuration, the liquid crystal polymer forming the insulator layer has excellent moisture resistance, a small dielectric constant, and good bump-punching properties. As a result, the reliability of the semiconductor package is improved.

【0027】請求項5ないし8の発明では、すぐれた耐
湿性、小さい誘電率、良好なバンプ突き抜き性を有する
液晶ポリマーシートなどを絶縁体層とすることにより、
電気的特性および配置精度などの信頼性向上が図られた
半導体パッケージが、繁雑な操作を要せずに、かつ歩留
まりよく生産される。
According to the fifth to eighth aspects of the present invention, a liquid crystal polymer sheet having excellent moisture resistance, a small dielectric constant, and a good bump punching property is used as an insulating layer.
A semiconductor package in which reliability such as electrical characteristics and placement accuracy is improved can be produced with high yield without requiring complicated operations.

【0028】[0028]

【発明の実施の形態】図1,図2 (a)〜 (c)および図3
を参照して実施例を説明する。
1 and 2 (a) to (c) and FIG.
An example will be described with reference to FIG.

【0029】図1は、第1の実施例に係る半導体パッケ
ージ(半導体モジュール)の要部構成を示す断面図であ
る。図1において、6は一主面に外部接続端子6a群が配
設された液晶ポリマーを絶縁体とした基板、6bは前記基
板6を厚さ方向に貫挿して各外部接続端子6aに一端が電
気的に接続する導電性バンプ(スルホール接続部)であ
る。ここで、基板6は、たとえば厚さ約30μm ,13×13
mm角であり、各外部接続端子6aは、厚さ12μm の銅箔を
フォトエッチングし、一部を配線パターンで延設させて
0.5mm程度の間隔で、マトリックス状に外部接続端子6a
が設置されている。また、導電性バンプ6bは、たとえば
エポキシ樹脂をバインダー成分としたAgペーストで形成
されており、一般的には、ほぼ円柱状もしくは円錐形を
成している。
FIG. 1 is a sectional view showing the structure of a main part of a semiconductor package (semiconductor module) according to the first embodiment. In FIG. 1, reference numeral 6 denotes a substrate having a liquid crystal polymer as an insulator having a group of external connection terminals 6a disposed on one main surface, and 6b, one end of each of the external connection terminals 6a penetrating the substrate 6 in the thickness direction. These are conductive bumps (through-hole connection portions) that are electrically connected. Here, the substrate 6 is, for example, about 30 μm thick, 13 × 13
Each external connection terminal 6a is a 12 μm thick copper foil photo-etched and partially extended with a wiring pattern.
External connection terminals 6a in a matrix at intervals of about 0.5mm
Is installed. The conductive bump 6b is formed of, for example, an Ag paste using an epoxy resin as a binder component, and generally has a substantially columnar or conical shape.

【0030】さらに、7は前記基板6の他主面にフェー
スダウンに配設され、前記各導電性バンプ6bの他端が電
極7a面に接続された半導体チップである。ここで半導体
チップ7は、たとえば13×13mmのICチップで、入出力よ
うの電極7aはAlパットあるいは金属コートパットであ
る。
Reference numeral 7 denotes a semiconductor chip which is disposed face-down on the other main surface of the substrate 6 and the other end of each of the conductive bumps 6b is connected to the surface of the electrode 7a. Here, the semiconductor chip 7 is, for example, a 13 × 13 mm IC chip, and the input / output electrodes 7a are Al pads or metal coated pads.

【0031】なお、この構成においては、一般的に、外
部接続端子6a形成面に、外部接続端子6aを露出させてカ
バーコートが行われており、また、外部接続端子6a面
に、たとえば半田ボールバンプを設けておき、GA(Grid
Arrey)パッケージとして、実装用配線基板などに対して
搭載・実装し易くしておいてもよい。
In this configuration, the external connection terminal 6a is generally covered with a cover coat on the surface on which the external connection terminal 6a is formed by exposing the external connection terminal 6a. With bumps provided, GA (Grid
Arrey) The package may be easily mounted and mounted on a mounting wiring board or the like.

【0032】次に、上記構成の半導体パッケージの製造
方法例を説明する。
Next, an example of a method of manufacturing the semiconductor package having the above configuration will be described.

【0033】先ず、図2 (a)に断面的に示すごとく、半
導体ウエハ8(切断分離して複数個の半導体素子もしく
は半導体チップ7となる)の各電極7a面に、所定のスク
リーン版を用いて、Ag系の導電性ペーストを印刷し、乾
燥後、再び重ねてAg系導電性ペーストを印刷・乾燥する
工程を繰り返して、高さ30〜80μm 程度の円錐状の導電
性バンプ6b′群を設ける。ここで、半導体ウエハー8
は、一般的に、電極7a面以外の面に絶縁コート、もしく
はパッシベーション膜(図示を省略)が設けられてお
り、また、これら絶縁コートやパッシベーション膜は、
予め、粗面化処理もしくはプラズマ処理などを施してお
き、絶縁体との接着力を高めるようにしておくことが好
ましい。なお、上記導電性バンプ6b′群の形成は、Ag系
導電性ペーストの印刷の代りに、たとえば半田メッキで
形成してもよい。
First, as shown in cross section in FIG. 2A, a predetermined screen plate is used on each electrode 7a surface of a semiconductor wafer 8 (cut and separated into a plurality of semiconductor elements or semiconductor chips 7). Then, after printing and drying the Ag-based conductive paste, the process of printing and drying again the Ag-based conductive paste is repeated to form a group of conical conductive bumps 6b 'having a height of about 30 to 80 μm. Provide. Here, the semiconductor wafer 8
In general, an insulating coat or a passivation film (not shown) is provided on a surface other than the electrode 7a surface, and these insulating coats and passivation films are
It is preferable that a roughening treatment or a plasma treatment is performed in advance to increase the adhesive strength with the insulator. The conductive bumps 6b 'group may be formed by, for example, solder plating instead of printing the Ag-based conductive paste.

【0034】次いで、図2 (b)に断面的に示すごとく、
前記導電性バンプ6b′を設けた半導体ウエハー8面に、
液晶ポリマーシート6′を介して導電性金属層(たとえ
ば厚さ12μm の電解銅箔)6a′を重ね合わせ配置する。
Next, as shown in cross section in FIG.
On the surface of the semiconductor wafer 8 provided with the conductive bumps 6b ',
A conductive metal layer (for example, a 12 μm-thick electrolytic copper foil) 6 a ′ is placed one over the other via a liquid crystal polymer sheet 6 ′.

【0035】その後、前記重ね合わせ体を加熱・加圧す
ると、図2 (c)に断面的に示すごとく、導電性バンプ6
b′先端側は、液晶ポリマーシート6′を貫挿し、対向
する電解銅箔(導電性金属層)6a′面に対接・接続す
る。すなわち、液晶ポリマーシート(絶縁体層)6′を
貫挿した導電性バンプ6b′先端側は塑性変形などしなが
ら、対向する電解銅箔6a′面に電気的および機械的に接
続する。同時に半導体ウエハー8面が、液晶ポリマーシ
ート6′を介して電解銅箔6a′面に機械的に接合する。
引き続いて、前記電解銅箔6a′をパターンニングし、
外部接続端子6a群を形成する。この外部接続端子6a群の
形成に当たっては、半導体ウエハー8の電極7aの数や間
隔・ピッチなどを考慮し、外部接続端子6aも分散的に配
置することがあるので、一部配線パターンを含む形を採
ることもある。
Thereafter, when the laminated body is heated and pressed, as shown in FIG.
The front end side of b 'penetrates the liquid crystal polymer sheet 6' and contacts and connects to the opposing surface of the electrolytic copper foil (conductive metal layer) 6a '. That is, the tip of the conductive bump 6b 'penetrating the liquid crystal polymer sheet (insulator layer) 6' is electrically and mechanically connected to the opposing surface of the electrolytic copper foil 6a 'while performing plastic deformation or the like. At the same time, the surface of the semiconductor wafer 8 is mechanically bonded to the surface of the electrolytic copper foil 6a 'via the liquid crystal polymer sheet 6'.
Subsequently, the electrolytic copper foil 6a 'is patterned,
The external connection terminals 6a are formed. In forming the group of external connection terminals 6a, the external connection terminals 6a are sometimes arranged in a dispersed manner in consideration of the number, interval, pitch, and the like of the electrodes 7a of the semiconductor wafer 8, so that the shape including a part of the wiring pattern is used. Sometimes adopted.

【0036】このようにして、液晶ポリマーシート6′
を介し半導体ウエハー8および電解銅箔6a′が接合し、
かつ局所的に接続した一体的な導体パターンをダイシン
グにより切断して個片の半導体パッケージとする。すな
わち、インタポーザ基板による外部接続端子を有する半
導体パッケージを得ることができる。
Thus, the liquid crystal polymer sheet 6 '
The semiconductor wafer 8 and the electrolytic copper foil 6a 'are joined through
In addition, the locally connected integral conductor pattern is cut by dicing into individual semiconductor packages. That is, it is possible to obtain a semiconductor package having an external connection terminal using the interposer substrate.

【0037】上記構成された半導体装置は、スルホール
接続部を成す導電性バンプ6bが微細で、かつ微小なピッ
チで配置されている場合でも、位置ずれや隣接する導電
性バンプ6b同士の短絡発生などの恐れがなく、かつ電気
的に低抵抗の接続、機械的に強い接合を成している。つ
まり、絶縁体層を成す液晶ポリマーの特性が効果的に利
用され、信頼性の高い半導体モジュールとして機能す
る。すなわち、導電性バンプの液晶ポリマー層における
貫通性が良好で、エポキシ樹脂などの接着層を用いた場
合に起こり易い電解銅箔6a′との接合界面に薄い樹脂層
の形成もほとんどないので、信頼性の高い電気的な接続
が形成される。
In the semiconductor device configured as described above, even when the conductive bumps 6b forming the through-hole connection portion are fine and arranged at a fine pitch, the conductive bumps 6b may be misaligned or short-circuited between adjacent conductive bumps 6b. There is no danger, and the connection is electrically low resistance and mechanically strong. That is, the characteristics of the liquid crystal polymer forming the insulator layer are effectively used, and the semiconductor module functions as a highly reliable semiconductor module. That is, since the conductive bumps have good penetrability in the liquid crystal polymer layer, and there is almost no formation of a thin resin layer at the bonding interface with the electrolytic copper foil 6a ', which is likely to occur when an adhesive layer such as an epoxy resin is used. A highly reliable electrical connection is formed.

【0038】図3は、第2の実施例に係る半導体パッケ
ージ(半導体モジュール)の要部構成を示す断面図であ
る。スルホール接続部を成す導電性バンプ6bの構成が相
違する他は、第1の実施例に係る半導体パッケージと同
様の構造と成っている。すなわち、第1の実施例に係る
半導体パッケージ例では、導電性バンプ6bがAgペースト
系のみで形成されているが、第2の実施例に係る半導体
パッケージでは、メッキバンプ6b1 およびAgペースト系
バンプ6b2 の複合形で形成され、かつAgペースト系バン
プ6b2 側が外部接続端子6aに接合した構成を採ってい
る。そして、この半導体パッケージの場合も、第1の実
施例の場合と同様に、信頼性の高い半導体モジュールと
して機能する。
FIG. 3 is a cross-sectional view showing a configuration of a main part of a semiconductor package (semiconductor module) according to a second embodiment. The structure is the same as that of the semiconductor package according to the first embodiment except that the configuration of the conductive bump 6b forming the through-hole connection portion is different. That is, in the semiconductor package example according to the first embodiment, although the conductive bump 6b are formed only in the Ag paste systems, in the semiconductor package according to the second embodiment, the plated bump 6b 1 and Ag paste systems bumps It is formed of a composite type 6b 2, and adopts a configuration in which Ag paste systems bump 6b 2 side is joined to the external connection terminal 6a. Then, also in the case of this semiconductor package, as in the case of the first embodiment, it functions as a highly reliable semiconductor module.

【0039】なお、第2の実施例に係る半導体パッケー
ジは、前記第1の実施例に係る半導体パッケージの製造
方法に準じた手段で容易に製造できる。
The semiconductor package according to the second embodiment can be easily manufactured by means according to the method for manufacturing a semiconductor package according to the first embodiment.

【0040】本発明は上記例示に限定されるものでな
く、発明の主旨を逸脱しない範囲でいろいろの変化を採
ることができる。
The present invention is not limited to the above examples, and various changes can be made without departing from the gist of the invention.

【0041】[0041]

【発明の効果】請求項1〜4の発明によれば、絶縁体層
を形成する液晶ポリマーなどが、すぐれた耐湿性、小さ
い誘電率、良好なバンプ突き抜き性を有することに伴っ
て、微細な外部接続端子配置でも、隣接するスルホール
接続部同士の短絡発生が解消され、かつ電気的特性など
も良好で、耐久性ないし信頼性のすぐれた半導体パッケ
ージが低コストで提供される。なお、絶縁体が液晶ポリ
マーの場合は、熱軟化性を有するので、半導体パッケー
ジを外部回路板に実装した状態での熱膨脹係数差による
熱ストレスが緩和され、熱ストレスに起因する損傷など
が防止される。
According to the first to fourth aspects of the present invention, the liquid crystal polymer or the like forming the insulator layer has excellent moisture resistance, a small dielectric constant, and good bump piercing properties. Even with such an external connection terminal arrangement, a short-circuit between adjacent through-hole connection portions is eliminated, electrical characteristics and the like are excellent, and a semiconductor package having excellent durability or reliability is provided at low cost. When the insulator is a liquid crystal polymer, it has thermal softening properties, so that thermal stress due to a difference in thermal expansion coefficient when the semiconductor package is mounted on an external circuit board is reduced, and damage due to thermal stress is prevented. You.

【0042】請求項5ないし8の発明では、液晶ポリマ
ーシートなどを絶縁体シートとし、絶縁体層を形成する
ため、すぐれた耐湿性、小さい誘電率、良好なバンプ突
き抜き性を有することに伴って、微細な外部接続端子配
置でも、隣接するスルホール接続部同志の短絡発生が回
避され、かつ電気的特性なども良好で、信頼性向上が図
られた半導体パッケージを、繁雑な操作を要せずに、歩
留まりよく提供できる。
According to the fifth to eighth aspects of the present invention, the liquid crystal polymer sheet or the like is used as an insulator sheet to form an insulator layer, so that it has excellent moisture resistance, a small dielectric constant, and good bump punching properties. Even with a fine external connection terminal arrangement, short-circuiting between adjacent through-hole connection parts can be avoided, and the electrical characteristics etc. are good, and a semiconductor package with improved reliability can be manufactured without complicated operations. In addition, it can be provided with good yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施例に係る半導体パッケージの要部構
成例を示す断面図。
FIG. 1 is a sectional view showing a configuration example of a main part of a semiconductor package according to a first embodiment.

【図2】第1の実施例に係る半導体パッケージの製造法
例を模式的に示すもので、 (a)は半導体ウエハーの電極
面に導電性バンプを設けた状態の断面図、 (b)は半導体
ウエハー、液晶ポリマーシートおよび導電性体層の積層
状態の断面図、 (c)は積層一体化状態の断面図。
FIGS. 2A and 2B schematically show an example of a method of manufacturing a semiconductor package according to a first embodiment, in which FIG. 2A is a cross-sectional view in which conductive bumps are provided on electrode surfaces of a semiconductor wafer, and FIG. FIG. 3C is a cross-sectional view of a laminated state of a wafer, a liquid crystal polymer sheet, and a conductive material layer, and FIG.

【図3】第2の実施例に係る半導体パッケージの要部構
成例を示す断面図。
FIG. 3 is a sectional view showing a configuration example of a main part of a semiconductor package according to a second embodiment.

【図4】従来の半導体パッケージの要部構成を示す断面
図。
FIG. 4 is a cross-sectional view showing a main part configuration of a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

1……基板 1a,6a……基板の接続端子 2,7……半導体チップ 2a,7a……半導体チップの電極 3……導体バンプ 4,6a……基板の外部接続端子 5……封止樹脂層 6……液晶ポリマー系基板 6a′……銅箔 6b……導電性バンプ(スルホール接続部) 8……半導体ウエハー DESCRIPTION OF SYMBOLS 1 ... Board 1a, 6a ... Connection terminal of board 2, 7 ... Semiconductor chip 2a, 7a ... Electrode of semiconductor chip 3 ... Conductor bump 4, 6a ... External connection terminal of board 5 ... Sealing resin Layer 6: Liquid crystal polymer substrate 6a ': Copper foil 6b: Conductive bump (through hole connection) 8: Semiconductor wafer

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 一主面に外部接続端子群が配設された回
路基板と、 前記基板を厚さ方向に貫挿して各外部接続端子に一端が
電気的に接続する導電性バンプ群と、 前記基板の他主面にフェースダウンに配設され、各導電
性バンプの他端が電極面に接続された半導体チップと、
を有することを特徴とする半導体パッケージ。
A circuit board having an external connection terminal group disposed on one main surface thereof; a conductive bump group having one end electrically connected to each external connection terminal by penetrating the substrate in a thickness direction; A semiconductor chip disposed face-down on the other main surface of the substrate, the other end of each conductive bump being connected to an electrode surface;
A semiconductor package comprising:
【請求項2】 一主面の外部接続端子群が配線によって
分散的に配設されていることを特徴とする請求項1記載
の半導体パッケージ。
2. The semiconductor package according to claim 1, wherein the external connection terminal group on one main surface is dispersedly arranged by wiring.
【請求項3】 一主面の各外部接続端子面に、導電性バ
ンプが設けられていることを特徴とする請求項1もしく
は請求項2記載の半導体パッケージ。
3. The semiconductor package according to claim 1, wherein a conductive bump is provided on each of the external connection terminal surfaces on one main surface.
【請求項4】 回路基板が液晶ポリマーを絶縁体として
形成されていることを特徴とする請求項1ないし請求項
3いずれか一記載の半導体パッケージ。
4. The semiconductor package according to claim 1, wherein the circuit board is formed using a liquid crystal polymer as an insulator.
【請求項5】 半導体チップの電極面に導電性バンプを
設ける工程と、 前記導電性バンプを設けた半導体チップ面に絶縁性シー
トを介して導電性金属層を重ね合わせ配置する工程と、 前記重ね合わせ体を加圧して、絶縁性シートを貫挿する
導電性バンプ先端側を導電性金属層面に対接・接続する
工程と、 前記導電性金属層をパターンニングし、外部接続端子部
を形成する工程と、を有することを特徴とする半導体パ
ッケージの製造方法。
5. A step of providing a conductive bump on an electrode surface of a semiconductor chip, a step of superposing and arranging a conductive metal layer on a surface of the semiconductor chip provided with the conductive bump via an insulating sheet, and Pressurizing the joined body, contacting and connecting the front end side of the conductive bump penetrating the insulating sheet to the surface of the conductive metal layer, and patterning the conductive metal layer to form an external connection terminal portion And a method of manufacturing a semiconductor package.
【請求項6】 半導体ウエハーの各半導体素子電極面に
導電性バンプを設ける工程と、 前記導電性バンプを設けた半導体チップ面に絶縁性シー
トを介して導電性金属層を重ね合わせ配置する工程と、 前記重ね合わせ体を加圧して、絶縁性シートを貫挿する
導電性バンプ先端側を導電性金属層面に対接・接続する
工程と、 前記導電性金属層をパターンニングし、外部接続端子部
を形成する工程と、 前記外部部接続端子部を形成した積層体をカッティング
加工する工程と、を有することを特徴とする半導体パッ
ケージの製造方法。
6. A step of providing a conductive bump on each semiconductor element electrode surface of a semiconductor wafer, and a step of superposing and arranging a conductive metal layer via an insulating sheet on the semiconductor chip surface provided with the conductive bump. Pressurizing the superimposed body, contacting and connecting the front end side of the conductive bump penetrating the insulating sheet to the surface of the conductive metal layer, and patterning the conductive metal layer to form an external connection terminal portion. And a step of cutting the stacked body on which the external connection terminal portions are formed.
【請求項7】 外部接続端子部面に、さらに、導電性バ
ンプを設けることを特徴とする請求項5もしくは請求項
6記載の半導体パッケージの製造方法。
7. The method for manufacturing a semiconductor package according to claim 5, wherein a conductive bump is further provided on the surface of the external connection terminal portion.
【請求項8】 絶縁性シートが液晶ポリマーシートであ
ることを特徴とする請求項5ないし請求項7いずれか一
記載の半導体パッケージの製造方法。
8. The method of manufacturing a semiconductor package according to claim 5, wherein the insulating sheet is a liquid crystal polymer sheet.
JP14387397A 1997-06-02 1997-06-02 Semiconductor package manufacturing method Expired - Fee Related JP3378171B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14387397A JP3378171B2 (en) 1997-06-02 1997-06-02 Semiconductor package manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14387397A JP3378171B2 (en) 1997-06-02 1997-06-02 Semiconductor package manufacturing method

Publications (2)

Publication Number Publication Date
JPH10335528A true JPH10335528A (en) 1998-12-18
JP3378171B2 JP3378171B2 (en) 2003-02-17

Family

ID=15348997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14387397A Expired - Fee Related JP3378171B2 (en) 1997-06-02 1997-06-02 Semiconductor package manufacturing method

Country Status (1)

Country Link
JP (1) JP3378171B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196390A (en) * 2000-01-11 2001-07-19 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
US6429043B1 (en) 1999-05-07 2002-08-06 Nec Corporation Semiconductor circuitry device and method for manufacturing the same
JP2003051570A (en) * 2001-08-07 2003-02-21 Sumitomo Bakelite Co Ltd Semiconductor device and its manufacturing method
JP2003110053A (en) * 2001-09-28 2003-04-11 Kuraray Co Ltd Film covering semiconductor device and manufacturing method thereof
JP2005101507A (en) * 2003-08-21 2005-04-14 Seiko Epson Corp Method of manufacturing electronic component package and method of manufacturing electrooptic device
US6991965B2 (en) 2002-12-13 2006-01-31 Nec Electronics Corporation Production method for manufacturing a plurality of chip-size packages
EP1906445A2 (en) 2006-09-26 2008-04-02 Shinko Electric Industries Co., Ltd. Manufacturing method of semiconductor device
EP2075833A2 (en) 2007-12-27 2009-07-01 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device
US8884433B2 (en) 2005-06-24 2014-11-11 Qualcomm Incorporated Circuitry component and method for forming the same

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429043B1 (en) 1999-05-07 2002-08-06 Nec Corporation Semiconductor circuitry device and method for manufacturing the same
JP2001196390A (en) * 2000-01-11 2001-07-19 Sanyo Electric Co Ltd Method of manufacturing semiconductor device
JP4711483B2 (en) * 2000-01-11 2011-06-29 三洋電機株式会社 Manufacturing method of semiconductor device
JP2003051570A (en) * 2001-08-07 2003-02-21 Sumitomo Bakelite Co Ltd Semiconductor device and its manufacturing method
JP2003110053A (en) * 2001-09-28 2003-04-11 Kuraray Co Ltd Film covering semiconductor device and manufacturing method thereof
US6991965B2 (en) 2002-12-13 2006-01-31 Nec Electronics Corporation Production method for manufacturing a plurality of chip-size packages
CN100374912C (en) * 2003-08-21 2008-03-12 精工爱普生株式会社 Manufacture of electronic device installing bodies
JP2005101507A (en) * 2003-08-21 2005-04-14 Seiko Epson Corp Method of manufacturing electronic component package and method of manufacturing electrooptic device
US8884433B2 (en) 2005-06-24 2014-11-11 Qualcomm Incorporated Circuitry component and method for forming the same
EP1906445A2 (en) 2006-09-26 2008-04-02 Shinko Electric Industries Co., Ltd. Manufacturing method of semiconductor device
EP1906445A3 (en) * 2006-09-26 2009-11-25 Shinko Electric Industries Co., Ltd. Manufacturing method of semiconductor device
US7749889B2 (en) 2006-09-26 2010-07-06 Shinko Electric Industries Co., Ltd. Manufacturing method of semiconductor device
EP2075833A2 (en) 2007-12-27 2009-07-01 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device
US7964493B2 (en) 2007-12-27 2011-06-21 Shinko Electric Industries Co., Ltd. Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JP3378171B2 (en) 2003-02-17

Similar Documents

Publication Publication Date Title
EP2172089B1 (en) Method for manufacturing a multilayer wiring element having pin interface
US8030137B2 (en) Flexible interposer for stacking semiconductor chips and connecting same to substrate
US7640655B2 (en) Electronic component embedded board and its manufacturing method
KR100507791B1 (en) Electric component embedded module and method of manufacturing the same
US8618669B2 (en) Combination substrate
US5949142A (en) Chip size package and method of manufacturing the same
US20090020870A1 (en) Electronic device provided with wiring board, method for manufacturing such electronic device and wiring board for such electronic device
WO2001026147A1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JP5406572B2 (en) Electronic component built-in wiring board and manufacturing method thereof
US20080298023A1 (en) Electronic component-containing module and manufacturing method thereof
JP4950743B2 (en) Multilayer wiring board and manufacturing method thereof
US6441486B1 (en) BGA substrate via structure
JP2004311598A (en) Substrate with reinforcement, wiring board consisting of semiconductor element, reinforcement and substrate
JP5238182B2 (en) Manufacturing method of multilayer wiring board
JP3378171B2 (en) Semiconductor package manufacturing method
JP2009146940A (en) Laminated wiring board and manufacturing method therefor
WO2013061500A1 (en) Flexible wiring board and method for manufacturing same
JP4718890B2 (en) MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME, MULTILAYER WIRING BOARD STRUCTURE
JP5285385B2 (en) Manufacturing method of multilayer wiring board
KR20080073648A (en) Multilayer wiring board and method of manufacturing the same
JP2006310543A (en) Wiring board and its production process, wiring board with semiconductor circuit element
CN108305864B (en) Terminal with a terminal body
US9673063B2 (en) Terminations
JP3692810B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
KR101283747B1 (en) The printed circuit board and the method for manufacturing the same

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20021126

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071206

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081206

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees