CN108305864B - Terminal with a terminal body - Google Patents

Terminal with a terminal body Download PDF

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Publication number
CN108305864B
CN108305864B CN201710021398.0A CN201710021398A CN108305864B CN 108305864 B CN108305864 B CN 108305864B CN 201710021398 A CN201710021398 A CN 201710021398A CN 108305864 B CN108305864 B CN 108305864B
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Prior art keywords
support structure
electronic support
layer
copper
dielectric material
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CN201710021398.0A
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CN108305864A (en
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卓尔·赫尔维茨
黄士辅
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Zhuhai Yueya Semiconductor Co ltd
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Zhuhai Yueya Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An electronic support structure comprising one or more copper feature layers, such as copper wiring layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix, wherein pairs of adjacent copper feature layers are connected by via layers, wherein terminals on at least one side of the electronic support structure comprise modified on-trace bond attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of the copper features for conductively connecting solder.

Description

Terminal with a terminal body
Technical Field
The present invention relates to terminals for multilayer electronic support structures such as interposers and methods of making the same.
Background
With the drive for ever greater demands for miniaturization of increasingly complex electronic devices, consumer electronics products such as computing and telecommunications equipment are becoming more and more integrated. This has led to the requirement for support structures, such as IC substrates and IC packages, to have a high density of multiple conductive layers and vias that are electrically isolated from each other by dielectric materials.
The overall requirements for such a support structure are reliability and adequate electrical performance, thinness, rigidity, flatness, good heat dissipation, and competitive unit price.
Among the high-density wiring technologies used to interconnect substrates and chips, the mature technology is the "flip chip" technology, in which solder bumps, lead-free solder bumps, or copper bumps with solder or lead-free solder at their ends are grown on the terminal pads of the chip, and then the chip is flipped over to interconnect its bumps with the pads on the upper surface of the substrate. As chip bumps and pitches become denser, advanced substrates are sometimes themselves provided with bumps to assist in interconnection with the chip bumps. Such bumps on the substrate pads are also referred to as "SoP" (Solder on Pad) bumps and are typically composed of Solder or lead-free Solder. SoP bumps are typically applied to substrate terminal pads by screen printing followed by reflow, or by a plating process followed by reflow, or by dropping solder balls onto the fluxed pads of the substrate. Such bumps are typically "coined" by applying heat and pressure to create a top planar surface on the bump, which may facilitate placement of the bump from the die side.
Minimum bump array pitch on substrates of 140 μm to 150 μm solder bumps are currently used in many applications, and 50 μm to 60 μm pitch corresponding to the introduction of 14nm node silicon is expected to be required.
The creation of solder bumps on substrates at increasingly tight pitches is very tricky, as existing methods of screen printing, solder ball drop or solder bump plating are required to be increasingly accurate and thus more expensive in order to overcome the risk of short circuits between more finely spaced adjacent connections.
United states patent US 9,049,791 entitled "Novel terminals and connections Between chip and substrate" (Novel Terminations and Couplings Between Chips and Substrates) "filed by helvets (Hurwitz) and yellow (Huang) on 2013, 6/7 discloses a multilayer composite electronic structure comprising at least one pair of feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer comprising via posts connecting adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner dielectric, the multilayer composite structure further comprising terminals consisting of outer layers of via posts embedded in an outer dielectric material exposed, which are thinned to end portions of the outer layers of the via posts.
U.S. patent application USSN13/912,652 to herrwitz (Hurwitz) teaches a copper via post that is embedded in a dielectric and then thinned so that the end of the copper via post is flush with the surface of the dielectric. Typically, a thinned outer layer of the via post having an exposed end is embedded in a substantially flat outer dielectric material having a roughness of less than 3 microns, and the exposed outer layer of the via post is interconnectable with the flip-chip bump. The via post ends, which are flush with the dielectric in which they are embedded, may be connected to the flip chip bumps by reflow or by a Z-conductive anisotropic adhesive material with a solderable metal.
It should be understood that the contact area between the solder bump and the copper via post is limited to the cross-sectional area of the copper via post. All the contacts are located on one plane. This results in a certain susceptibility to open contacts and electrical open faults.
Us patent application USSN14/150,683 entitled "Substrates with Protruding Copper Termination Posts (Substrates with projecting Copper Termination Posts)" filed by herwitz (Hurwitz) and yellow (Huang) on 8.1.2004 describes a different approach. Wherein again a multilayer composite electronic structure is described comprising feature layers extending in an X-Y plane, wherein each pair of adjacent feature layers is separated by a via-hole layer comprising via posts connecting adjacent feature layers in a Z-direction perpendicular to the X-Y plane, the via posts being embedded in an interlayer dielectric. In the disclosed structure, the multilayer composite structure further includes at least one terminal outer layer comprising at least one microbump, wherein the at least one microbump includes a via post covered with a solderable material. The solderable material on the micro-bumps fuses with the solder bumps of the flip-chip package to be attached to the chip. This provides additional solderable material and aids adhesion. This solution is somewhat more expensive than other termination techniques because of the additional handling and the different composition of the weldable materials required.
Us patent application USSN 18/015,812 entitled "Substrates with Protruding Copper Termination Posts" (Substrates with projecting Copper Termination Posts) filed by helvets (Hurwitz) and yellow (Huang) 24/2014 teaches a multilayer composite electronic structure comprising feature layers extending in an X-Y plane, each pair of adjacent feature layers being separated by an inner via layer comprising via Posts connecting adjacent feature layers in a Z-direction perpendicular to the X-Y plane, the via Posts being embedded in an inner layer dielectric, the multilayer composite electronic structure further comprising at least one terminal outer layer comprising a two-dimensional array of Copper Posts only partially embedded in the dielectric outer layer such that a portion of each Copper post protrudes beyond the surface of the dielectric outer layer.
This method can enhance bonding because the solder bumps of the chip can be coated and bonded not only to the top surfaces of the protruding ends but also to the side walls from which they protrude. This provides a greater bonding surface area and is less likely to simply shear and fail because the solder-pillar interface is not linear. The method also supports the degree of adhesion of the copper pillars to the substrate, as the copper pillars are anchored to the substrate by their bases and non-protruding sidewalls. However, because the copper pillars have a relatively large thickness compared to the conductor layers, and because each copper pillar must be precisely aligned with the underlying conductor layer, the pillars are subject to separation spacing limitations, which can have a detrimental effect on their application in tight pitch flip chip devices. Furthermore, it should be appreciated that the additional copper pillar layers increase the number of process steps required to manufacture such substrates, thereby increasing manufacturing costs and reducing yield.
Despite various developments in interposer terminals, there is a continuing drive factor for tighter pitch conductors with terminals to which flip chip devices may be attached by solder bumps to avoid additional structures such as copper pillars, which may result in the need for additional processing and alignment steps and an increase in undesirable thickness.
Disclosure of Invention
The present invention relates to a novel terminal that enables lower cost, higher yield, more reliable packages and multi-layered support structures with tighter pitches.
A first aspect relates to an electronic support structure comprising an underlying structure, an outer via layer and a copper feature layer (e.g. a copper wiring layer), the inner portions of the outer via layer and the copper feature layer being laminated within a dielectric material, the outer portions of the copper feature layer protruding beyond the dielectric material.
Typically, the exterior of the copper feature layer protruding beyond the dielectric material is coated with an organic solderability preservative OSP.
Preferably, the outer portion of the copper feature layer that protrudes beyond the dielectric material by at least 5 microns.
Preferably, the copper feature layer is partially embedded in the dielectric material to a depth of at least 5 microns.
Typically, the dielectric material comprises a polymer matrix.
Typically, the polymer matrix comprises a polymer resin selected from the group consisting of thermosets and thermoplastics.
Typically, the dielectric material also comprises glass fibers.
Typically, the dielectric material also includes an inorganic filler.
Typically, the terminals on at least one side of the electronic support structure include bond-on-trace attachment sites that include a top surface and portions of side surfaces of copper features that are selectively exposed in an outer layer of the copper feature layer as sites for conductive connection with solder.
Typically, the outer side surfaces of the external copper features protrude at least 5 microns beyond the dielectric material for wetting by solder to facilitate attachment of the IC chip.
Generally, the electronic support structure of claim 1 comprises an insert.
Typically, the underlying structure includes a terminal layer.
Optionally, the substructure includes at least one additional feature layer.
Optionally, the underlying structure comprises at least one additional via layer.
A second aspect relates to a method of attaching an IC chip to an electronic support structure as described, comprising selectively removing the organic solderability preservative OSP (if present) and connecting the chip directly to the outer layer of the feature by flip chip technology such that solder from the chip terminals engages with a top surface and a portion of the exposed side surfaces of the outer layer of the feature, enabling strong anchoring.
Optionally, the exposed features are exposed by selective plasma ablation of the dielectric matrix.
In the present specification, the term micrometer or μm means micrometer or 10-6m。
Drawings
For a better understanding of the invention and to show embodiments thereof, reference is made, purely by way of example, to the accompanying drawings.
With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the preferred embodiments of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; the description taken with the drawings making apparent to those skilled in the art how the several embodiments of the invention may be embodied in practice. In the drawings:
FIG. 1 is a simplified cross-sectional schematic view of a prior art multi-layered composite support structure;
FIG. 2 is a simplified cross-sectional schematic view of a prior art chip package including a chip attached to a wiring level by solder balls and entirely embedded in a dielectric, and terminals including a post layer embedded in the dielectric and having ends flush with the dielectric, the ends being protected by a termination material such as nickel, gold, tin, lead, tin-lead alloys, silver, palladium, and alloys thereof;
fig. 3 is a simplified cross-sectional schematic diagram showing how the wiring layer of the interposer may partially protrude from the surrounding dielectric and be protected with an organic solderability preservative OSP;
fig. 4 is a simplified cross-sectional schematic diagram showing how an organic solderability preservative OSP is stripped from a interposer wiring layer partially protruding from a surrounding dielectric and enhanced bonding of the IC to the interposer wiring layer is achieved by solder balls which not only contact the outermost surface of the wiring layer, but also flow over and around the protruding wiring layer to bond with the partially protruding sidewalls of the wiring layer to achieve a stronger bond.
Detailed Description
In the following description, reference is made to a support structure consisting of metal vias, in particular copper via pillars in a dielectric matrix, such as polyimide, epoxy or BT (bismaleimide/triazine) resin or blends thereof. The dielectric may be a glass fiber reinforced material or applied as a pre-form. Other embodiments use other thermoplastic or thermoset polymers.
FIG. 1 is a simplified cross-sectional schematic view of a prior art multi-layered composite support structure. For example, as described in U.S. patents US 7,682,972, US 7,669,320, and US 7,635,641, a prior art multilayer support structure 100 includes functional layers 102, 104, 106 of components or features 108 separated by dielectric layers 110, 112, 114, 116 that insulate the various layers. Vias 118 through the dielectric layers provide electrical connections between features 108 in adjacent functional or featured layers 102, 104, 106. Thus, the feature layers 102, 104, 106 include features 108 arranged generally in the X-Y plane within the layers, and vias 118 conduct current through the dielectric layers 110, 112, 114, 116. Vias 118 are typically designed to have minimal inductance and are sufficiently isolated to have minimal capacitance therebetween.
Typically, the chip is attached to one side of the multilayer composite support structure, while the other side is connected to a printed circuit board, PCB.
Referring to fig. 2, an ultra-thin package 200 is shown consisting of a die 210 directly connected to a fan-out wiring layer 214 in a "flip-chip" configuration by an array of solder bumps 218. The chip 210, solder bumps 218, and wiring layer 214 are all embedded in a dielectric 220, which dielectric 220 comprises a polymer matrix that may be reinforced with glass fibers. The ultra-thin package 200 has terminals for connecting a printed circuit board PCB or the like. The terminals are vias 212 coated with a termination material 222, such as nickel, gold, tin, lead, tin-lead alloys, silver, palladium, and alloys thereof. The vias are embedded in a dielectric 216, the dielectric 216 comprising a polymer matrix that may be reinforced with glass fibers. The structure of fig. 2 is described in US patent US 8,866,286 entitled "single layer Coreless Substrate" to herrwitz et al.
The via post layer between the wiring layer 218 and the IC chip 210 is avoided by connecting the IC chip 210 directly to the wiring layer 214 through the solder bumps 218 on the IC chip 210. This avoids additional manufacturing steps, reduces manufacturing costs, and also minimizes the thickness of the package 200.
Connecting the chip 210 to the fan-out wiring level 214 by an array of solder bumps 218 is a connection known as "Bond-on-Trace" (Bond-on-Trace BoT). Each solder bump 218 is connected to the top surface of the routing layer 214. The on-trace bond BoT type solution shows that the location of the routing layer 214 on the surface of the dielectric 216 is referred to as an "extended trace". A problem with this approach is that the traces (i.e., routing layer 214) are not tightly bonded to the underlying dielectric 216, and poor adhesion may result in trace flaking during curing of the underlying dielectric 216 after flip-chip connection by solder bumps 218, before dielectric 220 is applied over chip IC 210.
It will be appreciated that extended trace reliability becomes more difficult to achieve as the wires must be thinner so that the FC pitch becomes smaller. Thus, the adhesion strength of a wiring layer 214, such as a 10 micron line, is much more problematic than a line, such as a 20 micron wide line, because the contact area between the wiring layer 214 and the dielectric 216 is much smaller. Furthermore, wetting and bonding of the solder bumps 218 to the traces or features 214 occurs only on the top surface of the traces or features 214, and thus the bond between the solder and the traces (features) is not strong.
There is another type of on-trace bond "BoT" called an "embedded trace" in which not only the bottom, but also the edges of the trace are surrounded by dielectric 216, with its top surface flush or slightly submerged (0 μm to 5 μm) with the top surface of the dielectric. With embedded traces, the likelihood of conductor delamination is minimized, but the smaller the trace becomes, the more critical is the trace's flush with the surface, since the small amount of solder available from the solder bumps on the top of the flip chip is generally not sufficient to wet its surface, even to penetrate into the small voids between the trace and the prepreg.
Referring to fig. 3, a substrate 324 is shown that may be an insert or other multi-layer support structure. The only focus is on the outer layer of features 314 and vias 312. The remaining layers 325 are not shown in detail. The remaining layers 325 typically include terminals for connection to a printed circuit board and one or more feature layers separated by a via layer.
The outermost via layer 312 is covered by a feature layer 314. Unlike feature layer 214 in fig. 2, which is bonded over the trace as an extension, feature layer 314 is partially immersed in dielectric 316. Feature layer 314 is at least 10 microns thick, and features of at least 5 microns of feature layer 314 are embedded in dielectric 316 and protrude above dielectric 316 by at least 5 microns.
The embedded portion 315 of the feature in feature layer 314, together with the bottom surface of the feature that also contacts dielectric 316, serves as an anchor for dielectric 316 and prevents the feature of feature layer 314 from being lifted off. The protruding portions 313 of the feature layer 314 that protrude above the dielectric 316 are typically coated with an Organic Solderability Preservative (OSP)330, which is a water-based organic compound.
Plug 324 is made up of remaining layers 325 and an outer layer of vias 312, the outer layer of vias 312 being covered with an outer layer of features 314, which may serve as a routing layer. The outer layer of the via 312 and a portion of the outer layer of the feature 315 are embedded in a dielectric 316, the dielectric 316 comprising a polymer matrix that may be reinforced with glass fibers. The outermost portion 313 of the outer layer of feature 314 is exposed and protrudes beyond dielectric material 316. The outermost structure may be removed by mechanical, chemical or mechanochemical polishing to expose the top of the copper, and then further plasma etched away the outer layer, e.g., dielectric 316. There are various plasma etching modes that can be used. As a non-limiting example, one such approach is to use CF4:O2A carbon tetrafluoride oxygen mixture in a range between about 65:35 and about 1:20, a power of about 4KW, and a pressure in a range between about 0.1 torr and about 4 torr.
Alternatively, the outer feature layer 313 and outer via layer may be fabricated by pattern plating and lamination on a sacrificial substrate, and then the remaining layer 325 may be built upon. After stripping the sacrificial substrate, a portion of the dielectric surrounding outer feature layer 314 may be removed, leaving the outermost portion of feature layer 313 protruding and the lowest portion of feature layer 315 embedded in dielectric 316.
The protruding portion 313 of the via layer 314 may be coated with an organic solderability preservative OSP 330, which organic solderability preservative OSP 330 is a water-based organic compound that selectively bonds with copper and protects the copper from oxidation prior to soldering.
As shown in fig. 4, after removing the Organic Solderability Preservative (OSP)330, a chip 310, such as an IC, may be attached to the tabs 313 of the outer feature layer 314 using solder bumps 318. Because there is no dielectric 316 on the sidewalls of protrusion 313, solder balls 318 can flow and adhere to the exposed portions of the sidewalls, rather than only to the upper surfaces of the features of feature layer 314, and the adhesion of the solder-features of the terminals of structure 300 shown in fig. 4 is superior to the adhesion of known embedded or adhesively bonded connections on traces, due to the combination of the larger contact area and the fact that no simple shear line exists, in which case solder bumps 218 only contact the outer surfaces of feature layer 214. Thus, chip 310 is securely bonded to outer feature layer 314 even without subsequent packaging (as shown in fig. 2).
It should be appreciated that connecting IC chip 310 directly to wiring layer 314 via solder balls 318 avoids a via post layer between the wiring layer and the IC chip. This avoids additional manufacturing steps, reduces manufacturing costs, and also minimizes the thickness of the insert 324.
One fabrication technique is to use plasma to remove a portion of surrounding dielectric 316 from the embedded wiring layer, leaving embedded portions of wiring layer 315 for anchoring purposes and portions of wiring layer 313 protruding above dielectric 316. If the wiring layer 314 is deposited on a sacrificial substrate such as a copper plate, the wiring layer and underlying via layer 312 may be fabricated by electroplating in a patterned photoresist, followed by lamination of a dielectric 316, which is a prepreg or polymer sheet. After forming the underlying structure 325, the sacrificial substrate may be removed and then a portion of the dielectric 316 may be removed using plasma to expose the outer portion 313 of the wiring layer 315.
Other ways of manufacturing the partially protruding feature layer are possible. For example, a Method of manufacturing a Multilayer support Structure is described in detail in U.S. patent No. US 8,997,342 entitled "Method of manufacturing, Multilayer Electronic Structure and Structure in association with the Method" of herwitz and yellow (Huang). In this patent, the use of a release film (releasefilm) having a hardness higher than that of the prepreg resin but lower than that of the cured resin is discussed. The structure of fig. 4 may be manufactured by modifying the method of US 8,997,342, such as by only partially laminating the wiring layer 314 by applying one prepreg sheet rather than two.
It should be particularly appreciated that by using the double bond pad concept described in US 8,997,342, the dielectric thickness can be kept within 3 microns.
It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention is defined by the appended claims, including both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description.
In the claims, the terms "comprise" and variations such as "comprises," "comprising," and the like, mean that the recited elements are included, but generally not the exclusion of other elements.

Claims (16)

1. An electronic support structure comprising an underlying structure, an outer via layer and a copper feature layer, wherein the underlying structure and the copper feature layer are connected together by the outer via layer, the inner portions of the outer via layer and the copper feature layer are laminated in a dielectric material, and the outer portion of the copper feature layer protrudes beyond said dielectric material.
2. The electronic support structure of claim 1, wherein the exterior of the copper feature layer protruding beyond the dielectric material is coated with an organic solderability preservative OSP.
3. The electronic support structure of claim 1, wherein an outer portion of the copper feature layer protruding beyond the dielectric material protrudes beyond the dielectric material by at least 5 microns.
4. The electronic support structure of claim 1, wherein the copper feature layer is partially embedded in the dielectric material to a depth of at least 5 microns.
5. The electronic support structure of claim 1, wherein the dielectric material comprises a polymer matrix.
6. The electronic support structure of claim 1, wherein the polymer matrix comprises a polymer resin selected from the group consisting of thermosetting resins and thermoplastic resins.
7. The electronic support structure of claim 5, wherein the dielectric material further comprises glass fibers.
8. The electronic support structure of claim 5, wherein the dielectric material further comprises an inorganic filler.
9. The electronic support structure of claim 1, wherein the terminals on at least one side of the electronic support structure comprise attachment sites for improved bonding on traces, the sites comprising exposed top and partial side surfaces of copper features in the exterior of the copper feature layer as sites for conductive connection with solder.
10. The electronic support structure of claim 1, wherein the outer side surfaces of the copper feature layer protrude at least 5 microns above the dielectric material for wetting by solder to facilitate attachment of the IC chip.
11. The electronic support structure of claim 1, comprising an insert.
12. The electronic support structure of claim 1, wherein the substructure includes a terminal layer.
13. The electronic support structure of claim 1, wherein the substructure includes at least one additional feature layer.
14. The electronic support structure of claim 13, wherein the underlying structure includes at least one additional via layer.
15. A method of attaching an IC chip to the electronic support structure of claim 1, comprising: selectively removing the organic solderability preservative OSP if present; and connecting the chip directly to the exterior of the copper feature layer by flip chip technology such that solder from the chip terminals bonds to the top surface and a portion of the exposed side surface of the exterior of the copper feature layer to achieve a strong anchor.
16. The method of claim 15, wherein the exterior of the copper feature is exposed by selective plasma ablation of the dielectric matrix.
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