CN108305864A - Novel terminal - Google Patents
Novel terminal Download PDFInfo
- Publication number
- CN108305864A CN108305864A CN201710021398.0A CN201710021398A CN108305864A CN 108305864 A CN108305864 A CN 108305864A CN 201710021398 A CN201710021398 A CN 201710021398A CN 108305864 A CN108305864 A CN 108305864A
- Authority
- CN
- China
- Prior art keywords
- layer
- support construction
- electronics support
- copper
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052802 copper Inorganic materials 0.000 claims abstract description 46
- 239000010949 copper Substances 0.000 claims abstract description 46
- 229910000679 solder Inorganic materials 0.000 claims abstract description 36
- 238000010276 construction Methods 0.000 claims abstract description 28
- 239000000126 substance Substances 0.000 claims abstract description 24
- 239000003365 glass fiber Substances 0.000 claims abstract description 7
- 239000011159 matrix material Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 15
- 239000004744 fabric Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 239000003755 preservative agent Substances 0.000 claims description 10
- 230000002335 preservative effect Effects 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 229920000307 polymer substrate Polymers 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 7
- 238000004873 anchoring Methods 0.000 claims description 3
- 238000002679 ablation Methods 0.000 claims description 2
- 229920002313 fluoropolymer Polymers 0.000 claims description 2
- 239000004811 fluoropolymer Substances 0.000 claims description 2
- 230000004907 flux Effects 0.000 claims description 2
- 239000011256 inorganic filler Substances 0.000 claims description 2
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 3
- 229920000642 polymer Polymers 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 129
- 239000000758 substrate Substances 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000004577 thatch Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 230000002787 reinforcement Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000002346 layers by function Substances 0.000 description 2
- 239000011133 lead Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000002894 organic compounds Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 229910001074 Lay pewter Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 125000002252 acyl group Chemical group 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 150000001875 compounds Chemical group 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A kind of electronics support construction, including one or more copper characteristic layers, such as copper wiring layer, it is laminated in dielectric substance, dielectric substance includes continuous glass fibre in the polymer matrix, wherein pairs of adjacent copper characteristic layer is connected by via layer, terminal wherein on at least side of electronics support construction includes engaging attachment site on improved trace, the site is included in top surface and the surface of the selectivity exposure of the copper feature structure in the outer layer of copper feature structure, for being conductively connected solder.
Description
Technical field
The present invention relates to the terminal of the multi-layer support structure for such as plug-in unit and its manufacturing methods.
Background technology
Under the increasing drive of the miniature requirement of the electronic device for becoming increasingly complex, such as calculating and telecommunications
The integrated level of the consumption electronic products such as equipment is higher and higher.This already leads to require support construction, such as IC substrates and IC plug-in units, tool
There are highdensity multiple conductive layers and through-hole, these conductive layers and through-hole to be electrically insulated from each other by dielectric substance.
The general requirement of this support construction is reliability and electric property appropriate, thinness, rigidity, flatness, heat dissipation
Property good and competitive unit price.
For by substrate and the high density lead technology of chip interconnection, ripe technology to be " flip-chip " (" Flip
Chip ") technology, wherein growing solder projection, lead free solder bumps in the terminal pads of chip or there is solder in its end
Or the copper bump of lead-free solder, then chip is overturn with by the interconnected on the upper surface of its convex block and substrate.With core
Piece convex block and spacing become finer and close, and advanced substrate itself is furnished with convex block to assist the interconnection with chip lug sometimes.In base
This convex block on plate pad is also referred to as " SoP " (Solder on Pad, pad on solder) convex block, and usually by solder or
Lead-free solder is constituted.SoP convex blocks are usually applied in substrate terminal pads, method be then refluxed for by silk-screen printing, or
It is then flowed back by electroplating technology, or by dropping onto soldered ball on the pad of substrate handled through solder flux.This convex block is usual
By apply heat and pressure come " casting " (" coined "), to generate top flat surface on convex block, this can contribute to from
Chip side (the die side) arranges convex block.
Minimum bump array spacing is currently used for the solder projection in many applications on 140 μm to 150 μm of substrate, it is contemplated that
Need 50 μm to 60 μm spacing corresponding with 14nm node silicon is introduced.
It is very intractable to generate solder projection on substrate with more and more close spacing, because of existing screen printing
It is more and more accurate to also all the more expensive that brush, soldered ball drop or solder projection electric plating method are required, to overcome finer
Away from close on connection between occur short circuit risk.
Tie up entitled " new between chip and substrate filed in thatch (Hurwitz) and yellow (Huang) 7 days June in 2013 in Hull
Type terminal and connection (Novel Terminations and Couplings Between Chips and Substrates) "
United States Patent (USP) US 9,049,791 disclose a kind of multilayer electronic structure, be included at least one extended in X-Y plane
To characteristic layer, each adjacent pairs of characteristic layer is separated by interior bone layer, and the via layer is included in perpendicular to X-Y plane
Z-direction on connect the through-hole column of adjacent feature layer, the through-hole column is embedded in inner layer dielectric, the multi-layer compound structure
Further include the terminal being made of the outer layer for the through-hole column being embedded in outer dielectric substance, is thinned to expose outside through-hole column
The end of layer.
The U.S. Patent application USSN13/912 of thatch (Hurwitz) is tieed up in Hull, and 652 teach a kind of copper vias column, embedding
Enter and is then thinned in the dielectric so that the end of copper vias column is flushed with dielectric surface.In general, with exposed ends
The through-hole column outer layer being thinned is embedded in the outer dielectric substance of substantially flat of the roughness less than 3 microns, and through-hole column
Exposure outer layer can be interconnected with inversed-chip lug.Through-hole column end with its embedded by dielectric flush, the through-hole column end
Solderable metal can be utilized to be connected on inversed-chip lug by reflux or by Z electric anisotropy adhesive materials.
It should be appreciated that the contact area between solder projection and copper vias column is limited to the cross-sectional area of copper vias column.
All contacts are in a plane.This leads to disconnection contact, and there are certain liabilities with opens failure.
Tie up entitled " with copper outstanding termination filed in thatch (Hurwitz) and yellow (Huang) 8 days January in 2004 in Hull
The U.S. Patent application of the substrate (Substrates with Protruding Copper Termination Posts) of column "
USSN14/150,683 describes a kind of different method.Wherein, a kind of multilayer electronic structure is described again comprising
The characteristic layer extended in X-Y plane, wherein being separated by inner via hole layer per a pair of adjacent characteristic layer, the inner via hole layer includes
The through-hole column of adjacent feature layer is connected in the Z-direction perpendicular to X-Y plane, the through-hole column is embedded in inner layer dielectric.
In disclosed structure, which further includes at least one terminal outer layer comprising at least one dimpling block,
Described at least one dimpling block include the through-hole column for being covered with weldable material.Weldable material on dimpling block with it is to be attached
The solder projection of Flip-Chip Using on to chip fuses.This provides additional weldable material and helps to adhere to.It should
Solution is slightly more expensive than other termination technologies, since it is desired that the additional solderable material for carrying out processing and different constituents
Material.
Tie up entitled " with copper end outstanding filed in thatch (Hurwitz) and yellow (Huang) 24 days January in 2014 in Hull
Connect the substrate (Substrates with Protruding Copper Termination Posts) of column " United States Patent (USP) Shen
Please USSN 18/015,812 teach a kind of multilayer electronic structure comprising the characteristic layer extended in X-Y plane, often
A pair of of adjacent feature layer is separated by inner via hole layer, the via layer include connected in the Z-direction perpendicular to X-Y plane it is adjacent
The through-hole column of characteristic layer, the through-hole column are embedded in inner layer dielectric, and the multilayer electronic structure further includes at least one
A terminal outer layer comprising be only partially embedded into the two-dimentional copper post array in dielectric outer layer a so that part for each copper post
Protrude past the surface of dielectric outer layer.
This method can enhance engagement, because the solder projection of chip can coat and not only can be with the top of jag
Surface engages, and can be engaged with its side wall outstanding.This provides the surface area of engagement of bigger, and due to solder-column
Interface is not linear, is therefore less likely to simply shear and fail.This method also supports degree of adhesion of the copper post to substrate,
Because copper post is anchored to substrate by its base portion and non-protruding side wall.However, due to compared with conductor layer copper post have it is opposite
Larger thickness, and since each copper post must be precisely aligned with underlying conductor layer, so the segregated interval limit of these columns
System, this can have adverse effect its application in close spacing flip chip devices.Moreover, it will be appreciated that additional
Copper post layer increases the number of process steps manufactured needed for this substrate, to increase manufacturing cost and reduce yield.
Although having carried out various research and development for connector terminals, exists for the closer spacing conductor with terminal and hold
Continuous driving factors, flip chip devices can be attached to the additional knot to avoid such as copper post on terminal by solder projection
Structure, such additional structure can result in the need for additional processing and alignment procedures, and increase undesirable thickness.
Invention content
The present invention relates to a kind of novel terminal, low cost with closer spacing, high yield, more reliable can be realized by rising
Plug-in unit and multi-layer supporting structure.
First aspect is related to a kind of electronics support construction, including fabric, accessibke porosity layer and copper characteristic layer (such as copper cloth
Line layer), the inside of accessibke porosity layer and copper characteristic layer is laminated in dielectric substance, and the outside of copper characteristic layer protrudes past described
Dielectric substance.
In general, protrude past the copper characteristic layer of dielectric substance is externally coated with organic solderability preservative OSP.
Preferably, the outside for protruding past the copper characteristic layer of dielectric substance protrudes past at least 5 microns of dielectric substance.
Preferably, copper characteristic layer is partially embedded into dielectric substance, and insert depth is at least 5 microns.
In general, dielectric substance includes polymer substrate.
In general, polymer substrate includes the fluoropolymer resin selected from thermosets and thermoplastic.
In general, dielectric substance further includes glass fibre.
In general, dielectric substance further includes inorganic filler.
In general, the terminal on at least side of electronics support construction includes engagement (bond-on- on improved trace
Trace attachment site), the site be included in the outer layer of copper characteristic layer selectively exposed copper feature structure top surface and
Component side surface, as the site being conductively connected using solder.
In general, the side surface of the outside of exterior copper feature structure protrudes from least 5 microns of dielectric substance, for by solder
Soak the attachment in order to IC chip.
In general, the electronics support construction of claim 1 includes plug-in unit.
In general, fabric includes terminal layer.
Optionally, fabric includes at least one additional features layer.
Optionally, fabric includes at least one additional vias layer.
Second aspect is related to a kind of method being attached to IC chip in electronics support construction as mentioned, including selectivity
Ground removes organic solderability preservative OSP (if present), and chip is directly connected to feature knot by flip chip technology (fct)
The outer layer of structure a so that part for the top surface of the outer layer of solder and feature structure from chip terminal and the side surface of exposure
Engagement, enabling realize strong anchoring.
Optionally, exposed feature structure is exposed by the selective plasma ablation of dielectric matrix.
In this specification, term micron or μm refer to micron or 10-6m。
Description of the drawings
For a better understanding of the present invention and embodiments of the present invention are shown, purely by way of example with reference to attached drawing.
Referring now particularly to attached drawing, it is necessary to, it is emphasized that being specifically illustrating merely illustrative and the present invention being discussed for schematic
The purpose of preferred embodiment, the reason of providing diagram are to firmly believe that attached drawing is most useful and should be readily appreciated that the principle of the present invention and general
The explanation of thought.In this regard, do not attempt the CONSTRUCTED SPECIFICATION of the present invention to exceed to detailed necessary to basic comprehension of the present invention
Thin degree illustrates；Those skilled in the art are made to understand that the several embodiments of the present invention can be how with reference to the explanation of attached drawing
Implement.In the accompanying drawings：
Fig. 1 is the simplification schematic cross-section of the MULTILAYER COMPOSITE support construction of the prior art；
Fig. 2 is the simplification schematic cross-section of prior art chip package, and the chip package includes chip and terminal, described
Chip be attached on wiring layer by soldered ball and its integrally it is embedded in the dielectric, the terminal include it is embedded in the dielectric simultaneously
And the column layer that end is flushed with dielectric, the end are terminated material such as nickel, gold, tin, lead, leypewter, silver, palladium and its alloy
Protection；
Fig. 3 is to show how the wiring layer of plug-in unit can project partly outwards of surrounding dielectric and with organic solderability preservative OSP
The simplification schematic cross-section of protection；
Fig. 4 is simplified schematic cross-section, shows how the plug-in unit wiring layer for being partially protrude through surrounding dielectric has divested
Machine solderability preservative OSP and how by soldered ball to realize that IC is engaged with the enhancing of plug-in unit wiring layer, wherein soldered ball not only contact layout
The outermost surface of layer, and the upper surface of flow to wiring layer outstanding and surrounding is engaged with wiring layer segment side wall outstanding, from
And realize stronger engagement.
Specific implementation mode
In following discussion, involved is support construction, by the metal throuth hole in dielectric matrix, is especially existed
Copper vias column in polymer substrate is constituted, and the dielectric matrix is, for example, that (span carrys out acyl by polyimides, epoxy resin or BT
Imines/triazine) resin or its blend.The dielectric can be the material of glass fiber reinforcement or be applied as preforming material
Add.Other embodiment then selects other thermoplasticity or heat cured polymer.
Fig. 1 is the simplification schematic cross-section of the MULTILAYER COMPOSITE support construction of the prior art.For example, such as United States Patent (USP) US 7,
682,972, US 7,669,320 and US 7, described in 635,641, the multi-layer supporting structure 100 of the prior art includes being situated between by electricity
The functional layer 102,104,106 for the component or feature structure 108 that matter layer 110,112,114,116 separates, the dielectric layer
Make each layer of insulation.Across feature structure of the through-hole 118 in successive functional layers or characteristic layer 102,104,106 of dielectric layer
Electrical connection is provided between 108.Therefore, characteristic layer 102,104,106 includes the feature knot usually arranged in layer on an x-y plane
Structure 108, through-hole 118 pass through dielectric layer 110,112,114,116 to conduct electric current.Through-hole 118 is typically designed to have minimum electricity
Feel and is fully isolated so as to have minimum capacity therebetween.
In general, chip is attached to the side of MULTILAYER COMPOSITE support construction, and the other side is then connected to printing board PCB.
With reference to Fig. 2, show to construct to be directly connected to " flip-chip " by the array by solder projection 218 to be fanned out to wiring
The Ultrathin packaging 200 that the chip 210 of layer 214 forms.Chip 210, solder projection 218 and wiring layer 214 are embedded in dielectric 220
In, which includes the polymer substrate that can use glass fiber reinforcement.Ultrathin packaging 200 has for connecting printing
The terminal of circuit board PCB etc..The terminal is to be coated with termination material 222 (such as nickel, gold, tin, lead, tin-lead alloy, silver, palladium
And its alloy) through-hole 212.The through-hole is embedded in dielectric 216, and dielectric 216 includes that can use glass fiber reinforcement
Polymer substrate.Entitled " single layer seedless substrate (Single of the structure description of Fig. 2 in Hull dimension thatch (Hurwitz) et al.
Layer Coreless Substrate) " United States Patent (USP) US 8,866,286 in.
IC chip 210 is directly connected to wiring layer 214 by the solder projection 218 in IC chip 210, is avoided in cloth
Through-hole column layer between line layer 218 and IC chip 210.This avoids additional manufacturing steps, reduce manufacturing cost, and also
So that the minimizing thickness of encapsulation 200.
It is a kind of to be known as " Bond-on- to be connected to chip 210 by the array of solder projection 218 and be fanned out to wiring layer 214
The connection of Trace " (BoT is engaged on trace).Each solder projection 218 is connected to the top surface of wiring layer 214.It is engaged on trace
The solution of BoT types shows that the position that wiring layer 214 is located on the surface of dielectric 216 is referred to as " extending trace ".It should
The problem of scheme, is that trace (i.e. wiring layer 214) is not tightly engaged to bottom dielectric 216, and adhere to it is bad can
It can cause after carrying out flip-chip connection by solder projection 218, before applying the covering chip IC 210 of dielectric 220,
Trace occurs during curing bottom dielectric 216 to peel off.
It should be understood that since conducting wire must be thinner so that FC spacing becomes smaller, becomes so extending trace reliability
It must be more difficult to realize.Thus, for example the problem of adhesion strength ratio of the wiring layer 214 of 10 micro wires such as 20 microns of wide circuits, is wanted
Seriously much, this is because the contact area between wiring layer 214 and dielectric 216 is much smaller.In addition, solder projection 218 with
The wetting and engagement of trace or feature structure 214 occur over just on trace or the top surface of feature structure 214, therefore solder and mark
Engagement between line (feature structure) is not strong.
It is known as engaging " BoT " on the trace of " embedded trace " there are another type of, wherein it is not only bottom, and mark
The edge of line is also surrounded by dielectric 216, and top surface is flushed with dielectric top surface or slightly submerged (0 μm to 5 μm).Make
Reduce to minimum with the possibility of embedded trace, conductor stripping, but trace becomes smaller, then trace is more closed with flushing for surface
Key, this is because a small amount of solder obtained from the solder projection on flip-chip top is typically not enough to soak its surface, even
It is not enough to penetrate into the small gap between trace and prepreg.
With reference to Fig. 3, showing can be as plug-in unit or the substrate 324 of other multi-layer supporting structures.Concern is only that feature
The outer layer of structure 314 and through-hole 312.It is not shown specifically remainder layer 325.Remainder layer 325 is generally included for being connected to printing electricity
The terminal of road plate and the one or more features floor separated by via layer.
Outermost layer via layer 312 is covered by characteristic layer 314.The characteristic layer engaged on the trace as extension in Fig. 2
214 is different, and characteristic layer 314 is partially immersed in dielectric 316.Characteristic layer 314 is at least 10 microns of thickness, and characteristic layer
314 at least 5 microns of feature structure is embedded in dielectric 316 and protrudes at least 5 microns above dielectric 316.
The bottom table of the feature structure of the embedded part 315 of feature structure in characteristic layer 314 and same contact dielectric 316
Face is used for the anchoring of dielectric 316 and the feature structure of characteristic layer 314 is prevented to be stripped together.It protrudes on dielectric 316
The protrusion 313 of the characteristic layer 314 of side is general coated with organic solderability preservative (OSP) 330, is water base organic compound.
Plug-in unit 324 is made of the outer layer of remainder layer 325 and through-hole 312, and the outer layer of through-hole 312 is covered with feature structure 314
Outer layer, can be used as wiring layer.A part for the outer layer of through-hole 312 and the outer layer of feature structure 315 is embedded in dielectric 316
In, dielectric 316 includes the polymer substrate that can use glass fiber reinforcement.The outermost layer segment of the outer layer of feature structure 314
313 expose and protrude from dielectric substance 316.It can be by machinery, chemically or mechanically chemical polishing removes the outermost layer knot
Structure is to expose the top of copper, and then further plasma etching falls the outer layer of such as dielectric 316.In the presence of what can be used
Various plasma etching modes.As non-limiting examples, a kind of such scheme is to use CF4:O2Ranging from about 65:35
To about 1:Carbon tetrafluoride oxygen mixture between 20, power are about 4KW, and pressure limit is about 0.1-4 supports.
As an alternative, outer characteristic layer 313 and accessibke porosity layer by pattern plating and can be laminated in sacrificial substrate
Manufacture, then can build remainder layer 325 on it.After removing sacrificial substrate, it can remove and surround outer characteristic layer 314
A dielectric part leaves the outermost portion of characteristic layer 313 outstanding, and the lowermost part of characteristic layer 315 is embedded in electricity
In medium 316.
The protrusion 313 of via layer 314 can be coated with organic solderability preservative OSP 330, organic solderability preservative OSP 330
It is the water base organic compound that oxidation is selectively engaged and protected the copper from before welding with copper.
As shown in figure 4, after removing organic solderability preservative (OSP) 330, the chip 310 of such as IC can utilize solder convex
Block 318 is connected on the protruding portion 313 of outer characteristic layer 314.Due to there is no dielectric 316 on the side wall of protruding portion 313, so weldering
Ball 318 can be flowed and be adhered on the expose portion of side wall, rather than only flow to the upper table of the feature structure of characteristic layer 314
On face, and due to larger contact area and the combination for the fact that there is no simple shear lines, structure 300 shown in Fig. 4
The adherency of solder-feature structure of terminal be better than embedded or adhesive bond adherency on known trace, in latter feelings
The outer surface of the only contact characteristic layer 214 of solder projection 218 under condition.Therefore, even if without subsequently encapsulating (as shown in Figure 2), chip
310 are also securely engaged to outer characteristic layer 314.
It should be appreciated that IC chip 310 is directly connected to wiring layer 314 by soldered ball 318, avoid in wiring layer and
Through-hole column layer between IC chip.This avoids additional manufacturing steps, reduce manufacturing cost, and also make plug-in unit 324
Minimizing thickness.
A kind of manufacturing technology is to remove a part for surrounding dielectric 316 from embedded wiring layer using plasma,
It leaves embedded part wiring layer 315 and is protruded above dielectric 316 for being anchored purpose and partial wiring layer 313.Such as
Fruit wiring layer 314 is deposited in the sacrificial substrate of such as copper coin, then wiring layer and bottom via layer 312 can be by patterning
It is electroplated in photoresist, then lamination is manufactured as the dielectric 316 of prepreg or polymer sheet.Forming fabric 325
Later, sacrificial substrate can be removed, part dielectric 316 then can be removed using plasma to expose wiring layer 315
Outside 313.
It is possible to manufacture the other manner of part characteristic layer outstanding.For example, in Hull dimension thatch (Hurwitz) and Huang
(Huang) entitled " manufacturing method, multilayer electronic structure and structure (the Method of obtained according to the method
Fabrication, A Multilayer Electronic Structure and Structures in Accordance
With the Method) " United States Patent (USP) US 8,997,342 in be described in detail it is a kind of manufacture multi-layer supporting structure side
Method.In that patent, the release film (release higher than prepreg resin but less than solidified resin using hardness is discussed
film).The structure of Fig. 4 can be manufactured by improving the method for United States Patent (USP) US 8,997,342, such as by applying one
Rather than two prepregs and be only partially laminated wiring layer 314.
Especially it should be appreciated that by using in United States Patent (USP) US 8, double bond pad (double described in 997,342
Press pad) concept, dielectric thickness may remain in the range of ± 3 microns.
It will be recognized by those skilled in the art the contents that the present invention is not limited to above be specifically illustrating and describe.Moreover,
The scope of the present invention is defined by the following claims, including each technical characteristic described above combination and sub-portfolio and its
Changes and improvements, those skilled in the art are after reading preceding description it will be foreseen that such combination, changes and improvements.
In detail in the claims, term " comprising " and its variant such as "comprising", refer to cited component " containing "
It is included, but is generally not excluded for other assemblies.
Claims (16)
1. a kind of electronics support construction, including fabric, accessibke porosity layer and copper characteristic layer, wherein accessibke porosity layer and copper characteristic layer
Inside be laminated in the dielectric material, the outside of copper characteristic layer protrudes past the dielectric substance.
2. electronics support construction as described in claim 1 applies wherein protruding past the external of the copper characteristic layer of dielectric substance
It is covered with organic solderability preservative OSP.
3. electronics support construction as described in claim 1, wherein the outside for protruding past the copper characteristic layer of dielectric substance is prominent
Go out is more than at least 5 microns of dielectric substance.
4. electronics support construction as described in claim 1, wherein copper characteristic layer are partially submerged into the dielectric material, embedded deep
Degree is at least 5 microns.
5. electronics support construction as described in claim 1, wherein dielectric substance include polymer substrate.
6. electronics support construction as described in claim 1, wherein polymer substrate include being selected from thermosetting resin and thermoplasticity
The fluoropolymer resin of resin.
7. electronics support construction as claimed in claim 5, wherein dielectric substance further include glass fibre.
8. electronics support construction as claimed in claim 5, wherein dielectric substance further include inorganic filler.
9. electronics support construction as described in claim 1, wherein the terminal packet on the electronics support construction at least side
The attachment site engaged on improved trace is included, the site is included in the exposure of the copper feature structure in the outside of copper characteristic layer
Top surface and surface, as the site being conductively connected using solder.
10. the side surface of electronics support construction as described in claim 1, the wherein outside of copper characteristic layer protrudes from dielectric material
At least 5 microns of material is used for by solder in order to the attachment of IC chip.
11. electronics support construction as described in claim 1, including plug-in unit.
12. electronics support construction as described in claim 1, wherein fabric include terminal layer.
13. electronics support construction as described in claim 1, wherein fabric include at least one additional features layer.
14. electronics support construction as claimed in claim 13, wherein fabric include at least one additional vias layer.
15. a kind of method that IC chip is attached to electronics support construction as described in claim 1, including：If organic guarantor
If solder flux OSP exists, selectivity removes organic solderability preservative OSP；And chip is connected directly to by flip chip technology (fct)
The outside of outer characteristic layer so that the solder from chip terminal engages the side surface of the top surface and exposure of the outside of outer characteristic layer
A part, to realize strong anchoring.
16. method as claimed in claim 15, wherein being exposed by selective plasma ablation dielectric matrix outer
The outside of characteristic layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710021398.0A CN108305864B (en) | 2017-01-12 | 2017-01-12 | Terminal with a terminal body |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710021398.0A CN108305864B (en) | 2017-01-12 | 2017-01-12 | Terminal with a terminal body |
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| CN108305864B CN108305864B (en) | 2020-08-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112216656A (en) * | 2020-09-02 | 2021-01-12 | 珠海越亚半导体股份有限公司 | Cavity substrate with directional photoelectric transmission channel and manufacturing method thereof |
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| CN104183566A (en) * | 2014-01-24 | 2014-12-03 | 珠海越亚封装基板技术股份有限公司 | Substrate with protruding copper terminal columns |
| CN106328604A (en) * | 2015-07-01 | 2017-01-11 | 珠海越亚封装基板技术股份有限公司 | Chip package |
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| US20120247822A1 (en) * | 2011-03-28 | 2012-10-04 | Endicott Interconnect Technologies, Inc. | Coreless layer laminated chip carrier having system in package structure |
| CN103066050A (en) * | 2011-10-21 | 2013-04-24 | 台湾积体电路制造股份有限公司 | Semiconductor package having solder jointed region with controlled ag content |
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| CN108305864B (en) | 2020-08-18 |
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