JP4835629B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a structure of a chip carrier and a semiconductor device used when flip-chip mounting is performed using solder.

  In a conventional solder flip chip mounting type semiconductor device, in order to prevent the solder from spreading over the wiring layer of the wiring board when the IC chip is mounted, or excessive solder overflowing and shorting with the adjacent IC chip pad, An insulating resin layer called a solder resist is provided on the outermost layer. This solder resist covers most of the wiring layer, and only the pads necessary for mounting are exposed to the outside. For this reason, the pad is located inside the solder resist and at a position lower than the solder resist surface, and is separated from the pad of the IC chip.

  Therefore, solder bumps are formed on the pads of the chip carrier surrounded by the solder resist to facilitate bonding to the IC chip pads. If the solder bump has a constant opening radius and a resist thickness of the solder resist pad and a constant supply amount of solder, the height of the solder bump can be controlled and high bonding reliability can be maintained.

  However, since there are actually process variations, the heights of the solder bumps on the chip carrier vary. As a result, there is a portion that is not joined between the IC chip pad and the solder bump of the chip carrier. Since the solder resist is interposed between the wiring layer of the chip carrier and the IC chip pad, a gap is formed between the solder bump of the chip carrier and the IC chip pad, and the distance is increased. It is necessary to form bumps on the side pads using gold or solder.

  The bumps formed on the IC chip are required to have a certain level of accuracy, and the wet plating method that is currently widely used has a problem that the yield of the IC chip is remarkably reduced due to the additional bump formation step. is there.

  Further, since the IC chip is manufactured by making use of expensive equipment as compared with a printed circuit board or a chip carrier, the operating rate of the equipment greatly affects the manufacturing cost of the IC chip. For this reason, forming bumps on the IC chip reduces the yield of the IC chip, which is a very heavy burden for the semiconductor manufacturer. For this reason, if possible, the IC chip bump formation process should be omitted before shipping.

  Therefore, bumps are formed on the chip carrier rather than on the IC chip side, which contributes to improving the yield of IC chips, which are higher value-added components, and can be expected to have advantages such as a reduction in manufacturing risk due to process shortening. .

  However, the current chip carrier manufacturing method uses a method of stacking in layers from the inner layer to the outer layer, or press laminating to form a solder resist at the end. Protruding configuration was difficult.

  The present invention has been made in view of the above problems, and provides a chip carrier and a semiconductor device that can obtain high bonding reliability after mounting an IC chip by separating a wiring layer and a bump forming surface of the chip carrier. Objective.

In order to solve the above problem, in claim 1,
Provided is a method for manufacturing a semiconductor device, wherein a chip carrier obtained by a manufacturing method having the following steps is used to bond a chip chip pad and a bump of a chip carrier and to perform solder flip chip mounting.
(A) A step of forming a spacer layer (12) and an insulating substrate (13) on the metal plate (11).
(B) A step of forming openings (14) at predetermined positions of the spacer layer (12) and the insulating substrate (13).
(C) A step of forming a joining braze (15) having a predetermined thickness in the opening (14) by electrolytic plating.
(D) A step of forming an electrode pad (16) by electrolytic plating on the remaining part of the opening (14) in which the bonding braze (15) is formed.
(E) A step of forming a multilayer wiring composed of wiring layers (17) and (19) on the electrode pad (16) and the insulating substrate (13).
(F) A step of peeling and removing the metal plate (11) and the spacer layer (12) to form the chip carrier (10).

Since the chip carrier of the present invention has a solder layer and bumps made of electrode pads on one side of an insulating substrate and a wiring layer on the other side, the insulating substrate can have the role of a solder resist. The resist formation step can be omitted.
Further, when the bump is formed by the manufacturing method of the present invention, the thickness of the joining brazing can be formed with high accuracy, and the joining brazing (material composition and thickness) suitable for the mounting conditions can be set and the uniform height on the insulating substrate. Bumps can be formed.
Furthermore, a semiconductor device having high bonding reliability can be realized when solder flip chip mounting is performed using the chip carrier of the present invention.
Thereby, a semiconductor device with high mounting reliability can be provided, and excellent practical effects can be exhibited in the semiconductor package field.

Hereinafter, embodiments of the present invention will be described.
FIG. 1A is a schematic perspective view showing one embodiment of the chip carrier of the present invention, and FIG. 1B is a perspective view showing one embodiment of the chip carrier of the present invention shown in FIG. A sectional view taken along line A, FIGS. 2A to 2F are sectional views showing one embodiment of the chip carrier of the present invention in the order of steps, and FIG. 3A shows the chip carrier of the present invention. FIG. 3B is a schematic perspective view showing an embodiment of the semiconductor device of the present invention in which an IC chip is solder flip-chip mounted, and FIG. 3B is a schematic perspective view showing an embodiment of the semiconductor device of the present invention. A schematic configuration cross-sectional view cut along a line is shown.

As shown in FIGS. 1A and 1B, the chip carrier 10 of the present invention has a bump 21 made of an electrode pad 16 and a bonding braze 15 on one side of an insulating substrate 13, and a wiring layer 17 and a wiring layer on the other side. A multilayer wiring composed of 19 is formed.
Further, the IC chip 31 is solder flip-chip mounted on the chip carrier 10 to obtain the semiconductor device 30 of the present invention.
The bump 21 is formed in such a manner that a part of the electrode pad 16 is embedded in the insulating substrate 13, and this insulating substrate 13 also serves as a solder resist. Therefore, like the conventional chip carrier, the solder resist is provided around the bump. The height of the bump 21 from the surface of the insulating substrate 13 is determined by the thickness of the spacer layer and the height of the bonding brazing 16 described later in the manufacturing process. Therefore, even when the IC chip 31 is solder flip-chip mounted, high bonding reliability between the pads 32 of the IC chip 31 and the bumps 21 of the chip carrier 10 can be realized.

Hereinafter, a method for forming the chip carrier 10 of the present invention will be described.
First, the spacer layer 12 and the insulating substrate 13 are formed on the metal substrate 11 (see FIG. 2A).
Here, the metal substrate 11 can be used as long as it is a metal having conductivity, but here, a stainless steel plate is preferable in terms of the manufacturing process. The spacer layer 12 is used for forming the bonding braze 15 and the electrode pad 16 by electrolytic plating, and any resin having an insulating property can be used. However, the spacer layer 12 is finally peeled off and removed in a subsequent process. Therefore, a liquid photosensitive resist or dry film resist that has sufficient resistance to the electrolytic plating process and that can be easily peeled off is suitable. Further, since the thickness of the spacer layer 12 determines the height of the bump 21 from the surface of the insulating substrate 13, it is necessary to form a layer having no uniform thickness variation. Furthermore, the height of the bump 21 from the surface of the insulating substrate 13 is 5 to 200 μm, preferably 40 to 100 μm.

  The insulating substrate 13 becomes an insulating substrate of the chip carrier 10 and is required to have insulating properties, heat resistance and mechanical strength, and a polyimide film is preferable. The insulating substrate 13 may be used by curing a liquid resin in addition to the film. In this case, polyester, epoxy, acrylic, polyimide resin, and the like can be used, but polyimide resin is also preferable.

Next, the openings 14 for forming the bumps 21 including the electrode pads 16 and the bonding brazing 15 are formed in the spacer layer 12 and the insulating substrate 13 by excimer laser processing (see FIG. 2B).
The shape of the opening 14 is generally a columnar shape or a truncated cone shape.

Next, a soldering braze 15 is formed in the opening 14 by electrolytic plating using the metal substrate 11 as a plating electrode (see FIG. 2C).
The metal material of the bonding brazing 15 is preferably a metal that can be formed by a wet plating method and that can be melted at the heating temperature during mounting to complete the bonding with the IC chip pad.
Here, lead-tin solder is suitable.

Next, an electrode pad 16 is formed on the bonding brazing 15 of the opening 14 by electrolytic plating using the metal substrate 11 as a plating electrode (see FIG. 2D).
As the metal material of the electrode pad 16, copper and copper alloy having low electric resistance are most suitable. Furthermore, since the wiring layer is formed of copper metal, it is advantageous from the viewpoint of connection reliability with the wiring layer. The electrode pad 16 can be formed by a metal paste filling method by screen printing or a high-speed electroless plating method in addition to the electrolytic plating method.

Next, the wiring layer 17 is formed on the electrode pad 16 by an additive method or a semi-additive method. Further, an insulating layer 18 is formed, and a wiring layer 19 via-connected to the wiring layer 17 is formed on the insulating layer 18 by an additive method or a semi-additive method to form a two-layer multilayer wiring (FIG. 2 ( e)).
Here, two layers of multilayer wiring have been described, but there is no particular limitation, and a single layer or two or more layers of multilayer wiring can be set as appropriate.

  Next, the substrate on which the bonding braze 15, the electrode pad 16, the wiring layer 17 and the wiring layer 19 are formed is dipped in a special stripping solution, and the metal substrate 11 and the spacer layer 12 are stripped and removed, thereby insulating substrate 13. Thus, the chip carrier 10 of the present invention can be manufactured in which the bump 21 made of the bonding braze 15 and the electrode pad 16 is formed on one side of the substrate and the multilayer wiring made of the wiring layer 17 and the wiring layer 19 is formed on the other side (see FIG. 2 (f)).

  Furthermore, the semiconductor device 30 can be obtained by bonding the pads 32 of the IC chip 31 and the bumps 31 of the chip carrier 10 and performing solder flip chip mounting (see FIGS. 3A and 3B).

Hereinafter, the present invention will be described in detail by way of examples.
First, a spacer layer 12 is formed by laminating a dry film resist (H-K825: manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 25 μm on a metal substrate 11 made of a stainless steel plate having a thickness of 0.3 mm. Was used as an adhesive layer, and a 90 μm-thick polyimide film (Kapton: manufactured by DuPont) was laminated to form an insulating substrate 13.

  Next, an opening 14 having a truncated cone shape of 40 μmφ was formed at predetermined positions of the spacer layer 12 and the insulating substrate 13 on the metal substrate 11 using an excimer laser processing machine.

  Next, using the metal substrate 11 as a plating electrode, electrolytic solder plating was performed to form a joining braze 15 made of lead-tin solder having a thickness of 15 μm in the opening 14.

  Next, using the metal substrate 11 as a plating electrode, an electrode pad 16 having a thickness of 100 μm made of copper metal was formed on the bonding brazing 15 of the opening 14 by electrolytic copper plating made of a copper sulfate bath.

  Next, copper was sputtered on the insulating substrate 13 and the electrode pad 16 to form a thin film conductor layer having a thickness of about 3000 mm. Further, a copper conductor layer having a thickness of 15 μm is formed on the thin film conductor layer by electrolytic copper plating, and the conductor layer is patterned using a photolithography process and an etching process, and is electrically connected to the electrode pad 16. Layer 17 was formed.

  Next, an epoxy resin solution was applied onto the insulating substrate 13 and the wiring layer 17 by screen printing, dried and cured to form the insulating layer 18. Further, a via hole is formed at a predetermined position of the insulating layer 18 by laser processing, a copper conductor layer is formed on the via hole and the insulating layer 18, and a patterning process is performed using a photolithography process and an etching process to form the wiring layer 17. A via-connected wiring layer 19 was formed.

  Next, the substrate on which the bonding solder 15, the electrode pad 16, the wiring layer 17 and the wiring layer 19 are formed is dipped in a 10% caustic soda solution, and the metal substrate 11 and the spacer layer 12 are peeled off and removed, and the insulating substrate 13. The chip carrier 10 having the bump 21 made of the bonding braze 15 and the electrode pad 16 on one side and the multilayer wiring made of the wiring layer 17 and the wiring layer 19 on the other side could be produced.

  Since the chip carrier 10 can use the polyimide insulating substrate 13 as a solder resist for chip mounting, the solder resist forming step can be omitted.

Further, the pads 32 of the IC chip 31 and the bumps 31 of the chip carrier 10 were joined and solder flip-chip mounted to produce the semiconductor device 30.
As a result of flip-chip mounting of the IC chip using the chip carrier 10 of the present invention, an appropriate amount of solder is supplied to the pad 32 side of the IC chip 31, and the semiconductor device 30 of the present invention having high bonding reliability is obtained. It was.

(A) is a model perspective view which shows one Example of the semiconductor device board | substrate of this invention. (B) shows the schematic structure sectional drawing which cut | disconnected the typical perspective view of one Example of the semiconductor device board | substrate of this invention by the AA line. (A)-(f) is typical structure sectional drawing which shows the manufacturing process of one Example of the semiconductor device substrate of this invention in order of a process. FIG. 2A is a schematic perspective view showing an embodiment of a semiconductor device of the present invention in which an IC chip is solder flip-chip mounted using the semiconductor device substrate of the present invention. (B) is a schematic cross-sectional view of a schematic perspective view of an embodiment of the semiconductor device of the present invention, cut along line BB.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Chip carrier 11 ... Metal substrate 12 ... Spacer layer 13 ... Insulating substrate 14 ... Opening 15 ... Joining brazing 16 ... Electrode pad 17 ... Wiring layer 18 ... Insulating layer 19 ... Wiring layer 21 …… Bump 30 …… Semiconductor device 31 …… IC chip 32 …… Pad

Claims (1)

A method of manufacturing a semiconductor device, wherein a chip carrier obtained by a manufacturing method including the following steps is used to bond a chip chip pad and a bump of a chip carrier and to perform solder flip chip mounting.
(A) A step of forming a spacer layer (12) and an insulating substrate (13) on the metal plate (11).
(B) A step of forming openings (14) at predetermined positions of the spacer layer (12) and the insulating substrate (13).
(C) A step of forming a joining braze (15) having a predetermined thickness in the opening (14) by electrolytic plating.
(D) A step of forming an electrode pad (16) by electrolytic plating on the remaining part of the opening (14) in which the bonding braze (15) is formed.
(E) A step of forming a multilayer wiring composed of wiring layers (17) and (19) on the electrode pad (16) and the insulating substrate (13).
(F) A step of peeling and removing the metal plate (11) and the spacer layer (12) to form the chip carrier (10).

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