JP2006222257A - Wiring substrate, manufacturing method thereof, and semiconductor device using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the strength and the connective reliability, etc. of each external connection terminal itself of a wiring substrate, and to perform the available shortening of its wiring distances for the improvement of its noise resistance. <P>SOLUTION: The wiring substrate 1 has a multilayer wiring structure 3 comprising a plurality of laminated buildup layers 2 having an insulation layer 6 and a wiring layer 7 including vias 9 formed in the insulation layer 6. The multilayer wiring structure 3 is so created as to form and laminate successively the buildup layers 2 on a metal plate 10. Each external connection terminal 4 is formed by etching and removing selectively the metal plate 10. Therefore, each external connection terminal 4 is so formed as to be integrated adhesively with the wiring layer 7 of the multilayer wiring structure portion 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring substrate applied to a package substrate or the like of a semiconductor element, a manufacturing method thereof, and a semiconductor device using the wiring substrate.

  In recent years, as a high-speed, multi-pin semiconductor package, a BGA package in which a semiconductor element is flip-chip mounted on one main surface of a wiring board and solder bumps or the like are formed as external connection terminals on the other main surface of the wiring board. It is popular. In addition, since a wiring board applied to such a BGA package is required to have high-density wiring, a build-up structure in which an insulating layer and a wiring layer are laminated on both sides or one side of a core board is formed. Multi-layer wiring boards (build-up boards) that have been used.

  By the way, the operating frequency exceeds 1 GHz for high-speed operation of the semiconductor element, and the compensation for reducing the operating voltage for reducing power consumption tends to reduce the noise resistance of the semiconductor package. In order to increase noise resistance, it is important to make the loop inductance as small as possible. For this purpose, it is effective to shorten the distance from the semiconductor element to the external connection terminal for the power supply. However, since the core board is indispensable for the conventional build-up board, the wiring distance is reduced by reducing the thickness of the whole board. It is difficult to shorten the length.

  Further, a package to which solder balls are applied as external connection terminals has the following problems due to the solder balls. That is, the solder balls are generally formed by applying Ni / Au plating on the electrode pads of the multilayer wiring board to prevent oxidation and then placing the solder balls on the electrode pads and reflowing them. Such a solder ball has a problem that the phosphorous component mixed in a minute amount during Ni plating is deposited on the Au plating surface, resulting in weak bonding with the solder and, in some cases, breaking from the bonding interface during use. is there.

  Furthermore, in a high-speed and large-power consumption LSI, the package must withstand the heat generated by the device itself or the burn-in overheating during the burn-in test. The temperature varies depending on burn-in conditions, device performance, and quality assurance conditions, but is generally around 100 to 150 ° C. The melting point of Sn—Pb eutectic solder is 183 ° C., but creep deformation starts near 150 ° C. under long-time load conditions. For this reason, there is a risk of deformation of the solder bump during the long-term heat resistance test. In addition, in a test at a high temperature, as a result of the test probe repeatedly contacting the solder bumps, there is a problem that the solder residue accumulates and complicated cleaning is required.

A BGA package circuit board is proposed in which a metal plate is attached to a multilayer printed circuit board and a metal terminal (bump) is formed by attaching a metal plate to the package board to which solder balls are applied as such external connection terminals. (See, for example, Patent Document 1). Here, a multilayer printed circuit board in which copper pattern layers and prepreg layers are alternately laminated and bonded is used. Further, a metal plate is attached to such a multilayer printed circuit board by thermocompression bonding, and a metal terminal is formed by etching such a metal plate.
Japanese Patent Laid-Open No. 11-16933

  As described above, the package board in which solder bumps are formed as external connection terminals on the conventional build-up board is effective for improving noise resistance due to the thickness of the build-up board where the core board is indispensable. Has a problem that it is difficult to shorten. Furthermore, due to the solder bump as the external connection terminal, there is a problem that the solder pad is likely to break from the joint interface between the electrode pad and the solder bump, and there is a risk that the solder bump is deformed during the burn-in test. Have a problem.

  On the other hand, a conventional package substrate in which metal bumps are formed by etching a metal plate is a multilayer printed circuit board in which a copper pattern layer and a prepreg layer are alternately laminated and pressure-bonded on a circuit board to which the metal plate is attached, so-called multilayer copper-clad. Since a laminated board is used, it is difficult to reduce the thickness more than the build-up substrate described above, and it is technically difficult to reduce the wiring distance in order to improve noise resistance. Furthermore, since the metal plates are attached to the multilayer printed circuit board by thermocompression bonding, the reliability of these joints is low, and there is a problem that the metal pump is likely to be peeled off due to thermal stress applied during practical use. Yes.

  The present invention has been made to cope with such a problem, and it has been possible to increase the strength and connection reliability of the external connection terminal itself and to shorten the wiring distance effective in improving noise resistance. It is an object of the present invention to provide a wiring board, a manufacturing method thereof, and a semiconductor device using such a wiring board.

  A wiring board according to an aspect of the present invention includes a multilayer wiring structure portion including a plurality of build-up layers having an insulating layer and a wiring layer including a via formed in the insulating layer, and the multilayer wiring structure portion And an external connection terminal made of a metal columnar body disposed on one main surface side and formed in close contact with the wiring layer.

  In the method for manufacturing a wiring board according to one aspect of the present invention, a plurality of buildup layers having an insulating layer and a wiring layer including a via formed in the insulating layer are sequentially formed on the surface of the metal plate. A step of producing a wiring structure, and at least a part of the metal plate excluding a portion to be the external connection terminal, so that a part of the metal plate becomes a plurality of columnar external connection terminals. And removing the connection terminals so as to be electrically independent from each other to form the plurality of external connection terminals.

  A semiconductor device according to one aspect of the present invention is mounted on the multilayer wiring structure portion of the wiring board according to the above-described aspect of the present invention and electrically connected to the wiring layer. And a semiconductor element.

  According to one embodiment of the present invention, since the metal columnar body is applied to the external connection terminal, the strength, connection reliability, and the like of the external connection terminal can be increased. Furthermore, since the multilayer wiring structure is composed of only the buildup layer, it is possible to shorten the wiring distance effective for improving noise resistance. By applying such a wiring board, the reliability, characteristics, and the like of a semiconductor device configured by mounting a semiconductor element thereon can be improved.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described based on drawing below, those drawings are provided for illustration and this invention is not limited to those drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a wiring board according to an embodiment of the present invention. A wiring board 1 shown in FIG. 1 includes a multilayer wiring structure portion 3 formed by laminating a plurality of buildup layers 2, and a metal columnar shape arranged on one main surface (lower surface) 3a side of the multilayer wiring structure portion 3. And an external connection terminal group 5 having a plurality of external connection terminals 4 made of a body. Each build-up layer 2 has an insulating layer 6 and a wiring layer 7. The wiring layer 7 has a conductor layer 8 such as a metal plating layer formed on the insulating layer 6 and a via 9 formed in the insulating layer 6 so as to connect each layer 8. A wiring pattern is formed.

  The build-up layer 2 is set in the number of layers according to the number of signal wires, the wiring pattern, etc., and the multilayer wiring structure unit 3 is configured by sequentially stacking the build-up layers 2 having such a number of layers. . On the lower surface 3 a side of the multilayer wiring structure portion 3, external connection terminals 4 made of metal columnar bodies connected to the wiring layer 7 are arranged. Although FIG. 1 shows a structure in which three buildup layers 2 are laminated, the number of buildup layers 2 is not limited to this, and depends on the number of signal wirings, wiring patterns, etc. as described above. Can be set appropriately.

  A specific structure of the above-described wiring board 1 including its manufacturing method will be described with reference to FIG. First, as shown in FIG. 2A, a metal plate 10 that is a material for forming the columnar external connection terminals 4 is prepared. Although it will not specifically limit if the metal plate 10 is an electroconductive metal, It is preferable to use a copper plate in consideration of electroconductivity etc. The outer shape of the metal plate 10 corresponds to the overall shape of the wiring board 1. The thickness of the metal plate 10 is selected according to the height of the external connection terminal 4. As a guideline, the height of the external connection terminal 4 is 50% of the formation pitch. The formation pitch of the external connection terminals 4 depends on the progress of mounting technology, but the current state is 0.8 to 1.0 mm. Therefore, it is appropriate that the thickness of the metal plate 10 is 0.4 to 0.5 mm.

  The first build-up layer 2A is formed on the metal plate 10 as described above. Here, for example, a semi-additive method or a full additive method can be applied to the formation process of the build-up layer 2. First, after forming the insulating layer 6 on the metal plate 10 using an insulating resin, the via hole 11 is formed in the insulating layer 6 by, for example, laser processing. Next, the wiring layer 7 is formed on the surface of the insulating layer 6 including the inside of the via hole 11 by applying electroless plating or electrolytic plating. Although various metal platings can be applied to the wiring layer 7, it is preferable to apply the same metal material as that of the metal plate 10. For example, when a copper plate is used for the metal plate 10 to be the external connection terminal 4, the wiring layer 7 is preferably formed by copper plating.

  The formation process of the wiring layer 7 to which the semi-additive method is applied is as follows. First, for example, electroless copper plating is performed on the insulating layer 6 including the copper plate 10 in the via hole 11, and then the shape corresponding to the wiring pattern ( A resist having a shape covering a portion excluding the wiring pattern portion is formed. Next, electrolytic copper plating is performed using the electroless copper plating layer as a seed layer. After removing the resist, the wiring layer 7 having a desired pattern is obtained by removing the electroless copper plating layer attached to the portion other than the wiring pattern portion by etching. At this time, a conductor layer 8 made of an electroless copper plating layer / electrolytic copper plating layer is formed on the insulating layer 6, and at the same time, a via 9 made of a similar copper plating layer is formed in the via hole 11.

  The via 9 formed by the copper plating layer is formed by directly depositing copper on the copper plate (metal plate) 10 to be the external connection terminal 4. Therefore, the via 9 and the copper plate 10 are integrated in a metallographic manner. . As a result, it is possible to obtain a state in which the external connection terminals 4 formed by etching the copper plate 10 in a process described later are integrally adhered to the vias 9. That is, the adhesion strength between the external connection terminal 4 and the via 9 can be significantly increased as compared with the conventional thermocompression bonding or the like. As described above, in order to increase the adhesion strength between the external connection terminals 4 and the vias 9, it is preferable to apply the same metal material as the metal plate 10 used as the external connection terminals 4 to the metal plating for forming the wiring layer 7. .

  Next, as shown in FIG. 2B, the second and third buildup layers 2B and 2C are sequentially stacked on the first buildup layer 2A. The formation process of these build-up layers 2B and 2C is the same as that of the first layer. Formation of insulating layer, formation of via hole, electroless plating treatment, formation of resist, electrolytic plating treatment, removal of resist, electroless plating layer It is carried out by repeating each process such as removal according to the number of layers. The third build-up layer 2 </ b> C has an electrode pad 12 and the surface thereof is protected by an insulating layer 13. After forming the multilayer wiring structure 3 in this way, a resist 14 is formed on the lower surface side of the metal plate 10 according to the formation pattern of the external connection terminals 4.

  The resist 14 is formed so as to cover the portion of the metal plate 10 so that the portion of the wiring layer 7 formed in close contact with the via 9 becomes the columnar external connection terminal 4. Thereafter, as shown in FIG. 2C, the metal plate 10 is selectively removed by etching using a resist 14, thereby forming the external connection terminals 4 that are in close contact with the vias 9, respectively. The etching process of the metal plate 10 is performed so that the plurality of external connection terminals 4 are electrically independent from each other. Thus, the target wiring board 1 is obtained by producing the external connection terminal group 5 having the plurality of external connection terminals 4 made of metal columnar bodies.

  The metal columnar body formed by selectively etching the metal plate 10 may be used as the external connection terminal 4 as it is. However, when a semiconductor package manufactured by mounting a semiconductor element or the like on the wiring board 1 is mounted on a mother board or the like, the external connection terminal made of a metal columnar body is used to improve the connection state with the electrodes on the mother board side. 4 is preferably covered with at least one metal film selected from Sb—Pb alloy, Sn—Ag—Cu alloy, Sn—Sb alloy, Sn—Ag alloy, and Ni / Au laminated film. . FIG. 1 shows a state in which a metal film 15 is formed on the surface of an external connection terminal 4 made of a metal columnar body.

  Here, FIG. 1 and FIG. 2 show a state in which all portions except the external connection terminal 4 of the metal plate 10 are removed by etching. However, if the external connection terminal 4 becomes electrically independent, the external connection terminal It is also possible to leave a part of the metal plate 10 around 4. That is, the wiring board 16 shown in FIG. 3 and FIG. 4 is in a state where the entire plane of the metal plate 10 is electrically separated from the external connection terminals 4 in addition to the external connection terminals 4 and is higher than the external connection terminals 4 Is left to be lower. That is, the external connection terminals 4 protrude in an electrically independent state, and a part of the metal plate 10 remains around the external connection terminals 4.

  Thus, the rigidity of the wiring board 1 can be increased by leaving a part of the metal plate 10 within a range in which the separated state of the external connection terminals 4 and the protruding state as the terminals are not impaired. That is, as shown in FIG. 1 and FIG. 2, when all the portions of the metal plate 10 excluding the external connection terminals 4 are removed by etching, the rigidity of the wiring board 1 is maintained only by the multilayer wiring structure portion 3. There is a concern about insufficient rigidity when the substrate size is increased. On the other hand, the rigidity of the wiring board 16 can be maintained by leaving the planar shape of the metal plate 10 as shown in FIGS. Such a state in which the planar shape of the metal plate 10 is left can be obtained by performing two-step etching on the metal plate 10.

  According to the manufacturing process of the wiring boards 1 and 16 described above, since the multilayer wiring structure portion 3 having the plurality of buildup layers 2 is first formed on the metal plate 10 to be the external connection terminals 4, the conventional buildup is performed. A plurality of buildup layers 2 can be satisfactorily stacked without using a core substrate like a substrate. Since the thickness of such a multilayer wiring structure 3 depends only on the number of stacked build-up layers 2, it can be made thinner than a conventional build-up substrate having a core substrate. This is directly connected to the reduction of the wiring distance by the multilayer wiring structure unit 3, so that, for example, the loop inductance of the power supply wiring can be reduced and the noise resistance can be increased.

  Furthermore, since the external connection terminals 4 are formed by selectively etching the metal plate 10, the external connection terminals 4 can be formed of metal columnar bodies that are superior in load resistance characteristics compared to conventional solder bumps. As a result, it is possible to suppress a connection failure or a decrease in reliability due to deformation or breakage of the external connection terminal 4 when a semiconductor package using the wiring boards 1 and 16 is mounted on a mother board or the like or in a burn-in test. It becomes. In addition, since the external connection terminals 4 and the wiring layer 7 made of metal pillars are integrated by subjecting the metal plate 10 to direct plating, the adhesion strength can be greatly increased compared to conventional thermocompression bonding or the like. it can. Thereby, it is possible to improve the reliability of the joint portion of the external connection terminal 4 itself and the connection portion using the external connection terminal 4. Such wiring boards 1 and 16 are suitable for a package substrate of a semiconductor element.

  Next, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows a semiconductor device 20 including the wiring substrate 1 shown in FIG. 1 as a package substrate. FIG. 6 shows a semiconductor device 20 having the wiring substrate 16 shown in FIG. 3 as a package substrate. A semiconductor element 21 is flip-chip connected on the element mounting surface (the upper surface 3a of the multilayer wiring structure 3) of the package substrates 1 and 16 described above, and a semiconductor device (semiconductor package) 20 is constituted by these. . The connection of the semiconductor element 21 is not limited to the flip chip connection, but the semiconductor device 20 in which the semiconductor element 21 is flip chip connected is particularly suitable.

  The package substrates 1 and 16 and the semiconductor element 21 are electrically and mechanically connected by metal bumps 22 arranged between the electrode pads 12 of the package substrates 1 and 16 and the electrode terminals of the semiconductor element 21 not shown. Has been. The power supply terminal of the semiconductor element 21 is connected to the external connection terminal 4 through a wiring layer having a stacked via structure in the package substrates 1 and 16, for example. Resin 23 is injected and solidified as an underfill agent into the gap between the package substrates 1 and 16 and the semiconductor element 21. According to such a semiconductor device 20, since the distance of the power supply wiring depends only on the thickness of the multilayer wiring structure portion 3, it is possible to shorten the wiring distance and thereby reduce the inductance.

  The present invention is not limited to the above-described embodiment, and various wiring boards having a multilayer wiring structure portion to which an external connection terminal and a buildup layer made of a metal columnar body are applied, and a semiconductor element mounted thereon. The present invention can be applied to various semiconductor devices. Such wiring boards and semiconductor devices are also included in the present invention. The embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

It is sectional drawing which shows schematic structure of the wiring board by one Embodiment of this invention. It is sectional drawing which shows the principal part manufacturing process of the wiring board shown in FIG. It is sectional drawing which shows schematic structure of the modification of the wiring board shown in FIG. It is a perspective view which expands and shows the principal part of the wiring board shown in FIG. It is sectional drawing which shows the structure of the semiconductor device by one Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device by other embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,16 ... Wiring board, 2 ... Build-up layer, 3 ... Multilayer wiring structure part, 4 ... External connection terminal which consists of metal columnar body, 6 ... Insulating layer, 7 ... Wiring layer, 9 ... Via, 10 ... Metal plate, DESCRIPTION OF SYMBOLS 15 ... Metal film, 20 ... Semiconductor device, 21 ... Semiconductor element.

Claims (5)

A multilayer wiring structure comprising a plurality of build-up layers having an insulating layer and a wiring layer including a via formed in the insulating layer;
An external connection terminal comprising a metal columnar body disposed on one main surface side of the multilayer wiring structure portion and formed in close contact with the wiring layer. The wiring board according to claim 1,
The wiring layer and the external connection terminal are made of Cu or Cu alloy, and the surface of the external connection terminal is formed of Sb—Pb alloy, Sn—Ag—Cu alloy, Sn—Sb alloy, Sn—Ag alloy, and Ni / A wiring board, wherein at least one metal film selected from an Au laminated film is formed. Forming a multilayer wiring structure by sequentially forming a plurality of buildup layers having an insulating layer and a wiring layer including a via formed in the insulating layer on the surface of the metal plate;
The plurality of external connection terminals are electrically independent from each other at least a part of the metal plate excluding the portion to be the external connection terminal so that a part of the metal plate becomes a plurality of columnar external connection terminals. And a step of forming the plurality of external connection terminals by removing as described above. In the manufacturing method of the wiring board of Claim 3,
The step of forming the external connection terminal includes the metal plate such that the plurality of external connection terminals protrude in an electrically independent state and a part of the metal plate remains around the external connection terminal. A method for manufacturing a wiring board, comprising: partially removing the substrate. The wiring board according to claim 1 or 2,
A semiconductor device comprising: a semiconductor element mounted on the multilayer wiring structure portion of the wiring board and electrically connected to the wiring layer.

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