JP2004327940A - Wiring board and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board exhibiting excellent electrical characteristics and connection reliability and having a structure advantageous to compaction. <P>SOLUTION: The wiring board 11 comprises a substrate 12, a first major surface side connection terminal 17, and a second major surface side connection terminal 18. The first major surface side connection terminal 17 has such a structure as an electroless gold plating layer 26 is formed on a copper layer 23 through an electrolytic plating layer 29 and is solder jointed to the connection terminal 76 of an electronic component 15 mounted on the first major surface 13 side of the substrate 12. The second major surface side connection terminal 18 has such a structure as an electroless gold plating layer 30 is formed directly on a copper layer 24 and has a larger area than the first major surface side connection terminal 17 and is solder jointed to the connection terminal of another substrate 61 supporting the second major surface 14 of the substrate 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board and a method of manufacturing the same, and more particularly to a wiring board having a pad structure on both surfaces of the wiring board and a method of manufacturing the same.
[0002]
[Prior art]
Conventionally, a semiconductor package having a structure in which an IC chip, an LSI chip, or the like is mounted on a wiring board is well known. Usually, a plurality of flip-chip pads are arranged on the first main surface of the wiring board in the semiconductor package in order to connect with the LSI chip. On the second main surface side, for example, a plurality of pads for BGA (ball grid array) are arranged for connection with the motherboard. These two types of pads are electrically connected to each other via an internal conductor circuit provided in the wiring board. The internal conductor circuit is generally formed using copper which is a good conductor, and the main body portion of each of the above two types of pads is formed as a copper plating layer. However, since these pads come into contact with the solder at the time of connection, their surfaces are plated with gold to improve the bonding strength with the solder and the wettability.
[0003]
By the way, the copper plating layer forming the main body of the pad is not so good in corrosion resistance. If the surface is covered with an oxide layer or the like, the adhesion between the copper plating layer and the gold plating layer deteriorates. there is a possibility. Therefore, a pad structure in which a nickel plating layer having good adhesion to copper is formed after a copper plating layer is formed, and a gold plating layer is formed on the nickel plating layer is widely used. As a method for forming a nickel plating layer, two types of an electrolytic nickel plating method and an electroless nickel plating method are conventionally known (for example, see Patent Documents 1 and 2).
[0004]
[Patent Document 1]
JP-A-2002-4098 (FIG. 4, etc.)
[0005]
[Patent Document 2]
JP 2001-339140 A (FIG. 2, etc.)
[0006]
[Problems to be solved by the invention]
According to the electroless nickel plating method, a nickel plating layer can be formed relatively easily even on a plurality of pads electrically insulated from each other. However, since a phosphate compound such as sodium hypophosphite is added as a reducing agent to a generally used electroless nickel plating bath, a relatively large amount of 4 to 8% by mass is contained in the nickel plating layer. Phosphorus is inevitably included. And when the solder which consists of a Sn-Pb alloy is made to contact on a gold plating layer, the solder which melted the gold plating layer may contact the base nickel plating layer. At this time, if a large amount of phosphorus is contained in the nickel plating layer, a brittle layer will be formed at the solder interface. The BGA pad has a larger area than the flip chip pad, and also has a larger area in contact with the motherboard, so if heating and cooling are performed when connecting the motherboard, thermal stress will be concentrated especially on the connection part of the BGA pad. Cheap. Accordingly, breakage or the like occurs at the connection portion, and disconnection failure is likely to occur, which is one of the causes of lowering the connection reliability of the wiring board.
[0007]
In this respect, the electrolytic nickel plating method has an advantage that a nickel plating layer having good adhesion can be obtained because a reducing agent containing phosphorus is not used. Therefore, it is considered that the above two types of pads may be formed by the electrolytic nickel plating method. However, in the conventional pad forming process using electrolytic nickel plating, it is necessary to form a complicated and complicated conductive path for plating (so-called plating tie bar) connected to the pad on the surface of the insulating layer on which the pad is formed. There is. In this method, it is necessary to secure a space between the pads for inserting the plating tie bar, so the pad arrangement interval cannot be reduced as desired, which tends to cause an increase in the board area, and there are very few design restrictions. There is a problem that it becomes larger. Further, the plating tie bar eventually remains on the substrate as an unnecessary conductive path having an electrically open end, which is attached to the pad. Then, the portion serves as a noise collection source, deteriorating the noise resistance of the substrate, or causing impedance mismatch of the transmission path including the pad. Therefore, there is a disadvantage that it is difficult to realize a semiconductor package having excellent electric characteristics.
[0008]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board having excellent electrical characteristics and connection reliability and having a structure advantageous for downsizing. Another object of the present invention is to provide a preferable manufacturing method capable of relatively easily obtaining the above excellent wiring board.
[0009]
Means for Solving the Problems, Functions and Effects
Means for solving the above problems include a substantially plate-shaped substrate having a first main surface and a second main surface, and an electroless gold plating layer formed on a copper layer via an electroless nickel plating layer. A first main surface side connection terminal for solder connection with a connection terminal of an electronic component mounted on the first main surface side of the substrate, and an electroless gold plating layer directly on the copper layer. A second main surface having a formed structure, having a larger area than the first main surface side connection terminal, and being connected by soldering to a connection terminal of another substrate supporting the second main surface side of the substrate; There is a wiring board provided with a side connection terminal.
[0010]
Therefore, in the wiring board of the present invention, for the second main surface side connection terminal having a larger area than the first main surface side connection terminal, the nickel plating layer is not interposed between the copper layer and the gold plating layer. A structure in which an electroless gold plating layer is directly formed on a copper layer is adopted. For this reason, the disadvantage of interposing an electroless nickel plating layer between the copper layer and the electroless gold plating layer is eliminated. That is, the generation of a fragile layer at the solder interface due to a large amount of phosphorus contained in the electroless nickel plating layer is prevented beforehand, and the occurrence of disconnection failure due to breakage of the connection portion is prevented. Therefore, the connection reliability of the wiring board can be improved.
[0011]
On the other hand, the first main surface side connection terminal has a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer, so that the bonding strength with solder and wettability are improved. In addition, since the electroless nickel plating layer functions as a barrier layer, the adhesion between the copper layer and the electroless gold plating layer is also improved. Since the structure has the electroless nickel plating layer, generation of a fragile layer at the solder interface is a concern, but the first main surface side connection terminal has a smaller area than the second main surface side connection terminal. In addition, the area in contact with the electronic component is not so large. For this reason, even if heating and cooling are performed at the time of connection, the thermal stress concentrated on the connection portion of the first main surface side connection terminal is not so large as the thermal stress concentrated on the connection portion of the second main surface side connection terminal. The rate of occurrence of breakage and the like at the connection portion of the main surface side connection terminal is low in the first place. That is, the advantage of the structure is larger than the disadvantage of the structure in which the electroless gold plating layer is formed on the copper layer via the electroless nickel plating layer. Therefore, as a result, the solder connection with the connection terminal of the electronic component can be reliably performed, and the connection reliability of the wiring board can be improved.
[0012]
Further, since the wiring board of the present invention does not have the electrolytic nickel plating layer, unnecessary conductive paths whose terminals are electrically open such as plating tie bars are excluded from the wiring board. As a result, it is possible to effectively prevent the noise resistance of the board from deteriorating due to unnecessary conductive paths and to prevent impedance mismatching of the transmission path, and to improve the electrical characteristics of the wiring board. Since no unnecessary conductive path is provided, the space between the connection terminals can be reduced, and the external dimensions of the substrate can be reduced. In addition, since the wiring layout is less likely to be complicated, design restrictions are reduced, and the wiring board structure is easy to manufacture.
[0013]
The wiring board of the present invention includes a substantially plate-shaped substrate having a first main surface and a second main surface, and the substrate includes an insulating layer and a conductor. Examples of the material forming the main portion of the substrate include resin, ceramic, and metal. These materials are appropriately selected in consideration of cost, ease of drilling, conductivity and the like.
[0014]
Suitable resins used for the substrate include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), and PPE resin (polyphenylene ether resin). In addition, a composite material of these resins and organic fibers such as glass fiber (glass woven fabric or glass nonwoven fabric) or polyamide fiber may be used. Alternatively, a resin-resin composite material in which a thermosetting resin such as an epoxy resin is impregnated into a three-dimensional network-like fluororesin substrate such as continuous porous PTFE may be used.
[0015]
Suitable ceramics used for the substrate include, for example, low temperature firing materials such as alumina, beryllia, aluminum nitride, boron nitride, silicon carbide, glass ceramics, crystallized glass, and the like.
[0016]
Suitable metals used for the substrate include, for example, copper plates and copper alloy plates, simple metals other than copper, and metal alloys other than copper. Examples of the copper alloy include aluminum bronze (Cu-Al system), phosphor bronze (Cu-P system), brass (Cu-Zn system), cupronickel (Cu-Ni system), and the like. Metals other than copper include aluminum, iron, chromium, nickel, molybdenum, and the like. As alloys other than copper, stainless steel (iron alloys such as Fe-Cr-based and Fe-Cr-Ni-based), amber (Fe-Ni-based alloy, 36% Ni), so-called 42 alloy (Fe-Ni-based alloy, 42 % Ni), so-called 50 alloy (Fe-Ni alloy, 50% Ni), nickel alloy (Ni-P, Ni-B, Ni-Cu-P), cobalt alloy (Co-P, Co- B-based, Co-Ni-P-based), tin alloy (Sn-Pb-based, Sn-Pb-Pd-based) and the like.
[0017]
Conductors (such as wiring patterns and via conductors) are provided on inner and outer layers of the substrate, and the conductors are separated from each other by the insulating layer. Such a conductor may be disposed on only one layer on one side of the substrate, or may be disposed on two or more layers on one side of the substrate. In this case, a build-up layer formed by alternately laminating a conductor and a resin insulating layer may be formed on one side surface of the substrate.
[0018]
The conductor is mainly made of copper, and is formed by a known method such as a subtractive method, a semi-additive method, and a full-additive method. Specifically, for example, a technique such as copper foil etching, electroless copper plating or electrolytic copper plating is applied. Note that it is also possible to form a conductor by etching after forming a thin film by a method such as sputtering or CVD, or to form a conductor by printing a conductive paste or the like.
[0019]
A solder resist that covers at least one of the first main surface and the second main surface of the substrate to protect the conductor in the outer layer may be disposed on the outermost layer of the substrate. As such a solder resist, for example, a thermosetting resin is preferable. The solder resist can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the thermosetting resin include an EP resin (epoxy resin), a PI resin (polyimide resin), a BT resin (bismaleimide-triazine resin), a phenol resin, a xylene resin, a polyester resin, and a silicon resin.
[0020]
The wiring board includes a first main surface side connection terminal for solder connection with a connection terminal of an electronic component mounted on the first main surface side of the substrate.
[0021]
Preferred examples of the electronic component include a semiconductor integrated circuit chip having a plurality of electrodes (connection terminals) on the back surface. In this case, the first main surface side connection terminals are preferably a plurality of flip chip pads for solder connection with connection terminals of a semiconductor integrated circuit chip as the electronic component. The electronic component may be a chip component (for example, a chip transistor, a chip diode, a chip resistor, a chip capacitor, a chip coil, and the like), and may be an active component or a passive component.
[0022]
When the first main surface side connection terminal is a flip chip pad, the pad is usually adapted to the number, position, size (area), connection terminal pitch and the like of the connection terminals of the semiconductor integrated circuit chip. It is formed. Usually, flip-chip pads are arranged in a lattice or in a staggered manner in an electronic component mounting region (in a so-called die area) substantially at the center on the first main surface of the substrate. When the wiring board is a so-called multi-piece wiring board, such electronic component mounting areas may be set at a plurality of locations on the first main surface of the board.
[0023]
The first main surface side connection terminal basically has a structure in which three kinds of different metals are laminated. Specifically, an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer. It has a formed structure. The copper layer is a so-called main body portion of the first main surface side connection terminal, and is formed thicker than the electroless nickel plating layer and the electroless plating layer. The electroless nickel plating layer serves to prevent oxidation of the copper layer surface and also serves as a barrier layer separating the copper layer and the electroless gold plating layer. Such an electroless nickel plating layer is preferably formed to a thickness of 1.00 μm or more and 10.00 μm or less. The electroless gold plating layer is preferably formed to be thinner than the electroless nickel plating layer, specifically, to have a thickness of 0.01 μm or more and 1.00 μm or less.
[0024]
The wiring board further includes a second main surface side connection terminal for solder connection with a connection terminal of another substrate supporting the second main surface side of the substrate. The second main surface side connection terminal may be a plurality of ball grid array pads (BGA pads) for connecting to the connection terminal of the another substrate via solder balls. The second main surface side connection terminal may be a pad for a pin grid array (PGA pad) to which a pin is attached, or a pad for a land grid array (LGA pad) to which a ball or a pin is not particularly attached. Good.
[0025]
When the second main surface side connection terminal is a pad for a ball grid array, the pad is usually the number, position, size (area), connection between connection terminals of another substrate such as a motherboard or the like. It is formed according to the pitch and the like. Therefore, the area of the second main surface side connection terminals and the pitch between the connection terminals are formed to be considerably larger than the area of the first main surface side connection terminals and the pitch between the connection terminals. Furthermore, the occupancy of the second main surface side connection terminal on the second main surface (that is, (total area of second main surface side connection terminal / area of second main surface) × 100 (%)) is equal to the first. The occupancy of the first main surface side connection terminals on the main surface (that is, (total area of first main surface side connection terminals / area of first main surface) × 100 (%)) is considerably large. I have. The second main surface side connection terminals are usually arranged in a row at the outer peripheral portion of the second main surface, or are arranged in a lattice or staggered pattern over substantially the entire area of the second main surface including the outer peripheral portion. . Incidentally, the second main surface side connection terminal having a relatively large area, the pitch between the connection terminals, and the surface occupancy is relatively smaller than the first main surface side connection terminal having a relatively small area, the pitch between the connection terminals, and the surface occupancy. In comparison, it is more susceptible to thermal stress during heating and cooling.
[0026]
The second main surface side connection terminal basically has a structure in which two kinds of different metals are laminated, and specifically has a structure in which an electroless gold plating layer is directly formed on a copper layer. I have. The copper layer is a so-called main body portion of the second main surface side connection terminal, and is formed thicker than the electroless gold plating layer. Such an electroless gold plating layer is preferably formed with a thickness of 0.01 μm or more and 1.00 μm or less.
[0027]
The wiring board includes an internal conductor circuit for conducting the first main surface side connection terminal and the second main surface side connection terminal. The internal conductor circuit is provided inside the substrate as described above, and specifically includes a wiring pattern, a via conductor, and the like.
[0028]
When the first main surface side connection terminal is a flip chip pad, some of the plurality of flip chip pads may be electrically isolated floating pads that are not electrically connected to the internal conductor circuit. . For convenience of description, a pad that is electrically connected to the internal conductor circuit and is not electrically isolated is referred to as a non-floating pad.
[0029]
In circuit design, only non-floating pads are important, but the pads alone may not provide a sufficient number or arrangement to complete a grid arrangement suitable for flip-chip connection. There is a possibility that the pad is unevenly arranged in the region. In this case, when the semiconductor integrated circuit chip is flip-chip connected, the load distribution becomes non-uniform, which may cause a connection failure or the like. Therefore, it can be said that it is desirable to compensate for the grid-like arrangement of pads that cannot be completed only by the non-floating pads with the floating pads as described above in order to realize a stable connection state.
[0030]
Therefore, it is preferable that the floating pad also has a structure in which an electroless gold plating layer is formed on a copper layer, and in particular, a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer. It is good to do. Adopting such a pad structure can improve the bonding strength with solder and the wettability of the floating pad and also improve the adhesion between the copper layer and the electroless gold plating layer. Therefore, the bonding strength between the electronic component and the connection terminal is increased, and the connection reliability of the wiring board can be further improved. Also, the color of the pad exposed on the first main surface is unified, and the appearance is improved.
[0031]
Further, as another means for solving the above problems, a substantially plate-shaped substrate having a first main surface and a second main surface, and an electroless gold plating layer on a copper layer via an electroless nickel plating layer. A first main surface side connection terminal for solder connection with a connection terminal of an electronic component mounted on the first main surface side of the substrate, and an electroless gold plating layer on the copper layer Having a larger area than the first main surface side connection terminal, and a second surface for solder connection with a connection terminal of another substrate supporting the second main surface side of the substrate. In a method of manufacturing a wiring board having main surface side connection terminals, electroless nickel plating is performed by electroless nickel plating to form the electroless nickel plating layer on the surface of the copper layer on the first main surface side Performing electroless gold plating, and performing electroless plating on the first main surface side. Performing a first gold plating step of forming the electroless gold plating layer on the surface of the Kel layer and electroless gold plating, and forming the electroless gold plating layer on the surface of the copper layer on the second main surface side. And a second gold plating step of directly forming a wiring board.
[0032]
Alternatively, in a method of manufacturing a wiring board having the same configuration, an electroless nickel plating step of performing electroless nickel plating to form the electroless nickel plating layer on the surface of the copper layer on the first main surface side; Performing plating, forming the electroless gold plating layer on the surface of the electrolytic nickel layer on the first main surface side, and forming the electroless gold plating layer on the surface of the copper layer on the second main surface side There is also a method for manufacturing a wiring board, which includes a step of forming a layer directly on both surfaces at the same time.
[0033]
Therefore, according to these manufacturing methods, since only the electroless plating is used as a method of forming the metal layer on the copper layer in the first place, a plating tie bar is unnecessary, and an unnecessary conductive path is not provided in the completed wiring board. Will not remain. Therefore, it is possible to effectively prevent the noise resistance of the board from being deteriorated due to the unnecessary conductive path and to prevent the impedance mismatch of the transmission path, and to improve the electrical characteristics of the wiring board. Since no unnecessary conductive path is provided, the space between the connection terminals can be reduced, and the external dimensions of the substrate can be reduced. In addition, since the wiring layout is less likely to be complicated, design restrictions are reduced, and the wiring board structure is easy to manufacture. Further, since there is no step of post-forming and removing the plating tie bar, the overall steps are simplified.
[0034]
As described above, according to these manufacturing methods, it is possible to relatively easily obtain a new wiring board having excellent electrical characteristics and connection reliability and having a structure advantageous for downsizing.
[0035]
Hereinafter, the manufacturing method will be described.
[0036]
In the electroless nickel plating step, the electroless nickel plating layer is selectively formed on the surface of the copper layer on the first main surface side. The plating bath to be used may be a well-known plating bath, but it is desirable that the amount of the phosphorus compound-based additive is small.
[0037]
In the first gold plating step performed after the electroless nickel plating step, electroless plating is performed to selectively form the electroless gold plating layer on the surface of the electroless nickel layer on the first main surface side. I do. Examples of the type of the electroless gold plating include reduction plating performed using a strong alkaline plating bath, displacement plating performed using an acidic or neutral plating bath, and the like. An advantage of electroless gold plating is that gold can be deposited on the surface of the pad even if there is a floating pad on the first main surface side, for example. However, it is preferable to select displacement plating. The reason is that in an acidic or neutral plating bath, a resin layer such as a solder resist layer is hardly corroded, and moreover, since the resin layer is hardly dissolved in the plating bath, plating can be performed under stable conditions. is there.
[0038]
Here, before the electroless nickel plating step and the first gold plating step, a second main surface side protective material forming step of forming a second main surface side protective material covering the second main surface side is performed in advance. Good to go. If such a second main surface side protective material is formed, the plating bath does not come into contact with the second main surface side because the second main surface side is covered and reliably protected. The plating can be selectively deposited only on a predetermined portion on the side. Therefore, a simple operation such as simply immersing the substrate in a plating bath may be performed, and an operation of removing plating adhered to an unnecessary portion is not required. Accordingly, productivity is improved.
[0039]
The material or structure of the second principal surface side protective material is not particularly limited as long as it can cover the second principal surface side. For example, an adhesive layer may be provided on one surface of a protective base film. Protective tapes and the like are preferred. This is because such a protective tape is advantageous in that the sticking operation and the peeling operation can be easily performed. Note that a dry film or the like for forming an insulating layer may be attached instead of the protective tape.
[0040]
The second main surface side protective material does not necessarily need to cover the entire second main surface, but only covers a necessary portion (for example, a region that finally becomes a product) in the conductive layer, and an unnecessary portion (final portion). (A region that does not become a product) may be exposed. Such a second main surface side protective material is removed after the electroless nickel plating step and the first gold plating step.
[0041]
Here, it is preferable that the electroless nickel plating step and the first gold plating step be performed continuously. In other words, after performing the electroless nickel plating step, the first gold plating step is performed without separately providing a step other than plating (for example, a step other than plating performed using a strong acid or strong alkali solution). It is desirable to carry out. If the two types of plating are continuously performed in this manner, the electroless nickel plating layer serving as a base is not attacked by a strong acid or strong alkaline solution, and the electroless nickel plating layer is roughened or thinned. Be avoided. As a result, the function of the electroless nickel plating layer as a barrier layer is ensured, and suitable adhesion between the copper layer and the electroless gold plating layer is obtained. As a result, the connection reliability of the wiring board can be reliably improved. it can.
[0042]
In the second gold plating step, electroless gold plating is performed to directly form the electroless gold plating layer on the surface of the copper layer on the second main surface side. As the electroless gold plating performed at this stage, it is particularly preferable to select displacement plating. Prior to the second gold plating step, a first main surface side protection material forming step of forming a first main surface side protection material covering the first main surface side may be performed in advance. If such a first main surface side protective material is formed, the first main surface side is covered and securely protected, so that the plating bath does not contact the plating layer on the first main surface side. Plating can be selectively deposited on a predetermined portion on the second main surface side. Therefore, a simple operation such as simply immersing the substrate in a plating bath may be performed, and an operation of removing plating adhered to an unnecessary portion is not required. Accordingly, productivity is improved. The material and structure of the first main surface side protective material are not particularly limited as long as they can cover the first main surface side, but the above-described protective tapes and the like are preferable. Then, such a first main surface side protective material is removed after the second gold plating step.
[0043]
Alternatively, after performing the electroless nickel plating step as described above, perform a double-sided simultaneous gold plating step to form the electroless gold plating layer on the surface of the electroless nickel layer on the first main surface side, and The electroless gold plating layer may be formed directly on the surface of the copper layer on the second main surface side. According to this method, at least the first main surface side protective material forming step and the first main surface side protective material removing step of removing the first main surface side protective material removing step can be omitted, and further simplification of the steps and improvement of productivity can be achieved. Becomes possible. Note that “forming the gold plating layer on the surface of the electroless nickel layer” includes forming the electroless gold plating layer directly on the surface of the electroless nickel layer, The method also includes forming an electroless gold plating layer directly on the surface of the electroless gold plating layer, and further forming an electroless gold plating layer on the electroless gold plating layer.
[0044]
In the above method, electroless nickel plating and electroless gold plating are first performed on the first main surface side, and then electroless gold plating is performed on the second main surface side. It is permissible to do so. That is, the order may be the second gold plating step → the electroless nickel plating step → the first gold plating step. In particular, in the case of forming a protective material, for example, a first principal surface side protective material forming step → a second gold plating step → a first principal surface side protective material removing step → a second principal surface side protective material forming step → electroless It may be in the order of a nickel plating step → a first gold plating step → a second main surface side protective material removing step.
[0045]
Then, an electronic component such as a semiconductor integrated circuit chip is soldered to the first main surface side of the wiring board manufactured as described above, and a gap between the electronic component and the wiring board is formed as necessary. Resin sealing with underfill material. In this case, not only the electronic component and the wiring board are fixed to each other by the solder, but also to each other by the underfill material. Therefore, when a thermal stress acts on the connection portion of the first main surface side connection terminal, breakage hardly occurs. Therefore, the disadvantage of the structure in which the electroless gold plating layer is formed on the copper layer via the electroless nickel plating layer can be surely offset.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
[0047]
Hereinafter, a wiring board 11 and a method of manufacturing the same according to a first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a sectional view of a main part showing a wiring board 11 of the present embodiment. FIG. 2 is a schematic plan view showing a flip chip connection surface (hereinafter, referred to as an “FC connection surface”) of the wiring board 11, and FIG. 3 is a ball grid array connection surface (hereinafter, a “BGA connection surface”) of the wiring substrate 11. FIG. 4 to 10 are schematic cross-sectional views for explaining a manufacturing process of the wiring board 11 of the present embodiment. FIG. 11 is a flowchart for explaining a manufacturing process of the wiring board 11 of the present embodiment.
[0048]
As shown in FIG. 1, a board 12 constituting the wiring board 11 is a multilayer plate-like member having a substantially rectangular shape in plan view, and includes an FC connection surface 13 (first main surface) and a BGA connection surface 14 (first 2 main surfaces). In FIG. 1, the FC connection surface 13 (first main surface) is located on the upper side, and the BGA connection surface 14 (second main surface) is located on the lower side. The surface of the FC connection surface 13 (first main surface) of the substrate 12 is almost entirely covered with the solder resist 21. The surface of the BGA connection surface 14 (second main surface) of the substrate 12 is also almost entirely covered with the solder resist 22.
[0049]
As shown in FIGS. 1 and 2, a substantially rectangular die area (electronic component mounting area) is set on the FC connection surface 13 (first main surface) side of the substrate 12 at a substantially central portion thereof. . In this die area, a rectangular semiconductor integrated circuit chip 16, which is a kind of electronic component, can be mounted. In the die area, a large number of FC pads 17 (first main surface side connection terminals) for electrical connection with the semiconductor integrated circuit chip 16 are formed in a grid pattern (see FIG. 2). . On the other hand, no electronic component mounting area is particularly set on the BGA connection surface 14 (second main surface) side of the substrate 12, and instead, a motherboard 61 (another substrate) can be connected by soldering. For this reason, a large number of BGA pads 18 are formed in a grid pattern on almost the entire area of the BGA connection surface 14 of the substrate 12 as second main surface side connection terminals connected to connection terminals (not shown) on the motherboard 61 side. (See FIG. 3).
[0050]
The FC pad 17 as the first main surface side connection terminal has a structure in which an electroless gold plating layer 26 is formed on a copper layer 23 via an electroless nickel plating layer 29. The FC pads 17 are connected to the bumps 76 of the semiconductor integrated circuit chip 16 by soldering. Here, the copper layer 23 is set to 30 μm, the electroless nickel plating layer 29 is set to 6 μm, and the electroless gold plating layer 26 is set to 0.05 μm.
[0051]
On the other hand, the BGA pad 18 as the second main surface side connection terminal has a structure in which the electroless gold plating layer 30 is directly formed on the copper layer 24 by displacement plating, and the electroless nickel plating layer has no structure. I haven't. The BGA pad 18 is connected to a connection terminal of a motherboard 61 that supports the BGA connection surface 14 (second main surface) of the substrate 12 by soldering. Here, the thickness of the copper layer 24 is set to 30 μm, and the thickness of the electroless gold plating layer 30 is set to 0.05 μm. That is, in the case of this wiring board 11, the pad structures on the front and back surfaces are different, and one has a three-layer structure and the other has a two-layer structure.
[0052]
In the present embodiment, the BGA pads 18 are formed according to the size and pitch of the connection terminals on the motherboard 61, while the FC pads 17 are formed according to the size and pitch of the bumps 76 on the semiconductor integrated circuit chip 16. It is formed. Accordingly, the diameter and area of each BGA pad 18 are larger than the diameter and area of each FC pad 17. Specifically, the diameter of each BGA pad 18 is set to about 600 μm, and the diameter of each FC pad 17 is set to about 100 μm. The center distance (ie, pitch) between adjacent BGA pads 18, 18 is larger than the center distance (ie, pitch) between adjacent FC pads 17, 17. Specifically, the pitch between the BGA pads 18, 18 is set to about 600 μm, and the pitch between the FC pads 17, 17 is set to about 100 μm. Furthermore, the occupancy of the BGA pad 18 on the BGA connection surface 14 is considerably larger than the occupancy of the FC pad 17 on the FC connection surface 13. Specifically, the occupancy of the BGA pad 18 on the BGA connection surface 14 is set to 40% to 70%, and the occupancy of the FC pad 17 on the FC connection surface 13 is set to 5% to 15%.
[0053]
As shown in FIG. 1, an opening 25 for exposing the FC pad 17 is formed at a predetermined position of the solder resist 21. An opening 27 for exposing the BGA pad 18 is formed at a predetermined position of the solder resist 22. On the surface of the FC pad 17, a substantially hemispherical solder bump 28 called a so-called C4 bump is formed. On the surface of the BGA pad 18, a substantially spherical solder ball 62 is formed.
[0054]
As shown in FIG. 1, the substrate 12 has a core material 31 made of a glass cloth impregnated with an epoxy resin at a central portion thereof. On the upper surface 32 and the lower surface 33 of the core material 31, wiring patterns 34 and 35 made of copper having a thickness of several tens μm are formed. Via conductors 36 are formed at a plurality of locations in the core material 31. The via conductor 36 electrically connects the wiring pattern 34 on the upper surface 32 of the core material 31 to the wiring pattern 35 on the lower surface 33. Note that the inside of the via conductor 36 is filled with a closing body 37 having conductivity.
[0055]
On the upper surface 32 and the lower surface 33 of the core material 31, inner resin insulation layers 41 and 42 are formed using a photosensitive epoxy resin. On the surface (that is, the first main surface) of the resin insulating layer 41, a wiring pattern 51 is also formed in addition to the FC pad 17. On the surface (that is, the second main surface) of the resin insulating layer 42, a wiring pattern 52 is formed in addition to the BGA pad 18. Blind via conductors 53 and 54 are formed in the resin insulating layers 41 and 42. The upper blind via conductor 53 connects and connects the wiring pattern 34 and the wiring pattern 51. The lower blind via conductor 54 connects and connects the wiring pattern 35 and the wiring pattern 52.
[0056]
Then, as shown in FIG. 3, the gap between the wiring board 11 and the semiconductor integrated circuit chip 16 is filled with an underfill material 75 made of epoxy resin. Thus, the wiring substrate 11 and the semiconductor integrated circuit chip 16 are fixed to each other with the interface sealed.
[0057]
Next, a method for manufacturing the wiring board 11 of the present embodiment will be described in order with reference to FIGS.
[0058]
First, the substrate 12 having the above configuration is manufactured. Specifically, the following is performed. That is, the starting material is a double-sided copper-clad laminate in which copper foil is adhered to both sides of the core material 31, and laser processing is performed on the double-sided copper-clad laminate using a YAG laser or a carbon dioxide gas laser. Form. Next, after the via conductor 36 is formed by electroless copper plating on the inner surface of the through hole, the wiring patterns 34 and 35 are patterned by etching the copper foil. Here, after filling the via conductor 36 with the closing member 37, resin insulating layers 41 and 42 are formed on the upper surface 32 and the lower surface 33 of the core material 31. Next, holes are formed in the resin insulating layers 41 and 42 by laser processing, and blind holes for forming blind via conductors 53 and 54 are formed. Further, by performing electroless copper plating without forming a mask, copper plating is deposited inside the blind hole to form blind via conductors 53 and 54. At this time, electroless copper plating is also deposited on the entire outer surfaces of the resin insulating layers 41 and 42. Thereafter, exposure and development are performed to form a plating resist having a predetermined pattern. In this state, after performing electrolytic copper plating using the electroless copper plating layer as a common electrode, first, the resist is dissolved and removed, and the unnecessary electroless copper plating layer is further removed by etching. As a result, the wiring pattern 51 is formed on the surface of the upper resin insulating layer 41, and the copper layer 23 serving as the main body of the FC pad 17 is formed. In addition, the wiring pattern 52 is formed on the surface of the lower resin insulating layer 42, and the copper layer 24 serving as the main body of the BGA pad 18 is formed.
[0059]
Then, a photosensitive epoxy resin is applied and cured on the surfaces of the FC connection surface 13 (first main surface) and the BGA connection surface 14 (second main surface) of the substrate 12 manufactured as described above. Then, solder resists 21 and 22 are formed. Next, exposure and development are performed in a state where a predetermined mask is arranged, and the openings 25 and 27 are patterned in the solder resists 21 and 22 (see FIG. 4).
[0060]
Although not specifically shown, the wiring board 11 of the present embodiment is manufactured in a large-sized state in which a plurality of wiring boards are integrated vertically and horizontally at the stage of an intermediate product. Are performed collectively for intermediate products.
[0061]
Next, in step S110 of FIG. 11, a protective tape 82 having an adhesive layer on one surface of a protective base film is attached to almost the entire BGA connection surface 14 (second main surface) side (second main surface side). Protective material forming step). At this time, as shown in FIG. 5, a protective tape 82 is provided so as to cover each product area.
[0062]
Next, in step S120 of FIG. 11, the substrate 12 is immersed in an electroless nickel plating bath to perform electroless nickel plating. As a result, as shown in FIG. 6, the electroless nickel plating layer 29 is selectively formed only on the surface of the copper layer 23 on the FC connection surface 13 (first main surface) side (electroless nickel plating). Process).
[0063]
Next, in step S130 of FIG. 11, the substrate 12 is transferred to a replacement gold plating bath to perform electroless gold plating, and as shown in FIG. 6, the electroless nickel layer on the FC connection surface 13 (first main surface) side. The electroless gold plating layer 26 is selectively formed only on the surface of the substrate 29 (first gold plating step). As a result, the roughening and thinning of the electroless nickel plating layer 29 are avoided, so that the function as a barrier layer is ensured, and a favorable adhesion between the copper layer 23 and the electroless gold plating layer 26 is obtained. Can be.
[0064]
In the electroless nickel plating step and the first gold plating step, the BGA connection surface 14 (second main surface) side is securely protected by the protective tape 82. Therefore, the plating bath does not contact the BGA connection surface 14 (second main surface) side, and plating can be selectively deposited only on a predetermined portion on the FC connection surface 13 (first main surface) side. Therefore, a simple operation such as simply immersing the substrate 12 in a plating bath may be performed, and an operation of removing plating adhered to an unnecessary portion is not required.
[0065]
Next, in step S140 of FIG. 11, the substrate 12 is taken out of the electroless gold plating bath, and the protective tape 82 is peeled off as shown in FIG. 7 (second main surface side protective material removing step). Since the protective tape 81 is only temporarily fixed by the adhesive force of the adhesive and is not necessarily firmly bonded, it can be peeled off relatively easily.
[0066]
Next, in step S150 of FIG. 11, a protective tape 86 covering the BGA connection surface 13 (first main surface) side of the substrate 12 is attached as shown in FIG. 8 (second main surface side protective material forming step). At this time, it is desirable that the pressure-sensitive adhesive of the protection tape 86 is not brought into contact with the electroless gold plating layer 26 as much as possible.
[0067]
Next, in step S160 of FIG. 11, by performing displacement gold plating, the electroless gold plating layer 30 as shown in FIG. 9 is formed on the surface of the copper layer 24 on the BGA connection surface 14 (second main surface) side. Is directly formed (second gold plating step).
[0068]
In such a second gold plating step, the FC connection surface 13 (first main surface) side is securely protected by the protective tape 86. Therefore, the plating bath does not contact the FC pad 17 on the FC connection surface 13 (second main surface) side, and the plating is selectively deposited on a predetermined portion on the BGA connection surface 14 (second main surface) side. Can be. Therefore, a simple operation such as simply immersing the substrate 12 in a plating bath may be performed, and an operation of removing plating adhered to an unnecessary portion is not required.
[0069]
Next, in step S170 in FIG. 11, the substrate 12 is taken out of the replacement gold plating bath, and the protective tape 86 is peeled off as shown in FIG. 10 (first principal surface side protective material removing step). Since the protective tape 86 is only temporarily fixed by the adhesive force of the adhesive and is not necessarily firmly bonded, it can be peeled off relatively easily.
[0070]
Thereafter, a solder bump forming step is performed according to a well-known method, and a solder bump 28 is formed on the surface of the FC pad 17. Specifically, a mask having a predetermined pattern is placed on the solder resist 21, and a solder paste is printed on the FC pads 17. Then, the solder paste is reflowed. Thereafter, the intermediate product integrated in a large format is cut into individual pieces using a cutting tool such as a dicing blade, thereby completing the wiring board 11 of the present embodiment.
[0071]
Further, the semiconductor integrated circuit chip 16 is mounted on the die area of the wiring board 11. At this time, reflow is performed by aligning the solder bumps 28 on the wiring board 11 and the bumps 76 on the semiconductor integrated circuit chip 16. Thus, the solder bumps 28 and the bumps 76 are joined to each other, and the wiring board 11 side and the semiconductor integrated circuit chip 16 side are electrically connected. Further, a gap between the wiring board 11 and the semiconductor integrated circuit chip 16 is filled with an underfill material 75 and a hardening process is performed, and the gap is sealed with a resin. Further, if the solder balls 62 are provided on the BGA connection surface 14 (second main surface) side, a desired semiconductor package (so-called organic package) is completed.
[0072]
Therefore, according to the present embodiment, the following effects can be obtained.
[0073]
(1) In the wiring board 11 of the present embodiment, the BGA pads 18 are formed on the copper layer 24 without the nickel plating layer between the copper layer 24 and the electroless gold plating layer 30. The structure in which the plating layer 30 is directly formed is adopted. For this reason, the disadvantage of interposing an electroless nickel plating layer between the copper layer 24 and the electroless gold plating layer 30, for example, is eliminated. That is, the generation of a fragile layer at the solder interface due to a large amount of phosphorus contained in the electroless nickel plating layer is prevented beforehand, and the occurrence of disconnection failure due to breakage of the connection portion is prevented. Therefore, the connection reliability of the wiring board 11 can be improved.
[0074]
(2) Since the FC pad 17 has a structure in which the electroless gold plating layer 26 is formed on the copper layer 23 via the electroless nickel plating layer 29, the bonding strength with solder and the wettability are obtained. Since the electroless nickel plating layer 29 functions as a barrier layer, the adhesion between the copper layer 23 and the electroless gold plating layer 26 is also improved. Although the structure having the electroless nickel plating layer 29 causes concern about the generation of a fragile layer at the solder interface, the FC pad 17 has a larger area, pad pitch, and surface occupancy than the BGA pad 18. The rate is small. In addition, the gap between the semiconductor integrated circuit chip 16 and the wiring board 11 is tightly sealed with an underfill material 75 with resin. For this reason, even when heating and cooling are performed at the time of connection, the thermal stress concentrated on the connection portion of the FC pad 17 is not so large as the thermal stress concentrated on the connection portion of the BGA pad 18, and The occurrence rate of breakage is small in the first place. That is, the benefit of the structure in which the electroless gold plating layer 26 is formed on the copper layer 23 via the electroless nickel plating layer 29 is larger than the disadvantage of the structure. Therefore, as a result, the solder connection with the connection terminal of the semiconductor integrated circuit chip 16 can be reliably performed, and the connection reliability of the wiring board 11 can be improved.
[0075]
(3) Further, since the wiring board 11 of the present embodiment does not have the electrolytic nickel plating layer, unnecessary conductive paths whose terminals are electrically open such as plating tie bars are excluded from the wiring board 11. As a result, it is possible to effectively prevent the noise resistance of the substrate 12 from deteriorating due to unnecessary conductive paths and to prevent the impedance mismatch of the transmission path, and to improve the electrical characteristics of the wiring substrate 11. In addition, the space between the pads can be reduced because unnecessary conductive paths are not provided, which can contribute to downsizing of the outer dimensions of the substrate 12. In addition, since the wiring layout is less likely to be complicated, design restrictions are reduced, and the wiring board structure is easy to manufacture.
[0076]
(4) If the manufacturing method of the present embodiment is adopted, as described above, the novel wiring board 11 having excellent electrical characteristics and connection reliability and having a structure advantageous for downsizing can be relatively easily manufactured. And it can be obtained reliably. In addition, according to the manufacturing method of the present embodiment, the electroless gold plating is performed on the FC connection surface 13 (first main surface) in a state where the protection tape 82 is arranged, while the BGA connection surface is formed in a state where the protection tape 86 is arranged. (Second main surface) 14 is subjected to electroless gold plating. That is, electroless gold plating on the FC connection surface 13 (first main surface) and electroless gold plating on the BGA connection surface 14 (second main surface) are performed separately. Therefore, according to this manufacturing method, it is possible to individually set the film thickness of the electroless gold plating layers 26 and 30 to a suitable value, and it is easy to achieve improvement in connection reliability.
[Second embodiment]
[0077]
Next, a wiring board 11 and a method of manufacturing the same according to a second embodiment will be described with reference to the flowchart of FIG. In this embodiment, the wiring board 11 having the structure shown in FIG. 1 is manufactured through a slightly different process.
[0078]
In the manufacturing method of the first embodiment, the second main surface side protective material forming step (Step S110) → the electroless nickel plating step (Step S120) → the first gold plating step (Step S130) → the first main surface side protective material Removal step (step S140) → first main surface side protection material forming step (step S150) → second gold plating step (step S160) → first main surface side protection material removal step (step S170). .
[0079]
On the other hand, in the present embodiment, instead of performing the first main surface side protective material forming step to the first main surface side protective material removing step (steps S150 to S170), a double-sided simultaneous gold plating step (step S180) is performed. It is characterized by the following. That is, the electroless gold plating layer 26 is formed on the surface of the electroless nickel layer 29 on the FC connection surface 13 (first main surface) side (more precisely, on the surface of the existing electroless gold plating layer 26). The electroless gold plating layer 30 is directly formed on the surface of the copper layer 24 on the BGA connection surface 14 (second main surface) side. In this case, the electroless gold plating layer 26 on the FC connection surface 13 (first main surface) side is thicker than the electroless gold plating layer 30 on the BGA connection surface 14 (second main surface) side.
[0080]
According to the manufacturing method of the present embodiment, the first main surface side protective material forming step and the first main surface side protective material removing step can be omitted, so that the number of man-hours is further reduced than in the first embodiment. And the productivity can be further improved. Further, according to this manufacturing method, even if a floating pad exists on the FC connection surface 13 (first main surface) side, gold can be deposited on the surface of the pad. Therefore, also for the floating pad, the bonding force with solder and wettability can be improved, and the adhesion between the copper layer 23 and the electroless gold plating layer 26 can be improved. Therefore, the bonding strength between the semiconductor integrated circuit chip 16 and the bump 76 is increased, and the connection reliability of the wiring board 11 can be further improved.
[Third Embodiment]
[0081]
Next, a wiring board 11 and a method of manufacturing the same according to a third embodiment will be described with reference to the flowchart of FIG. In this embodiment, the wiring board 11 having the structure shown in FIG. 1 is manufactured through a slightly different process.
[0082]
In the first embodiment, nickel plating and gold plating are first performed on the FC connection surface 13 (first main surface) side, and then gold plating is performed on the BGA connection surface 14 (second main surface) side. In contrast, in the present embodiment, gold plating is first performed on the BGA connection surface 14 (second main surface) side, and then nickel plating and gold plating are performed on the FC connection surface 13 (first main surface) side. It is characterized by. Specifically, the first main surface side protection material forming step (step S150) → the second gold plating step (step S160) → the first main surface side protection material removing step (step S170) → the second main surface side protection material The forming step (step S110), the electroless nickel plating step (step S120), the first gold plating step (step S130), and the second principal surface side protective material removing step (step S140) are performed in this order.
[0083]
Even when the manufacturing method of the present embodiment is adopted, it is possible to relatively easily and reliably obtain a new wiring board 11 having excellent electrical characteristics and connection reliability and having a structure advantageous for downsizing. Can be.
[0084]
Next, in addition to the technical ideas described in the claims, technical ideas grasped by the above-described embodiments will be listed below.
[0085]
(1) The distance between centers between adjacent second main surface side connection terminals is larger than the distance between centers between adjacent second main surface side connection terminals. Wiring board.
[0086]
(2) The occupation ratio of the second main surface side connection terminal on the second main surface is larger than the occupation ratio of the first main surface side connection terminal on the first main surface. 3. The wiring board according to 1 or 2.
[0087]
(3) In a semiconductor package in which a semiconductor integrated circuit chip having a plurality of connection terminals is flip-chip connected on a wiring substrate, the wiring substrate has a flip chip connection surface as a first main surface and a second main surface. Substantially plate-shaped substrate having a ball grid array connection surface, and having a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer, on the side of the first flip chip connection surface of the substrate A plurality of flip-chip pads for solder connection with a plurality of connection terminals of the semiconductor integrated circuit chip to be mounted; and a structure in which an electroless gold plating layer is directly formed on a copper layer; A ball grid array pad for solder connection with a connection terminal of another substrate which has a larger area than that of the substrate and supports the ball grid array connection surface side of the substrate. And a de and semiconductor package gap between the semiconductor integrated circuit chip and the wiring board substrate is characterized in that it is sealed with an underfill material.
[0088]
(4) a substantially plate-shaped substrate having a first main surface and a second main surface, and a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer, A first main surface side connection terminal for solder connection with a connection terminal of an electronic component mounted on the first main surface side, and a structure in which an electroless gold plating layer is directly formed on a copper layer; A wiring board having a larger area than the main surface side connection terminal and having a second main surface side connection terminal for solder connection with a connection terminal of another substrate supporting the second main surface side of the substrate. In the manufacturing method, a second main surface side protective material forming step of forming a second main surface side protective material covering the second main surface side, and electroless nickel plating are performed, and the copper layer on the first main surface side is formed. Electroless nickel plating step of forming the electroless nickel plating layer on the surface of A first gold plating step of forming the electroless gold plating layer on the surface of the electroless nickel plating layer on the first main surface side, and forming the electroless nickel plating layer and the electroless gold plating layer after forming the electroless gold plating layer. (2) a second main surface side protection material removing step of removing the main surface side protection material, and forming a first main surface side protection material covering the first main surface side on which the first main surface side connection terminals are formed. A first main surface side protective material forming step, a second gold plating step of performing gold plating, and directly forming the electroless gold plating layer on the surface of the copper layer on the second main surface side, A first main surface side protective material removing step of removing the first main surface side protective material after the direct formation of the gold plating layer.
[0089]
(5) The method for manufacturing a wiring board according to claim 3, wherein the electroless nickel plating step and the first gold plating step are performed continuously.
[0090]
(6) Before the electroless nickel plating step and the first gold plating step, a second main surface side protective material forming step of forming a second main surface side protective material covering the second main surface side is performed. 4. The method according to claim 3, wherein a first main surface side protective material forming step of forming a first main surface side protective material covering the first main surface side is performed before the second gold plating step. Method of manufacturing a wiring board.
[0091]
(7) Before the electroless nickel plating step, a second main surface side protection material forming step of forming a second main surface side protection material covering the second main surface side is performed, and the double-sided simultaneous gold plating step is performed. 5. The method according to claim 4, wherein a first main surface side protective material forming step of forming a first main surface side protective material that covers the first main surface side is performed before the first main surface side.
[Brief description of the drawings]
FIG. 1 is an essential part cross-sectional view showing a wiring board according to a first embodiment of the present invention;
FIG. 2 is a schematic plan view showing an FC connection surface (first main surface) of the wiring board according to the first embodiment.
FIG. 3 is a schematic plan view showing a BGA connection surface (second main surface) of the wiring board according to the first embodiment.
FIG. 4 is a schematic cross-sectional view showing a state where a solder resist is formed on a substrate in the manufacturing process of the first embodiment.
FIG. 5 is a schematic cross-sectional view showing a state in which a protective tape (a second main surface side protective material) is adhered to a BGA connection surface (a second main surface) in the manufacturing process of the first embodiment.
FIG. 6 is a schematic cross-sectional view showing a state in which an electroless nickel plating layer and a gold plating layer are formed on the FC connection surface (first main surface) side in the manufacturing process of the first embodiment.
FIG. 7 is a schematic cross-sectional view showing a state in which a protection tape (a second main surface side protection material) has been removed in the manufacturing process of the first embodiment.
FIG. 8 is a schematic cross-sectional view showing a state in which a protection tape (first main surface side protection material) is attached to the FC connection surface (first main surface) side in the manufacturing process of the first embodiment.
FIG. 9 is a schematic cross-sectional view showing a state where a gold plating layer is directly formed on the BGA connection surface (second main surface) side in the manufacturing process of the first embodiment.
FIG. 10 is a schematic cross-sectional view showing a state in which a protection tape (first main surface side protection material) has been removed in a manufacturing process of the first embodiment.
FIG. 11 is a flowchart illustrating a manufacturing process according to the first embodiment.
FIG. 12 is a flowchart illustrating a manufacturing process according to a second embodiment.
FIG. 13 is a flowchart illustrating a manufacturing process according to a third embodiment.
[Explanation of symbols]
11 Wiring board
12 ... Substrate
13: FC connection surface as first main surface
14 BGA connection surface as second main surface
16. Semiconductor integrated circuit chips as electronic components
17: FC pad as first main surface side connection terminal
18 BGA pad as second main surface side connection terminal
23, 24 ... copper layer
26,30 ... Electroless gold plating layer
29 ... Electroless nickel plating layer
61: Motherboard as another board
62 solder ball
76 ... Solder bumps as connection terminals for electronic components
82 ... Protective tape as second principal surface side protective material
86: Protective tape as first main surface side protective material

Claims (4)

A substantially plate-shaped substrate having a first main surface and a second main surface;
It has a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer, and has a structure for solder connection with a connection terminal of an electronic component mounted on the first main surface side of the substrate. 1 main surface side connection terminal,
It has a structure in which an electroless gold plating layer is directly formed on a copper layer, has a larger area than the first main surface side connection terminal, and connects another substrate that supports the second main surface side of the substrate. A wiring board comprising: a terminal and a second main surface side connection terminal for solder connection. The first main surface side connection terminal is a plurality of flip chip pads for solder connection with a connection terminal of a semiconductor integrated circuit chip as the electronic component, and the second main surface side connection terminal is the another main body side connection terminal. The wiring board according to claim 1, wherein the wiring board is a plurality of pads for a ball grid array for connecting to connection terminals of the board via solder balls. A substantially plate-shaped substrate having a first main surface and a second main surface, and a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer, A first main surface side connection terminal for solder connection with a connection terminal of an electronic component mounted on the surface side, and a structure in which an electroless gold plating layer is directly formed on a copper layer; A method of manufacturing a wiring board having a larger area than a connection terminal and including a second main surface side connection terminal for solder connection with a connection terminal of another substrate supporting the second main surface side of the substrate. ,
Performing an electroless nickel plating to form the electroless nickel plating layer on the surface of the copper layer on the first main surface side;
A first gold plating step of performing electroless gold plating and forming the electroless gold plating layer on the surface of the electroless nickel layer on the first main surface side;
A second gold plating step of performing electroless gold plating and directly forming the electroless gold plating layer on the surface of the copper layer on the second main surface side. A substantially plate-shaped substrate having a first main surface and a second main surface, and a structure in which an electroless gold plating layer is formed on a copper layer via an electroless nickel plating layer, A first main surface side connection terminal for solder connection with a connection terminal of an electronic component mounted on the surface side, and a structure in which an electroless gold plating layer is directly formed on a copper layer; A method of manufacturing a wiring board having a larger area than a connection terminal and including a second main surface side connection terminal for solder connection with a connection terminal of another substrate supporting the second main surface side of the substrate. ,
Performing an electroless nickel plating to form the electroless nickel plating layer on the surface of the copper layer on the first main surface side;
Gold plating is performed to form the electroless gold plating layer on the surface of the electrolytic nickel layer on the first main surface, and the electroless gold is formed on the surface of the copper layer on the second main surface. A method for manufacturing a wiring board, comprising: a step of simultaneously forming a plating layer on both sides by simultaneously performing a gold plating step.

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