JP2015159223A - Post electrode, method of manufacturing post electrode and circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a post electrode of a circuit board for mounting a semiconductor chip that can be manufactured in a manufacturing process not requiring highly accurate alignment, and is less likely to be peeled off from the circuit board even if heat stress is applied.SOLUTION: A post electrode formed on a circuit board 1 for mounting a semiconductor chip becomes thinner as it recedes from the circuit board toward the semiconductor chip.

Description

  The present invention relates to a circuit board for mounting a semiconductor chip. Furthermore, it is related with the post electrode formed in a circuit board.

  With the progress of narrowing the pitch of electrodes of semiconductor chips such as LSIs, reducing the amount of solder used for the purpose of avoiding the problem that solder shorts are likely to occur will reduce the semiconductor chip and the circuit for mounting it. Since the gap between the substrates becomes narrow, a problem that the cleaning property of the flux is insufficient and the problem that the filling property of the underfill is deteriorated newly occur.

  In order to secure a gap between the semiconductor chip and the circuit board, a technique for forming a post electrode (post-shaped electrode terminal) on both or either of the electrode on the semiconductor chip side and the electrode on the circuit board side has been developed.

  For example, Patent Documents 1 and 2 disclose a technique in which a post electrode is formed on a circuit board. However, since it is necessary to align a pattern with a solder resist opening, the pitch is reduced. Along with this, the positioning accuracy of the opening and the post electrode becomes strict, and there is a problem that stable manufacturing becomes difficult.

  Patent Document 3 discloses a technique that does not require positioning of the solder resist opening and the post electrode. However, the post electrode protruding from the insulating member has a uniform diameter and is easily peeled off by stress. , Have a problem that is easy to peel off.

Japanese Patent No. 5011329 JP 2012-231130 A Japanese Patent No. 5258716

  The present invention has been made to solve the above-described problems, and can be manufactured in a manufacturing process that does not require high-precision alignment, and can be manufactured by a post electrode on a circuit board for mounting a semiconductor chip. An object of the present invention is to provide a post electrode that does not easily peel off from a circuit board even when stress is applied by thermal stress.

  As a means for solving the above problems, the invention according to claim 1 is a post electrode formed on a circuit board for mounting a semiconductor chip, the post electrode from the circuit board to the semiconductor chip. This is a post electrode characterized in that the portion closer to is thinner.

The invention according to claim 2 includes a step of forming an insulating resin layer on the surface of the support,
A step of forming a via hole in the insulating resin layer, a step of forming a narrower via hole in a deeper portion;
Forming a pad electrode in the via hole and forming a multilayer wiring portion in the insulating resin layer;
Removing the support;
Removing the insulating resin layer to expose the pad electrode to form a post electrode;
It is the manufacturing method of the post electrode characterized by comprising.

  The invention described in claim 3 is the method for manufacturing a post electrode according to claim 2, wherein the step of exposing the post electrode is a step of laser ablating the insulating resin layer. .

  By making the post electrode into a tapered shape, it is possible to provide a circuit board having a post electrode that is difficult to peel off even when stress is applied to the post electrode.

1 is a schematic cross-sectional view showing an example of a circuit board of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic sectional drawing which shows an example of the manufacturing process of the circuit board of this invention, Comprising: (a) is a schematic sectional drawing which shows the example of the support body to be used, (b) forms an insulating resin layer in the front and back of a support body After, schematic sectional view showing an example of a state in which a via hole is formed, (c) after (b), after applying electroless plating and electrolytic plating to the entire surface, the copper plating layer is patterned to form a copper pattern Each state is shown. It is a schematic sectional drawing explaining the manufacturing process which follows the manufacturing process of the circuit board of this invention shown in FIG. 2, Comprising: (d) is an insulating resin layer and a copper pattern by repeating (b)-(c). After forming the laminate and forming the solder resist layer on the outermost surface of the front and back, the state where the opening is formed in the pad electrode portion, (e) is the peelable on the front and back surfaces of the support after FIG. The state where the laminate of the insulating resin layer and the copper pattern is peeled off from the peeled surface of the copper foil, (f) is the removal of the copper layer on the peeled surface of the peeled insulating resin layer and the copper pattern laminate, The state in which the insulating resin layer is exposed, and (h) shows the state in which the insulating resin layer exposed in (f) is removed with a certain thickness and the post electrode is exposed.

The circuit board of the present invention and the manufacturing method thereof will be described with reference to the drawings.
FIG. 1 is a schematic sectional view showing an example of a circuit board 1 of the present invention. The circuit board 1 of the present invention is covered with a solder resist 8 on the side connected to the printed wiring board, and the portion of the pad electrode 7 on the outermost surface for electrical connection becomes an opening of the solder resist 8. It can be connected to the electrodes of the printed wiring board by soldering.

  On the other surface of the circuit board 1 of the present invention, a post electrode 3 for electrical connection with a pad electrode of a semiconductor chip is formed, and the others are covered with an insulating resin layer 2. Further, in the multilayer wiring portion 9 laminated by the build-up method, wiring (not shown) and an interlayer connection portion are formed in each insulating resin layer as necessary.

  The present invention is characterized in that the post electrode 3 for electrical connection with the pad electrode of the semiconductor chip has a tapered shape. The taper shape indicates that the post electrode 3 becomes thinner as it approaches the semiconductor chip from the circuit board 1. For example, the case where the post electrode 3 is not a columnar shape but a truncated cone corresponds.

  When a force is applied to the post electrode 3 along a plane parallel to the surface of the circuit board 1, the post electrode 3 has a cylindrical shape and a truncated cone shape with the same height and bottom diameter, In the truncated cone, the force to peel off the post electrode 3 from the base is weakened.

Therefore, the post electrode 3 is difficult to peel off from the circuit board 1 even when a thermal stress is applied when the semiconductor chip is mounted on the circuit board 1 or when the circuit board 1 is mounted on the printed wiring board.

Next, the manufacturing method of the circuit board 1 of this invention is demonstrated using FIG. 2 and FIG.
Fig.2 (a) has shown the example of the schematic sectional drawing of the support body 4 used for manufacture of the circuit board 1 of this invention. For this support 4, for example, a peelable copper foil 5 can be used on the front and back, and the prepreg bonded as an adhesive layer with the surfaces to be bonded facing each other. The peelable copper foil 5 is used in order to make it peelable later, and usually an ultrathin copper foil of about 2 μm to 5 μm is bonded to a support copper foil of about 18 μm via a release layer. . The support copper foil sides are bonded face to face. Although the prepreg was used as an adhesive layer, any prepreg may be used as long as an ultrathin copper foil is bonded to the front and back surfaces of a substrate having sufficient rigidity as a support via a release layer. In addition, the support 4 may be provided with an alignment mark, a guide hole, or the like necessary for the subsequent steps.

Moreover, as a material which can be used for the support body 4, it is also possible to use the laminated substrate which provided the metal and copper foil which can be removed by etching on both surfaces.
As a metal that can be removed by etching, a metal or alloy mainly composed of Cu, Fe, Mn, Al, Ni, Cr, and stainless steel can be used. A structure in which a plurality of metals are bonded only at the outer periphery may be used so that they can be separated in a later step. In the case of one sheet, it may be cut using a slicer or a water cutter.

  When using the laminated substrate which provided copper foil on both surfaces, the structure which has the area | region which can overlap and isolate | separate several copper foil may be sufficient, and said peelable copper foil may be used. In order to control the thickness and rigidity, a configuration in which a prepreg is stacked on a core material may be used. In that case, you may provide the alignment pattern required for lamination | stacking, such as copper foil, in a core material.

  FIG. 2B shows a state in which the via hole 6 is formed after the insulating resin layer 2 is formed on the surface of the peelable copper foil 5 on the front and back of the support 4 in FIG. As a method for forming the via hole 6, when a photosensitive insulating resin is used, processing by a photolithography method is possible, but when a non-photosensitive insulating resin is used, a convex portion corresponding to laser processing or a via hole is used. It is also possible to employ a method of pressing a mold having When the via hole is formed, the copper foil of the support 4 is exposed at the bottom of the via hole. If necessary, processing such as desmear may be performed.

  The insulating resin layer 2 can be formed on the front and back surfaces of the support 4 with a film or sheet insulating resin material using a vacuum laminator or a vacuum press.

  As the material of the insulating resin layer 2, an epoxy resin, an acrylic resin, a urethane resin, an epoxy acrylate resin, a phenol epoxy resin, a polyimide resin, a polyamide resin, a cyanate resin, an organic resin mainly composed of a liquid crystal resin, and these resins are made of glass. Alternatively, a material impregnated in a reinforcing fiber made of polyamide, liquid crystal, or the like may be used. Further, they may contain a filler such as silica, butyl organic material or calcium carbonate.

  FIG. 2C shows a state in which a wiring pattern including the pad electrode 7 is formed on the surface including the via hole 6 formed in FIG. As a method for forming the wiring pattern, a subtracting method or a semi-additive method can be employed.

  In FIG. 3D, the insulating resin layer 2 and the pad are formed by forming a multilayer wiring by repeating the formation of the insulating resin layer 2, the formation of the via hole 6, and the formation of the wiring pattern after FIG. 2C. After the multilayer wiring part 9 in which the wiring pattern including the electrode 7 is formed is formed on the front and back surfaces, a solder resist 8 is formed on the outermost surface, and an opening for exposing the pad electrode 7 is formed. .

  The solder resist 8 is formed by applying a solder resist ink with a roll coater or a screen printing apparatus, then putting it in a clean oven or the like to dry the solvent, volatilizing it to room temperature, and then forming a pattern by photolithography. Thus, after providing an opening in the pad electrode 7, it can be performed by performing thermal curing or UV curing as necessary as a curing process.

  FIG. 3 (e) shows a state where the multilayer wiring portions 9 on the front and back surfaces are peeled from the support 4 by the peelable copper foil 5 in FIG. 3 (d).

  The peeling from the support 4 can be performed by using the outer periphery of the support 4 in a structure in which a plurality of copper foils can be overlapped and separated without using the peelable copper foil 5. Even when an adhesive part is provided on the part, by cutting the outer peripheral part of the support 4, in the case of peelable copper foil, the adhesive surface is exposed, and in the case of a single metal plate, a slicer or water It can also be implemented in a structure having a region where a plurality of copper foils can be separated by being overlapped by dividing in the thickness direction with a cutter or the like.

  FIG. 3 (f) shows a state in which the ultrathin copper foil (thickness 2 to 5 μm) remaining in the portion facing the peelable copper foil of the multilayer wiring portion 9 on the front and back surfaces separated in FIG. 3 (e) is removed by wet etching. Is shown. At this time, the terminal formed at the portion corresponding to the bottom surface of the via hole formed first is exposed, and the top of the post electrode is exposed. The wet etching is performed so that the terminal (the top of the post electrode) is not excessively etched so that the portions of the insulating resin 2 and the pad electrode 7 facing the peelable copper foil 5 are flush with each other.

  In FIG. 3 (h), the insulating resin layer 2 was removed from the state of FIG. 3 (f), so that the pad electrode 7 was buried in the insulating resin layer 2 on the side facing the peelable copper foil 5. The state where the post electrode 3 that is an electrode protruding from the insulating resin layer 2 is formed by exposing the portion is shown. It is desirable that the insulating resin layer 2 be removed to a depth that does not expose the multilayer wiring portion 9.

As a method for removing the insulating resin layer 2, in addition to laser ablation, blasting methods such as sand blasting, wet blasting, and powder blasting, dry etching such as RIE (Reactive Ion Etching), IBE (Ion Beam Etching), etc. Also good. Laser ablation or blasting is suitable because it is easy to taper the insulating resin on the bottom side wall of the post electrode 3.
Further, the post electrode 3 may be subjected to a surface treatment such as Au / Ni, Au / Pd / Ni, Sn, OSP, or solder, as necessary.

  The shape of the post electrode 3 of the present invention is, for example, a truncated cone. The reason is that when the insulating resin layer 2 is laser processed, for example, to form a via hole, an inverted truncated cone is formed. Since the post electrode 3 is formed as a shape obtained by inverting it vertically, it becomes a truncated cone. Even when the via hole is formed by pressing the insulating resin layer using a mold, it cannot be processed unless it is an inverted truncated cone, so that the situation is the same as in the case of laser processing. Here, the shape of the post electrode 3 is not limited to a truncated cone, and may be any shape as long as the portion closer to the semiconductor chip from the circuit board 1 is thinner.

  In addition, the semi-additive method used to form a wiring pattern is to form a thin electroless plating layer over the entire insulating resin layer in which via holes are formed, and then form a resist pattern on the insulating resin layer and apply electrolytic plating. After that, the resist pattern is peeled off, and a thin electroless plating layer under the resist pattern is flash-etched to form a pad electrode and a wiring pattern. In this case, it is easy to peel off at the interface between electroless plating and electrolytic plating.

  On the other hand, in the present invention, since the post electrode 3 is formed only by electroplating, it does not peel off at the interface between the electroless plating layer and the electroplating layer that are easily peeled off. Further, since the portion of the post electrode buried in the insulating resin layer 2 is thicker than the exposed portion, the post electrode 3 is held by the insulating resin layer 2, and thus it is difficult to peel off and to fall easily. Become.

Next, the present invention will be described in more detail using examples.
<Example>
(Production of circuit board)
Using 0.4 mm thick FR-4 containing glass cloth as a core material, using 0.07 mm thick prepreg and peelable copper foil (ultra thin copper foil: 5 μm thickness, support copper foil: 18 μm) on the front and back surfaces, Lamination was carried out with the ultrathin copper foil side facing out, to form a support.
Next, an insulating resin layer was formed by laminating an insulating resin film (ABF-GX13: manufactured by Ajinomoto Co., Inc.) on the front and back surfaces of the support using a vacuum laminator.
Next, using a UV laser, a via hole having an inverted truncated cone shape having a bottom opening of φ45 μm and becoming thicker toward the surface of the insulating resin layer was formed.
Next, wiring was formed using a semi-additive method. The via hole was filled with copper plating.
In this example, a multilayer wiring portion was formed by repeating a series of steps from laminating an insulating resin film to forming a wiring by a semi-additive method and filling a via hole with copper plating so as to form a seven-layer wiring.
Next, a solder resist (PSR-4000 AUS700 series: manufactured by Taiyo Ink Co., Ltd.) is applied to the surface of the multilayer wiring portion on the front and back surfaces thus produced, dried at 70 ° C., and exposed to light. The opening of the pad electrode was formed by passing through a development process.
Next, after heat curing at 180 ° C., 1000 mJ / cm ² UV treatment was performed to insulate the solder resist.
Next, by cutting the outer peripheral portion of the article thus prepared using a slicer, the end of the interface between the ultra-thin copper foil of the peelable copper foil and the support copper foil is exposed and peeled off by the adhesive layer Then, the multilayer wiring parts on the front and back sides were separated.
The surface on the support side of the multilayer wiring portion exposed by this separation is in a state where an ultrathin copper foil (5 μm thickness) is exposed, and this was removed by wet etching. Thus, the copper terminal which is the bottom of the via hole was exposed.
Next, the exposed insulating resin layer on the copper terminal surface was removed from the surface with a thickness of 10 μm by laser ablation. Thus, the bottom of the exposed via hole is a post electrode. (Evaluation of circuit board)
The post electrode of the circuit board thus fabricated had a truncated cone shape that became thinner toward the top. A semiconductor chip was mounted on this circuit board, and a circuit board on which the semiconductor chip was further mounted was mounted on a printed wiring board, but no defect was found in the post electrode.

DESCRIPTION OF SYMBOLS 1 ... Circuit board 2 ... Insulating resin layer 3 ... Post electrode 4 ... Support body 5 ... Peelable copper foil 6 ... Via hole 7 ... Pad electrode 8 ... Solder resist 9 ... Multilayer wiring section

Claims (4)

  A post electrode formed on a circuit board for mounting a semiconductor chip, wherein the post electrode is thinner from the circuit board toward a portion closer to the semiconductor chip. Forming an insulating resin layer on the surface of the support;
A step of forming a via hole in the insulating resin layer, a step of forming a narrower via hole in a deeper portion;
Forming a pad electrode in the via hole and forming a multilayer wiring portion in the insulating resin layer;
Removing the support;
Removing the insulating resin layer to expose the pad electrode to form a post electrode;
A post electrode manufacturing method comprising:   The method for manufacturing a post electrode according to claim 2, wherein the step of exposing the post electrode is a step of removing the insulating resin layer by laser ablation.   A circuit board comprising the post electrode according to claim 1.