JP6076431B2 - Manufacturing method of semiconductor package substrate - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor package board having a cavity for mounting a semiconductor element is formed.

The following techniques are known as a method for forming a cavity for mounting a semiconductor element on a semiconductor package substrate.
In the first method, a copper foil with a copper bump is positioned and bonded to both sides of a substrate having wiring patterns formed on both sides of a resin substrate via a prepreg. At this time, the wiring pattern of the resin substrate and the copper bump are aligned and laminated so as to be electrically connected. Next, a wiring pattern connected to the copper bump is formed on the copper foil layer on the outer surface of the substrate by etching. Then, counterboring is performed from the opposite side of the wiring pattern connected to the copper bump, and the prepreg, the resin substrate, etc. are cut by a router to expose the copper bump at the bottom to form a cavity. After the semiconductor element is flip-chip connected to the cavity, underfill molding is performed to seal the semiconductor element with resin (see Patent Document 1).

  In the second method, an opening for forming a cavity is formed at a position where a semiconductor element is mounted on a substrate on which a copper foil is laminated, and a substrate having an internal connection terminal connected to the semiconductor element is laminated and bonded to the bottom of the cavity. This is a method for manufacturing a semiconductor package substrate in which a cavity is formed (see Patent Document 2).

JP 2004-31848 A JP 2002-43454 A

When the cavity is formed by counterboring by the router shown in Patent Document 1 described above, processing time is required and the corner portion R cannot be reduced. In addition, there are problems such as poor machining depth accuracy and poor cavity position accuracy.
In addition, as shown in Patent Document 2, when an opening is formed in a substrate on which copper foils are stacked, an expensive mold is required to cut out with a mold. Accuracy is required when a substrate having an opening is bonded to a substrate having no opening.
Furthermore, since the bottom of the cavity in which the cavity is formed is thinner and less rigid than the other substrate portions, there is a problem that deformation such as warpage, distortion, and undulation easily occurs.

An object of the present invention, the solve the problems of the prior art, short processing time of forming a cavity with respect to multi-layer substrate, a manufacturing method also high semiconductor package board accuracy of dimensional accuracy of the cavity is high yet machining depth Is to provide.

In order to achieve the above object, a semiconductor package substrate manufacturing method according to the present invention comprises the following arrangement. That is, a cavity bottom conductor pattern is formed on the inner layer using a copper foil in which a second copper foil layer is detachably laminated on a first copper foil layer on at least one surface of an insulating resin base material. A step of preparing a multilayer substrate in which a conductor layer is laminated on both sides via a material, etching on both sides of the multilayer substrate, and the cavity bottom conductor pattern via the insulating resin substrate and the resin substrate. Forming a conductor pattern having an opening above the outer edge of the cavity bottom conductor pattern in the conductor layer to be laminated; and an outer edge of the cavity bottom conductor pattern from above the resin base exposed from the opening of the multilayer substrate The resin base material and the insulating resin base material are removed by irradiating a laser beam along the portion, and a slit in which the cavity bottom conductor pattern is exposed at the bottom is formed around the slit. Removing the cavity bottom conductor pattern exposed in the slit by etching, and the resin base material and the insulating resin base material surrounded by the slit together with the first copper foil layer. And removing the second copper foil layer from the second copper foil layer to form a cavity in which the second copper foil layer is exposed at the bottom.

If the semiconductor package substrate manufacturing method described above is used, the slit is formed by irradiating laser light along the outer edge of the cavity bottom conductor pattern from above the resin base exposed from the opening of the multilayer substrate. The processing time required for laser processing can be shortened. Furthermore, since the processing of the laser beam is stopped by the cavity bottom conductor pattern, the processing depth accuracy of the cavity is increased.
The resin base material and the insulating resin base material surrounded by the slit where the cavity bottom conductor pattern is exposed are transferred from the second copper foil layer together with the first copper foil layer by transferring it to an adhesive tape or roller. It can be easily peeled off and removed, and the cavity can be easily formed.

A step of preparing a base substrate on which the copper foil is laminated on the first copper foil layer so that the second copper foil layer is peelable on at least one surface of the insulating resin base; Etching the base substrate to form a core substrate having the cavity bottom conductor pattern formed on at least one surface, and heating the copper foil on both surfaces of the core substrate via a semi-cured resin base material. a step of preparing the multilayer substrate by pressurizing, cured to form a hole penetrating the resin base material, as well as the product layer copper layers on both surfaces of the substrate continuously performed electroless copper plating and electrolytic copper plating And a step of copper-plating the through hole to make an electrical connection.
According to this, when preparing a multilayer substrate, the cavity bottom conductor pattern can be easily formed in advance on at least one surface of the base substrate serving as the inner layer.

In another method of manufacturing a semiconductor package substrate, a cavity bottom conductor is formed using a copper foil in which a second copper foil layer is detachably laminated on a first copper foil layer on at least one surface of an insulating resin base material. pattern has a guide body on which the conductor layer is laminated on the cavity bottom conductor pattern is formed, a first conductor pattern having a first opening above the outer edge of the cavity bottom conductor pattern on the other surface inner layer And a step of preparing a multilayer substrate in which a conductor layer is laminated on both sides via a resin base material, etching on both sides of the multilayer substrate, and a second opening above the first opening. Irradiating a laser beam along the outer edge of the cavity bottom conductor pattern from above the resin base exposed from the second opening of the multilayer substrate, A step portion of Aburamoto material and the insulating said the bottom of the resin base material is removed cavity bottom conductor pattern and the conductor layer to be laminated thereto to form orbiting the slit exposure, exposed in the slit The step of removing the first copper foil layer on the surface layer of the cavity bottom conductor pattern by etching; the resin base material surrounded by the slit; and the insulating resin base material together with the first copper foil layer And removing the second copper foil layer from the second copper foil layer to form a cavity in which the second copper foil layer is exposed at the bottom.

If the semiconductor package substrate manufacturing method described above is used, the resin substrate and the insulation can be obtained by irradiating the laser beam along the outer edge of the cavity bottom copper pattern from above the resin substrate exposed from the second opening of the multilayer substrate. Even if it is a multilayer board with multiple layers of conductor patterns, the cavity is shortened by removing the resin base material and forming it around the slit with the first conductor pattern including the cavity bottom conductor pattern exposed at the bottom. It can be processed accurately in time. Furthermore, since the laser beam is stopped by the first conductor pattern including the cavity bottom conductor pattern, the processing depth accuracy of the cavity is also increased.
Furthermore, since the thick conductor part which the 2nd copper foil layer exposed is formed in the cavity bottom part, the rigidity of a cavity bottom part can be improved.

A step of preparing a base substrate on which the copper foil is laminated on both sides of the insulating resin base material so that the second copper foil layer is peelable on the first copper foil layer; Etching to form a core substrate on which the cavity bottom conductor pattern is formed on one surface of the copper foil, and excluding the cavity bottom conductor pattern, and peeling off the second copper foil layer; and the insulating resin forming a hole penetrating the base, performed continuously electroless copper plating and electrolytic copper plating, the step of the copper layer on both surfaces of the substrate and the copper plating in the through-hole as well as a product layer to electrically connect Etching the core substrate to form the first conductor pattern having the first opening above the outer edge of the cavity bottom conductor pattern on the surface where the cavity is to be formed; and Core substrate A process of forming a multilayer by heating and pressurizing copper foil on both sides via a semi-cured resin base material, and a via hole having the first conductor pattern as a bottom in the resin base material laminated on both surfaces of the core substrate forming a continuously performed electroless copper plating and electrolytic copper plating in the copper foil laminated on both sides of the core substrate, the through the steps of the product layer the copper layer on the copper foil A multilayer substrate may be prepared.
Thereby, in the step of forming the multilayer substrate, a thick conductor portion in which the conductor layer is thickly laminated on the cavity bottom conductor pattern which is the inner layer can be easily formed.

A step of forming a multilayer by heating and pressurizing a copper foil on the second conductor pattern formed on both surfaces of the multilayer substrate via a semi-cured resin base material, and laminating on both surfaces of the multilayer substrate A step of forming a via hole having the second conductor pattern as a bottom in a resin base material, and electroless copper plating and electrolytic copper plating are continuously performed on both surfaces of the multilayer substrate, and a copper layer is stacked on the copper foil. And a step of etching on both surfaces of the multilayer substrate to form a third conductor pattern having a third opening above the second opening.
In this case, it is possible to provide a method for manufacturing a semiconductor package substrate that has a short processing time for forming a cavity, a high dimensional accuracy of the cavity, and a high processing depth accuracy even for a multilayer substrate having six or more layers. it can.

According to the method for manufacturing a semiconductor package substrate described above, it is possible to provide a method for manufacturing a semiconductor package substrate with a short processing time required for laser processing on a multilayer substrate, a high cavity outer shape accuracy, and a high processing depth accuracy. I can .

It is sectional drawing which shows the manufacturing process of the manufacturing method of the semiconductor package board | substrate which concerns on 1st Example. FIG. 2 is a cross-sectional view showing a processing step of the semiconductor package substrate manufacturing method following FIG. It is sectional drawing which shows the manufacturing process of the manufacturing method of the semiconductor package board | substrate which concerns on 2nd Example. FIG. 4 is a cross-sectional view showing a processing step of the semiconductor package substrate manufacturing method following FIG. It is sectional drawing of the semiconductor package board | substrate which shows the modification of FIG. It is sectional drawing of the semiconductor package board | substrate which shows the modification of FIG.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
With reference to FIGS. 1A to 1I and FIGS. 2J and 2K, a method for manufacturing a semiconductor package substrate will be described together with the configuration of the semiconductor package substrate. In the following description, a copper foil with a carrier is used as an example of a two-layer copper foil that can be peeled. The copper foil with a carrier is obtained by, for example, laminating a carrier copper foil (thickness: 18 μm; carrier foil) through an adhesive layer having a weak adhesive force that can be peeled off to an ultrathin copper foil (copper foil; thickness: 2 to 5 μm). (For example, F-HP; Heat-Resistant Peelable Copper Foil) is used.

[First embodiment]
First, in FIG. 1A, a base substrate 3 is prepared in which a carrier-added copper foil 2 is laminated on both surfaces (or one surface) of an insulating resin substrate 1 (for example, a glass epoxy substrate; FR-4). The copper foil 2 with a carrier is obtained by laminating a copper foil layer 2a (first copper foil layer) and a carrier copper foil layer 2b (second copper foil layer) called a carrier foil, for example, with a weak adhesive force capable of being peeled off. Is used. In the base substrate 3, the carrier-attached copper foil 2 is bonded to the copper foil layer 2a (first copper foil layer) bonded to the insulating resin base material 1 with the carrier copper foil layer 2b (second copper foil layer). It is. The carrier copper foil layer 2b can be easily separated from the copper foil layer 2a.

  As shown in FIG. 1B, the base substrate 3 is etched, and the core substrate 5 in which the cavity bottom conductor pattern 4 is formed on one surface (the lower surface in FIG. 1B) on the copper foil 2 with a carrier. Form. Etching is performed by laminating an etching resist having a pattern formed on the copper foil with carrier 2 of the base substrate 3.

  In FIG. 1C, a copper foil 7 (conductor layer; thickness: 2 to 5 μm) is superposed on both surfaces of the core substrate 5 via a semi-cured resin base material 6 (for example, prepreg), and heated and pressed to form a multilayer substrate 8. (Laminate press). At this time, the semi-cured resin substrate 6 is cured by being heated and pressurized to become a cured resin substrate 6 (for example, a thickness of 60 μm).

  In FIG. 1D, the multilayer substrate 8 is etched, and the conductor pattern is formed on the substrate surface on one side (the lower surface in FIG. 1D) on which the cavity bottom conductor pattern 4 is formed with the insulating resin base material 1 as the center. A conductor having an opening 9 above the outer edge portion of the cavity bottom conductor pattern 4 in the copper foil 7 formed on the substrate surface opposite to the cavity bottom conductor pattern 4 (upper surface in FIG. 1D). Each pattern 10a is formed. Since the opening 9 only needs to be formed at a position where laser processing is performed later, the conductor pattern 10 a may remain in the opening 9.

  Next, as shown in FIG. 1E, the laser beam 11 is irradiated along the outer edge portion of the cavity bottom conductor pattern 4 from above the cured resin substrate 6 exposed from the opening 9 of the multilayer substrate 8. Specifically, an alignment mark is formed at an appropriate position on the same surface as the cavity bottom conductor pattern 4 of the core substrate 5, the multilayer substrate 8 is formed by a lamination press, and then the alignment mark of the core substrate 5 is formed by an X-ray drilling machine. Recognize and drill holes. The laser processing apparatus recognizes this hole as an alignment mark and irradiates the laser beam 11 along the outer edge of the cavity bottom conductor pattern 4 from above the cured resin substrate 6. As the laser beam 11, a carbon dioxide laser having a high energy level is preferably used.

Thereby, as shown in FIG. 1 (F), the cured resin base material 6 and the insulating resin base material 1 at the laser light irradiation position are removed, and the slit 12 where the outer edge portion of the cavity bottom conductor pattern 4 is exposed at the bottom is circulated. Can be formed.
At this time, the processing time required for the laser processing for forming the slit 12 around the multilayer substrate 8 is short, and the corner portion R can be processed small. Further, even if the multilayer substrate 8 is irradiated with the laser beam 11, the laser processing is stopped by the first conductor pattern including the cavity bottom conductor pattern 4, so that the finally formed cavity 13 (see FIG. 1 (I)). ) Processing depth accuracy is high.

  Here, in FIG. 1G, in order to remove the cured resin base material 6 and the insulating resin base material 1 surrounded by the slits 12 of the multilayer substrate 8, the cavity bottom conductor pattern 4 (copper copper) exposed at the bottom of the slits 12 is removed. The foil layer 2a and the carrier copper foil layer 2b) are removed by etching to expose the cured resin substrate 6.

In FIG. 1H, the cured resin base material 6 and the insulating resin base material 1 surrounded by the slits 12 are peeled off from the multilayer substrate 8 and removed. Specifically, the adhesive tape is attached to the substrate and peeled off to peel off the copper foil layer 2a forming the cavity bottom conductor pattern 4 from the carrier copper foil layer 2b, and the cured resin base 6 and insulating resin base Material 1 is transferred to an adhesive tape.
As a result, a cavity 13 in which the carrier copper foil layer 2b remains in the cavity bottom conductor pattern 4 is formed in the multilayer substrate 8.

  Next, as shown in FIG. 2J, a solder resist is coated on both surfaces of the multilayer substrate 8 excluding the cavity 13 (for example, a dry film resist is laminated and a pattern is formed by photolithography). Specifically, the conductor pattern 10a formed on one substrate surface is coated with the solder resist 14a, and the conductor pattern 10b formed on the other substrate surface is coated with the solder resist 14b.

  Finally, as shown in FIG. 2K, surface treatment is performed on both sides of the substrate. Specifically, the semiconductor package substrate 15 in which the plating layer 17 is formed by performing nickel plating and gold plating on the conductor patterns 10a and 10b exposed from the solder resists 14a and 14b and the conductor pattern 2b at the bottom of the cavity is formed. Manufactured (surface treatment). In the cavity 13 formed in the semiconductor package substrate 15, electronic components such as semiconductor elements and various sensors are arranged.

If the method for manufacturing the semiconductor package substrate 15 described above is used, the multilayer substrate 8 is irradiated with the laser light 11 along the outer edge portion of the cavity bottom conductor pattern 4 from above the cured resin base material 6 to circulate around the slit 12. By forming them, the processing time required for laser processing can be shortened. Further, by reducing the beam diameter of the laser beam 11, the corner portion R can be reduced. Further, the laser beam 11 is stopped by the cavity bottom conductor pattern 4, so that the processing depth accuracy of the cavity 13 is also increased. .
Further, the cured resin base material 6 and the insulating resin base material 1 surrounded by the slit 12 where the cavity bottom conductor pattern 4 is exposed can be easily transferred from the carrier copper foil layer 2b together with the copper foil layer 2a by transferring it to an adhesive tape. The cavity 13 can be easily formed.

[Second Embodiment]
Next, another example of the method for manufacturing the semiconductor package substrate will be described with reference to FIGS. 3 (A) to (N) and FIGS. 4 (O) to (Q). In addition, the same number is attached | subjected to the same member as 1st Example, and description shall be used.
First, in FIG. 3A, the carrier-attached copper foil 2 in which the carrier copper foil layer 2b is bonded to the copper foil layer 2a with an adhesive force capable of being peeled on both surfaces of the insulating resin substrate 1 (for example, FR-4). A base substrate 3 that is laminated is prepared. In the base substrate 3, the carrier-attached copper foil 2 is a carrier copper foil layer 2 b (second copper foil) called a carrier foil on a copper foil layer 2 a (first copper foil layer) bonded to the insulating resin substrate 1. Layer). The carrier copper foil layer 2b can be peeled off more easily than the copper foil layer 2a.

  Next, as shown in FIG. 3 (B), the base substrate 3 is etched so that the bottom conductor pattern 4 of the cavity is formed on the copper foil 2 with a carrier in the slit 2c on one substrate surface (the lower surface in FIG. 3 (B)). It is formed in an enclosed island shape. In this state, when the carrier copper foil layer 2b is peeled from the copper foil layer 2a on both sides of the base substrate 3, the carrier copper foil 2b remains only in the cavity bottom conductor pattern 4, as shown in FIG. The core substrate 5 having only the copper foil layer 2a is formed in the other portions except the slit 2c. That is, in the core substrate 5, the cavity bottom conductor pattern 4 is formed on one substrate surface (the lower surface in FIG. 3C) by the thickness of the carrier copper foil layer 2b.

  Next, as illustrated in FIG. 3D, a through hole 2 d is formed in the insulating resin base material 1 of the core substrate 5. The through hole 2d is drilled by a carbon dioxide laser or the like. Note that when the core substrate 5 is manufactured, the through-holes 2 d may be formed in the insulating resin base material 1 in advance. Next, as shown in FIG. 3E, electroless copper plating and electrolytic copper plating are performed on both surfaces of the core substrate 5 to form a copper layer 2e on the copper foil layer 2a, the slit 2c and the cavity bottom conductor pattern 4. The through hole 2d is filled with a copper layer (plating process). Thereby, electrical conduction can be established between the conductor layers made of the copper foil layer 2a and the copper layer 2e formed on both surfaces of the core substrate 5, and one of the substrate surfaces of the core substrate 5 (FIG. 3E ), The portion of the cavity bottom conductor pattern 4 formed on the lower surface is in a state in which the thickness of the copper layer is increased by the thickness of the carrier copper foil layer 2b as compared with the surrounding copper foil layer 2a.

  In FIG. 3 (F), etching is performed on both surfaces of the core substrate 5, and the first conductor pattern 10d (inner layer) is formed on one substrate surface (the lower surface in FIG. 3 (F)) on which the cavity bottom conductor pattern 4 is formed. The first conductor pattern 10c (inner layer conductor pattern) having the first opening 9a on the other substrate surface (upper surface in FIG. 3F) is formed. At this time, the copper layer 2e (conductor layer) is thickened on the conductor pattern 4 at the bottom of the cavity.

  Next, as shown in FIG. 3 (G), copper foils 7 (conductor layers) are respectively stacked on both sides of the core substrate 5 via a semi-cured resin base material 6 (for example, prepreg), and heated and pressed to form the multilayer substrate 8. Form (lamination press). At this time, the semi-cured resin substrate 6 becomes the cured resin substrate 6 by the lamination press.

  Next, as shown in FIG. 3H, the via hole 10e having the first conductor pattern 10c as the bottom or the first conductor pattern 10d as the bottom in the cured resin base material 6 laminated on both sides of the multilayer substrate 8 is used. Each via hole 10f is formed. The via holes 10e and 10f are drilled by a carbon dioxide laser or the like. Laser processing of the laser beam 11 is stopped by the first conductor pattern 10c or the first conductor pattern 10d. Next, as shown in FIG. 3 (I), electroless copper plating and electrolytic copper plating are continuously performed on both surfaces of the multilayer substrate 8 to thicken the copper layer 2 e (conductor layer) on the copper foil 7.

  Next, in FIG. 3J, the multilayer substrate 8 is etched to form a second conductor pattern 10h (outer layer conductor pattern) on one substrate surface (the lower surface in FIG. 3J), and the other substrate. Second conductor patterns 10g (outer layer conductor patterns) each having a second opening 9c immediately above the first opening 9a are formed on the surface (the upper surface in FIG. 3J). A second conductor pattern 10g (outer layer conductor pattern) may be formed in the second opening 9c.

  Next, in FIG. 3K, the laser beam 11 is irradiated along the outer edge portion of the cavity bottom conductor pattern 4 from above the cured resin base 6 exposed from the second opening 9 c of the multilayer substrate 8. Specifically, an alignment mark is formed at an appropriate position on the same surface as the cavity bottom conductor pattern 4 of the core substrate 3, the multilayer substrate 8 is formed by a lamination press, and then the alignment mark of the core substrate 3 is formed by an X-ray drilling machine. Recognize and drill holes. The laser processing apparatus recognizes this hole as an alignment mark and irradiates the laser beam 11 along the outer edge of the cavity bottom conductor pattern 4 from above the cured resin substrate 6. As the laser beam 11, a carbon dioxide laser having a high energy level is preferably used.

Thereby, as shown in FIG. 3 (L), the first resin pattern 10d (inner layer conductor) including the cavity bottom conductor pattern 4 at the bottom by removing the cured resin substrate 6 and the insulating resin substrate 1 at the laser light irradiation position. It can be formed by circling the slit 12 where the pattern) is exposed.
At this time, the processing time required for the laser processing for forming the slit 12 around the multilayer substrate 8 is short, and the corner portion R can be processed small. Even when the multilayer substrate 8 is irradiated with the laser beam 11, the laser processing is stopped by the first conductor pattern 10 d (inner layer conductor pattern) including the cavity bottom conductor pattern 4, so that the finally formed cavity 13 ( The processing depth accuracy shown in FIG.

  Next, as shown in FIG. 3 (M), at least the copper foil layer 2a of the first conductor pattern 10d (inner layer conductor pattern) exposed in the slit 12 is soft-etched (for example, sulfuric acid-hydrogen peroxide etchant). Remove with.

Next, in FIG. 3N, the cured resin base material 6 and the insulating resin base material 1 surrounded by the slits 12 are peeled off from the multilayer substrate 8 and removed. Specifically, the adhesive tape is attached to the substrate and peeled off to peel off the copper foil layer 2a forming the cavity bottom conductor pattern 4 from the carrier copper foil layer 2b, and the cured resin base 6 and insulating resin base Material 1 is transferred to an adhesive tape.
As a result, as shown in FIG. 4 (O), the cavity 13 is formed in the multilayer substrate 8 as the cavity bottom conductor pattern 4 where the carrier copper foil layer 2b and the first conductor pattern 10d (copper layer 2e) surrounding it are exposed. The

  Next, as shown in FIG. 4P, a solder resist is coated on both surfaces of the multilayer substrate 8 excluding the cavity 13 (for example, a dry film resist is laminated and a pattern is formed by photolithography). Specifically, the second conductor pattern 10h formed on one substrate surface (the lower surface in FIG. 4 (P)) was coated with a solder resist 14b, and formed on the other substrate surface (the upper surface in FIG. 4 (P)). The second conductor pattern 10g is coated with a solder resist 14a.

Finally, as shown in FIG. 4Q, surface treatment is performed on both sides of the substrate. Specifically, the semiconductor package in which the plated layer 17 is formed by performing nickel plating and gold plating on the second conductor patterns 10g and 10h exposed from the solder resists 14a and 14b and the conductor pattern 10d at the bottom of the cavity, respectively. A substrate 18 is manufactured.
In the cavity 13 formed in the semiconductor package substrate 18, electronic components such as semiconductor elements and various sensors are arranged.

  Since the semiconductor package substrate 18 is formed with a conductor layer in which the carrier copper foil layer 2b and the copper layer 2e are thickened on the outermost layer of the cured resin base material 6 forming the bottom of the cavity 13, the plate at the bottom of the cavity Even if the thickness is small, the rigidity is increased, so that deformation such as warpage, distortion, and undulation hardly occurs.

In addition, although the said semiconductor package board | substrate 18 illustrated about the 4 layer board, it may be formed in the multilayer further.
Specifically, returning to FIG. 3 (G) after FIG. 3 (J), the copper foil 7 is overlapped on both surfaces of the multilayer substrate 8 via the semi-cured resin base material 6 on the second conductor patterns 10g and 10h. And pressurizing and laminating and forming via holes having the second conductor patterns 10g and 10h as bottom portions in the cured resin base material 6 laminated on both surfaces of the multilayer substrate 8 shown in FIG. Electroless copper plating and electrolytic copper plating are continuously performed on both surfaces of the multilayer substrate 8 shown in (I) to thicken the copper layer 2e (conductor layer) on the copper foil 7, and then shown in FIG. In this way, a six-layer plate may be formed by further etching the both surfaces of the substrate to form a third conductor pattern having a third opening on the substrate surface immediately above the second opening 9c. Further, it is also possible to stack in multiple layers (8 layers or more) by repeating the steps of FIGS. 3 (G) to 3 (J). To become.

In addition, although the said semiconductor package board | substrate was illustrated about the case where the base board | substrate 3 is made into a 2 layer board, it can also be made into a multilayer board | substrate. The structure in the case where the base substrate 3 is a four-layer plate is shown in FIGS.
FIG. 5 illustrates a semiconductor package substrate 15 ′ having a six-layer structure with the base substrate 3 of FIG. A deep cavity 19 is formed in the semiconductor package substrate 15 '. The interlayer connection of the semiconductor package substrate 15 ′ is performed by forming a through-hole plating 20 on the inner wall of the through-hole, and the through-hole is filled with a hole-filling resin 21, for example, an epoxy resin filled with a high-density filler. Done. The outermost conductor patterns 10a 'and 10b' are covered with solder resists 14a and 14b, and nickel plating is applied to the conductor patterns 10a 'and 10b' exposed from the solder resists 14a and 14b and the conductor pattern 2b at the bottom of the cavity. The plating layer 17 is formed by performing gold plating.

  FIG. 6 illustrates a semiconductor package substrate 18 ′ having a six-layer structure with the base substrate 3 of FIG. 4Q having a four-layer structure. A deep cavity 22 is formed in the semiconductor package substrate 18 '. Interlayer connection of the semiconductor package substrate 18 'is performed by filling the via hole with copper plating. The outermost conductor patterns 10g 'and 10h' are coated with solder resists 14a and 14b, and nickel plating is applied to the conductor patterns 10g 'and 10h' exposed from the solder resists 14a and 14b and the conductor pattern 2b at the bottom of the cavity. The plating layer 17 is formed by performing gold plating.

  As described above, by forming the base substrate 3 on which the cavity bottom pattern is formed as a multilayer board having two or more layers, an arbitrary layer can be used as the bottom of the cavity, and a cavity having a desired depth can be formed in the semiconductor package substrate. Can be formed.

In this embodiment, the hole forming process of the resin base material layer is performed with a carbon dioxide gas laser, but the same process can be performed using another laser such as a UV-YAG laser.
Moreover, although the case where the plating process performed copper plating was demonstrated, not only copper but other electroconductive metal plating, such as a copper alloy, may be sufficient.
The conductor pattern formed on the bottom of the cavity 13 may be used as a terminal on which a semiconductor chip is mounted and electrically connected, or may be used as a heat sink for heat dissipation.
In addition, as the two layers of copper foil (copper foil 2 with carrier) laminated on the insulating resin base material 1, a copper foil layer 2 a bonded to the carrier copper foil layer 2 b was used. The layer may be inverted and the carrier copper foil layer 2b (first copper foil layer) may be adhered to the insulating resin substrate 1 and the copper foil layer 2a (second copper foil layer) may be bonded. .

  DESCRIPTION OF SYMBOLS 1 Insulation resin base material 2 Copper foil with a carrier 2a Copper foil layer 2b Carrier copper foil layer 2c, 12 Slit 2d Through-hole 2e Copper layer 3 Base substrate 4 Cavity bottom conductor pattern 5 Core substrate 6 Semi-cured resin substrate (cured resin base Material) 7 copper foil 8 multilayer substrate 9 opening 9a first opening 9c second opening 10a, 10b, 10a ′, 10b ′, 10g ′, 10h ′ conductor pattern 10c, 10d first conductor pattern (inner layer conductor pattern) 10e , 10f Via hole 10g, 10h Second conductor pattern (outer layer conductor pattern) 11 Laser light 13, 19, 22 Cavity 14a, 14b Solder resist 17 Plating layer 15, 15 ', 18, 18' Semiconductor package substrate 20 Through-hole plating 21 Hole filling resin

Claims (5)

A cavity bottom conductor pattern is formed on the inner layer using a copper foil in which the second copper foil layer is peelably laminated on the first copper foil layer on at least one surface of the insulating resin base material. the conductor layer via the higher engineering prepare a multilayer substrate which is laminated on both sides,
Etching is performed on both surfaces of the multilayer substrate, and an opening is provided above the outer edge of the cavity bottom conductor pattern in the conductor layer laminated on the cavity bottom conductor pattern via the insulating resin substrate and the resin substrate. Forming a conductor pattern;
The resin base material and the insulating resin base material are removed by irradiating laser light along the outer edge portion of the cavity bottom conductor pattern from above the resin base material exposed from the opening of the multilayer substrate, and the bottom portion Forming the cavity bottom conductor pattern around the exposed slit,
Removing the cavity bottom conductor pattern exposed in the slit by etching;
The resin base material and the insulating resin base material surrounded by the slit are peeled off from the second copper foil layer together with the first copper foil layer, and the second copper foil layer is exposed at the bottom. Forming a cavity,
A method for manufacturing a semiconductor package substrate, comprising: Preparing a base substrate in which the copper foil is laminated on the first copper foil layer so that the second copper foil layer can be peeled off on at least one surface of the insulating resin base;
Etching the base substrate to form a core substrate having the cavity bottom conductor pattern formed on at least one surface;
A step of preparing the multilayer substrate by heating and pressurizing copper foils on both sides of the core substrate via a semi-cured resin base material, respectively;
The holes through the cured the resin base material to form a copper layer on both surfaces of the substrate continuously performed electroless copper plating and electrolytic copper plating to electrically and copper plating the through-holes as well as the product layer A process of establishing a connection;
The manufacturing method of the semiconductor package substrate of Claim 1 containing this. A cavity bottom conductor pattern is formed on at least one surface of the insulating resin base material using a copper foil in which a second copper foil layer is peelably laminated on a first copper foil layer, and a conductor is formed on the cavity bottom conductor pattern. It has an electrical body which layers are laminated, above the outer edge of the cavity bottom conductor pattern on the other surface each have a first conductor pattern having a first opening in the inner layer through the resin substrate Preparing a multi-layer substrate having conductor layers laminated on both sides;
Etching both surfaces of the multilayer substrate to form second conductor patterns each having a second opening above the first opening; and
The resin base material and the insulating resin base material are removed by irradiating laser light along the outer edge of the cavity bottom conductor pattern from above the resin base material exposed from the second opening of the multilayer substrate. a step portion of the conductor layer to be laminated said cavity bottom conductor pattern and to the bottom portion is formed by orbiting the slit exposure,
Removing the first copper foil layer of the surface layer of the cavity bottom conductor pattern exposed in the slit by etching;
The resin base material and the insulating resin base material surrounded by the slit are peeled off from the second copper foil layer together with the first copper foil layer, and the second copper foil layer is exposed at the bottom. Forming a cavity,
A method for manufacturing a semiconductor package substrate, comprising: Preparing a base substrate on which the copper foil is laminated on the first copper foil layer so that the second copper foil layer is peelable on both surfaces of the insulating resin base;
Etching the base substrate to form a core substrate on which the cavity bottom conductor pattern is formed on one surface of the copper foil, and excluding the cavity bottom conductor pattern, and peeling off the second copper foil layer; ,
Said insulating resin base material hole is formed to penetrate, the electroless copper plating and electrolytic copper plating is performed continuously, electrically connecting the copper layers on both surfaces of the substrate and the copper plating in the through-hole as well as a product layer A process of taking
Etching the core substrate to form the first conductor pattern having the first opening above the outer edge of the cavity bottom conductor pattern on the surface where the cavity is formed;
A process of forming a multilayer by heating and pressing a copper foil on both sides of the core substrate through a semi-cured resin base material,
Forming a via hole having the first conductor pattern as a bottom in the resin base material laminated on both surfaces of the core substrate;
Performed continuously electroless copper plating and electrolytic copper plating in the copper foil laminated on both sides of the core substrate, wherein providing the multi-layer substrate through the steps of the product layer the copper layer on the copper foil Item 4. A method for manufacturing a semiconductor package substrate according to Item 3. A step of forming a multilayer by heating and pressurizing a copper foil over a semi-cured resin base material on the second conductor pattern formed on both surfaces of the multilayer substrate; and
Forming a via hole having the second conductor pattern as a bottom in the resin base material laminated on both surfaces of the multilayer substrate;
Performed continuously electroless copper plating and electrolytic copper plating on both surfaces of the multilayer substrate, a step of a product layer of copper layer on the copper foil,
5. The semiconductor package substrate according to claim 3, further comprising a step of etching the both surfaces of the multilayer substrate to form a third conductor pattern having a third opening above the second opening. Production method.