JP2015088544A - Method for manufacturing printed wiring board, and printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board which makes possible to solve the problem of the worsening of the reliability of connection between conductor circuits connected through via conductors.SOLUTION: A method for manufacturing a printed wiring board comprises the steps of: preparing an insulator layer which includes a reinforcement layer containing a reinforcement material, and a resin layer formed on the reinforcement layer, and not including the reinforcement layer; laminating a first metal foil onto the resin layer of the insulator layer; forming, by laser irradiation, through-holes piercing the first metal foil and the insulator layer; removing the first metal foil from the insulator layer; forming a conductor layer on the resin layer of the insulator layer; and forming a via conductor in each through-hole.

Description

  The present invention relates to a method for manufacturing a printed wiring board and a printed wiring board.

  Patent document 1 is disclosing the manufacturing method of a circuit board. According to FIG. 1 of Patent Document 1, the manufacturing method of Patent Document 1 includes preparing a double-sided copper-clad laminate, forming a via hole in an insulating substrate by a conformal mask method, and applying a desmear to the via hole. Processing and forming a plating layer in the via hole. And performing a desmear process includes forming a protrusion part in copper foil, as FIG. 1 (B) of patent document 1 shows. The conformal mask method is disclosed in Patent Document 2, for example.

  Since patent document 1 has the protrusion part of copper foil, when a via conductor is formed by electroplating in a via hole, as shown in FIG. 1 (C) of patent document 1, the protrusion part of copper foil An electrolytic plating layer is also formed on the edges of the film. Since the plating solution is supplied into the via hole through the opening of the copper foil, it is considered that the deposition rate of the plating deposited in the protruding portion is faster than the deposition rate of the plating deposited in the via hole. Therefore, when the plating layer is formed in the via hole by the method shown in FIG. 1 of Patent Document 1, the opening formed in the copper foil is closed by plating before the via hole is filled with plating. Conceivable. In that case, it is assumed that voids are generated in the plating layer in the via hole. In particular, it is considered that voids are generated at the corners surrounded by the protruding portion of the copper foil and the inner wall of the via hole.

It is considered that the plating solution remains in the via hole when the opening of the copper foil is closed. When using a printed wiring board, corrosion of the via conductor may occur due to the plating solution in the via hole. It is speculated that via conductor breakage may occur due to corrosion.
If voids remain in the via conductor, the cross-sectional area of the via conductor is locally reduced. The electrical resistance of the part becomes high. It is considered that there is a delay in supplying power to the IC chip. If a via conductor including a void is included in the inductor circuit, it is expected that a desired inductance and Q value cannot be obtained.

JP 2010-232590 A JP 2000-124605 A

  An object of the present invention is to ensure connection reliability between conductor circuits connected through via conductors. Another object is to reduce the resistance of the circuit containing the via conductor. Yet another object is to reduce the diameter of the via conductor.

  The method for producing a printed wiring board of the present invention comprises preparing an interlayer resin insulating layer comprising a reinforcing layer including a reinforcing material and a resin layer formed on the reinforcing layer and not including the reinforcing layer, and the interlayer resin. Laminating a first metal foil on the resin layer of the insulating layer, forming a through-hole penetrating the first metal foil and the interlayer resin insulating layer with a laser, and attaching the first metal foil to the interlayer Removing from the resin insulation layer, forming a conductor layer on the resin layer of the interlayer resin insulation layer, and forming a via conductor in the through hole.

A reinforcing layer including a reinforcing material is prepared, and forming a resin layer on the reinforcing layer includes a reinforcing layer including the reinforcing material and a resin layer that is formed on the reinforcing layer and does not include the reinforcing layer. It is included in preparing an interlayer resin insulation layer.
Also, an interlayer resin insulation layer with a metal foil comprising an interlayer resin insulation layer and a metal foil laminated on the interlayer resin insulation layer is prepared, and then a through-hole penetrating the metal foil and the interlayer resin insulation layer is formed. May be.

  The printed wiring board of the present invention includes a reinforcing layer including a reinforcing material, an insulating layer formed on the reinforcing layer and including a resin layer not including the reinforcing layer, and a first seed formed on the resin layer. And a first conductor layer formed of a first electroplating layer on the first seed layer and a second electrolysis formed on the reinforcing layer and on the metal foil, the second seed layer, and the second seed layer. A second conductor layer formed of a plating layer, penetrating the insulating layer, connecting the first conductor layer and the second conductor layer, the first seed layer and the first electrolytic plating layer being And a via conductor formed.

(A)-(e) is sectional drawing which shows typically each process in the manufacturing method of the printed wiring board of one Embodiment of this invention. (A)-(c) is sectional drawing which shows typically each process in the manufacturing method of the printed wiring board of embodiment. (A)-(e) is sectional drawing which shows typically each process in the manufacturing method of the printed wiring board of embodiment. Sectional drawing which shows typically the core board | substrate of the printed wiring board of embodiment. Sectional drawing which shows typically the multilayer printed wiring board of one Embodiment of this invention. Sectional drawing which shows typically the example of application of the multilayer printed wiring board of one Embodiment of this invention.

  Below, the manufacturing method and printed wiring board of the printed wiring board of one Embodiment of this invention are demonstrated in detail. FIG. 5 is a cross-sectional view schematically showing the multilayer printed wiring board 1 of the embodiment, and FIG. 6 shows an application example of the multilayer printed wiring board 1 of the embodiment. In the application example, electronic components 70 and 700 such as IC chips are mounted on the multilayer printed wiring board 1.

  A multilayer printed wiring board 1 shown in FIG. 5 is formed on a first core F having a first surface F and a second surface S opposite to the first surface, and on the first surface F of the multilayer core substrate 2. The first buildup layer 3U and the second buildup layer 3D formed on the second surface S of the multilayer core substrate 2 are included.

FIG. 4 shows the multilayer core substrate 2. As shown in FIG. 4, the multilayer core substrate 2 has a double-sided plate 10 at the center in the stacking direction. A plurality of resin insulation layers (insulation layers) 30 and a plurality of conductor layers 44 are laminated on both surfaces of the double-sided board 10. In FIG. 4, four resin insulation layers 30 and four conductor layers 44 are laminated on both sides of the double-sided board 10.
1 and 2 show a method for manufacturing the double-sided board 10 of the multilayer core substrate 2.

(1) In order to manufacture the double-sided board 10, the insulating layer 11 with metal foil shown by Fig.1 (a) is prepared. In Fig.1 (a), the insulating layer 11 with metal foil is a double-sided copper clad laminated board. The double-sided copper clad laminate 11 has a resin insulating layer (first insulating layer) 14 formed of a reinforcing layer 12 including a reinforcing material and a resin layer 13 formed on the reinforcing layer 12 and not including the reinforcing layer. The first insulating layer (resin insulating layer) 14 has a first surface FF and a second surface SS opposite to the first surface.
The double-sided copper clad laminate 11 is further laminated on the copper foil as the first metal foil 16 laminated on the first surface FF of the first insulating layer 14 and the second surface SS of the first insulating layer 14. It has a copper foil as the second metal foil 17. The insulating layer 11 with metal foil is made by laminating metal foil on the first surface FF and the second surface SS of the first insulating layer 14.

The reinforcing layer 12 is formed of a reinforcing material such as glass cloth and a resin such as epoxy. The reinforcing layer 12 preferably further contains inorganic particles such as silica.
The thickness of the reinforcing layer 12 is desirably 100 μm or less, and more desirably within a range of 30 to 70 μm. When the thickness exceeds 100 μm, the thickness of the printed wiring board increases.

The resin layer 13 is formed of a resin such as epoxy. The resin layer 13 does not include a reinforcing material such as fiber, but preferably includes inorganic particles such as silica. The thickness of the resin layer 13 is 5 μm to 20 μm, and the ratio of the thickness of the resin layer 13 to the thickness of the reinforcing layer 12 (thickness of the resin layer 13 / thickness of the reinforcing layer 12) is 1/3 to 1/10.
A rough surface can be formed on the resin layer 13. Therefore, a seed layer described later can be directly formed on the resin layer 13.
By forming the resin layer 13 on the reinforcing layer 12, a fine conductor circuit can be formed on the first surface FF of the first insulating layer 14.
The thickness of the 1st metal foil 16 and the 2nd metal foil 17 is 1-5 micrometers.

(2) Next, the first metal foil 16 is directly irradiated with a laser such as a carbon dioxide laser. A via conductor opening 18 that penetrates the first metal foil 16 and the first insulating layer 14 and reaches the second metal foil 17 is formed (see FIG. 1B).
In the embodiment, a direct laser method is used.

Laser processing is performed, for example, by a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions are shown below. For example, the pulse energy is 0.5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, and the number of shots is in the range of 2 to 10. The diameter of the via conductor opening 18 formed under these processing conditions is 50 to 250 μm.
At this time, the first metal foil 16 is harder to be processed by the laser than the first insulating layer 14. As a result, as shown in FIG. 1B, the diameter of the opening 18 formed in the first metal foil 16 is smaller than the diameter of the opening 18 formed in the first insulating layer 14. The outer periphery of the opening of the first insulating layer 14 is covered with a first metal foil 16. The first metal foil 16 protrudes over the opening 18 of the first insulating layer 14. The first metal foil 16 protruding on the opening 18 of the first insulating layer 14 is called eaves.

(3) Next, a desmear process is performed in order to remove the resin residue which exists in the side wall and bottom face of the opening 18. At this time, the inner wall of the opening 18 is roughened.
The desmear process is performed, for example, with a chemical solution or plasma.

(4) Next, the second metal foil 17 is covered with a protective film. Thereafter, the first metal foil 16 is removed by etching (FIG. 1C). At this time, the matte surface of the first metal foil 16 is transferred to the resin layer 13. A rough surface is formed on the resin layer 13. Further, the thickness of the second metal foil 17 exposed from the via conductor opening 18 is reduced by etching. In order to increase the connection reliability between the via conductor and the conductor layer, the thickness of the second metal foil 17 is preferably thicker than the thickness of the first metal foil 16. When the ratio of the thickness of the second metal foil 17 to the thickness of the first metal foil 16 (thickness of the second metal foil 17 / thickness of the first metal foil 16) is 1.3 to 1.5, the connection reliability Is expensive. In addition, fine conductor circuits can be formed on both surfaces of the first insulating layer 14.
As a result, the first metal foil (eave) 16 existing on the opening 18 of the first insulating layer 14 shown in FIG. 1B disappears. Electrolytic plating solution tends to enter the via conductor opening 18. Replacement of the plating solution in the via conductor opening 18 is likely to occur. It becomes easy to fill the opening 18 for the via conductor with the plating film.

(5) Next, the protective film on the second metal foil 17 is removed. Then, by the electroless copper plating process, on the copper foil 17 formed on the second surface SS of the first insulating layer 14, the first surface FF of the first insulating layer 14, and the inner wall of the opening 18. Then, a seed layer 20 such as an electroless copper plating film is formed (FIG. 1D). The thickness of the electroless copper plating film 20 is, for example, 0.5 μm to 2 μm. The electroless copper plating film 20 is formed directly on the resin layer 13. The electroless copper plating film 20 is formed on the rough surface of the resin layer 13.
The seed layer 20 on the first surface FF is a first seed layer, and the seed layer 20 on the second surface SS is a second seed layer.

(6) Subsequently, electrolytic copper plating film 22 is formed on electroless copper plating film 20 by electrolytic copper plating treatment. At this time, the via conductor 24 is formed in the opening 18 for the via conductor. The thickness of the electrolytic copper plating film 22 is 5 μm to 20 μm. Since the eaves are removed in the previous step, the plating solution easily reaches the bottom of the opening 18. In addition, a fresh plating solution can be supplied into the opening 18. The stagnation of the plating solution is reduced in the opening 18. Therefore, the opening 18 is filled with the electrolytic plating film.
The electrolytic copper plating film 22 on the first surface FF is a first electrolytic plating layer, and the electrolytic copper plating film 22 on the second surface SS is a second electrolytic plating layer.

(7) Next, an etching resist layer 26 is formed on the electrolytic copper plating film 22 (FIG. 2A).
(8) Next, the conductor exposed from the etching resist layer 26 is removed by etching (FIG. 2B). At this time, the electroless copper plating film 20 and the electrolytic copper plating film 22 formed on the first surface FF of the first insulating layer 14 are removed. The copper foil 17, the electroless copper plating film 20, and the electrolytic copper plating film 22 formed on the second surface SS of the first insulating layer 14 are removed.

(9) Thereafter, the etching resist layer 26 is removed. The double-sided board 10 is completed (FIG. 2 (c)). A first conductor layer 28 is formed on the first surface FF of the first insulating layer 14. A second conductor layer 29 is formed on the second surface SS of the first insulating layer 14. A via conductor 24 connecting the first conductor layer 28 and the second conductor layer 29 is formed in the opening 18. The first conductor layer 28 includes a plurality of conductor circuits, a conductor covering the via conductor 24, and a land 27 formed around the via conductor 24. The land 27 is larger than the diameter of the via conductor 24, and the land 27 has a diameter of 75 μm to 350 μm. The first conductor layer 28 is formed of an electroless copper plating film 20 and an electrolytic copper plating film 22.

  The second conductor layer 29 includes a plurality of conductor circuits, a conductor covering the via conductor 24, and a land 27 formed around the via conductor 24. The land 27 is larger than the diameter of the via conductor 24, and the land 27 has a diameter of 75 μm to 350 μm. The second conductor layer 29 is formed of the copper foil 17, the electroless copper plating film 20, and the electrolytic copper plating film 22.

  The second conductor layer 29 includes a metal foil such as the copper foil 17, but the first conductor layer 28 does not include a metal foil. Therefore, the thickness of the first conductor layer 28 is thinner than the thickness of the second conductor layer 29. A fine conductor circuit can be formed on the first conductor layer 28. Therefore, it is preferable that the first conductor layer 28 mainly functions as a signal layer. When the first conductor layer 28 includes a signal line and other circuits (for example, a power supply layer), the signal line and the function are included in the area of the conductor layer formed on the first surface FF of the first insulating layer 14. When the area of the wiring to be performed is 55% or more, the first conductor layer 28 mainly functions as a signal layer. When there are a plurality of signal lines, the area of the signal layer is calculated by adding the areas of the respective signal lines.

  Since the second conductor layer 29 is thick, the resistance of the second conductor layer 29 is low. Therefore, the second conductor layer 29 preferably functions mainly as a power supply layer or a ground layer. Electric power is smoothly supplied to the IC chip. When the second conductor layer 29 includes a power source layer and other circuits (for example, signal lines), it functions as a power source within the area of the conductor layer formed on the second surface SS of the first insulating layer 14. When the area of the wiring is 55% or more, the second conductor layer 29 mainly functions as a power supply layer. When there are a plurality of power supply circuits, the area of the power supply layer is calculated by adding the areas of the respective power supply circuits. Similarly, when the area of the ground layer is 55% or more, the second conductor layer 29 mainly functions as a ground layer.

  The first conductor layer 28 is formed simultaneously with the via conductor 24. The first conductor layer 28 includes an electrolytic copper plating film 22 extending from the via conductor 24. The opening 18 is filled with plating. Therefore, the thickness of the electrolytic plating film 22 formed on the first surface FF of the first insulating layer 14 tends to be thicker than the thickness of the electrolytic plating film 22 formed on the second surface SS of the first insulating layer 14. However, in the embodiment, since the first conductor layer 28 does not include a metal foil, the thickness of the first conductor layer 28 is reduced. For example, the difference between the thickness of the first conductor layer 28 and the thickness of the second conductor layer 29 is smaller than the thickness of the metal foil 17 included in the second conductor layer 29.

When the electrolytic plating film 22 of the first conductor layer 28 is formed on the metal foil, the seed layer on the first insulating layer 14 includes the metal foil and the electroless plating film 20, and the seed layer in the opening 18 is electroless. The plating film 20 is formed. Therefore, the resistance value of the seed layer for the first conductor layer 28 (seed layer on the first insulating layer 14) is lower than the resistance value of the seed layer for the via conductor 24 (seed layer in the opening 18). Since the seed layer on the first surface FF of the first insulating layer 14 and the electroless plating film 20 in the opening 18 are connected, the resistance value for forming the first conductor layer 28 is likely to vary depending on the location. Variations in the thickness of the first conductor layer 28 tend to increase.
However, in the embodiment, the seed layer for forming the via conductor 24 and the first conductor layer 28 is the electroless plating film 20. The seed layer does not contain metal foil. Therefore, the variation in the film thickness of the electrolytic plating film 22 forming the first conductor layer 28 is reduced. The seed layer for forming the second conductor layer 29 does not include the seed layer for forming the via conductor 24. Therefore, the seed layer for forming the second conductor layer 29 may include the metal foil 17. Since the seed layer for forming the second conductor layer 29 includes the metal foil 17, the resistance of the seed layer is reduced. Therefore, the variation in the thickness of the electrolytic plating film 22 forming the second conductor layer 29 is reduced.

  According to the manufacturing method of the embodiment and the double-sided board 10 manufactured by the method, the electrolytic copper plating film (layer) 22 forming the via conductor 24 is unlikely to contain a void. As a result, the cross-sectional area of the electrolytic copper plating film 22 forming the via conductor 24 is unlikely to be locally reduced. Within the via conductor 24, the electrical resistance is unlikely to increase locally. Therefore, for example, even if an inductor is formed by the conductor circuit included in the first conductor layer 28 and the second conductor layer 29 of the double-sided board 10 and the via conductor 24 penetrating the first insulating layer 14, a desired inductance and Q value can be obtained. Can be obtained.

  The following reasons can be considered as the reason. The first conductor layer 28 does not include the metal foil 16, and the second conductor layer 29 includes the metal foil 17. The resistance of the via conductor 24 is low. The variation in the film thickness of the first conductor layer 28 and the film thickness of the second conductor layer 29 is small. The difference between the film thickness of the first conductor layer 28 and the film thickness of the second conductor layer 29 is less than the thickness of the metal foil 17. The thickness of the metal foils 16 and 17 is 1 μm to 5 μm. In order to reduce the difference between the thickness of the first conductor layer 28 and the thickness of the second conductor layer 29, the thickness of the metal foil 17 included in the second conductor layer 29 is preferably 3 μm or less.

Next, insulating layers and conductor layers are alternately laminated on the first surface FF and the second surface SS of the double-sided board 10 shown in FIG. The first surface FF of the double-sided plate 10 and the first surface FF of the first insulating layer 14 are the same surface, and the second surface SS of the double-sided plate 10 and the second surface SS of the first insulating layer 14 are the same surface. The multilayer core substrate 2 is manufactured. In the embodiment, since the insulating layer and the conductor layer are laminated on both sides of the double-sided board 10, the double-sided board 10 is referred to as a central core board of the multilayer core board 2.
A method for manufacturing the multilayer core substrate 2 will be described with reference to FIGS.

(10) A commercially available prepreg and a metal foil 34 such as a copper foil are laminated on the first surface FF of the central core substrate 10. A commercially available prepreg and a metal foil 34 such as a copper foil are laminated on the second surface of the central core substrate 10. The copper foil is laminated on the prepreg. Thereafter, the insulating layers 32 and 32 are formed on both sides of the double-sided board 10 by heating press. Metal foils 34 and 34 are laminated on the insulating layers 32 and 32. As the metal foils 34, 34, copper foil is preferable. (FIG. 3A).
The insulating layer 32 is formed of a reinforcing material such as glass cloth and a resin such as epoxy. The insulating layer 32 ensures the strength and thinness of the printed wiring board. The thickness of the insulating layer 32 is desirably 100 μm or less, and more desirably within a range of 30 to 70 μm. The strength of the printed wiring board is ensured and a thin printed wiring board is obtained.

The thickness of the copper foil 34 laminated on the insulating layer 32 is 1 to 5 μm. The thickness of the copper foil 34 laminated on the insulating layer 32 is desirably thinner than the thickness of the metal foil (metal foil included in the second conductor layer) 17 of the central core substrate 10.
The thickness of the electrolytic plating film 40 formed on the insulating layer in the plating process described later is reduced. The variation in the thickness of the electrolytic plating film 40 is reduced. The reason is considered that the difference between the resistance value of the seed layer in the opening 36 for the via conductor and the resistance value of the seed layer on the insulating layer 32 becomes small.

(11) Next, the metal foil 34 is irradiated with a laser. Openings 36 for via conductors that penetrate through the metal foil 34 and the insulating layer 32 and reach the conductor layers 28 and 29 of the central core substrate 10 are formed (FIG. 3B).
The metal foil 34 has eaves on the opening of the insulating layer 32. When the multilayer core substrate 2 is warped by heat cycle or the like, the deformation amount of the insulating layer 32 located outside is considered to be larger than the deformation amount of the insulating layer 14 located in the center. The eaves of the metal foil 34 pierce a via conductor (via conductor formed in the insulating layer 32) 42 described later. Therefore, the via conductor 42 is not peeled off from the insulating layer 32 and the conductor layers 28 and 29 of the central core substrate 2 in a heat cycle.

The insulating layer 32 and the conductor layer 44 on the double-sided board 10 are formed by the following method, for example.
Similarly to the first insulating layer 14, the insulating layer 32 may be formed of a reinforcing layer and a resin layer that is formed on the reinforcing layer and does not include the reinforcing layer. When the insulating layer 32 is formed of the same insulating layer as the first insulating layer 14, the insulating layer 32 and the metal foil 34 formed of the reinforcing layer and the resin layer on the reinforcing layer are formed on both surfaces of the central core substrate 10. Laminated. The metal foil 34 is laminated on the resin layer of the insulating layer 32. The metal foil 34 is irradiated with laser, and an opening 36 for a via conductor that penetrates the metal foil 34 and the insulating layer 32 is formed in the insulating layer 32. The metal foil 34 has eaves. Thereafter, the metal foil 34 is removed from the resin layer of the insulating layer 32. At this time, the matte surface of the metal foil 34 is transferred to the resin layer. A rough surface is formed on the surface of the resin layer.

If the conductor layer 44 on the insulating layer 32 is formed by the same method as the first conductor layer 28 of the double-sided board 10, the variation in the thickness of the conductor layer 44 on the insulating layer 32 is reduced. The resistance of the via conductor 42 formed in the insulating layer 32 is reduced. When the conductor circuit included in the conductor layer 44 on the insulating layer 32 and the via conductor 42 formed in the insulating layer 32 are included in the inductor in the multilayer core substrate 2, the inductance value and the Q value increase.
An insulating layer with metal foil may be laminated on the central core substrate 2. In this case, a metal foil is pasted on the insulating layer in advance.

(12) Thereafter, desmearing for removing the resin residue on the side wall and bottom of the opening 36 is performed. Then, a seed layer 38 such as an electroless copper plating layer is formed on the inner wall of the opening 36 and the insulating layer 32 (FIG. 3C). In FIG. 3C, the seed layer 38 is formed on the metal foil 34, but when the insulating layer 32 includes a resin layer, the seed layer 38 is directly formed on the resin layer.

(13) Subsequently, an electrolytic copper plating layer 40 is formed on the seed layer 38. The opening 36 is filled with an electrolytic copper plating layer 40 (FIG. 3D). The via conductor 42 filling the opening 36 is called a filled via.
(14) Next, an etching resist is formed on the electrolytic copper plating layer 40 and the via conductor 42. The electrolytic copper plating layer 40, the electroless copper plating layer 38 and the copper foil 34 exposed from the etching resist are removed by etching.
When the insulating layer 32 has a resin layer, since the metal foil does not exist on the resin layer, the seed layer 38 and the electrolytic plating layer 40 on the seed layer 38 are removed by etching.

(15) The etching resist is removed. On the insulating layer 32, a conductive layer 44 formed by a metal foil 34, a seed layer 38 on the metal foil 34 and an electrolytic plating layer 40 on the seed layer 38 is formed. The conductor layer 44 includes a plurality of conductor circuits and lands of via conductors 42. In addition, a via conductor 42 that penetrates the insulating layer 32 and connects the conductor layers 28 and 29 of the central core substrate 2 and the conductor layer 44 on the insulating layer 32 is formed (FIG. 3E).
When the insulating layer 32 includes a resin layer, the conductor layer 44 is formed of a seed layer on the insulating layer 32 and an electrolytic plating layer 40 on the 38 seed layer 38.

In the manufacturing method of the embodiment, the steps (10) to (15) are further repeated. The multilayer core substrate 2 is completed (FIG. 4). In the multilayer core substrate 2 shown in FIG. 4, the four insulating layers 30 and the four conductor layers 44 are alternately cleaned on both surfaces of the central core substrate 10.
The second conductor layer 29 of the central core substrate 10 includes the copper foil 17. Therefore, the strength of the central core substrate 10 is increased. The central core substrate 10 having high strength is located at the center (center in the cross-sectional direction) of the multilayer core substrate 2. Accordingly, the warp of the multilayer core substrate 2 is reduced. The warp of the multilayer printed wiring board 1 is reduced.

  Next, in the manufacturing method of the embodiment, build-up layers 3U and 3D having an insulating layer 50, a conductor layer 52, and a via conductor 54 are formed on both surfaces of the multilayer core substrate 2 (FIG. 5). A solder resist layer 60 is laminated on the outermost buildup layers 3U and 3D. The conductor layer 52 exposed from the opening 62 of the solder resist layer 60 functions as the solder pad 56. Solder bumps 64 are formed on the solder pads 56. The multilayer printed wiring board 1 is completed. The build-up layers 3U and 3D, the solder resist layer 60, and the solder bumps 64 are formed by a known method. A buildup layer and a method for manufacturing the buildup layer are disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-347391. A portion indicated by reference numeral 30 in FIG. 8 of JP-A-2005-347391 is a buildup layer.

  FIG. 6 shows an application example of the multilayer printed wiring board 1. An IC chip 70 and a memory 700 are mounted on the multilayer printed wiring board 1 via solder bumps 64. An underfill 66 is filled between the solder resist layer 60 and the IC chip 70 and between the solder resist layer 60 and the memory 700. In the multilayer printed wiring board 1, an inductor having a high inductance and a high Q value is formed in a multilayer core substrate 2. Therefore, electric power is smoothly supplied to the electronic component. Therefore, the IC chip 70 and the memory 700 can be mounted on the multilayer printed wiring board 1 (FIG. 6).

1 multilayer printed wiring board 2 multilayer core board 3U, 3D build-up layer 10 central core board (double-sided board)
11 Insulating layer with metal foil (double-sided copper-clad laminate)
12 Reinforcing layer 13 Resin layer 14 First insulating layer 16 First metal foil (copper foil)
17 Second metal foil (copper foil)
18 Opening 20 Electroless copper plating film (seed layer)
22 Electrolytic copper plating film 24 Via conductor 26 Etching resist 27 Land 28 First conductor layer 29 Second conductor layer 32 Resin insulation layer (insulation layer)
34 Metal foil (copper foil)
36 Opening 38 Electroless plating film (seed layer)
40 Electroplating film 42 Via conductor 44 Conductor layer 50 Insulating layer 52 Conductor layer 54 Via conductor 60 Solder resist layer 62 Opening 64 Solder bump 66 Underfill 70 IC chip 700 Memory F, FF First surface S, SS Second surface

Claims (5)

Preparing an insulating layer comprising a reinforcing layer including a reinforcing material and a resin layer formed on the reinforcing layer and not including the reinforcing layer;
Laminating a first metal foil on the resin layer of the insulating layer;
Forming a through-hole penetrating the first metal foil and the insulating layer with a laser;
Removing the first metal foil from the insulating layer;
Forming a conductor layer on the resin layer of the insulating layer;
Forming a via conductor in the through hole;
A method of manufacturing a printed wiring board including: It is a manufacturing method of the printed wiring board of Claim 1,
Preparing the insulating layer includes forming the resin layer on the reinforcing layer. An insulating layer comprising a reinforcing layer including a reinforcing material and a resin layer formed on the reinforcing layer and not including the reinforcing layer;
A first conductor layer formed on the resin layer and formed of a first seed layer and a first electrolytic plating layer on the first seed layer;
A second conductor layer formed on the reinforcing layer and formed of a metal foil, a second seed layer, and a second electrolytic plating layer on the second seed layer;
A printed wiring board, which penetrates the insulating layer, connects the first conductor layer and the second conductor layer, and includes a via conductor formed of the first seed layer and the first electrolytic plating layer.   4. The printed wiring board according to claim 3, wherein a difference between the thickness of the first conductor layer and the thickness of the second conductor layer is smaller than the thickness of the metal foil.   4. The printed wiring board according to claim 3, wherein an inductor is formed by the conductor circuit included in the first conductor layer, the conductor circuit included in the second conductor layer, and the via conductor.

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