TWI500366B - Multilayer printed wiring board and manufacturing method thereof - Google Patents
Multilayer printed wiring board and manufacturing method thereof Download PDFInfo
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- TWI500366B TWI500366B TW100137889A TW100137889A TWI500366B TW I500366 B TWI500366 B TW I500366B TW 100137889 A TW100137889 A TW 100137889A TW 100137889 A TW100137889 A TW 100137889A TW I500366 B TWI500366 B TW I500366B
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Description
本發明是有關多層印刷配線板及其製造方法,尤其是有關具有填孔構造的多層印刷配線板及其製造方法。The present invention relates to a multilayer printed wiring board and a method of manufacturing the same, and more particularly to a multilayer printed wiring board having a hole-filling structure and a method of manufacturing the same.
近年,電子機器的小型化及高機能化愈來愈進步,連帶提高對於印刷配線板之高密度化的要求。因此,貼合複數印刷配線板,達到高密度化的多層印刷配線板,以攜帶式電話和數位相機等小型電子機器為中心擴大普及。以高密度化的印刷配線板為例而揭示了層積撓性印刷配線板的多層印刷配線板(例如:參照專利文獻1)。In recent years, the miniaturization and high performance of electronic devices have become more and more advanced, and the demand for higher density of printed wiring boards has been increased. For this reason, a multi-layer printed wiring board having a high density has been bonded to a plurality of printed wiring boards, and has been widely spread around small electronic devices such as portable telephones and digital cameras. A multilayer printed wiring board in which a flexible printed wiring board is laminated is disclosed as an example of a printed wiring board having a high density (for example, see Patent Document 1).
又,於專利文獻2及3中揭示,通孔的縱斷面形狀為鼓狀,或錐形狀的頂部彼此形成互相配合的形狀,形成以電鍍金屬填充的通孔(以下稱「填充貫通孔」)的方法。Further, in Patent Documents 2 and 3, the through-holes have a vertical cross-sectional shape in a drum shape, or the tapered top portions are formed in a mutually matching shape to form a through hole filled with a plating metal (hereinafter referred to as a "filled through hole"). )Methods.
[專利文獻1]日本特開第2004-200260號公報[Patent Document 1] Japanese Patent Laid-Open Publication No. 2004-200260
[專利文獻2]日本特開第2004-311919號公報[Patent Document 2] Japanese Patent Laid-Open Publication No. 2004-311919
[專利文獻3]日本特開第2003-046248號公報[Patent Document 3] Japanese Patent Laid-Open Publication No. 2003-046248
在此,針對有關比較例的多層撓性印刷配線板的製造方法,採用第5A圖及第5B圖做說明。Here, a method of manufacturing a multilayer flexible printed wiring board according to a comparative example will be described with reference to FIGS. 5A and 5B.
(1)首先,準備一片在由聚醯亞胺製成的可撓性之絕緣基層膜的兩面形成有銅箔的雙面覆銅層積板。而且針對該雙面覆銅層積板,進行通孔的形成、鍍銅處理及銅箔的圖案化等,製作內層電路基材100。像是由第5A圖(1)即可明白,內層電路基材100,係具有:形成在絕緣基層膜之兩面的配線圖案、和電性連接雙面的配線圖案的鍍通孔。(1) First, a double-sided copper-clad laminate in which copper foil is formed on both surfaces of a flexible insulating base film made of polyimide. Further, the inner layer circuit substrate 100 is produced by forming a through hole, plating a copper plating, and patterning a copper foil on the double-sided copper clad laminate. As can be understood from Fig. 5A (1), the inner layer circuit substrate 100 has a wiring pattern formed on both surfaces of the insulating base film and a plated through hole electrically connecting the wiring patterns on both sides.
(2)其次,像是由第5A圖(1)即可明白,為了絕緣保護內層電路基材100的兩面,使用真空層壓機等,將具有絕緣膜130與接著劑層120的覆蓋層110,層壓在內層電路基材100的兩面。藉此製作出核心基板200。(2) Next, as can be understood from Fig. 5A (1), in order to insulate and protect both sides of the inner layer circuit substrate 100, a cover layer having the insulating film 130 and the adhesive layer 120 is used using a vacuum laminator or the like. 110, laminated on both sides of the inner layer circuit substrate 100. Thereby, the core substrate 200 is produced.
(3)接著,製作增建層用的外層電路基材300。該外層電路基材300隨著既定的圖案來加工雙面覆銅層積板的兩面銅箔。外層電路基材300的配線圖案,是在盲孔形成部位具有開口部310。該開口部310,是在後段的雷射加工製程作為正形光罩的功能。(3) Next, an outer layer circuit substrate 300 for the build-up layer is produced. The outer layer circuit substrate 300 processes the double-sided copper foil of the double-sided copper clad laminate in accordance with a predetermined pattern. The wiring pattern of the outer layer substrate 300 has an opening portion 310 at a blind hole forming portion. The opening portion 310 functions as a positive-shaped mask in the laser processing process in the subsequent stage.
(4)接著,在核心基板200的兩面介設層積接著劑層210來層積外層電路基材300,藉此製作出第5A圖(1)所示的多層電路基材400。(4) Next, the multilayer circuit substrate 300 is laminated by laminating the adhesive layer 210 on both surfaces of the core substrate 200, whereby the multilayer circuit substrate 400 shown in Fig. 5A (1) is produced.
(5)接著,如第5A圖(2)所示,在多層電路基材400形成盲孔及通孔。更具體是對外層電路基材300的開口部310照射雷射光進行雷射加工,來形成在底面露出內層電路基材100的配線圖案的盲孔410、以及在底面露出外層電路基材300的裏面的配線圖案的盲孔420。並且在通孔的形成部位進行鑽孔加工,藉此形成貫通多層電路基材400的通孔430。(5) Next, as shown in Fig. 5A (2), blind vias and via holes are formed in the multilayer circuit substrate 400. More specifically, the opening portion 310 of the outer layer circuit substrate 300 is irradiated with laser light to perform laser processing to form a blind hole 410 in which the wiring pattern of the inner layer circuit substrate 100 is exposed on the bottom surface, and the outer circuit substrate 300 is exposed on the bottom surface. A blind hole 420 of the wiring pattern inside. Further, drilling is performed at a portion where the through hole is formed, thereby forming a through hole 430 penetrating the multilayer circuit substrate 400.
(6)接著,如第5A圖(3)所示,對著形成有盲孔410、420、以及通孔430的多層電路基材400施行電鍍處理,形成鍍皮膜450。在盲孔410、420、以及通孔430的側面形成有鍍皮膜450,藉此形成有作為層間連接路徑之功能的鍍盲孔460、470、480、以及鍍通孔490。(6) Next, as shown in Fig. 5A (3), the multilayer circuit substrate 400 on which the blind vias 410, 420 and the via holes 430 are formed is subjected to a plating treatment to form a plating film 450. A plating film 450 is formed on the side faces of the blind holes 410, 420 and the through holes 430, whereby the plating blind holes 460, 470, 480 and the plated through holes 490 functioning as interlayer connection paths are formed.
(7)接著,如第5B圖(4)所示,使用感光蝕刻加工手法,以既定的圖案來加工外層電路基材300之表面的導電膜,來形成外層電路配線圖案500。(7) Next, as shown in Fig. 5B (4), the outer layer circuit wiring pattern 500 is formed by processing the conductive film on the surface of the outer layer substrate 300 in a predetermined pattern by a photosensitive etching process.
(8)接著,如第5B圖(5)所示,形成絕緣保護外層電路配線圖案500、鍍盲孔460、470、480、以及鍍通孔490的防焊劑510。該防焊劑510是形成在零件安裝用的端子以及連接用的端子之形成預定部位具有開口部510a。再者,作為絕緣保護材,也可以取代防焊劑,而使用覆蓋層。(8) Next, as shown in Fig. 5B (5), the insulating protective outer layer wiring pattern 500, the plating blind holes 460, 470, and 480, and the solder resist 510 of the plated through holes 490 are formed. The solder resist 510 has an opening 510a formed at a predetermined portion where the terminal for mounting the component and the terminal for connection are formed. Further, as the insulating protective material, a cover layer may be used instead of the solder resist.
(9)接著,對著露出於開口部510a之底面的外層電路配線圖案500施行鍍金或鍍錫等的表面處理,來形成端子520。(9) Next, the outer layer circuit wiring pattern 500 exposed on the bottom surface of the opening 510a is subjected to surface treatment such as gold plating or tin plating to form the terminal 520.
藉由上述製程,完成具有:鍍盲孔460、470、480、以及鍍通孔490的多層撓性印刷配線板600。The multilayer flexible printed wiring board 600 having the plated blind holes 460, 470, and 480 and the plated through holes 490 is completed by the above process.
像是由第5B圖即可明白,端子520並非設置在鍍盲孔460、470、480、以及鍍通孔490的的正上方。此乃為了對多層撓性印刷配線板平行地安裝,電子機器典型上是晶片尺寸封裝(CSP:Chip Size Package)之類的裸晶片。亦即,在鍍盲孔460、470、480、以及鍍通孔490的正上方安裝電子零件的場合,對印刷配線板平行地安裝電子零件是很困難的事情。為了理解該理由,針對CSP的安裝製程做說明。As can be understood from Fig. 5B, the terminal 520 is not disposed directly above the plating blind holes 460, 470, 480, and the plated through holes 490. This is for the parallel mounting of a multilayer flexible printed wiring board, which is typically a bare wafer such as a Chip Size Package (CSP). That is, when electronic components are mounted directly above the plating blind holes 460, 470, and 480 and the plated through holes 490, it is difficult to mount the electronic components in parallel with the printed wiring boards. In order to understand the reason, the installation process of the CSP is explained.
首先,設置在CSP之端子上的複數個焊球,是以各自位在鍍盲孔460、470、480、以及鍍通孔490之正上方的方式,在印刷配線板之上載置CSP。然後,在廻焊製程中,溶解焊球,將CSP固定在印刷配線板。然而,如第5B圖(5)所示,由於鍍盲孔460、470、480、以及鍍通孔490的深度有所區別,吸入到該些孔的溶融的焊料量,每個孔各不相同。其結果,CSP無法對印刷配線板平行地安裝。First, a plurality of solder balls provided on the terminals of the CSP are placed on the printed wiring board so as to be placed on the printed wiring board so as to be positioned directly above the plating blind holes 460, 470, and 480 and the plated through holes 490. Then, in the soldering process, the solder balls are dissolved to fix the CSP to the printed wiring board. However, as shown in FIG. 5B (5), since the depths of the plated blind holes 460, 470, 480, and the plated through holes 490 are different, the amount of molten solder sucked into the holes is different for each hole. . As a result, the CSP cannot be mounted in parallel to the printed wiring board.
因而,無法在鍍盲孔460、470、480、以及鍍通孔490的正上方設置端子,如第5B圖(5)所示的端子520,必須在自鍍盲孔460、470、480、以及鍍通孔490之正上方左右偏離的位置設置端子。Therefore, it is not possible to provide terminals directly above the plating blind holes 460, 470, 480, and the plated through holes 490, such as the terminal 520 shown in FIG. 5B (5), which must be in the self-plating blind holes 460, 470, 480, and A terminal is provided at a position where the plated through hole 490 is offset right and left.
近年數位相機等之電子機器的小型化、高機能化非常驚人,CSP的焊墊間距愈來愈窄距化。具體而言,當初0.8mm左右的焊墊間距變成0.5mm以下,對應於此,而對印刷配線板要求更高密度化。In recent years, the miniaturization and high performance of electronic devices such as digital cameras have been amazing, and the pitch of CSP pads has become increasingly narrow. Specifically, the pitch of the pad of about 0.8 mm is 0.5 mm or less, and in response to this, the printed wiring board is required to have a higher density.
然而,如上記,為了限制端子的位置,以往要安裝窄距且多針腳的晶片,例如10×10以上的焊墊以柵壓來配置的CSP是非常困難的。However, as described above, in order to limit the position of the terminal, it has been conventionally difficult to mount a chip having a narrow pitch and a plurality of stitches, for example, a CSP having a gate voltage of 10 × 10 or more pads is extremely difficult.
因此,考慮藉由對盲孔或通孔進行填充金屬的填孔電鍍(filling plated)處理,形成填孔構造。如前述,在專利文獻2及3提案一種通孔的縱斷面形狀為鼓狀,而形成填充貫通孔的方法。Therefore, it is considered to form a hole-filling structure by a filling plated process of filling a metal through a blind hole or a via hole. As described above, Patent Documents 2 and 3 propose a method in which the through hole has a vertical cross-sectional shape in a drum shape to form a through hole.
然而,該些的文獻無論那一個都是以由單一材料所製成的單層之基板為對象,對於多層印刷配線板而言無法適用。例如第5B圖(5)所示的多層印刷配線板的場合,被加工層是層積著絕緣膜、接著劑、以及銅箔等加工特性相異的各種材料。因而,即便採用雷射加工等,欲將被加工層加工成為縱斷面為鼓狀的情形是極為困難的。However, none of these documents is aimed at a single-layer substrate made of a single material, and it is not applicable to a multilayer printed wiring board. For example, in the case of the multilayer printed wiring board shown in Fig. 5B (5), the processed layer is formed by laminating various materials having different processing characteristics such as an insulating film, an adhesive, and a copper foil. Therefore, even if laser processing or the like is employed, it is extremely difficult to process the layer to be processed into a drum shape in a longitudinal section.
再者,多層印刷配線板的場合,也有別的問題。亦即,電子零件的端子不光是設置在通孔上,也必須設置在盲孔上,但由於通孔與盲孔,在構造上,電鍍藥液的流動性不同,因此就會有所謂的在同一個填孔電鍍製程中進行處理相當困難的問題。更詳細就是,填孔電鍍處理具有電鍍藥液之流動性低者,其效率上較為容易的特徵。有底的盲孔的場合,由於電鍍藥液的流動性低,因此可得到良好的填孔構造。對此,通孔的場合,由於電鍍藥液的流動性高,因此無法效率的良好將電鍍金屬填充到通孔內。Furthermore, in the case of a multilayer printed wiring board, there are other problems. That is, the terminals of the electronic component are not only disposed on the through hole, but also must be disposed on the blind hole, but due to the through hole and the blind hole, the fluidity of the plating solution is different in structure, so there is a so-called It is quite difficult to handle in the same hole filling process. More specifically, the hole-fill plating treatment has a feature that the fluidity of the plating solution is low, and the efficiency is relatively easy. In the case of a bottomed blind hole, since the fluidity of the plating solution is low, a good hole-filling structure can be obtained. On the other hand, in the case of a through hole, since the fluidity of the plating solution is high, it is impossible to efficiently fill the plating metal into the through hole.
藉由本發明之一形態,提供一種具備:內層電路基材;介設絕緣層被層積在前記內層電路基材之表面的第一外層電路基材;介設絕緣層被層積在前記內層電路基材之畫面的第二外層電路基材;和對貫通前記第一外層電路基材、前記內層電路基材以及前記第二外層電路基材的通孔,填充電鍍金屬的填充貫通孔;前記通孔,係構成連通著貫通前記第一外層電路基材的第一針孔、貫通前記內層電路基材的內層通孔、以及貫通前記第二外層電路基材的第二針孔,前記第一及第二針孔,具有較前記內層通孔的最大開口徑更大的最小開口徑為其特徵的多層印刷配線板。According to an aspect of the present invention, there is provided a first outer layer circuit substrate comprising: an inner layer circuit substrate; a dielectric layer laminated on a surface of the front inner circuit substrate; the dielectric layer is laminated in the pre-record a second outer layer circuit substrate of the inner layer circuit substrate; and a through hole for the first outer layer circuit substrate, the front inner layer circuit substrate, and the second outer layer circuit substrate, which are filled with the filling metal a through hole, a first pinhole through which the first outer layer circuit substrate is connected, an inner layer through hole penetrating the inner layer circuit substrate, and a second pin penetrating the second outer layer circuit substrate The hole, the first and second pinholes, has a multilayer printed wiring board characterized by a minimum opening diameter larger than the maximum opening diameter of the inner layer through hole.
藉由本發明之另一形態,提供一種準備具有:可撓性之絕緣基膜、形成在該絕緣基膜之兩面的金屬箔的雙面覆金屬層積板,形成朝厚度方向貫通前記両面覆金屬層積板的內層通孔,將前記雙面覆金屬層積板的金屬箔圖案化,形成內層配線圖案,藉此製作內層電路基材,準備具有:可撓性之絕緣基膜、和形成在該絕緣基膜之至少一方的面的金屬箔的第一及第二覆金屬層積板,將前記第一覆金屬層積板的金屬箔圖案化,形成第一外層配線圖案,藉此製作第一外層電路基材,將前記第二覆金屬層積板的金屬箔圖案化,形成第二外層配線圖案,藉此製作第二外層電路基材,在前記內層電路基材之表面將前記第一外層電路基材,以前記第一外層配線圖案位在外側的方式,介設著絕緣層而層積,且在前記內層電路基材的裏面將前記第二外層電路基材,以前記第二外層配線圖案位在外側的方式,介設著絕緣層而層積,藉此製作多層電路基材,藉由對前記多層電路基材之既定的領域施行照射雷射光的雷射加工製程,來貫通前記第一外層電路基材,作為連通具有比前記內層通孔之最大開口徑還大的最小開口徑的第一針孔、和貫通前記內層通孔與前記第二外層電路基材,且具有比前記內層通孔之最大開口徑還大的最小開口徑的第二針孔所構成,形成貫通前記多層電路基材的通孔,且施行對前記通孔填充電鍍金屬的填充電鍍處理,形成電性連接前記內層配線圖案、前記第一外層配線圖案及前記第二外層配線圖案的填充貫通孔之多層印刷配線板之製造方法。According to another aspect of the present invention, there is provided a double-sided metal-clad laminate in which an insulating base film having flexibility and a metal foil formed on both surfaces of the insulating base film are prepared, and a metal-clad surface is formed in the thickness direction. The inner layer through hole of the laminated board is patterned by forming a metal foil of the double-sided metal-clad laminate, and an inner layer wiring pattern is formed, thereby preparing an inner layer circuit substrate, and preparing an insulating base film having flexibility: And the first and second metal-clad laminates of the metal foil formed on at least one of the insulating base films, and the metal foil of the first metal-clad laminate is patterned to form a first outer wiring pattern. The first outer circuit substrate is formed, and the metal foil of the second metal-clad laminate is patterned to form a second outer wiring pattern, thereby fabricating a second outer circuit substrate, which is preceded by the surface of the inner circuit substrate. The first outer layer circuit substrate is preceded by the first outer layer wiring pattern being placed on the outer side, and the insulating layer is laminated, and the second outer layer circuit substrate is preceded by the inner layer of the inner layer circuit substrate. Previously recorded The outer wiring pattern is placed on the outer side, and an insulating layer is laminated to form a multilayer circuit substrate, and a laser processing process for irradiating the laser light to a predetermined field of the pre-recorded multilayer circuit substrate is used. The first outer layer circuit substrate is a first pinhole that communicates with a minimum opening diameter larger than a maximum opening diameter of the inner layer through hole, and a through hole inner layer through hole and a second outer layer circuit substrate, and a second pinhole having a minimum opening diameter larger than a maximum opening diameter of the inner layer through hole of the preceding layer, forming a through hole penetrating the multilayer circuit substrate beforehand, and performing a filling plating process for filling the plating hole with the front via hole. A method of manufacturing a multilayer printed wiring board in which an inner layer wiring pattern, an upper first wiring pattern, and a second outer wiring pattern filled through hole are electrically connected is formed.
有關本發明之實施形態的通孔是構成連通有:貫通第一外層電路基材的第一針孔、貫通內層電路基材的內層通孔、和貫通第二外層電路基材的第二針孔。又,第一及第二針孔,是具有比內層通孔之最大開口徑還大的最小開口徑。在具有此種構成的通孔中,在第一針孔與內層通孔之連接部分及第二針孔與內層通孔的連接部分形成角隅部,在通孔內填充電鍍金屬之際,藉由具有角隅部使電鍍藥液的流動性下降,電鍍金屬變得很容易析出。再者,由於第一及第二針孔,是作為具有比內層通孔之最大開口徑還大的最小開口徑所構成,因此通孔係愈往內層側孔徑愈小。因此,填孔電鍍處理之際,內層通孔會因電鍍金屬而最先閉塞,形成上下兩個V字型的凹部。藉此,由於可抑制氣泡等的產生而形成高品質的填充貫通孔,同時電鍍藥液的流動性更為下降,因此填孔電鍍處理的效率提昇,就能縮短填充貫通孔的形成時間。The through hole according to the embodiment of the present invention is configured to communicate with the first pinhole penetrating the first outer layer circuit substrate, the inner layer through hole penetrating the inner layer circuit substrate, and the second through hole of the second outer layer circuit substrate. Pinhole. Further, the first and second pinholes have a minimum opening diameter which is larger than the maximum opening diameter of the inner layer through hole. In the through hole having such a configuration, the connecting portion of the first pinhole and the inner layer through hole and the connecting portion of the second pinhole and the inner layer through hole form a corner portion, and the through hole is filled with the plating metal By having a corner portion, the fluidity of the plating solution is lowered, and the plating metal is easily precipitated. Furthermore, since the first and second pinholes are formed as a minimum opening diameter which is larger than the maximum opening diameter of the inner layer through hole, the through hole is made smaller toward the inner layer side. Therefore, at the time of the hole-fill plating treatment, the inner-layer through-holes are first blocked by the plating metal, and the upper and lower V-shaped recesses are formed. Thereby, since high-quality filled through-holes can be formed by suppressing generation of bubbles or the like, and the fluidity of the plating solution is further lowered, the efficiency of the hole-fill plating process is improved, and the formation time of the filled through-holes can be shortened.
以下參照圖面,針對本發明之實施形態做說明。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
再者,在各圖中具有同等功能的構成要素附上相同的符號,相同符號的構成要素之詳細說明不予重複。又,圖面是以特徵部分為中心來表現,厚度與平面尺寸的關係、各層之厚度的比例等與實物不同。The components having the same functions in the respective drawings are denoted by the same reference numerals, and the detailed description of the components of the same reference numerals will not be repeated. Further, the drawing surface is represented by the feature portion, and the relationship between the thickness and the plane size, the ratio of the thickness of each layer, and the like are different from the actual object.
有關本實施形態的多層印刷配線板之製造方法,採用第1A圖、第1B圖、第2A圖、第2B圖、第3圖、第4A圖及第4B圖做說明。The method for manufacturing the multilayer printed wiring board according to the present embodiment will be described with reference to FIGS. 1A, 1B, 2A, 2B, 3, 4A, and 4B.
首先,採用第1A圖,針對核心基板之製造方法做說明。First, the manufacturing method of the core substrate will be described using FIG. 1A.
(1)準備具有:由聚醯亞胺等製成的可撓性之絕緣基層膜1、形成在該絕緣基層膜1之兩面的銅箔2及銅箔3的雙面覆銅層積板4。(1) A double-sided copper clad laminate 4 having a flexible insulating base film 1 made of polyimide or the like, and a copper foil 2 and a copper foil 3 formed on both surfaces of the insulating base film 1 .
(2)接著,像是由第1A圖(1)即可明白,對於雙面覆銅層積板4,藉由NC鑽頭加工(或雷射加工法)等,形成貫通雙面覆銅層積板4的內層通孔5。(2) Next, it can be understood from Fig. 1A (1) that the double-sided copper clad laminate 4 is formed by double-sided copper lamination by NC bit processing (or laser processing). The inner layer through hole 5 of the plate 4.
(3)接著,像是由第1A圖(1)即可明白,對內層通孔5內施行去膠渣(desmear)處理及導電化處理之後,對形成內層通孔5之雙面覆銅層積板4的全面施行電鍍處理(例如電解銅電鍍處理)。藉此,在銅箔2、3上、以及內層通孔5之內壁形成鍍皮膜6,同時形成電性連接銅箔2及銅箔3的鍍通孔7。(3) Next, it can be understood from Fig. 1A (1) that after the desmear treatment and the conductive treatment are performed on the inner layer via hole 5, the double layer of the inner layer via hole 5 is formed. The copper laminate 4 is fully subjected to a plating treatment (for example, electrolytic copper plating treatment). Thereby, the plating film 6 is formed on the inner walls of the copper foils 2, 3 and the inner layer through holes 5, and the plated through holes 7 for electrically connecting the copper foil 2 and the copper foil 3 are formed.
(4)接著,藉由減除法(Subtractive Process),以既定的圖案來加工絕緣基層膜1之雙面的導電膜(鍍皮膜6及銅箔2、3)。更詳細是以被覆鍍皮膜6及鍍通孔7的方式,來形成乾薄膜阻劑等之蝕刻層(圖未揭示),然後,藉由感光蝕刻加工法來曝光、顯像蝕刻層,以既定的圖案來加工蝕刻層。然後,以圖案化的蝕刻層作為光罩,來蝕刻鍍皮膜6及銅箔2、3,藉此來形成內層配線圖案8A、8B。然後,剝離蝕刻層。(4) Next, the double-sided conductive film (the plating film 6 and the copper foils 2, 3) of the insulating base film 1 is processed in a predetermined pattern by a subtractive process. More specifically, an etching layer (not shown) of a dry film resist or the like is formed so as to cover the plating film 6 and the plated through hole 7, and then the etching layer is exposed and developed by a photolithography process. The pattern is used to process the etch layer. Then, the plating film 6 and the copper foils 2 and 3 are etched by using the patterned etching layer as a mask to form the inner layer wiring patterns 8A and 8B. Then, the etching layer is peeled off.
藉由至此的製程,如第1A圖(1)所示,在表面及裏面分別形成有內層配線圖案8A、8B,製成出具有鍍通孔7的內層電路基材10。By the process thus far, as shown in FIG. 1A (1), the inner layer wiring patterns 8A and 8B are formed on the front surface and the inner surface, respectively, and the inner layer circuit substrate 10 having the plated through holes 7 is formed.
再者,在上記之順序中,雖是在形成內層通孔5之後施行電鍍處理,但也可以不施行該電鍍處理就施行銅箔2、3的圖案化。Further, in the above-described order, although the plating treatment is performed after the formation of the inner layer via hole 5, the patterning of the copper foils 2, 3 may be performed without performing the plating treatment.
(5)接著,準備具有:由聚醯亞胺膜等製成的絕緣膜12、形成在該絕緣膜12之單面的接著劑層11的覆蓋層13。接著劑層11是例如由壓克力、環氧樹脂等的接著劑製成。而且,為了絕緣保護內層配線圖案8A、8B,使用真空層壓機等,對內層電路基材10的雙面層壓各個覆蓋層13。經過本製程,製作出第1圖(2)所示的核心基板20。再者,如第1圖(2)所示,內層配線圖案8A、8B、以及鍍通孔7是藉由接著劑層11被填充。(5) Next, a cover layer 13 having an insulating film 12 made of a polyimide film or the like and an adhesive layer 11 formed on one surface of the insulating film 12 is prepared. The subsequent agent layer 11 is made of, for example, an adhesive such as acryl, epoxy resin or the like. Further, in order to insulate and protect the inner layer wiring patterns 8A, 8B, the respective cover layers 13 are laminated on both sides of the inner layer circuit substrate 10 using a vacuum laminator or the like. Through this process, the core substrate 20 shown in Fig. 1 (2) is produced. Further, as shown in FIG. 1 (2), the inner layer wiring patterns 8A, 8B and the plated through holes 7 are filled by the adhesive layer 11.
其次,針對成為層積在核心基板20的增建層的外層電路基材40、50的製造方法,採用第1B圖做說明。Next, a method of manufacturing the outer layer circuit substrates 40 and 50 which are laminated layers in the core substrate 20 will be described with reference to FIG.
(1)首先,準備雙面覆銅層積板34及雙面覆銅層積板44。該雙面覆銅層積板34(44),係具有:由聚醯亞胺等製成的可撓性之絕緣基層膜31(41)、和形成在該兩面的銅箔32(42)及銅箔33(43)。(1) First, a double-sided copper clad laminate 34 and a double-sided copper clad laminate 44 are prepared. The double-sided copper-clad laminate 34 (44) has a flexible insulating base film 31 (41) made of polyimide or the like, and a copper foil 32 (42) formed on both sides and Copper foil 33 (43).
(2)接著,藉由減除工法,以既定的圖案來加工雙面覆銅層積板34的銅箔32、33,藉此製作出第1B圖(a)所示的外層電路基材40。銅箔32具有開口部35、37及38,銅箔33具有包含開口部36的外層配線圖案39。(2) Next, the copper foils 32 and 33 of the double-sided copper clad laminate 34 are processed in a predetermined pattern by the subtractive method, thereby producing the outer layer substrate 40 shown in Fig. 1(a). . The copper foil 32 has openings 35, 37, and 38, and the copper foil 33 has an outer layer wiring pattern 39 including the opening 36.
同樣地,以既定的圖案來加工雙面覆銅層積板44的銅箔42、43,藉此製作出第1B圖(b)所示的外層電路基材50。銅箔42具有包含開口部47的外層配線圖案49,銅箔43具有開口部45、46及48。開口部35~38及開口部45~48,是設置在通孔或盲孔的形成預定領域,在後段的雷射加工製程中,作為正形投影光罩(Conformal mask)功能。Similarly, the copper foils 42 and 43 of the double-sided copper clad laminate 44 are processed in a predetermined pattern to fabricate the outer layer substrate 50 shown in Fig. 1B(b). The copper foil 42 has an outer layer wiring pattern 49 including an opening 47, and the copper foil 43 has openings 45, 46, and 48. The openings 35 to 38 and the openings 45 to 48 are provided in a predetermined area in which the through holes or the blind holes are formed, and function as a conformal mask in the laser processing in the subsequent stage.
又,於第1B圖(a)及(b)表示由圖中下方觀看時的開口部36及開口部45的形狀。像這樣地開口部36及45,試著以最小開口徑為基準的話,成為葉狀地具有複數個凹部的星形形狀所形成,且試著以最大開口徑為基準的話,成為具有向著內側的複數個突起部所形成。Moreover, in FIGS. 1B (a) and (b), the shapes of the opening 36 and the opening 45 when viewed from the lower side in the drawing are shown. In the case of the opening portions 36 and 45, the opening portions 36 and 45 are formed in a star shape having a plurality of concave portions in a leaf shape with reference to the minimum opening diameter, and the inner opening is tried to be based on the maximum opening diameter. A plurality of protrusions are formed.
接著,使用在上記製成所製作的核心基板20、外層電路基材40及外層電路基材50,來說明製作有關本實施形態之可撓性印刷配線板之方法。Next, a method of producing the flexible printed wiring board according to the present embodiment will be described using the core substrate 20, the outer layer circuit substrate 40, and the outer layer circuit substrate 50 which are produced as described above.
(1)如第2A圖(1)所示,將外層電路基材40及50,介設接著劑層51,分別層積接著在核心基板20的表面以及裏面之既定的領域。藉此,製作第2A圖(2)所示的多層電路基材60。未層積多層電路基材的領域,是成為供拉出配線的可撓性電線部。(1) As shown in Fig. 2A (1), the outer layer base materials 40 and 50 are interposed with the adhesive layer 51, and are laminated on the surface and the inside of the core substrate 20, respectively. Thereby, the multilayer circuit substrate 60 shown in FIG. 2A (2) is produced. The field of the unstacked multilayer circuit substrate is a flexible electric wire portion for pulling out wiring.
再者,作為應用在接著劑層51的接著材,理想上是低流量(low flow)型之所謂預漬體或黏合薄片等之流出量少的物質。Further, as the adhesive material applied to the adhesive layer 51, it is desirable that the low flow type so-called pre-stained body or adhesive sheet has a small amount of outflow.
(2)接著,如第2A圖(2)及(3)所示,對著多層電路基材60的開口部35、37、38、45、46、48照射雷射光(例如CO2 雷射),進行正形投影雷射(Conformal laser)。藉此,形成通孔61、以及盲孔62~65。然後,藉由去膠處理等,進行通孔61、以及盲孔62~65內的洗淨。(2) Next, as shown in Figs. 2A (2) and (3), the openings 35, 37, 38, 45, 46, 48 of the multilayer circuit substrate 60 are irradiated with laser light (for example, a CO 2 laser). , performing a Conformal laser. Thereby, the through hole 61 and the blind holes 62 to 65 are formed. Then, the through holes 61 and the blind holes 62 to 65 are cleaned by a glue removal process or the like.
如第2A圖(3)所示,通孔61是朝厚度方向貫通多層電路基材60,更詳細從圖中上側向下側,貫通絕緣基層膜31、接著劑層51(上側)、絕緣膜12(上側)、接著劑層11(上側)、接著劑層11(下側)、絕緣膜12(下側)、接著劑層51(下側)、以及絕緣基層膜41。As shown in FIG. 2A (3), the through hole 61 penetrates the multilayer circuit substrate 60 in the thickness direction, and penetrates the insulating base film 31, the adhesive layer 51 (upper side), and the insulating film in more detail from the upper side to the lower side in the drawing. 12 (upper side), adhesive layer 11 (upper side), adhesive layer 11 (lower side), insulating film 12 (lower side), adhesive layer 51 (lower side), and insulating base film 41.
盲孔62是貫通絕緣基層膜31、接著劑層51、絕緣膜12、以及接著劑層11,在其底面露出鍍皮膜6。該盲孔62是跳過(skip)設置在外層電路基材40之裏面的外層配線圖案39的跳過盲孔(skip via hole)。The blind via 62 penetrates the insulating base film 31, the adhesive layer 51, the insulating film 12, and the adhesive layer 11, and the plating film 6 is exposed on the bottom surface thereof. The blind via 62 is a skip via hole that skips the outer wiring pattern 39 disposed inside the outer layer circuit substrate 40.
盲孔63是貫通絕緣基層膜41、接著劑層51、絕緣膜12、以及接著劑層11,在其底面露出鍍皮膜6。該盲孔63,是在中段露出銅箔42的階梯盲孔(step via hole)。The blind via 63 penetrates the insulating base film 41, the adhesive layer 51, the insulating film 12, and the adhesive layer 11, and the plating film 6 is exposed on the bottom surface thereof. The blind hole 63 is a step via hole in which the copper foil 42 is exposed at the middle portion.
盲孔64是貫通絕緣基層膜31,在其底面為露出銅箔33的盲孔。盲孔65是貫通絕緣基層膜41,在其底面為露出銅箔42的盲孔。The blind via 64 penetrates the insulating base film 31, and the bottom surface thereof is a blind via which exposes the copper foil 33. The blind via 65 penetrates the insulating base film 41, and the bottom surface thereof is a blind via which exposes the copper foil 42.
在此,有關通孔61的構造,採用第3圖,做更詳細地說明。第3圖是表示以第2A圖(3)之虛線所框起來的部分(A部)之放大剖面圖。通孔61是作為連通內層通孔5、針孔67、以及針孔66所構成。Here, the structure of the through hole 61 will be described in more detail using FIG. Fig. 3 is an enlarged cross-sectional view showing a portion (A portion) which is framed by a broken line in Fig. 2A (3). The through hole 61 is configured to communicate with the inner layer through hole 5, the pinhole 67, and the pinhole 66.
針孔67是具有以銅箔32之開口部35作為光罩而形成的上孔和以銅箔33之開口部36作為光罩而形成的下孔的踏板盲孔。如第3圖所示,按內層通孔5、針孔67之下孔、針孔67之上孔的順序,將直徑變大。亦即,貫通多層電路基材的通孔之直徑,是隨著往內層側而段差變小。The pinhole 67 is a stepped blind hole having an upper hole formed by the opening 35 of the copper foil 32 as a mask and a lower hole formed by using the opening 36 of the copper foil 33 as a mask. As shown in Fig. 3, the diameter is increased in the order of the inner layer through hole 5, the hole below the pinhole 67, and the hole above the pinhole 67. That is, the diameter of the through hole penetrating the multilayer circuit substrate is smaller as the step toward the inner layer side.
針孔66是以銅箔43的開口部45為光罩而形成的針孔。如第3圖所示,針孔66的直徑比內層通孔5的直徑還大。The pinhole 66 is a pinhole formed by the opening 45 of the copper foil 43 as a mask. As shown in Fig. 3, the diameter of the pinhole 66 is larger than the diameter of the inner layer through hole 5.
就一般而言,設置在內層電路基材10的內層通孔5的最大開口徑,是比設置在外層電路基材40、50的針孔66、67的最小開口徑還小。在此,最大開口徑是意味著開口徑的最大值。若內層通孔5的橫斷面形狀是如第3圖所示的圓形,最大開口徑就是該圓的直徑(第3圖中的長度a)。In general, the maximum opening diameter of the inner layer through holes 5 provided in the inner layer circuit substrate 10 is smaller than the minimum opening diameter of the pin holes 66, 67 provided in the outer layer circuit substrates 40, 50. Here, the maximum opening diameter means the maximum value of the opening diameter. If the cross-sectional shape of the inner layer through hole 5 is a circle as shown in Fig. 3, the maximum opening diameter is the diameter of the circle (the length a in Fig. 3).
在此,最小開口徑是意味著開口徑的最小值。若針孔66或針孔67的下孔的橫斷面形狀是具有朝向如第3圖所示的內側之突起部的星形,最小開口徑就能該星形之面對面的兩個突起部間的距離(第3圖中的長度b)。Here, the minimum opening diameter means the minimum value of the opening diameter. If the cross-sectional shape of the lower hole of the pinhole 66 or the pinhole 67 is a star having a protrusion toward the inner side as shown in FIG. 3, the minimum opening diameter is such that the star faces face between the two protrusions. Distance (length b in Figure 3).
在第3圖之放大斷面圖的上方及下方,是分別表示從上側及下側觀看通孔61時的通孔61之俯視圖。The top and bottom of the enlarged cross-sectional view of Fig. 3 are plan views showing the through holes 61 when the through holes 61 are viewed from the upper side and the lower side, respectively.
針孔67之下孔的橫斷面是成為與開口部36的形狀相同。因此,在針孔67之下孔的側壁,是反映開口部36的星形形狀而形成凹凸。同樣地,針孔66的橫斷面是成為與開口部45的形狀相同。因此,在針孔66的側壁,是反映開口部45的星形形狀而形成凹凸。The cross section of the hole below the pinhole 67 is the same as the shape of the opening 36. Therefore, the side wall of the hole below the pinhole 67 reflects the star shape of the opening portion 36 to form irregularities. Similarly, the cross section of the pinhole 66 is the same as the shape of the opening 45. Therefore, the side wall of the pinhole 66 reflects the star shape of the opening 45 to form irregularities.
(3)接著,如第2B圖(4)所示,對通孔61、以及盲孔62~65進行導電化處理。然後,藉由使用填孔電鍍處理用的電鍍藥液(硫酸銅電鍍添加劑,例如奧野製藥工業社製的Top Lucina THF)的填孔電鍍處理(電解電鍍處理),在通孔61、以及盲孔62~65內填充電鍍金屬68,形成填充貫通孔71、以及填孔72~75。(3) Next, as shown in FIG. 2B (4), the via hole 61 and the blind via holes 62 to 65 are electrically conductive. Then, by using a plating solution (copper sulfate plating additive such as Top Lucina THF manufactured by Okuno Pharmaceutical Co., Ltd.) for the hole-fill plating treatment, a hole-fill plating process (electrolytic plating process), a through hole 61, and a blind hole The plating metal 68 is filled in 62 to 65 to form a filled through hole 71 and a filling hole 72 to 75.
藉此,如第2B圖(4)所示,就可以得到以電鍍金屬68填充通孔61、以及盲孔62~65的多層電路基材70。Thereby, as shown in FIG. 2B (4), the multilayer circuit substrate 70 in which the through holes 61 are filled with the plating metal 68 and the blind holes 62 to 65 can be obtained.
在此,針對有關在通孔61內填充有電鍍金屬68的樣子,採用第4A圖及第4B圖做詳細地說明。Here, the manner in which the plating metal 68 is filled in the through hole 61 will be described in detail using FIGS. 4A and 4B.
如第4A圖(1)所示,在填孔電鍍處理的初期,以填孔電鍍藥液之流動性較小的角隅部C為中心,析出電鍍金屬68。然後,連帶進行電鍍處理,如第4A圖(2)所示,析出至通孔61內的電鍍金屬,就會成為以通孔61中之最小徑的領域D為頂部的鼓狀。As shown in Fig. 4A (1), at the initial stage of the hole-fill plating process, the plating metal 68 is deposited centering on the corner portion C having a small fluidity of the hole-fill plating solution. Then, the plating treatment is carried out in association, and as shown in Fig. 4A (2), the plating metal deposited in the through hole 61 is in the shape of a drum having the smallest diameter D in the through hole 61 as the top.
若進一步進行電鍍處理,如第4A圖(2)及(3)所示,通孔61在領域D藉由電鍍金屬69被閉塞。其結果,如第4A圖(3)所示,形成上下兩個研鉢狀的凹部69。由於形成凹部69,電鍍藥液的流動性更為降低,因此促進電鍍填孔。If the plating treatment is further performed, as shown in Figs. 4A (2) and (3), the through hole 61 is occluded in the field D by the plating metal 69. As a result, as shown in Fig. 4A (3), the upper and lower two recessed portions 69 are formed. Since the concave portion 69 is formed, the fluidity of the plating solution is further lowered, thereby promoting plating and filling.
然後,連帶進行填孔電鍍處理,如第4B圖(4)及(5)所示,凹部69變淺,最後成為既定的深度以下,完成填孔電鍍處理。Then, the hole-fill plating treatment is carried out, and as shown in Figs. 4B (4) and (5), the concave portion 69 becomes shallow, and finally becomes a predetermined depth or less, and the hole-fill plating treatment is completed.
像這樣,由於通孔61,是構成具有角隅部,且往內側孔徑變小,所以能迅速地且不會產生氣泡等地,利用電鍍金屬68來填充通孔61。In this manner, since the through hole 61 is formed to have a corner portion and the inner diameter is reduced, the through hole 61 can be filled with the plating metal 68 so that bubbles or the like can be generated quickly.
又,藉由通孔61的填孔電鍍處理,盲孔62、63、64、65也能利用電鍍金屬68填充。因而,能統一通孔61和盲孔62、63、64、65的電鍍填孔製程。Moreover, the blind vias 62, 63, 64, 65 can also be filled with the plating metal 68 by the via plating process of the via 61. Therefore, the plating and hole filling process of the through hole 61 and the blind holes 62, 63, 64, 65 can be unified.
進而,如採用第3圖做說明,針孔67的下孔及針孔66的側壁是褶狀地設有複數個凹部。由於藉由該凹部也會使電鍍藥液的流動性降低,因此填孔電鍍處理之際,會促使電鍍金屬析出至該凹部。其結果,可更迅速地進行金屬的填充。Further, as will be described with reference to Fig. 3, the lower hole of the pinhole 67 and the side wall of the pinhole 66 are provided with a plurality of concave portions in a pleated shape. Since the fluidity of the plating solution is also lowered by the concave portion, the plating metal is deposited to the concave portion during the hole filling plating treatment. As a result, the filling of the metal can be performed more quickly.
(4)接著,如第2B圖(5)所示,例如藉由前述的減除工法,依照既定的圖案來蝕刻多層電路基材70之表層的導電膜,來形成外層配線圖案80A及80B。(4) Next, as shown in FIG. 2B (5), the outer layer wiring patterns 80A and 80B are formed by etching the conductive film on the surface layer of the multilayer circuit substrate 70 in accordance with a predetermined pattern by the above-described subtraction method.
(5)接著,如第2B圖(6)所示,形成保護外層配線圖案80A、80B的防焊劑91。該防焊劑91是在零件安裝用的端子以及連接用的端子之形成預定部位具有開口部91a。 再者,取代防焊劑,也可以使用覆蓋層來形成外層配線圖案80A、80B的保護膜。(5) Next, as shown in Fig. 2B (6), the solder resist 91 for protecting the outer layer wiring patterns 80A, 80B is formed. The solder resist 91 has an opening 91a at a predetermined portion where the terminal for mounting the component and the terminal for connection are formed . Further, instead of the solder resist, a protective film of the outer layer wiring patterns 80A and 80B may be formed using a cover layer.
(6)接著,如第2B圖(6)所示,對著露出於開口部91a之底面的電鍍金屬68施行鍍金或鍍錫等之所要的表面處理,來形成端子92。(6) Next, as shown in Fig. 2B (6), the plating metal 36 exposed on the bottom surface of the opening 91a is subjected to a surface treatment such as gold plating or tin plating to form the terminal 92.
經過以上的製程,完成有關本發明之實施形態的多層撓性印刷配線板90。Through the above process, the multilayer flexible printed wiring board 90 according to the embodiment of the present invention is completed.
接著,針對有關本實施形態之多層撓性印刷配線板90的構成做說明。Next, the configuration of the multilayer flexible printed wiring board 90 of the present embodiment will be described.
如第2B圖(6)所示,多層撓性印刷配線板90,是作為在內層電路基板10的表面及裏面分別層積有多層電路基板40及50所構成。多層電路基材40,是介設著絕緣層(接著劑層11、絕緣膜12、接著劑層51)而層積在內層電路基材10的表面。多層電路基材50,是介設著絕緣層(接著劑層11、絕緣膜12、接著劑層51)而層積在內層電路基材10的裏面。As shown in FIG. 2B (6), the multilayer flexible printed wiring board 90 is formed by laminating a plurality of circuit boards 40 and 50 on the front surface and the back surface of the inner layer circuit board 10. The multilayer circuit substrate 40 is laminated on the surface of the inner layer circuit substrate 10 via an insulating layer (the adhesive layer 11, the insulating film 12, and the adhesive layer 51). The multilayer circuit substrate 50 is laminated on the inside of the inner layer circuit substrate 10 via an insulating layer (the adhesive layer 11, the insulating film 12, and the adhesive layer 51).
又,多層撓性印刷配線板90是在貫通外層電路基板40、內層電路基板10及外層電路基板50的通孔61,具備填充有電鍍金屬的填充貫通孔71。Further, the multilayer flexible printed wiring board 90 is a through hole 61 that penetrates the outer layer circuit board 40, the inner layer circuit board 10, and the outer layer circuit board 50, and has a filled through hole 71 filled with a plating metal.
通孔61是構成連通有:貫通外層電路基材40的針孔67、貫通內層電路基材10的內層通孔5、貫通外層電路基材50的針孔66。又,針孔66、67,是具有比內層通孔5之最大開口徑還大的最小開口徑。The through hole 61 is configured to communicate with a pinhole 67 penetrating the outer layer circuit substrate 40, an inner layer through hole 5 penetrating the inner layer circuit substrate 10, and a pinhole 66 penetrating the outer layer circuit substrate 50. Further, the pinholes 66 and 67 have a minimum opening diameter which is larger than the maximum opening diameter of the inner layer through hole 5.
填充貫通孔71,是電性連接設置在外層電路基材40之兩面的配線圖案、設置在內層電路基材10之兩面的配線圖案、以及設置在外層電路基材50之兩面的配線圖案之合計六層。再者,在通孔5的側壁設有鍍皮膜6,可進一步提昇填充貫通孔71之層間連接的可靠性。The filled through hole 71 is a wiring pattern electrically connected to both surfaces of the outer layer circuit substrate 40, a wiring pattern provided on both surfaces of the inner layer circuit substrate 10, and a wiring pattern provided on both surfaces of the outer layer circuit substrate 50. A total of six floors. Further, a plating film 6 is provided on the side wall of the through hole 5, and the reliability of the interlayer connection filling the through hole 71 can be further improved.
而且,在多層撓性印刷配線板90中,在盲孔亦具備填充有電鍍金屬的填孔72~75。填孔(surface via)74、75,是電性連接被設置在增建層的外層電路基材40、50之兩面的雙層配線圖案。填孔(surface via)72,是電性連接被設置在外層電路基材40與內層電路基材10之雙層的配線圖案。又,填孔(surface via)73,是電性連接被設置在外層電路基材50之兩面的配線圖案以及被設置在內層電路基材10之兩面的配線圖案的三層。Further, in the multilayer flexible printed wiring board 90, the blind holes are also provided with the filling holes 72 to 75 filled with the plating metal. The surface vias 74 and 75 are electrically connected to a double-layer wiring pattern provided on both sides of the outer layer circuit substrates 40 and 50 of the build-up layer. The surface via 72 is a wiring pattern electrically connected to the double layer of the outer layer circuit substrate 40 and the inner layer circuit substrate 10. Further, the surface via 73 electrically connects the wiring patterns provided on both surfaces of the outer layer circuit substrate 50 and the wiring patterns provided on both surfaces of the inner layer circuit substrate 10 in three layers.
如上記,在多層撓性印刷配線板90,層間導電路是利用填孔構造所構成。藉此,如第2B圖(6)所示,可以在填充貫通孔71或填孔72~75的正上方設置端子92。因而,端子之配置自由度增加,可對多層撓性印刷配線板90平行地安裝窄距之CSP等等的電子零件。As described above, in the multilayer flexible printed wiring board 90, the interlayer conductive circuit is constituted by a hole-filling structure. Thereby, as shown in FIG. 2B (6), the terminal 92 can be provided directly above the filling through hole 71 or the filling holes 72 to 75. Therefore, the degree of freedom in the arrangement of the terminals is increased, and electronic components such as a narrow-distance CSP or the like can be mounted in parallel to the multilayer flexible printed wiring board 90.
如以上說明,藉由本發明,積體度高,就可得到能搭載窄距之CSP等等的電子零件的多層印刷配線板。As described above, according to the present invention, a multilayer printed wiring board capable of mounting an electronic component such as a narrow-distance CSP or the like can be obtained with a high degree of integration.
又,多層撓性印刷配線板90,也可以具備作為拉出自由度高的可換性電纜部。該可撓性電纜部,是設成從層積有外層電路基材40、50的零件安裝部開始延伸。Further, the multilayer flexible printed wiring board 90 may be provided with a replaceable cable portion having a high degree of freedom in pulling out. The flexible cable portion is formed to extend from a component mounting portion in which the outer layer circuit substrates 40 and 50 are laminated.
在上記之實施形態之說明中,外層電路基材40、50,是使用雙面覆銅層積板34、44製作,但不限於此,也可以使用單面覆銅層積板製作。第6圖(A),是表示將利用單面覆銅層積板製作的外層電路基材40A、50A,層積在核心基板20的多層印刷配線板90A的斷面圖。In the above description of the embodiment, the outer layer circuit substrates 40 and 50 are formed using the double-sided copper clad laminates 34 and 44. However, the present invention is not limited thereto, and a single-sided copper clad laminate may be used. Fig. 6(A) is a cross-sectional view showing the multilayer printed wiring board 90A laminated on the core substrate 20 by the outer layer circuit substrates 40A and 50A produced by using the single-sided copper clad laminate.
如第6圖(A)所示,外層電路基材40A及50A,是具有加工單面覆銅層積板之銅箔而形成的外層配線圖案,以該外層配線圖案位於外側的方式,使外層電路基材40A及50A介設著接著劑層51A而分別層積在核心基板20的表面及裏面。As shown in Fig. 6(A), the outer layer base materials 40A and 50A are outer layer wiring patterns formed by processing a copper foil of a single-sided copper-clad laminate, and the outer layer wiring pattern is positioned on the outer side to make the outer layer The circuit substrates 40A and 50A are laminated on the surface and the inside of the core substrate 20 via the adhesive layer 51A.
又,在上記之實施形態的說明中,雖是在內層電路基材10層壓覆蓋層13而製作核心基板20,然後將外層電路基材層積在核心基板20,但並不限於此,也可以在內層電路基材10直接層積外層電路基材。第6圖(B),是表示將利用單面覆銅層積板製作的外層電路基材40B、50B,層積在內層電路基材10的多層印刷配線板90B的斷面圖。Further, in the above description of the embodiment, the core substrate 20 is formed by laminating the cover layer 13 on the inner layer circuit substrate 10, and then the outer layer circuit substrate is laminated on the core substrate 20. However, the present invention is not limited thereto. It is also possible to directly laminate the outer layer circuit substrate on the inner layer substrate 10. Fig. 6(B) is a cross-sectional view showing the multilayer printed wiring board 90B in which the outer layer circuit substrates 40B and 50B produced by the single-sided copper clad laminate are laminated on the inner layer circuit substrate 10.
如第6圖(B)所示,外層電路基材40B及50B,是具有加工單面覆銅層積板之銅箔而形成的外層配線圖案,以該外層配線圖案位於外側的方式,使外層電路基材40B及50B介設著接著劑層51B而分別層積在內層電路基材10的表面及裏面。如第6圖(B)即可明白,為了絕緣保護內層電路基材10的內層配線圖案,外層電路基材40B、50B也可層積在可撓性電纜部。As shown in Fig. 6(B), the outer layer base materials 40B and 50B are outer layer wiring patterns formed by processing a copper foil of a single-sided copper-clad laminate, and the outer layer wiring pattern is positioned on the outer side to make the outer layer The circuit substrates 40B and 50B are laminated on the surface and the inside of the inner layer circuit substrate 10 via the adhesive layer 51B. As can be seen from Fig. 6(B), in order to insulate and protect the inner layer wiring pattern of the inner layer circuit substrate 10, the outer layer circuit substrates 40B and 50B may be laminated on the flexible cable portion.
再者,將外層電路基材40B、50B層積在內層電路基材10之方法,具有兩大方法。Further, there are two major methods for laminating the outer layer circuit substrates 40B and 50B on the inner layer circuit substrate 10.
第一方法,是以填充內層電路基材10之內層配線圖案8A、8B及電鍍通孔7的方式來形成接著劑層51B,在該接著劑層51B之上層積外層電路基材40B、50B的方法。In the first method, the adhesive layer 51B is formed by filling the inner wiring patterns 8A and 8B of the inner layer circuit substrate 10 and the plated through holes 7, and the outer layer circuit substrate 40B is laminated on the adhesive layer 51B. 50B method.
第二方法,是採用在未形成有銅箔之一方的面具有接著劑層的附接著劑層單面覆銅積層板的方法。在該方法中,加工單面覆銅層積板的銅箔而製作外層電路基材40B、50B,將該外層電路基材40B、50B層壓在內層電路基材10。再者,也可以將附接著劑層單面覆銅層積板層壓在內層電路基材10之後,加工表面的銅箔來形成外層配線圖案。The second method is a method of using a single-sided copper-clad laminate having an adhesive layer having an adhesive layer on a side where no copper foil is formed. In this method, the copper foil of the single-sided copper-clad laminate is processed to form the outer-layer circuit substrates 40B and 50B, and the outer-layer circuit substrates 40B and 50B are laminated on the inner-layer circuit substrate 10. Further, after the adhesive layer single-sided copper-clad laminate is laminated on the inner layer substrate 10, the copper foil on the surface may be processed to form an outer wiring pattern.
而且,也可以在核心基板20(或是內層電路基材10)之一方的面,自雙面覆銅層積板開始層積已製成的外層電路基材,在另一面,自單面覆銅層積板開始層積已製成的外層電路基材。Further, on the one side of the core substrate 20 (or the inner layer circuit substrate 10), the outer layer circuit substrate which has been formed may be laminated from the double-sided copper-clad laminate, and the other surface may be self-contained. The copper clad laminate begins to laminate the finished outer circuit substrate.
以上,針對有關本發明之多層印刷配線板及其製造方法做說明。The multilayer printed wiring board and the method of manufacturing the same according to the present invention will be described above.
在上記實施形態之說明中,作為將銅箔等之導電膜圖案化而設置配線圖案及開口部的手法,雖是採用減除工法,但並不限於此,也可以使用半加成工法(Semi-additive process)等其他的工法。In the above description, the method of providing a wiring pattern and an opening by patterning a conductive film such as a copper foil is not limited thereto, and a semi-additive method (Semi) may be used. -additive process) and other methods.
又,作為正形投影光罩之功能的開口部,也可以在將外層電路基材層積在核心基板之後予以形成。除此之外,作為雷射加工法,也可以不採用正形投影光罩的方法,亦即可採用直接對導電膜上照射雷射光,除去導電膜及其下面的絕緣層之直接雷射加工法。Further, the opening portion functioning as a positive projection mask may be formed after the outer layer circuit substrate is laminated on the core substrate. In addition, as a laser processing method, it is also possible to use a method of directly projecting a reticle, or to directly irradiate the conductive film with laser light, and to remove the conductive film and the direct laser processing of the insulating layer below it. law.
又,於針孔66、67,橫斷面之形狀並不限於第3圖所示的星形。只要在填孔電鍍處理中,設有欲令電鍍藥液之流動性下降的構造(凹凸等)即可。而且,不光是針孔67的下孔,也可以在上孔之側壁設置凹部。Further, in the pinholes 66 and 67, the shape of the cross section is not limited to the star shape shown in Fig. 3. In the hole-fill plating process, a structure (concavity or the like) for degrading the fluidity of the plating solution may be provided. Further, not only the lower hole of the pinhole 67 but also the concave portion may be provided on the side wall of the upper hole.
而且,在上記實施形態中,雖是針對多層撓性印刷配線板做說明,但並不限於此,對於軟硬複合(Rigid-Flex)印刷配線板或多層剛性印刷(Rigid-Printed)配線板等其他多層印刷配線板也適用本發明。Further, in the above-described embodiment, the multilayer flexible printed wiring board is described. However, the present invention is not limited thereto, and a Rigid-Flex printed wiring board or a multi-layer rigid printed (Rigid-Printed) wiring board is not limited thereto. Other multilayer printed wiring boards are also applicable to the present invention.
而且,配線圖案或電鍍金屬並不限於銅。亦即,在上記實施形態之說明中,雖然構成配線圖案的金屬及填充到針孔等的電鍍金屬是銅,但本發明並不限於此,例如也可以是鋁或銀等其他金屬。Moreover, the wiring pattern or the plating metal is not limited to copper. In other words, in the description of the above embodiment, the metal constituting the wiring pattern and the plating metal filled in the pinhole or the like are copper. However, the present invention is not limited thereto, and for example, other metals such as aluminum or silver may be used.
而且,雖然上記實施形態的多層撓性印刷配線板是具有六層之配線圖案者,但並不限於此。對於在多層電路基材40、50之上進一步層積外層電路基材的多層印刷配線板,也能應用本發明。Further, the multilayer flexible printed wiring board according to the above embodiment is a wiring pattern having six layers, but is not limited thereto. The present invention can also be applied to a multilayer printed wiring board in which an outer layer circuit substrate is further laminated on the multilayer circuit substrates 40, 50.
根據上記記載,雖說只要是該業者,或許也能思及本發明之追加效果和各種變形,但本發明之形態,並不限於上述之實施形態。在不脫離申請專利範圍所規定的內容及其等效設計所導出的本發明之概念上的思想與主旨之範圍下,可做各種追加、變更及部分增減。According to the above description, the additional effects and various modifications of the present invention may be considered as long as the manufacturer is concerned, but the form of the present invention is not limited to the above embodiment. Various additions, modifications, and partial additions and deletions may be made without departing from the spirit and scope of the invention as set forth in the appended claims.
1...絕緣基層膜1. . . Insulating base film
2、3...銅箔2, 3. . . Copper foil
4...雙面覆銅層積板4. . . Double-sided copper laminate
5...內層通孔5. . . Inner through hole
6...鍍皮膜6. . . Coating
7...鍍通孔7. . . Plated through hole
8A、8B...內層配線圖案8A, 8B. . . Inner wiring pattern
10...內層電路基材10. . . Inner circuit substrate
11...接著劑層11. . . Subsequent layer
12...絕緣膜12. . . Insulating film
13...覆蓋蓋13. . . Cover cover
20...核心基板20. . . Core substrate
31、41...絕緣基層膜31, 41. . . Insulating base film
32、33、42、43...銅箔32, 33, 42, 43. . . Copper foil
34、44...雙面覆銅層積板34, 44. . . Double-sided copper laminate
35、36、37、38、45、46、47、48...開口部35, 36, 37, 38, 45, 46, 47, 48. . . Opening
39、49...外層配線圖案39, 49. . . Outer wiring pattern
40、40A、40B、50、50A、50B...外層電路基材40, 40A, 40B, 50, 50A, 50B. . . Outer circuit substrate
51、51A、51B...接著劑層51, 51A, 51B. . . Subsequent layer
60...多層回路基材60. . . Multilayer circuit substrate
61...通孔61. . . Through hole
62、63、64、65...盲孔62, 63, 64, 65. . . Blind hole
66、67...針孔66, 67. . . Pinhole
68...電鍍金屬68. . . Plating metal
69...凹部69. . . Concave
70...多層電路基材70. . . Multilayer circuit substrate
71...填充貫通孔71. . . Filling through hole
72、73、74、75...填孔72, 73, 74, 75. . . Fill hole
80A、80B...外層配線圖案80A, 80B. . . Outer wiring pattern
90、90A、90B...多層印刷配線板90, 90A, 90B. . . Multilayer printed wiring board
91...防焊劑91. . . Solder resist
91a...開口部91a. . . Opening
92...端子92. . . Terminal
100...內層電路基材100. . . Inner circuit substrate
110...覆蓋層110. . . Cover layer
120...接著劑層120. . . Subsequent layer
130...絕緣膜130. . . Insulating film
200...核心基板200. . . Core substrate
210...層積接著劑層210. . . Laminated adhesive layer
300...外層電路基材300. . . Outer circuit substrate
310...開口部310. . . Opening
400...多層電路基材400. . . Multilayer circuit substrate
410、420...盲孔410, 420. . . Blind hole
430...通孔430. . . Through hole
450...鍍皮膜450. . . Coating
460、470、480...鍍盲孔460, 470, 480. . . Plating blind hole
490...鍍通孔490. . . Plated through hole
500...外層電路配線圖案500. . . Outer circuit wiring pattern
510...防焊劑510. . . Solder resist
510a...開口部510a. . . Opening
520...端子520. . . Terminal
600...多層印刷配線板600. . . Multilayer printed wiring board
C...角隅部C. . . Corner
D...中央領域D. . . Central area
第1A圖是表示有關本發明之實施形態的多層撓性印刷配線板之製造方法的製程剖面圖。Fig. 1A is a cross-sectional view showing a process of a method of manufacturing a multilayer flexible printed wiring board according to an embodiment of the present invention.
第1B圖是表示有關本發明之實施形態的多層撓性印刷配線板之製造方法的製程剖面圖。Fig. 1B is a cross-sectional view showing a process of a method of manufacturing a multilayer flexible printed wiring board according to an embodiment of the present invention.
第2A圖是表示有關本發明之實施形態的多層撓性印刷配線板之製造方法的製程剖面圖。Fig. 2A is a cross-sectional view showing a process of manufacturing a multilayer flexible printed wiring board according to an embodiment of the present invention.
第2B圖是接續第2A圖,表示有關本發明之實施形態的多層撓性印刷配線板之製造方法的製程剖面圖。Fig. 2B is a cross-sectional view showing a process of manufacturing a multilayer flexible printed wiring board according to an embodiment of the present invention, taken along line 2A.
第3圖是表示放大第2A圖(3)之A部的剖面圖,以及通孔之俯視圖。Fig. 3 is a cross-sectional view showing a portion A of Fig. 2A (3), and a plan view of the through hole.
第4A圖是表示在通孔內填充電鍍金屬之形態的剖面圖。Fig. 4A is a cross-sectional view showing a state in which a plating metal is filled in a through hole.
第4B圖是接續第4A圖,表示在通孔內填充電鍍金屬之形態的剖面圖。Fig. 4B is a cross-sectional view showing the form in which the plating metal is filled in the through hole, continued from Fig. 4A.
第5A圖是表示有關比較例之多層撓性印刷配線板之製造方法的製程剖面圖。Fig. 5A is a process sectional view showing a method of manufacturing a multilayer flexible printed wiring board according to a comparative example.
第5B圖是接續第5A圖,表示有關比較例之多層撓性印刷配線板之製造方法的製程剖面圖。Fig. 5B is a cross-sectional view showing a process of manufacturing a multilayer flexible printed wiring board according to a comparative example, taken along line 5A.
第6圖(A)是從單面覆銅層積板開始將已製成的外層電路基材層積在核心基板的多層撓性印刷配線板的剖面圖,(B)是從單面覆銅層積板開始將已製成的外層電路基材層積在內層電路基材的多層撓性印刷配線板的剖面圖。Fig. 6(A) is a cross-sectional view showing a multilayer flexible printed wiring board in which a completed outer layer circuit substrate is laminated on a core substrate from a single-sided copper clad laminate, and (B) is a single-sided copper clad layer. The laminated board starts a cross-sectional view of a multilayer flexible printed wiring board in which an outer layer circuit substrate which has been formed is laminated on an inner layer circuit substrate.
10...內層電路基材10. . . Inner circuit substrate
40、50...外層電路基材40, 50. . . Outer circuit substrate
68...電鍍金屬68. . . Plating metal
70...多層電路基材70. . . Multilayer circuit substrate
71...填充貫通孔71. . . Filling through hole
72、73、74、75...填孔72, 73, 74, 75. . . Fill hole
80A、80B...外層配線圖案80A, 80B. . . Outer wiring pattern
90...多層印刷配線板90. . . Multilayer printed wiring board
91...防焊劑91. . . Solder resist
91a...開口部91a. . . Opening
92...端子92. . . Terminal
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JP7032128B2 (en) * | 2017-12-25 | 2022-03-08 | 住友電工プリントサーキット株式会社 | Manufacturing method of printed wiring board and printed wiring board |
JP2019161204A (en) * | 2018-03-16 | 2019-09-19 | 株式会社 大昌電子 | Method for forming via hole in printed wiring board, filled via structure in printed wiring board, and printed wiring board |
US11315827B2 (en) | 2020-03-09 | 2022-04-26 | International Business Machines Corporation | Skip via connection between metallization levels |
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