WO2011096293A1

WO2011096293A1 - Method of manufacturing multi-layered printed circuit board

Info

Publication number: WO2011096293A1
Application number: PCT/JP2011/051255
Authority: WO
Inventors: 文彦松田
Original assignee: 日本メクトロン株式会社
Priority date: 2010-02-08
Filing date: 2011-01-25
Publication date: 2011-08-11
Also published as: CN102308679A; JP5485299B2; TW201146123A; JPWO2011096293A1; CN102308679B; TWI487451B

Abstract

Disclosed is a method of manufacturing build-up type multi-layer printed circuit boards having a stacked via structure allowing high-density component mounting. After forming a plated through via hole (9) and a plated via hole with a bottom (10) in a dual-side copper-clad laminate board, the copper foil on both sides of the dual-side copper-clad laminate board is patterned, resulting in a substrate with dual-side flexibility. Two cover lays (16) are prepared and laminated upon both sides of the substrate with dual-side flexibility. The laminating process is carried out under the following conditions: the interior of the plated through via hole (9) is completely filled with an adhesive agent derived by melting an adhesive agent layer (15) of the cover lay (16); and an air void (15a) may be allowed to occur, such that the interior of the plated via hole with the bottom (10) cannot be filled with the adhesive agent. After adhering a single-side copper-clad laminate board (20) to an insulator film (14) with an adhesive agent layer (22), laser working is used to remove the adhesive agent, and eliminate the air void (15a), within the plated via hole with the bottom (10), forming a step via hole such that the plated via hole with the bottom (10) becomes a lower hole.

Description

Manufacturing method of multilayer printed wiring board

The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a build-up type multilayer printed wiring board.

In recent years, as represented by mobile information terminals such as mobile phones, electronic devices are becoming smaller and more functional. For this reason, there is an increasing demand for higher density of printed wiring boards used in electronic devices.

Therefore, a build-up type multilayer flexible printed wiring board has been actively researched and developed in order to mount electronic components and the like on the printed wiring board with high density (see, for example, Patent Document 1). This build-up type multilayer flexible printed wiring board is obtained by forming a double-sided flexible printed wiring board or a multilayer flexible printed wiring board as a core substrate and forming one or two build-up layers on both sides or one side of the core substrate. . In order to electrically connect the buildup layer and the inner core substrate, the buildup type multilayer flexible printed wiring board is subjected to interlayer conduction by plating the inner wall of the bottomed via hole (conduction hole). The plated via hole obtained is provided.

However, the following problems occur as the bottomed via hole becomes deeper. First, each component of the printed wiring board is thermally expanded, so that the plated via hole is easily broken. Further, when a plating film is formed on the inner wall of a bottomed via hole in order to obtain interlayer conduction, the plating solution tends to stay at the bottom of the via hole, so that a desired plating thickness cannot be obtained. For this reason, the deeper the bottomed via hole is, the more difficult it is to ensure the electrical reliability of the via wiring.

As a countermeasure against this problem, it is conceivable to form a sufficiently thick plating film on the inner wall of the bottomed via hole. However, when the thickness of the plating film formed on the inner wall of the bottomed via hole is increased, the thickness of the conductor layer formed on the buildup layer is inevitably increased accordingly. The circuit pattern of the outer layer is formed by wet etching the conductor layer on the buildup layer according to a desired pattern. For this reason, as the thickness of the conductor layer increases, it becomes difficult to finely process the conductor layer on the build-up layer. As a result, a fine pattern cannot be formed as the circuit pattern of the outer layer, and it is difficult to mount electronic components on the buildup layer at high density.

As described above, the conventional build-up type multilayer flexible printed wiring board has a problem that it is difficult to satisfy the demand for high-density mounting.

Incidentally, among the build-up type multilayer flexible printed wiring boards, in particular, a build-up type multilayer flexible printed wiring board having a so-called stack via structure is demanded from the viewpoint of increasing the density and improving the degree of freedom in design. Here, the stack via structure refers to a structure in which an interlayer connection portion constituted by a plating via hole of a buildup layer is placed on an interlayer connection portion constituted by a plating via hole of a core substrate.

There is a strong demand for a method for stably and inexpensively manufacturing a multilayer printed wiring board having a stacked via structure capable of high-density mounting.

Conventionally, there has been disclosed a method of forming via holes having a so-called step via structure (step via holes) collectively by laser processing (see Patent Document 2, Patent Document 3 and Patent Document 4). According to the methods disclosed in these documents, a step via structure can be formed efficiently. However, in this method, the electrolytic copper plating for covering the inner wall of the step via hole with a plating film is usually performed all at once. For this reason, the plating film formed on the side wall of the prepared hole (small diameter side) of the step via hole tends to be thin. Therefore, it may be difficult to ensure sufficient reliability of interlayer connection.

Next, a method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure according to the prior art will be described in detail with reference to FIG. FIG. 3 is a process cross-sectional view for explaining a manufacturing method of a build-up type multilayer printed wiring board having a stacked via structure.

First, a double-sided copper clad laminate 104 having a flexible insulating base material 101 such as polyimide (for example, 25 μm thick) and a copper foil 102 and a copper foil 103 (both for example 8 μm thick) on both sides thereof is prepared.

Next, as can be seen from FIG. 3A, a bottomed via hole 105 which is a bottomed via hole is formed on the double-sided copper-clad laminate 104 by a laser processing method. The copper foil 103 is exposed at the bottom of the bottomed via hole 105. Thereafter, a conductive treatment and subsequent electrolytic plating treatment are performed on the

copper foils

102 and 103 and the bottomed via hole 105, thereby forming an electrolytic plating film on the

copper foils

102 and 103 and on the inner wall of the bottomed via hole 105. The thickness of the electrolytic plating film is set to a value (for example, about 15 μm) necessary to ensure connection reliability of the via wiring. Through the steps so far, the plated bottomed via hole 106, which is a bottomed interlayer conductive portion that electrically connects the copper foil 102 and the copper foil 103 of the flexible insulating base material 101, is formed.

Next, as can be seen from FIG. 3A, a circuit pattern (inner layer circuit) is obtained by etching the copper foil 102 and the copper foil 103 of the flexible insulating base material 101 according to a predetermined pattern by a photofabrication method. Pattern). More specifically, circuit patterns are formed on both surfaces of the flexible insulating base material 101 by a series of steps including resist layer formation, exposure, development, copper foil etching, and resist layer peeling.

Next, as can be seen from FIG. 3 (1), a coverlay 109 having an adhesive layer 108 is prepared on an insulating film 107 (for example, 12 μm thick) such as a polyimide film. The adhesive layer 108 is made of an adhesive such as acrylic or epoxy. Then, using a vacuum laminator or the like, a laminating process is performed in which the cover lay 109 is attached onto the flexible insulating base material 101 on which the circuit pattern is formed. The thickness of the adhesive layer 108 is set to a thickness (for example, 25 μm) that can completely fill the inside of the plated bottomed via hole 106 with an adhesive. Through the steps so far, a double-sided core substrate 110 shown in FIG.

Next, as can be seen from FIG. 3B, a single-sided copper clad laminate 111 having a copper foil (for example, 12 μm thick) on one side of a flexible insulating base material (for example, polyimide having a thickness of 25 μm) is prepared. An opening is formed in a predetermined portion of the copper foil of the single-sided copper clad laminate 111 by the photofabrication method described above. The copper foil having the opening serves as a conformal mask (also referred to as a metal mask) for laser shielding. The opening formed in the copper foil is for removing a resin such as a flexible insulating base material exposed at the bottom of the opening by laser processing to form a via hole.

Next, as can be seen from FIG. 3 (2), the single-sided copper-

clad laminates

111 and 111 having a conformal mask are bonded to the

adhesive layers

112 and 112 using an adhesive for building up the double-sided core substrate 110. Are laminated and adhered to the front and back surfaces of the double-sided core substrate 110, respectively.

Next, as can be seen from FIG. 3B, the step via hole 113A and the

via holes

113B and 113C are formed by performing laser processing using the conformal mask of the single-sided copper clad laminate 111.

Next, as can be seen from FIG. 3 (3), the conductive treatment and the subsequent electroplating treatment are performed on the copper foil of the single-sided copper clad laminate 111 on the inner wall of the step via hole 113A and the inner walls of the

via holes

113B and 113C. Thus, an electrolytic plating film is formed. The thickness of the electrolytic plating film is, for example, about 25 to 30 μm in order to ensure the reliability of interlayer connection. As a result, plating buildup via

holes

114A, 114B, and 114C for obtaining interlayer conduction between the core substrate and the buildup layer are formed. The plating buildup via hole 114A is obtained by plating the inner wall of the step via hole 113A, and the plating buildup via hole 114B is obtained by plating the inner wall of the via hole 113B facing the step via hole 113A. The plating buildup via hole 114C is obtained by plating the inner wall of the via hole 113C.

Next, as can be seen from FIG. 3 (3), the outer

layer circuit patterns

115 and 115 are formed by etching the copper foil of the single-sided copper-

clad laminates

111 and 111 according to a predetermined pattern using a photofabrication method. To do. After that, if necessary, a photo solder resist layer (not shown) is formed, surface treatments such as solder plating, nickel plating, gold plating are applied to the terminals of the circuit pattern, and outer shape processing is performed by punching with a mold or the like. Do.

Through the above steps, a build-up type multilayer printed wiring board 116 having a stacked via structure is obtained. As can be seen from FIG. 3 (3), the plated buildup via hole 114A is formed immediately above the plated bottomed via hole 106 of the inner-layer double-sided core substrate 110, and the plated bottomed via hole 106 and the plated buildup via hole 114A are stacked. A via structure is formed. In the build-up type multilayer printed wiring board 116, the interlayer connection between the front surface and the back surface of the double-sided core substrate 110 is made by the plated bottom via hole 106.

As can be seen from FIG. 3 (3), the build-up type multilayer printed wiring board 116 includes a component mounting portion 116a in which a build-up layer is laminated on the double-sided core substrate 110, and a flexible extending from the component mounting portion 116b. Cable portion 116b. The flexible cable portion 116b is a part of the double-sided core substrate 110 on which no buildup layer is provided.

In the above process, the inside of the plated bottomed via hole 106 needs to be completely filled with an adhesive. However, the plated-bottomed via hole 106 is harder to fill the adhesive than the plated through via hole formed by plating the inner wall of the via hole that penetrates the double-sided copper clad laminate 104. This is because a through-plating via hole can be filled from two directions of the front and back surfaces, whereas a bottomed plated via hole can be filled only from one direction. For this reason, the thickness of the adhesive layer 108 is inevitably increased as compared to the case where the interlayer connection of the double-sided core substrate 110 is performed by a plated through via hole. Therefore, the build-up via hole 113 is deepened. Then, as described above, the plating thickness for ensuring the reliability of the interlayer connection is increased. For example, when the plated build-up via

holes

114A, 114B, and 114C are formed as described above, it is necessary to perform electrolytic plating to form a plating film of about 25 to 30 μm. If this level of electrolytic plating is performed on the copper foil (12 μm thick) of the single-sided copper-clad laminate 111, the thickness of the conductor layer (copper foil + electrolytic plating film) on the single-sided copper-clad laminate 111 is 37-42 μm. Since the patterning of the conductor layer is performed by wet etching, it is difficult to form a fine circuit pattern with a circuit pitch of about 100 μm with a high yield.

As described above, conventionally, there has been a problem that a build-up type multilayer printed wiring board that satisfies the demand for high-density mounting cannot be manufactured. Needless to say, this problem also applies to a multilayer printed wiring board that does not have the flexible cable 116b.

JP 2004-200260 A JP 2008-235801 A JP 2008-288434 A JP 2009-026912 A

The present invention solves the above-described problem that a multilayer printed wiring board capable of high-density mounting cannot be obtained because it is difficult to form a fine outer layer circuit pattern. An object of the present invention is to provide a method for producing a build-up type multilayer printed wiring board having a structure.

According to one embodiment of the present invention, the first conductive film and the second conductive film are electrically connected to a double-sided conductive film-clad laminate having a first conductive film and a second conductive film on a front surface and a back surface, respectively. Through-plating via holes and plated-bottomed via holes to be connected to each other,
Etching the first conductive film and the second conductive film according to a predetermined pattern to produce a double-sided flexible substrate having an inner circuit pattern,
Preparing a coverlay having an insulating film and an adhesive layer formed on one side of the insulating film;
Conditions that allow the inside of the plated through via hole to be completely filled with an adhesive in which the adhesive layer of the coverlay is melted, and allow the generation of air voids not filled with the adhesive into the plated bottomed via hole Underneath, performing a laminating step of pasting the coverlay on both sides of the double-sided flexible substrate, thereby producing a double-sided core substrate,
A buildup layer having a third conductive film formed on one side is laminated and bonded to at least the opening side of the plated bottomed via hole of the double-sided core substrate,
By laser processing, the adhesive inside the plated bottomed via hole is removed and the air voids disappear, thereby exposing the plated bottomed via hole to the bottom and forming a step via hole where the plated bottomed via hole serves as a pilot hole. Forming,
A plating buildup via hole that electrically connects the third conductive film and the inner layer circuit pattern is formed by plating the third conductive film and the inner wall of the step via hole.
An outer layer circuit pattern is formed by etching the third conductive film that has been plated in accordance with a predetermined pattern, thereby providing a method for manufacturing a multilayer printed wiring board.

Due to these features, the present invention has the following effects.

In a build-up type multilayer printed wiring board having a stacked via structure according to an embodiment of the present invention, the stacked via structure includes a plated bottomed via hole that electrically connects the front surface and the back surface of a double-sided flexible substrate, and this plating. It is comprised from the plating buildup via hole arrange | positioned on the bottomed via hole. This plated build-up via hole is for electrically connecting the outer layer circuit pattern and the inner layer circuit pattern, and the plating film is formed on the inner wall of the step via hole with the bottomed via hole formed on the double-sided flexible substrate as a small diameter hole. Is formed. As a result, a step via structure including a plated bottom via hole and a plated buildup via hole formed thereon is formed.

Due to such features, according to one embodiment of the present invention, when laminating a coverlay, it is not necessary to completely fill the inside of the plated bottomed via hole formed in the double-sided flexible substrate with the adhesive. Absent. This is because the adhesive in the plated-bottomed via hole is removed when forming the aforementioned step via hole. For this reason, the thickness of the adhesive layer can be made as small as possible within a range in which the adhesive can be filled into the through via hole of the double-sided flexible substrate.

As a result, the step via hole can be made shallower than in the prior art. Thereby, when performing an electroplating process in order to form a plating buildup via hole, the ease of electrodeposition is improved and the influence on the plating buildup via hole due to the thermal expansion of the constituent members is reduced.

For this reason, according to the present invention, the yield can be improved, and the plating thickness required to ensure the connection reliability of the via wiring can be reduced as much as possible. Therefore, according to the present invention, the outer layer circuit pattern formed in the buildup layer can be made finer.

Furthermore, according to the present invention, when the plated build-up via hole is formed, an electrolytic plating film is also formed on the plated bottomed via hole of the double-sided flexible substrate. This reinforces the plated bottomed via hole where thermal stress tends to concentrate compared to the plated through via hole due to the asymmetric shape, and can improve the connection reliability.

Furthermore, since the plated-bottomed via hole is reinforced as described above, the plating thickness of the plated-bottomed via hole can be reduced to such an extent that the connection reliability of the plated through via hole can be ensured. As a result, the time required for the plating process is shortened, and the cost can be reduced. Further, the inner layer circuit pattern formed on the double-sided flexible substrate can be miniaturized.

As described above, according to the present invention, a method for stably and inexpensively manufacturing a build-up type multilayer printed wiring board having a stack via structure capable of high-density mounting is provided.

It is process sectional drawing for demonstrating the manufacturing method of the buildup type multilayer printed wiring board which concerns on embodiment of this invention. It is process sectional drawing for demonstrating the manufacturing method of the buildup type multilayer printed wiring board which concerns on embodiment of this invention following FIG. 1A. It is process sectional drawing for demonstrating the manufacturing method of the buildup type multilayer printed wiring board which concerns on embodiment of this invention following FIG. 1B. It is sectional drawing of the buildup type multilayer printed wiring board which concerns on embodiment of this invention. It is process sectional drawing of the manufacturing method of the buildup type multilayer printed wiring board which has a stack via structure by a prior art.

Hereinafter, a method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure according to an embodiment of the present invention will be described with reference to the drawings.

In addition, the same code | symbol is attached | subjected to the component which has an equivalent function, and detailed description is abbreviate | omitted. Further, the drawings are schematic and show mainly the characteristic portions according to the embodiment, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the manufacturing method of the build-up type multilayer printed wiring board 32 having the stack via structure according to the embodiment of the present invention will be described with reference to FIGS. 1A to 1C and FIG.

1A to 1C are process cross-sectional views for explaining a manufacturing method of the build-up type multilayer printed wiring board 32. FIG. FIG. 2 is a cross-sectional view of the build-up type multilayer printed wiring board 32 according to the present embodiment.

First, as can be seen from FIG. 1A (1), copper foil 2 and copper foil 3 (first conductive film and second conductive film) are formed on both sides of a flexible insulating base material 1 (for example, polyimide having a thickness of 25 μm), respectively. 2 is prepared. The thicknesses of the copper foil 2 and the copper foil 3 are both 5 μm, for example.

Next, through via holes 5 and bottomed via holes 6 penetrating the double-sided copper-clad laminate 4 are formed on the double-sided copper-clad laminate 4 by using a laser processing method or a resin etching method. As can be seen from FIG. 1A (1), the bottomed via hole 6 is a bottomed via hole in which the copper foil 3 is exposed on the bottom surface. Both the through-hole 5 and the bottomed via-hole 6 have a processing diameter of, for example, 70 μm.

When the laser processing method is used in this step, the following two methods can be selected. The first method is a method called a conformal laser processing method. In this method, an opening having the same diameter as the via hole diameter is provided in the copper foils 2 and 3 to form a conformal mask. Thereafter, the conformal mask is irradiated with laser light to remove the insulating resin exposed in the opening. The second method is a method called a direct laser processing method. In this method, without forming a conformal mask, laser light is directly irradiated on the copper foil to remove the copper foil and the underlying insulating resin. In the present embodiment, a direct laser processing method using a carbon dioxide gas laser is selected in consideration of productivity, not a conformal laser processing method that requires a copper foil etching process by a photofabrication method.

Before performing this direct laser processing method, the copper foils 2 and 3 of the double-sided copper clad laminate 4 are subjected to surface treatment. That is, the roughening process which makes the copper foil surface irradiated with a laser beam low roughness is performed. Thereby, when performing laser processing using a carbon dioxide laser (wavelength: about 9.8 μm), the absorption of laser light of the copper foils 2 and 3 can be stably improved. In this embodiment, the multi bond 150 of Nippon McDermitt Co., Ltd. was used for this roughening process. Thereby, the adhesiveness with the electrolytic copper plating film 7 formed in a later step is ensured, and the absorption of the carbon dioxide laser beam on the surface of the copper foil can be improved. Actually, it was confirmed that the absorption rate of the carbon dioxide laser beam was improved from about 20% to about 30% before and after the surface treatment.

In the present embodiment, the through via hole 5 and the bottomed via hole 6 are processed simultaneously. For this reason, processing of the copper foil 2 is facilitated by performing the above-described roughening treatment on the surface of the copper foil 2. At the same time, as the back surface treatment of the copper foil 3, the copper foil surface is processed to have a low roughness so as not to penetrate the copper foil 3 when forming the bottomed via hole 6, thereby reducing the absorption of laser light. preferable. However, when it is desired to efficiently form the through via hole 5, it is preferable to perform a roughening treatment as the back surface treatment of the copper foil 3.

As the copper foils 2 and 3 of the double-sided copper-clad laminate 4 are thinner, penetration of the copper foils 2 and 3 is more likely to occur during laser processing. Therefore, when the thickness of the copper foil is as thin as 10 μm or less as in the present embodiment, in order to facilitate the formation of the bottomed via hole 6, the roughening treatment is hardly performed as the back surface treatment, and the low roughness. It is preferable to use a copper foil 3.

Here, the laser processing method will be described in detail. First, the case where the bottomed via hole 6 is processed will be described. When processing the copper foil 2, the energy of the laser beam per shot is increased (referred to as power P). Preferably, the processing of the copper foil 2 is completed with one shot. Thereafter, when the resin of the flexible insulating base material 1 is processed until the copper foil 3 is exposed, the energy of the laser beam per shot is reduced to (1/2) P to (1/3) P, and 2 Complete resin processing in 3 shots. Next, the case of the through via hole 5 will be described. In this case, the copper foil and the resin on both sides are processed using the laser beam having the above-mentioned power P as the energy of the laser beam per shot. 3 to 4 shots are continuously irradiated to complete the processing of the through via hole 5.

When a thinner copper foil is used, the back surface (surface in contact with the base material) of the copper foil 3 serving as the bottom of the bottomed via hole 6 is set to a low roughness in order to facilitate the formation of the bottomed via hole 6. At the same time, a roughening process is performed on the back surface (surface in contact with the base material) of the copper foil 2. The through via hole 5 is formed by processing from the surface of the copper foil 3. According to this method, the through via hole can be efficiently formed while facilitating the formation of the bottomed via hole 6. As another method, the through via hole 5 may be formed by performing laser processing from two directions of the surface of the copper foil 2 and the surface of the copper foil 3. In this case, since the surface of the copper foils 2 and 3 is subjected to the roughening treatment, the processing from any direction is easy, and the state of the back surface treatment (roughness level) of the copper foil is considered There is an advantage that it is not necessary.

Next, plasma treatment and wet etching (desmear treatment) are performed to remove smear (resin residue) generated when the through via hole 5 and the bottomed via hole 6 are formed. The optimum conditions for this plasma treatment for the through via hole 5 and the bottomed via hole 6 are almost the same. On the other hand, for wet etching using sodium persulfate or the like, optimum conditions differ between the two. That is, almost no wet etching is required for the through via hole 5. Rather, the etching may cause the copper foils 2 and 3 to recede and adversely affect the subsequent conductive treatment. On the other hand, the bottomed via hole 6 needs to be etched by 1 to 2 μm in order to remove dissimilar metals such as nickel and chromium on the back surface of the copper foil 3 by the back surface treatment. In consideration of the influence on the through via hole 5, it is preferable to complete the processing with as small an etching amount as possible. In this embodiment, 1 μm etching was performed.

Next, as can be seen from FIG. 1A (2), electrolysis treatment and subsequent electrolytic copper plating treatment are applied to the inner walls of the through via holes 5 and the bottomed via holes 6 on the copper foils 2 and 3. A copper plating film 7 (about 8 μm thick) is formed. Thereby, the copper plating layer 8 on the copper foils 2 and 3, the plating through via hole 9, and the plated bottomed via hole 10 are formed. The plated through via hole 9 is a through type interlayer conductive path, and the plated bottomed via hole 10 is a bottomed type interlayer conductive path. Both of these plated via holes electrically connect the copper foil 2 on the front surface of the flexible insulating base material 1 and the copper foil 3 on the back surface.

In addition, the through-hole via 5 and the bottomed via-hole 6 differ in the liquid renewability of the treatment liquid in the above-described conductive treatment process and electrolytic copper plating process. That is, the bottomed via hole 6 is inferior in liquid renewability as compared to the through via hole 5. For this reason, the process flow is basically performed under conditions that allow the bottomed via hole 6 to be processed. As for the electrolytic copper plating process, the contact with the side wall near the bottom of the bottomed via hole 6 tends to deteriorate. Therefore, the electrolytic copper plating treatment is preferably performed using a plating bath containing a high concentration of copper sulfate.

Next, as can be seen from FIG. 1A (3), resist

layers

11 and 11 are formed on the copper plating layers 8 and 8, respectively. A dry film resist is used for forming the resist layer 11. It is preferable to use a dry film resist having a thickness (for example, 20 μm) capable of tenting both the plated through via hole 9 and the plated bottomed via hole 10. Thereby, it is possible to prevent the resist from entering the plated through via hole 9 and the plated bottomed via hole 10 and facilitate the subsequent peeling of the resist layer 11. A liquid resist or an electrodeposition resist can be used instead of the dry film resist.

Next, as can be seen from FIG. 1A (4), the resist layer 11 is etched according to a predetermined pattern by exposure and development of the resist layer 11 by a photofabrication method, and then the patterned resist layer 11 is used as a mask. The copper plating layer 8 and the copper foils 2 and 3 are etched. Thereafter, the resist layer 11 is peeled off. Thereby, inner

layer circuit patterns

12A and 12B are formed on the front surface and the back surface of the flexible insulating base material 1, respectively.

The double-sided flexible substrate 13 shown in FIG. 1A (4) is obtained through the steps so far.

Next, as can be seen from FIG. 1B (5), a coverlay 16 having an insulating film 14 (for example, 12 μm thick) such as a polyimide film and an adhesive layer 15 formed on one surface of the insulating film 14 is prepared. The adhesive layer 15 is made of an adhesive such as acrylic or epoxy. And the lamination process which affixes the coverlay 16 on both surfaces of the double-sided flexible substrate 13 using a vacuum laminator etc. is performed. As a result, the inner layer circuit patterns 12 </ b> A and 12 </ b> B and the plated through via hole 9 are filled with the adhesive layer 15.

In this lamination process, it is not necessary to completely fill the inside of the plated bottomed via hole 10 with the adhesive. That is, in the laminating process, the inside of the plated through via hole 9 is completely filled with the adhesive in which the adhesive layer 15 of the cover lay 16 is melted, and the adhesive layer 15 is melted in the plated bottomed via hole 10. It is performed under conditions that allow the generation of air voids 15a not filled with the adhesive. As described above, the thickness of the adhesive layer 15 in the present embodiment only needs to be able to completely fill the plated through via hole 9, and it is not necessary to consider the filled state inside the plated bottomed via hole 10. Therefore, the adhesive layer 15 is made as thin as possible within a range in which the plated through via hole 9 can be completely filled. In the present embodiment, the thickness of the adhesive layer 15 is 15 μm. As shown in FIG. 1B (5), an air void 15a may be generated inside the plated bottomed via hole 10. However, since all the adhesive in the plated bottomed via hole 10 is removed by laser processing in a later step, the air void 15a is not a problem.

Through the steps so far, the double-sided core substrate 17 that is the core substrate of the multilayer printed wiring board shown in FIG. 1B (5) is obtained.

Next, as shown in FIG. 1B (6), a single-sided copper-clad having, for example, a 12 μm-thick copper foil 18 (third conductive film) on one side of a flexible insulating base material 19 (for example, 25 μm-thick polyimide) The laminated board 20 is prepared. And the opening part 18a is formed in the copper foil 18 of the single-sided copper clad laminated board 20 by the photofabrication method. More specifically, a resist layer (not shown) is formed on the copper foil 18, and this resist layer is patterned by exposure and development. Then, the copper foil 18 is etched using the patterned resist layer as a mask. Thereby, the conformal mask 21 is formed. The opening 18a is for forming a via hole by removing the resin of the base material by laser processing in a later process.

Next, as can be seen from FIG. 1B (6), the single-sided copper clad

laminates

20 and 20 on which the conformal mask 21 is formed using the adhesive for build-up are interposed through the

adhesive layers

22 and 22. Then, the both sides of the double-sided core substrate 17 are laminated and bonded. The adhesive used here is preferably a low-flow type prepreg, a bonding sheet, or the like that does not flow out. In addition, after bonding the single-sided copper clad laminate 20 having the raw copper foil 18 to the double-sided core substrate 17 via the adhesive layer 22, the copper foil 18 is etched according to a predetermined pattern to form the conformal mask 21. It may be formed.

Next, as can be seen from FIG. 1C (7), laser processing is performed using the conformal mask 21 to form step via holes 23 and via

holes

24A and 24B. The step via hole 23 penetrates the flexible insulating base material 19, the adhesive layer 22, the insulating film 14, and the adhesive layer 15, and the plated bottomed via hole 10 is exposed at the bottom. In this laser processing step, all the resin inside the plated bottom via hole 10 is removed, and the air void 15a disappears. The via holes 24A and 24B penetrate the flexible insulating base material 19, the adhesive layer 22, the insulating film 14, and the adhesive layer 15, and the inner

layer circuit patterns

12A and 12B are exposed at the bottoms.

In addition, in order to form the step via hole 23, it is necessary to remove the resin inside the plated bottom via hole 10 as well. For this reason, the amount of the resin material to be removed is larger in the step via hole 23 than in the via

holes

24A and 24B. For this reason, when forming the step via hole 23, it is preferable to increase the number of laser processing shots or to increase the pulse width of the laser beam. As a laser used for this laser processing, a UV-YAG laser, a carbonic acid laser, an excimer laser, or the like can be selected.

Next, as can be seen from FIG. 1C (8), the electroplating treatment and the subsequent electrolytic plating treatment are performed on the copper foil 18 on the inner wall of the step via hole 23 and the inner walls of the via holes 24A and 24B. Form. Thereby, the copper plating layer 26 on the copper foil 18 and the plating buildup via

holes

27, 28, and 29 are formed. All of these plated via holes electrically connect the inner

layer circuit patterns

12A and 12B to the copper foil 18 and the copper plating layer 26 (the later outer layer circuit pattern 30). The plating buildup via hole 27 is formed by forming a plating layer on the inner wall of the step via hole 23. The plating buildup via hole 28 is formed by forming a plating layer on the inner wall of the via hole 24 </ b> A facing the step via hole 23. The plating buildup via hole 29 is formed by forming a plating layer on the inner wall of the via hole 24B.

The thickness of the electrolytic plating film 25 is a value necessary for ensuring connection reliability. In this embodiment, the thickness of the adhesive layer 15 is reduced as compared with the prior art, so that the thickness of the electrolytic plating film 25 can be reduced to, for example, about 15 μm to 20 μm, compared to the conventional (for example, about 25 to 30 μm). it can.

As can be seen from FIG. 1C (8), the stacked via structure in which the plated build-up via hole 27 is formed on the plated bottomed via hole 10 is completed through the steps so far.

Next, as can be seen from FIG. 2, the outer layer circuit pattern 30 is formed by etching the copper foil 18 and the electrolytic plating film 25 in accordance with a predetermined pattern using a photofabrication method. After that, if necessary, a photo solder resist layer (not shown) is formed, surface treatments such as solder plating, nickel plating, gold plating are applied to the terminals of the circuit pattern, and outer shape processing is performed by punching with a mold or the like. Do.

Through the above steps, the build-up type multilayer printed wiring board 32 having the stack via structure according to the present embodiment shown in FIG. 2 is obtained.

In the build-up type multilayer printed wiring board 32 according to the present embodiment, outer-layer single-sided copper-clad

laminates

20 and 20 are laminated on the front and back surfaces of a double-sided core substrate 17 serving as an inner layer via

adhesive layers

22 and 22. It is what. The present embodiment is not limited to this, and the single-sided copper-clad laminate of the outer layer is provided via the adhesive layer 22 only on the surface of the double-sided core substrate 17, that is, on the opening side of the plated bottomed via hole 10 of the double-sided core substrate 17. The plate 20 may be laminated. Thereby, the multilayer printed wiring board provided with the buildup layer only on one side can be obtained.

The inner

layer circuit patterns

12A and 12B are electrically connected to the outer layer circuit pattern 30 through plating buildup via

holes

27, 28 and 29.

The build-up type multilayer printed wiring board 32 obtained by the manufacturing method according to the present embodiment includes a component mounting portion 32a in which the build-up layer 31 is laminated on the double-sided core substrate 17 that is a flexible printed wiring board, The double-sided core substrate 17 has a flexible cable portion 32b on which no buildup layer is laminated. That is, the flexible cable portion 32b is configured to extend from the component mounting portion 32a. The present embodiment is not limited to this, and a multilayer printed wiring board in which the double-sided core substrate 17 does not constitute the flexible cable 32b may be manufactured.

In the present embodiment, the method for manufacturing a flexible multilayer printed wiring board has been described, but the present invention is not limited to this.

In addition to the above-described conformal laser processing method and direct laser processing method, the laser processing method includes forming an opening larger than the diameter of the upper hole of the step via hole 23 in the copper foil 18, and then There is a large window method in which a laser beam having the same beam diameter as the hole diameter is irradiated. The laser processing methods that can be selected are not limited to those used in the description of the above embodiment, and a conformal method, a direct laser method, and a large window method can be arbitrarily selected for each step. When the direct laser method is used, the thickness of the copper foil is preferably 15 μm or less as in the present embodiment.

In the present embodiment, the cover lay 16 is laminated on both sides of the double-sided flexible substrate 13 to produce the double-sided core substrate 17 and then the build-up layer is laminated on the double-sided core substrate 17. Not limited to this, a single-sided copper-clad laminate with an adhesive may be used in place of the coverlay 16 to directly provide a buildup layer on the double-sided flexible substrate 13. In this case, a multilayer printed wiring board is produced as follows. First, as described above, the double-sided flexible substrate 13 on which the plated through via hole 9, the plated bottomed via hole 10, and the inner

layer circuit patterns

12A and 12B are formed. Thereafter, single-sided conduction with an adhesive layer comprising an insulating base material, a conductive film (third conductive film) formed on the surface of the insulating base material, and an adhesive layer formed on the back surface of the insulating base material A film-clad laminate is prepared. And the lamination process which affixes the single-sided electrically conductive film tension laminated board with an adhesive bond layer on both surfaces of the double-sided flexible substrate 13 is performed. In this laminating step, the inside of the plated through via hole 9 is completely filled with the adhesive in which the adhesive layer of the single-sided conductive film-clad laminate with the adhesive layer is melted, and the inside of the plated bottomed via hole 10 is adhesive. It is carried out under conditions that allow the generation of air voids in which the layer is not filled with molten adhesive. The multilayer printed wiring board obtained in this way is subjected to laser processing to remove the adhesive inside the plated bottomed via hole 10 and extinguish the air void, thereby exposing the plated bottomed via hole 10 to the bottom, A step via hole in which the plated bottom via hole 10 is a pilot hole is formed. Thereafter, a plating buildup via hole for electrically connecting the third conductive film and the inner layer circuit pattern 12A is formed by plating the third conductive film and the inner wall of the step via hole. Next, the third conductive film that has been plated is etched according to a predetermined pattern to form an outer layer circuit pattern, thereby obtaining a build-up type multilayer printed wiring board.

As described above, the double-sided core substrate 17 includes the plated through via hole 9 and the plated bottomed via hole 10 for electrically connecting the inner layer circuit pattern 12A and the inner layer circuit pattern 12B. The stacked via structure includes a plated bottomed via hole 10 and a plated buildup via hole 27 disposed on the plated bottomed via hole 10. The plated build-up via hole 27 is formed by forming an electrolytic plating film on the inner wall of the step via hole 23 in which the plated bottomed via hole 10 formed in the double-sided core substrate 17 is a small diameter hole. Further, the plated through via hole 10 is configured to only perform interlayer conduction between the front surface and the back surface of the double-sided core substrate 17 and does not perform interlayer conduction between the outer layer circuit pattern 30 and the inner

layer circuit patterns

12A and 12B.

Due to the above characteristics, the following effects can be obtained according to the present embodiment.

When laminating the coverlay 16, it is not necessary to completely fill the inside of the plated bottomed via hole 10 with an adhesive. That is, the inside of the plated bottomed via hole 10 is in an incompletely filled state with the adhesive, and the air void 15a may exist. Therefore, the thickness of the adhesive layer 15 of the cover lay 16 can be made as small as possible within a range in which the adhesive can be completely filled into the plated through via hole 9. As a result, the step via hole 23 can be made as shallow as possible (for example, about 10 μm), and the ease of electrodeposition when electrolytic plating is performed on the inner wall of the step via hole 23 and the via

holes

24A and 24B is improved. Further, the plated build-up via

holes

27, 28, and 29 have an advantageous structure such as being hardly affected by the thermal expansion of the constituent members of the printed wiring board. Among the constituent members, particularly the adhesive constituting the adhesive layer 15 has a large coefficient of thermal expansion, so that the effect obtained by making the adhesive layer 15 thinner is great. For this reason, it is possible to reduce the thickness of the electrolytic plating film 25 necessary for improving the yield and ensuring the connection reliability. As a result, according to the present embodiment, a fine outer layer circuit pattern 30 can be formed.

Furthermore, according to the present embodiment, when the plating buildup via hole 27 is formed, the electrolytic plating film 26 is also formed on the plated bottomed via hole 10. This reinforces the plated bottomed via hole 10 where thermal stress is more likely to concentrate than the plated through via hole 9 due to the asymmetric shape, thereby improving the connection reliability.

Furthermore, according to the present embodiment, since the plated bottomed via hole 10 is reinforced, the plating thickness of the plated bottomed via hole 10 (thickness of the electrolytic copper plating film 7) can be set to the connection reliability of the plated through via hole 9. It can be made as thin as possible. As a result, the time required for the plating process is shortened, and the cost can be reduced. In addition, since the copper plating layer 8 becomes thinner in accordance with the plating thickness of the plated bottomed via hole 10, the inner layer circuit pattern 12 of the double-sided core substrate 17 can be miniaturized.

In the description of the embodiment, the wiring pattern and the plating film are made of copper. However, the present invention is not limited to this, and other metals such as aluminum and silver may be used.

Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the above-described embodiments. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 1,19,101 Flexible

insulation base material

2,3,18,102,103 Copper foil 4,104 Double-sided copper clad laminated board 5 Through-via hole 6,105 Bottomed via hole 7 Electrolytic

copper plating film

8,26 Copper plating layer 9 Plating via

hole

10, 106 Plating bottomed via hole 11 Resist

layer

12A, 12B Inner layer circuit pattern 13 Double-sided flexible substrate 14, 107 Insulating

film

15, 22, 108, 112 Adhesive layer 15a Air void 16, 109

Coverlay

17, 110 Double-sided core substrate 18 Copper foil 18a Opening 20, 111 Single-sided copper clad laminate 21

Conformal mask

23, 113A Step via

hole

24A, 24B, 113B, 113C Via hole 25

Electrolytic plating film

27, 28, 29, 114A, 114B, 114C Plating build-up via hole 30 115 outer circuit pattern 31 buildup holes 32,116 buildup type multilayer printed

wiring board

32a, 116a

component mounting portion

32 b, 116 b flexible cable portion

Claims

A plated through via hole and a plating for electrically connecting the first conductive film and the second conductive film to a double-sided conductive film-clad laminate having a first conductive film and a second conductive film on the front and back surfaces, respectively. Forming a bottomed via hole,
Etching the first conductive film and the second conductive film according to a predetermined pattern to produce a double-sided flexible substrate having an inner circuit pattern,
Preparing a coverlay having an insulating film and an adhesive layer formed on one side of the insulating film;
Conditions that allow the inside of the plated through via hole to be completely filled with an adhesive in which the adhesive layer of the coverlay is melted, and allow the generation of air voids not filled with the adhesive into the plated bottomed via hole Underneath, performing a laminating step of pasting the coverlay on both sides of the double-sided flexible substrate, thereby producing a double-sided core substrate,
A buildup layer having a third conductive film formed on one side is laminated and bonded to at least the opening side of the plated bottomed via hole of the double-sided core substrate,
By laser processing, the adhesive inside the plated bottomed via hole is removed and the air voids disappear, thereby exposing the plated bottomed via hole to the bottom and forming a step via hole where the plated bottomed via hole serves as a pilot hole. Forming,
A plating buildup via hole that electrically connects the third conductive film and the inner layer circuit pattern is formed by plating the third conductive film and the inner wall of the step via hole.
A method of manufacturing a multilayer printed wiring board, wherein an outer layer circuit pattern is formed by etching the third conductive film that has been plated in accordance with a predetermined pattern.
A plated through via hole and a plating for electrically connecting the first conductive film and the second conductive film to a double-sided conductive film-clad laminate having a first conductive film and a second conductive film on the front and back surfaces, respectively. Forming a bottomed via hole,
Etching the first conductive film and the second conductive film according to a predetermined pattern to produce a double-sided flexible substrate having an inner circuit pattern,
A single-sided conductive film-clad laminate with an adhesive layer comprising an insulating base material, a third conductive film formed on the surface of the insulating base material, and an adhesive layer formed on the back surface of the insulating base material is prepared. And
Under the condition that the inside of the plated through via hole is completely filled with the adhesive in which the adhesive layer is melted, and the inside of the plated bottomed via hole is allowed to generate air voids that are not filled with the adhesive. Performing a laminating step of attaching a single-sided conductive film-clad laminate with an adhesive layer to both sides of the double-sided flexible substrate;
By laser processing, the adhesive inside the plated bottomed via hole is removed and the air voids disappear, thereby exposing the plated bottomed via hole to the bottom and forming a step via hole where the plated bottomed via hole serves as a pilot hole. Forming,
A plating buildup via hole that electrically connects the third conductive film and the inner layer circuit pattern is formed by plating the third conductive film and the inner wall of the step via hole.
A method of manufacturing a multilayer printed wiring board, wherein an outer layer circuit pattern is formed by etching the third conductive film that has been plated in accordance with a predetermined pattern.
The laser processing is a conformal laser processing method that uses a conformal mask formed by etching the third conductive film, a direct laser processing method that directly irradiates the third conductive film with laser light, or An opening larger than the diameter of the upper hole of the step via hole is formed in the third conductive film, and this is performed by a large window method in which a laser beam having the same beam diameter as the diameter of the upper hole is irradiated. Item 3. A method for producing a multilayer printed wiring board according to Item 1 or 2.