201146123 六、發明說明： 【發明所屬之技術領域】 本發明係關於多層印刷配線板之製造方法，更詳而言 之，係關於積層（b u i 1 d - u p )型之多層印刷配線板之製造 方法。 【先前技術】 近年來，如行動電話等攜帶式資訊終端所代表，電子 機器的小型化及高功能化不斷在進展。因此，對於電子機 器所使用的印刷配線板的高密度化的要求不斷提高。 因此，爲了在印刷配線板高密度安裝電子零件等，積 層型的多層可撓性印刷配線板不斷被硏究開發（參照例如 專利文獻1 )。該積層型多層可撓性印刷配線板係以雙面 可撓性印刷配線板或多層可撓性印刷配線板爲核心基板， 在該核心基板的雙面或單面形成1〜2層程度的增層（ build-up layer)者。在該積層型多層可撓性印刷配線板， 爲了將增層與內層的核心基板作電性連接，設置在有底型 的通孔（導通用孔）的內壁施行鍍敷處理而得到層間導通 的鏟敷通孔。 但是，隨著該有底型的通孔變深，會產生以下問題。 首先’由於印刷配線板的各構成構件作熱膨脹，鍍敷通孔 容易被破壞。此外，爲了獲得層間導通，當在有底型的通 孔的內壁形成鍍敷皮膜時，鍍敷液變得容易滯留在通孔的 底部’因此無法獲得所希望的鍍敷厚度。基於如上所示之 201146123 理由，有底型通孔愈深’愈不易確保通孔配線的電氣可靠 性。 以該問題的對策而言’考慮在有底型的通孔的內壁形 成充分厚的鍍敷皮膜。但是’若在形成在有底型通孔內壁 的鍍敷皮膜的厚度增加’無法避免隨此形成在增層上的導 體層的厚度亦變大。外層的電路圖案係藉由將增層上的導 體層按照所希望的圖案進行濕式蝕刻而形成。因此’隨著 導體層的厚度增加，愈不易將增層上的導體層微細加工。 結果，以外層的電路圖案而言’無法形成微細的圖案，要 在增層上高密度安裝電子零件變得困難。 如上所述，在習知的積層型多層可撓性印刷配線板， 會有難以滿足高密度安裝要求的問題。 但是，積層型的多層可撓性印刷配線板之中，由高密 度化及設計自由度的提升的觀點來看，尤其圖求一種具有 所謂的堆疊通孔（stack via )構造的積層型多層可撓性印 刷配線板。在此，堆疊通孔構造係指在由核心基板的鍍敷 通孔所構成的層間連接部之上，重疊配置由增層的鍍敷通 孔所構成的層間連接部的構造。 廉價且安定製造具有可高密度安裝的堆疊通孔構造的 多層印刷配線板的方法被強烈期望。 以往已揭示一種手法是藉由雷射加工而總括形成所謂 的階梯通孔構造的通孔（階梯通孔（step via))(參照 專利文獻2、專利文獻3及專利文獻4 )。藉由該等文獻所 揭示的手法，可有效率地形成階梯通孔構造。但是，在該 -6- 201146123 手法中，用以利用鑛敷皮膜來被覆階梯通孔的內壁的電解 銅鍍敷通常是一次彙整進行。因此，會有形成在階梯通孔 之下穴（小徑側）的側壁的鍍敷皮膜變薄的傾向。因此， 會有不易充分確保層間連接可靠性的情形。 接著，使用第3圖，詳加說明藉由習知技術所爲之具 有堆疊通孔構造的積層型多層印刷配線板之製造方法。第 3圖係用以說明具有堆疊通孔構造之積層型多層印刷配線 板之製造方法的工程剖面圖。 首先，準備聚醯亞胺等可撓性絕緣基底材1 〇 1 (例如 25 μιη厚）、及在其雙面具有銅箔102及銅箔103 (均爲例如 8μιτι厚）的雙面覆銅層積板104。 接著，由第3圖（1)可知，對該雙面覆銅層積板1〇4 ，藉由雷射加工法形成屬於有底型通孔的有底通孔1〇5。 在該有底通孔105的底部露出銅箔103。之後，藉由對銅箔 102、103及有底通孔105施行導電化處理及繼之的電解鍍 敷處理，在銅箔102、103上、及有底通孔105的內壁形成 電解鍍敷皮膜。該電解鍍敷皮膜的厚度係被形成爲用以確 保通孔配線之連接可靠性的所需値（例如1 5 μιη左右）。經 由至此爲止的工程，形成有將可撓性絕緣基底材1〇1的銅 箔102與銅箔103作電性連接之屬於有底型層間導通部的鍍 敷有底通孔106。 接著，由第3圖（1)可知，藉由感光蝕刻加工法（ photofabrication)，將可撓性絕緣基底材101的銅范102與 銅箔1 03按照預定的圖案進行蝕刻，藉此形成電路圖案（ 201146123 內層電路圖案）。更詳而言之，藉由由阻劑層的形成 光、顯影、銅箔的蝕刻及阻劑層的剝離等所構成的一 工程，在可撓性絕緣基底材101的雙面形成電路圖案。 接著，由第3圖（1)可知，準備在聚醯亞胺薄膜 緣薄膜107 (例如12 μηι厚）上具有接著劑層108的覆 1 09。接著劑層1 08係由例如丙烯酸、環氧等接著劑所 。接著，使用真空疊合機等，進行在形成有電路圖案 撓性絕緣基底材101上黏貼覆蓋膜109的層疊工程。該 材層108的厚度係被形成爲可利用接著劑來完全塡充 有底通孔106的內部的厚度（例如25μπι)。經由至此 的工程，取得第3圖（1 )所示之雙面核心基板1 1 〇。 接著，由第3圖（2 )可知，準備在可撓性絕緣基 (例如2 5 μιη厚的聚醯亞胺）的單面具有銅箔（例如 12 μιη)的單面覆銅層積板111。藉由前述的感光蝕刻 法，在該單面覆銅層積板111的銅箔的預定部分形成 部。將具有該開口部的銅箔形成爲雷射遮光用的共型 (Conformal Mask )(亦稱爲金屬遮罩）。形成在銅 開口係用以藉由雷射加工來去除在該開口的底面所露 可撓性絕緣基底材等的樹脂而形成通孔者。 接著，由第3圖（2 )可知，使用用以在雙面核心 110積層的接著材，將具有共型遮罩的單面覆銅層積| 、111透過接著劑層112、112而分別層積接著在雙面 基板1 10的表面及背面。 接著，由第3圖（2)可知，使用單面覆銅層積| 、曝 連串 等絕 蓋膜 構成 的可 接著 鍍敷 爲止 底材 厚度 加工 開口 遮罩 箔的 出的 基板 ί 1 1 1 核心 ΐ 1 1 1 -8 - 201146123 的共型遮罩來進行雷射加工，藉此形成階梯通孔1 1 3 A及通 孑 L 1 1 3 B、1 1 3 C。 接著，由第3圖（3)可知，對單面覆銅層積板111的 銅箔上、階梯通孔113A的內壁、及通孔113B、113C的內 壁施行導電化處理及繼之的電解鍍敷處理，藉此形成電解 鍍敷皮膜。該電解鍍敷皮膜的厚度係形成爲例如25〜3 Ομηι 程度，俾以確保層間連接的可靠性。藉此，形成用以獲得 核心基板與增層的層間導通的鑛敷積層通孔11 4A、1 1 4Β、 114C。鑛敷積層通孔114A係對階梯通孔U3A的內壁施行 鍍敷處理者，鍍敷積層通孔1 14B係對與階梯通孔1 13A相對 向的通孔1 13B的內壁施行鍍敷處理者，鍍敷積層通孔1 14C 係對通孔U3C的內壁施行鍍敷處理者。 接著，由第3圖（3 )可知，使用感光蝕刻加工法，將 單面覆銅層積板111、111的銅箔按照預定的圖案進行蝕刻 ’藉此形成外層電路圖案1 1 5、1 1 5。之後，視需要形成光 阻焊層（未圖示），在電路圖案的端子施行焊料鍍敷、錬 鎪敷、金鍍敷等表面處理，藉由利用模具所爲之鑽孔等來 進行外形加工。 經由以上工程，獲得具有堆疊通孔構造的積層型多層 印刷配線板1 1 6。由第3圖（3 )可知，鍍敷積層通孔1 1 4 A 係形成在內層的雙面核心基板1 10的鍍敷有底通孔106的正 上方，鍍敷有底通孔106與鍍敷積層通孔114A係形成堆疊 通孔構造。在積層型多層印刷配線板1 1 6中，雙面核心基 板1 10的表面與背面的層間連接係藉由鍍敷有底通孔106來 201146123 進行^ 其中’由第3圖（3 )可知，積層型多層印刷配線板 11 6係具有：在雙面核心基板110層積有增層的零件安裝部 H 6a、及由該零件安裝部〗丨6b延伸的可撓性線材部〗〗6b。 該可撓性線材部116b係未設有增層的雙面核心基板no的 一部分。 經由上述工程，鍍敷有底通孔1 06內部係必須利用接 著材來完全塡充。但是，若與在貫穿雙面覆銅層積板104 的通孔的內壁施行鍍敷處理所形成的鍍敷貫穿通孔相比， 鍍敷有底通孔1 06係不易塡充接著劑。此係基於鍍敷貫穿 通孔係可由表面與背面的2方向塡充，相對於此，有底鍍 敷通孔僅可由1方向塡充之故。因此，與以鍍敷貫穿通孔 來進行雙面核心基板1 1 0的層間連接的情形相比，接著材 層108的厚度會變得較厚的情形並無法避免。因此，積層 通孔1 1 3會變深。如此一來，如前所述，用以確保層間連 接可靠性的鍍敷厚度會變大。例如，如上所示在形成鍍敷 積層通孔114A、114B、114C時，必須進行用以形成25〜 3 Ομηι程度的鍍敷皮膜的電解鍍敷。假設將在單面覆銅層積 板111的銅箔（〗2μηι厚）上進行該程度的電解鍍敷，單面 覆銅層積板111上的導體層（銅箔+電解鍍敷皮膜）的厚 度總計爲37〜42μηι。導體層的圖案化係藉由濕式蝕刻來進 行，因此不易良率佳地形成電路間距爲1 〇〇μηι左右的微細 電路圖案。 如以上說明所示，以往會有無法製造滿足高密度安裝 -10- 201146123 要求的積層型多層印刷配線板的問題。其中，當然該問題 即使在不具有可撓性線材1 1 6b的多層印刷配線板亦爲相同 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2004-200260號公報 [專利文獻2]日本特開2008-235801號公報 [專利文獻3]曰本特開2008-288434號公報 [專利文獻4]日本特開2009-026912號公報 【發明內容】 (發明所欲解決之課題） 本發明係用以解決由於不易形成微細的外層電路圖案 而無法獲得可高密度安裝的多層印刷配線板的上述問題者 ’目的在提供具有可高密度安裝的堆疊通孔構造的積層型 多層印刷配線板之製造方法。 (解決課題之手段） 藉由本發明之一態樣，提供一種多層印刷配線板之製 造方法’其特徵爲：在表面及背面分別具有第1導電膜及 第2導電膜的雙面覆導電膜層積板，形成將前述第丨導電膜 與前述第2導電膜作電性連接的鍍敷貫穿通孔及鍍敷有底 通孔， -11 - 201146123 將前述第1導電膜及前述第2導電膜按照預定的圖案進 行蝕刻，藉此製作具有內層電路圖案的雙面可撓性基板， 準備具有：絕緣薄膜、及形成在前述絕緣薄膜之單面 的接著劑層的覆蓋膜， 在藉由前述覆蓋膜的前述接著劑層熔融後的接著劑， 使前述鍍敷貫穿通孔的內部被完全塡充，而且在前述鍍敷 有底通孔的內部容許發生未藉由前述接著劑予以塡充的空 氣空隙的條件下，進行將前述覆蓋膜黏貼在前述雙面可撓 性基板之雙面的層疊工程，藉此製作雙面核心基板， 在前述雙面核心基板的至少前述鍍敷有底通孔的開口 面側，層積接著具有形成在單面的第3導電膜的增層； 藉由雷射加工，去除前述鍍敷有底通孔內部的前述接 著劑而使前述空氣空隙消滅，藉此，在底部露出前述鍍敷 有底通孔，形成前述鍍敷有底通孔成爲下穴的階梯通孔， 藉由對前述第3導電膜及前述階梯通孔的內壁施行鍍 敷處理，形成將前述第3導電膜與前述內層電路圖案作電 性連接的鍍敷積層通孔， 將被施行鍍敷處理的前述第3導電膜按照預定的圖案 進行蝕刻，藉此形成外層電路圖案。 (發明之效果） 藉由該等特徵，本發明係達成如下所示之效果。 在本發明之一實施形態之具有堆疊通孔構造的積層型 多層印刷配線板中，堆疊通孔構造係由：將雙面可撓性基 -12- 201146123 板的表面與背面作電性連接的鍍敷有底通孔；及配置在該 鍍敷有底通孔之上的鍍敷積層通孔所構成。該鍍敷積層通 孔係將外層電路圖案與內層電路圖案作電性連接者，在將 形成在雙面可撓性基板的有底通孔形成爲小徑孔洞的階梯 通孔的內壁形成有鍍敷皮膜者。藉此，形成由鍍敷有底通 孔、及形成在其上的鍍敷積層通孔所構成的階梯通孔構造 〇 藉由如上所示之特徵，藉由本發明之一實施形態，在 將覆蓋膜層疊時，並不需要在形成在雙面可撓性基板的鍍 敷有底通孔的內部完全塡充接著材。其係基於在形成前述 階梯通孔時，鍍敷有底通孔內的接著劑會被去除之故。因 此，在可在雙面可撓性基板的貫穿通孔內塡充接著劑的範 圍內，可儘可能減小接著材層的厚度。 結果，與習知技術相比，可使階梯通孔變得較淺。藉 此，爲了形成鍍敷積層通孔而進行電解鍍敷處理時，電沈 積容易性會提升，並且因構成構件的熱膨脹所造成之對鍍 敷積層通孔的影響受到減輕。 因此，藉由本發明，可使良率提升，可儘可能減低用 以確保通孔配線的連接可靠性所需之鍍敷厚。因此，藉由 本發明，可使形成在增層的外層電路圖案更爲微細。 此外，藉由本發明，在形成鍍敷積層通孔時，在雙面 可撓性基板的鍍敷有底通孔之上亦形成有電解鍍敷皮膜。 藉此，因非對稱的形狀而起，與鍍敷貫穿通孔相比，熱應 力較易於集中的鍍敷有底通孔受到補強，可使連接可靠性 -13- 201146123 提升。 此外，如上所述鍍敷有底通孔受到補強，因此可使該 鍍敷有底通孔的鍍敷厚薄至可確保鍍敷貫穿通孔之連接可 靠性的程度。結果，可縮短鍍敷工程所需時間，可減低成 本。此外，可將形成在雙面可撓性基板的內層電路圖案微 細化。 如上所述’藉由本發明，提供一種廉價且安定製造具 有可高密度安裝之堆疊通孔構造的積層型多層印刷配線板 的方法。 【實施方式】 以下，一面參照圖示，一面針對具有本發明之實施形 態之堆疊通孔構造的積層型多層印刷配線板之製造方法加 以說明。 其中，對於具有同等功能的構成要素標註相同的元件 符號，且省略詳加說明。此外，圖示爲模式表示者，以實 施形態之特徵部分爲中心來顯示者，厚度與平面尺寸的關 係、各層的厚度比率等係與現實者有所不同。 首先，使用第1A圖至第1C圖及第2圖，針對本發明之 實施形態之具有堆®通孔構造的積層型多層印刷配線板3 2 之製造方法加以說明。 第1 A圖至第1 C圖係用以說明該積層型多層印刷配線板 32之製造方法的工程剖面圖。第2圖係本實施形態之積層 型多層印刷配線板32的剖面圖。 -14 - 201146123 首先，由第1A圖（1)可知’準備在可撓性絕緣基底 材1 (例如25 μπι厚的聚醯亞胺）的雙面分別具有銅箔2及銅 箔3 (第1導電膜及第2導電膜）的雙面覆銅層積板4。銅箔 2及銅箔3的厚度例如均爲5μιη。 接著，對該雙面覆銅層積板4 ’使用雷射加工法或樹 脂蝕刻法等，形成貫穿雙面覆銅層積板4的貫穿通孔5、及 有底通孔6。該有底通孔6由第1Α圖（1)可知，係在底面 露出銅箔3的有底型的通孔。其中，該貫穿通孔5及有底通 孔6的加工直徑均爲例如直徑70μχη。 在本工程中使用雷射加工法時，係可選擇以下2個方 法。第1方法係被稱爲共型雷射加工法的方法。在該方法 中，在銅箔2、3設置與通孔直徑相同直徑的開口部，而形 成共型遮罩。之後，對共型遮罩照射雷射光而去除在開口 部露出的絕緣樹脂。第2方法係被稱爲直接雷射加工法的 方法。在該方法中，未形成共型遮罩，而對銅箔上直接照 射雷射光，來去除銅箔及其下方的絕緣樹脂。在本實施形 態中，並非爲必須進行藉由感光蝕刻加工法所爲之銅箔蝕 刻工程的共型雷射加工法，而是考慮到生產性，而選擇一 種藉由二氧化碳雷射所爲之直接雷射加工法。 在進行該直接雷射加工法之前，係對雙面覆銅層積板 4的銅箔2、3施行表面處理。亦即，進行將被照射雷射光 的銅箔面形成爲低粗度的粗化處理。藉此，當使用二氧化 碳雷射（波長：約9.8 μιη )進行雷射加工時，可使銅箔2、 3的雷射光的吸收穩定提升。在本實施形態中，在該粗化 -15- 201146123 處理使用日本MacDermid公司（股）的Multi-bond 150。藉 此，可確保與在後工程中所形成的電解銅鍍敷皮膜7的密 接性，並且可使銅箔的表面中的二氧化碳雷射光的吸收提 升。確認出實際上在表面處理的前後，二氧化碳雷射光的 吸收率由約20%提升至約30%。 其中，在本實施形態中，係將貫穿通孔5與有底通孔6 同時加工。因此，對銅箱2的表面，係藉由進行上述粗化 處理而容易進行銅箔2的加工。與此同時以在形成有底通 孔6時不會貫穿銅箔3的方式，進行將銅箔面形成爲低粗度 的處理來作爲銅箔3的背面處理，以使雷射光的吸收降低 爲佳。但是，在欲效率佳地形成貫穿通孔5時，以進行粗 化處理來作爲銅箔3的背面處理爲佳。 雙面覆銅層積板4的銅箔2' 3愈薄，在雷射加工時， 愈容易發生貫穿銅箔2、3。因此，若如本實施形態所示銅 箔的厚度較薄，爲ΙΟμηι以下時，由於容易形成有底通孔6 ’因此以使用幾乎未施行粗化處理來作爲背面處理的低粗 度的銅箱3爲佳。 在此，詳加說明雷射加工方式。首先，敘述將有底通 孔6進行加工的情形。在將銅箔2進行加工時，提高平均1 發射（shot )的雷射光能量（設爲功率ρ )。接著，較佳 爲以1發射結束銅箔2的加工。之後，在將可撓性絕緣基底 材1的樹脂加工至露出銅箔3爲止時，使平均1發射的雷射 光能量降低至（1/2) P〜（1/3) P，而以2〜3發射完成 樹脂加工。接著，針對貫穿通孔5的情形加以敘述。此時 -16- 201146123 ，使用將平均1發射的雷射光能量設爲前述功率P的雷射光 ，將雙面的銅箔及樹脂進行加工。連續照射3〜4發射’完 成貫穿通孔5的加工。 在使用更薄的銅箔時，爲了容易形成有底通孔6，先 將成爲有底通孔6之底部的銅箔3的背面（與基底材相接的 面）形成爲低粗度。伴隨此，在銅箔2的背面（與基底材 相接的面）進行粗化處理。接著，貫穿通孔5係由銅箔3的 表面加工形成。藉由該方法，可一面輕易形成有底通孔6 ，一面效率佳地形成貫穿通孔。此外，以其他方法而言， 亦可由銅箱2的表面及銅范3的表面的2方向進行雷射加工 ，而形成貫穿通孔5。此時，在銅箔2、3的表面係進行粗 化處理，因此具有從任何方向均容易加工，並且不需要考 慮銅箔的背面處理狀態（粗度的高低）的優點。 接著，爲了去除在形成貫穿通孔5及有底通孔6時所產 生的污跡（樹脂殘渣），進行電漿處理及濕式蝕刻（去污 跡處理）。對貫穿通孔5與有底通孔6的該電漿處理的最適 條件係大致相同。另一方面，關於使用過硫酸鈉等的濕式 蝕刻，在兩者之間，最適條件不同。亦即，濕式蝕刻對貫 穿通孔5而言幾乎不需要。不如進行蝕刻，藉此銅箔2、3 會後退，會有對之後的導電化處理造成不良影響的情形。 另一方面’對有底通孔6’爲了去除因背面處理所造成之 銅泊3的背面的錬、絡等異種金屬，必須進行1〜2μηι的倉虫 刻。考慮到對貫穿通孔5的影響，以儘量以較少的蝕刻量 來完成處理爲佳。在本實施形態中，係進行1 μηι的蝕刻。 -17- 201146123 接著，由第1A圖（2)可知，對銅箔2、3上、貫穿通 孔5的內壁及有底通孔6的內壁施行導電化處理及繼之的電 解銅鍍敷處理，藉此形成電解銅鍍敷皮膜7 (約8μπι厚）。 藉此’形成銅箔2、3上的銅鍍敷層8、鍍敷貫穿通孔9、及 鍍敷有底通孔10。該鍍敷貫穿通孔9係貫穿型的層間導電 路，鍍敷有底通孔10係有底型的層間導電路。該等鍍敷通 孔係均將可撓性絕緣基底材1的表面的銅箔2與背面的銅箔 3作電性連接。 其中，上述導電化處理工程及電解銅鍍敷工程中的處 理液的液體更新性，在貫穿通孔5與有底通孔6並不相同。 亦即，與貫穿通孔5相比，有底通孔6的液體更新性較差。 因此，基本上係進行以可處理有底通孔6的條件下的工程 流動。關於電解銅鍍敷工程，對有底通孔6的底部附近的 側壁到處附著容易變差。因此，電解銅鍍敷處理係以使用 包含高濃度硫酸銅的鍍敷浴來進行爲佳。 接著，由第1Α圖（3)可知，在銅鍍敷層8、8之上形 成阻劑層1 1、1 1。在形成該阻劑層1 1時係使用乾式薄膜阻 劑。該乾式薄膜阻劑係以使用可將鍍敷貫穿通孔9及鍍敷 有底通孔10之二者進行蓋孔（tenting)的厚度（例如20μιη )者爲佳。藉此，防止阻劑進入至鍍敷貫穿通孔9及鍍敷 有底通孔1 〇內，可輕易進行之後進行的阻劑層1 1的剝離。 其中，亦可使用液狀阻劑或電沈積阻劑來取代乾式薄膜阻 劑。 接著，由第1Α圖（4)可知，藉由感光蝕刻加工法， -18- 201146123 藉由阻劑層11的曝光、顯影，將阻劑層11按照預定的圖案 進行蝕刻，之後，將被圖案化的阻劑層11形成爲遮罩’將 銅鍍敷層8及銅箔2、3進行蝕刻。之後，將阻劑層1 1剝離 。藉此，在可撓性絕緣基底材1的表面及背面分別形成內 層電路圖案12A及12B。 藉由至此爲止的工程，獲得第1A圖（4)所示之雙面 可撓性基板1 3。 接著，由第1B圖（5)可知，準備具有：聚醯亞胺薄 膜等絕緣薄膜14 (例如12μηι厚）、及形成在絕緣薄膜14之 單面的接著劑層1 5的覆蓋膜1 6。接著劑層1 5係由例如丙烯 酸、環氧等接著劑所構成。接著，使用真空疊合機等，進 行在雙面可撓性基板13的雙面黏貼覆蓋膜16的層疊工程。 藉此’內層電路圖案12Α、12Β及鍍敷貫穿通孔9係藉由接 著劑層15予以塡充。 在本層疊工程中’並不需要利用接著劑而將鍍敷有底 通孔10的內部完全塡充。亦即，層疊工程係在藉由覆蓋膜 16的接著劑層15熔融後的接著劑而使鍍敷貫穿通孔9的內 部被完全塡充’而且在鍍敷有底通孔10的內部容許發生未 藉由接著劑層1 5熔融後的接著劑予以塡充的空氣空隙1 5 a 的條件下來進行。如上所示’本實施形態中的接著材層i 5 的厚度若可完全塡充鍍敷貫穿通孔9即可，並不需要考慮 鍍敷有底通孔1 0內部的塡充狀態。因此，接著劑層〗5係在 可完全塡充鍍敷貫穿通孔9的範圍內儘可能變薄。在本實 施形態中’接著劑層1 5的厚度係形成爲！ 5μηι。如第1 b圖 201146123 (5)所示，會有在鍍敷有底通孔10內部發生空氣空隙15a 的情形。但是，在後工程中藉由雷射加工，鍍敷有底通孔 10內的接著劑會全部去除，因此該空氣空隙15a並不會成 爲問題。 以至此爲止的工程，獲得第1B圖（5)所示之成爲多 層印刷配線板之核心基板的雙面核心基板1 7。 接著，如第1 B圖（6 )所示，準備在可撓性絕緣基底 材19 (例如25μπι厚的聚醯亞胺）的單面具有例如12μηι厚 的銅箔18 (第3導電膜）的單面覆銅層積板20。接著，藉 由感光蝕刻加工法，在單面覆銅層積板20的銅箔1 8形成開 口部18a。更詳而言之，在銅箔18之上形成阻劑層（未圖 示），藉由曝光及顯影將該阻劑層進行圖案化。接著，將 被圖案化的阻劑層形成爲遮罩，將銅箔1 8進行蝕刻。藉此 ，形成共型遮罩2 1 »該開口部1 8 a係用以在後工程中藉由 雷射加工來去除基底材的樹脂而形成通孔者。 接著，由第1B圖（6)可知，使用用以積層的接著劑 ，將形成有共型遮罩21的單面覆銅層積板20、20，透過接 著劑層22、22而層積接著在雙面核心基板17的雙面。以在 此使用的接著材而言，以低流量類型（Low Flow type)的 預浸體或接合片等流出較少者爲佳。其中，亦可在將具有 未加工的銅箔18的單面覆銅層積板20透過接著材層22而接 著在雙面核心基板1 7後，將銅箔1 8按照預定的圖案進行蝕 刻，來形成共型遮罩2 1。 接著，由第1C圖（7)可知，使用共型遮罩21來進行 -20- 201146123 雷射加工，形成階梯通孔23及通孔24A、24B。該階梯通孔 23係貫穿可撓性絕緣基底材19、接著劑層22、絕緣薄膜14 及接著劑層15，在底部露出鍍敷有底通孔10。在該雷射加 工工程中，鍍敷有底通孔10內部的樹脂被全部去除，空氣 空隙15a即會消滅。通孔24A、24B係貫穿可撓性絕緣基底 材19、接著劑層；22、絕緣薄膜I4及接著劑層I5，在其底部 露出內層電路圖案12A、12B。 其中，爲了形成階梯通孔23，必須連位於鍍敷有底通 孔1 〇內部的樹脂亦去除。因此，應去除的樹脂材料的量係 以階梯通孔23比通孔24A、24B還多。因此，在形成階梯通 孔23時’係以增加雷射加工的發射數、或加長雷射光的脈 衝寬幅爲佳。以使用在該雷射加工的雷射而言，可選擇 UV-YAG雷射、碳酸雷射、準分子雷射等。 接著，由第1C圖（8)可知，對銅箔18上、階梯通孔 23的內壁及通孔24A、24B的內壁施行導電化處理及繼之的 電解鍍敷處理，藉此形成電解鍍敷皮膜25。藉此，形成銅 箔18上的銅鍍敷層26、及鍍敷積層通孔27、28、29。該等 鍍敷通孔係均將內層電路圖案12A、12B、與銅箔18及銅鍍 敷層26 (之後的外層電路圖案30)作電性連接者。鍍敷積 層通孔27係在階梯通孔23的內壁形成有鑛敷層者。鍍敷積 層通孔28係在與階梯通孔23相對向的通孔24A的內壁形成 有鍍敷層者。鍍敷積層通孔29係在通孔24B的內壁形成有 鍍敷層者。 該電解鑛敷皮膜25的厚度係形成爲用以確保連接可靠 -21 - 201146123 性所需的値。在本實施形態中，相較於習知技術，使接著 劑層15的厚度更爲減低，藉此連電解鍍敷皮膜25的厚度亦 比習知技術（例如25〜30μηι程度），可減薄至例如15μηι 〜2 0 μ m程度。 由第1C圖（8)可知，藉由至此爲止的工程，完成在 鍍敷有底通孔10上形成有鍍敷積層通孔27的堆疊通孔構造 〇 接著，由第2圖可知，使用感光蝕刻加工法，將銅箔 1 8及電解鍍敷皮膜25按照預定的圖案進行蝕刻，藉此形成 外層電路圖案3 0。之後，視需要形成光阻焊層（未圖示） ，對電路圖案的端子施行焊料鍍敷、鎳鍍敷、金鍍敷等表 面處理，藉由利用模具所進行的鑽孔等來進行外形加工。 經由以上工程，可得第2圖所示之本實施形態之具有 堆疊通孔構造的積層型多層印刷配線板3 2。 本實施形態之積層型多層印刷配線板32係在成爲內層 的雙面核心基板17的表面及背面，透過接著劑層22、22而 層積外層的單面覆銅層積板20、20者。本實施形態並非侷 限於此，亦可僅在雙面核心基板1 7的表面’亦即雙面核心 基板17的鍍敷有底通孔1〇的開口面側，透過接著劑層22來 層積外層的單面覆銅層積板20。藉此’可得僅在單面具備 有增層的多層印刷配線板。 內層電路圖案12A、12B係藉由鍍敷積層通孔27、28、 29而與外層電路圖案30作電性連接。 其中，藉由本實施形態之製造方法所得之積層型多層 -22- 201146123 印刷配線板32係具有：在屬於可撓性印刷配線板的雙面核 心基板17層積有增層31的零件安裝部32a ;及在雙面核心 基板17未層積有增層的可撓性線材部32b。亦即，可撓性 線材部32b係由零件安裝部32a延伸的構成。本實施形態並 非侷限於此’亦可製造雙面核心基板17未構成可撓性線材 3 2b的多層印刷配線板。 此外’在本實施形態中，係針對可撓性多層印刷配線 板之製造方法加以說明，但是本發明並非侷限於此。 此外’以雷射加工法而言，除了前述的共型雷射加工 法或直接雷射加工法以外，亦有：在銅箔18形成比階梯通 孔23的上穴直徑爲更大的開口之後，照射與階梯通孔23的 上穴直徑相同的光束直徑的雷射光的開大窗（large window)法等。可選擇的雷射加工法並非侷限於在上述實 施形態的說明中所使用者，可按每個工程來任意選擇共型 法、直接雷射法及開大窗法》其中，若使用直接雷射法， 如本實施形態所示銅箔的厚度係以1 5 μιη以下爲佳。 此外，在本實施形態中，在雙面可撓性基板1 3的雙面 層疊覆蓋膜16而製作出雙面核心基板17之後，在雙面核心 基板1 7層積增層，但是本發明並非侷限於此，亦可使用附 接著劑的單面覆銅層積板來取代覆蓋膜16，而在雙面可撓 性基板1 3直接設置增層。此時，如下所述製作多層印刷配 線板。首先，如前所述’製作出形成有鍍敷貫穿通孔9、 鍍敷有底通孔10及內層電路圖案12Α、12Β的雙面可撓性基 板1 3。之後，準備具有：絕緣基底材、形成在前述絕緣基 -23- 201146123 底材的表面的導電膜（第3導電膜）、及形成在前述絕緣 基底材背面的接著劑層的附接著劑層的單面覆導電膜層積 板。接著，進行將附接著劑層的單面覆導電膜層積板黏貼 在雙面可撓性基板13的雙面的層疊工程。該層疊工程係在 藉由附接著劑層的單面覆導電膜層積板的接著劑層熔融後 的接著劑而使鍍敷貫穿通孔9的內部被完全塡充，而且在 鍍敷有底通孔10的內部容許發生未藉由接著劑層熔融後的 接著劑予以塡充的空氣空隙的條件下進行。對如上所示所 得的多層印刷配線板，藉由雷射加工，去除鑛敷有底通孔 10內部的接著劑而使空氣空隙消滅，藉此，在底部露出鑛 敷有底通孔10，形成鍍敷有底通孔10成爲下穴的階梯通孔 。之後，藉由對第3導電膜及階梯通孔的內壁施行鍍敷處 理，形成將第3導電膜與內層電路圖案12A作電性連接的鍍 敷積層通孔。接著，將已施行鍍敷處理的第3導電膜按照 預定的圖案進行蝕刻，藉此形成外層電路圖案，而獲得積 層型的多層印刷配線板。 如上所述，雙面核心基板1 7係具有用以將內層電路圖 案12A與內層電路圖案12B作電性連接的鍍敷貫穿通孔9與 鍍敷有底通孔10。堆疊通孔構造係由鍍敷有底通孔10、及 配置在該鍍敷有底通孔10上的鍍敷積層通孔27所構成。該 鍍敷積層通孔27係在將形成在雙面核心基板17的鍍敷有底 通孔1 〇形成爲小徑孔洞的階梯通孔2 3的內壁形成有電解鍍 敷皮膜者。此外，鍍敷貫穿通孔10係構成爲僅進行雙面核 心基板17的表面與背面的層間導通，外層電路圖案30與內 -24- 201146123 層電路圖案12A、12B的層間導通並未進行者。 根據上述特徵’藉由本實施形態可得以下效果。 在將覆蓋膜1 6層疊時，變得不需要利用接著材來完全 塡充鏟敷有底通孔10的內部。亦即，鍍敷有底通孔1〇的內 部亦可利用接著劑而以不完全塡充的狀態，而不存在有空 氣空隙15a。因此，在可在鍍敷貫穿通孔9的內部完全塡充 接著劑的範圍內，儘可能減小覆蓋膜1 6的接著材層1 5的厚 度。結果，可儘可能使階梯通孔23變淺（例如ΙΟμηι左右） ，使得在階梯通孔23及通孔24Α、24Β的內壁施行電解鍍敷 處理時的電沈積容易性提升。此外，鍍敷積層通孔27、28 、2 9係形成爲不易受到因印刷配線板的構成構件的熱膨脹 所造成的影響等有利的構造。構成構件之中尤其構成接著 劑層1 5的接著劑係熱膨脹率較大，因此因接著劑層1 5變薄 所造成的效果較大。因此，可提升良率及減低用以確保連 接可靠性所需的電解鍍敷皮膜25的厚度。結果，藉由本實 施形態，可形成微細的外層電路圖案30。 此外，藉由本實施形態，在形成鑛敷積層通孔27時， 在鍍敷有底通孔10之上亦形成有電解鑛敷皮膜26。藉此， 因非對稱形狀而起，與鍍敷貫穿通孔9相比，熱應力較易 於集中的鍍敷有底通孔1 〇受到補強，可使連接可靠性提升 〇 此外，藉由本實施形態，由於鍍敷有底通孔1 0受到補 強，因此可使鍍敷有底通孔1 0的鍍敷厚（電解銅鍍敷皮膜 7的厚度）薄至可確保鍍敷貫穿通孔9之連接可靠性的程度 -25- 201146123 。結果，可縮短鍍敷工程所需時間，而可減低成本。此外 ，由於配合鍍敷有底通孔1〇的鍍敷厚度，銅鍍敷層8亦變 得較薄，因此可將雙面核心基板17的內層電路圖案12微細 化。 其中，在實施形態之說明中，配線圖案及鍍敷皮膜係 由銅所構成者，但是本發明並非限定於此，亦可爲例如鋁 或銀等其他金屬。 根據上述記載，若爲該領域熟習該項技術者，或許可 思及本發明之追加效果或各種變形，惟本發明之態樣並非 限定於上述實施形態。在未脫離由申請專利範圍所規定的 內容及其均等物所導出的本發明之槪念思想與趣旨的範圍 內，可爲各種追加、變更及局部刪除。 1 明 說 單 簡 式 圖 第1A圖係用以說明本發明之實施形態之積層型多層印 刷配線板之製造方法的工程剖面圖。 第1Β圖係接續第1 Α圖，用以說明本發明之實施形態之 積層型多層印刷配線板之製造方法的工程剖面圖。 第1C圖係接續第1B圖，用以說明本發明之實施形態之 積層型多層印刷配線板之製造方法的工程剖面圖。 第2圖係本發明之實施形態之積層型多層印刷配線板 的剖面圖。 第3圖係藉由習知技術所得之具有堆疊通孔構造的積 層型多層印刷配線板之製造方法的工程剖面圖。 -26- 201146123 【主要元件符號說明】 1、 1 9、1 0 1 :可撓性絕緣基底材 2、 3、 18、 102、 103 ：銅箔 4、104:雙面覆銅層積板 5 :貫穿通孔 6、105 :有底通孔 7 :電解銅鍍敷皮膜 8、2 6 :銅鍍敷層 9 :鍍敷貫穿通孔 10、106 :鍍敷有底通孔 1 1 :阻劑層 1 2A、1 2B :內層電路圖案 1 3 :雙面可撓性基板 14、 107 :絕緣薄膜 15、 22、 108 ' 112:接著材層 1 5 a :空氣空隙 1 6、1 0 9 :覆蓋膜 1 7、1 1 0 :雙面核心基板 18 :銅箔 1 8 a :開口部 20、111:單面覆銅層積板 21 :共型遮罩 23、1 13A :階梯通孔 -27- 201146123 24A、24B > 113B、1 1 3 C ：通孔 2 5 :電解鍍敷皮膜 27、28' 29、114A、114B、114C:鍍敷積層通孔 30、115:外層電路圖案 3 1 :積層通孔 3 2、1 1 6 :積層型多層印刷配線板 3 2 a、1 1 6 a :零件安裝部 3 2b、1 16b :可撓性線材部 -28-BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer printed wiring board, and more particularly to a method of manufacturing a multilayer printed wiring board of a stack type (bui 1 d - up ) type . [Prior Art] In recent years, miniaturization and high functionality of electronic devices have been progressing, as represented by portable information terminals such as mobile phones. Therefore, there is an increasing demand for higher density of printed wiring boards used in electronic equipment. Therefore, in order to mount an electronic component or the like at a high density on a printed wiring board, a laminated multilayer flexible printed wiring board has been continuously developed (see, for example, Patent Document 1). In the laminated multi-layer flexible printed wiring board, a double-sided flexible printed wiring board or a multilayer flexible printed wiring board is used as a core substrate, and an increase of 1 to 2 layers is formed on both sides or one side of the core substrate. Build-up layer. In the laminated multi-layer flexible printed wiring board, in order to electrically connect the build-up layer to the core substrate of the inner layer, plating is performed on the inner wall of the bottomed through hole (conductive hole) to obtain interlayer The shovel is applied through the through hole. However, as the bottomed through hole becomes deep, the following problems occur. First, since the constituent members of the printed wiring board thermally expand, the plated through holes are easily broken. Further, in order to obtain interlayer conduction, when a plating film is formed on the inner wall of the bottomed through hole, the plating solution becomes liable to stay at the bottom of the through hole', so that a desired plating thickness cannot be obtained. For the reason of 201146123 as shown above, the deeper the bottomed through hole is, the more difficult it is to ensure the electrical reliability of the via wiring. In view of the countermeasures of this problem, it is considered that a sufficiently thick plating film is formed on the inner wall of the bottomed through hole. However, if the thickness of the plating film formed on the inner wall of the bottomed through hole is increased, it is unavoidable that the thickness of the conductor layer formed on the buildup layer becomes large. The circuit pattern of the outer layer is formed by wet etching the conductor layer on the buildup layer in a desired pattern. Therefore, as the thickness of the conductor layer increases, it becomes less likely that the conductor layer on the buildup layer is finely processed. As a result, it is impossible to form a fine pattern in the circuit pattern of the outer layer, and it is difficult to mount the electronic component at a high density on the build-up layer. As described above, in the conventional laminated type multilayer flexible printed wiring board, there is a problem that it is difficult to meet the high-density mounting requirements. However, among the laminated multilayer flexible printed wiring boards, from the viewpoint of high density and improvement in design freedom, in particular, a laminated type multilayer having a so-called stacked via via structure can be obtained. Flexible printed wiring board. Here, the stacked via structure refers to a structure in which an interlayer connection portion composed of a plated through hole of a build-up layer is superposed on an interlayer connection portion formed by a plated through hole of a core substrate. A method of inexpensively and stably manufacturing a multilayer printed wiring board having a stacked via structure capable of high density mounting is strongly desired. In the prior art, a through hole (step via) of a so-called stepped via structure is collectively formed by laser processing (see Patent Document 2, Patent Document 3, and Patent Document 4). The stepped via structure can be efficiently formed by the techniques disclosed in these documents. However, in the -6-201146123 method, electrolytic copper plating for covering the inner wall of the stepped through hole by the mineral coating is usually performed once. Therefore, there is a tendency that the plating film formed on the side wall of the hole (small diameter side) below the stepped through hole tends to be thin. Therefore, there is a case where it is difficult to sufficiently ensure the reliability of the interlayer connection. Next, a method of manufacturing a laminated type multilayer printed wiring board having a stacked via structure by a conventional technique will be described in detail using FIG. Fig. 3 is an engineering sectional view for explaining a method of manufacturing a laminated type multilayer printed wiring board having a stacked via structure. First, a flexible insulating base material 1 〇 1 (for example, 25 μm thick) such as polyimide or a double-sided copper-clad layer having copper foil 102 and copper foil 103 (both of which are, for example, 8 μm thick) is prepared on both surfaces thereof. Stack 104. Next, as is clear from Fig. 3 (1), the double-sided copper-clad laminate 1 〇 4 is formed by a laser processing method to form a bottomed through hole 1 〇 5 which is a bottomed through hole. The copper foil 103 is exposed at the bottom of the bottomed through hole 105. Thereafter, electrolytic plating is performed on the copper foils 102 and 103 and the inner wall of the bottomed through hole 105 by performing electroconductive treatment on the copper foils 102 and 103 and the bottomed via 105 and subsequent electrolytic plating treatment. Membrane. The thickness of the electrolytic plating film is formed to be required to ensure the connection reliability of the via wiring (e.g., about 15 μm). Through the above-mentioned work, a plated bottomed through hole 106 belonging to the bottomed type interlayer conduction portion for electrically connecting the copper foil 102 of the flexible insulating base material 1〇1 and the copper foil 103 is formed. Next, as is apparent from Fig. 3 (1), the copper vane 102 of the flexible insulating base material 101 and the copper foil 103 are etched in a predetermined pattern by photofabrication, thereby forming a circuit pattern. ( 201146123 inner layer circuit pattern). More specifically, a circuit pattern is formed on both surfaces of the flexible insulating base material 101 by a process consisting of formation of light of a resist layer, development, etching of a copper foil, and peeling of a resist layer. Next, as is apparent from Fig. 3 (1), a coating having an adhesive layer 108 on the polyimide film edge film 107 (e.g., 12 μm thick) is prepared. The subsequent layer 108 is made of an adhesive such as acrylic or epoxy. Next, a lamination process in which the cover film 109 is adhered to the flexible insulating base material 101 having the circuit pattern formed thereon is performed using a vacuum laminator or the like. The thickness of the material layer 108 is formed such that the thickness of the inside of the bottomed via 106 (e.g., 25 μm) can be completely filled with an adhesive. Through the above work, the double-sided core substrate 1 1 所示 shown in Fig. 3 (1) is obtained. Next, as is clear from Fig. 3 (2), a single-sided copper clad laminate 111 having a copper foil (e.g., 12 μm) on one side of a flexible insulating base (e.g., 2 μ μm thick polyimide) is prepared. . A predetermined portion of the copper foil of the single-sided copper clad laminate 111 is formed by the above-described photolithography method. The copper foil having the opening is formed into a Conformal Mask (also referred to as a metal mask) for laser shading. The through hole is formed in the copper opening to remove the resin which is exposed to the flexible insulating base material or the like on the bottom surface of the opening by laser processing. Next, as is clear from Fig. 3 (2), the single-sided copper-clad laminates | and 111 having the common-type mask are passed through the adhesive layers 112 and 112, respectively, using the bonding material for laminating the double-sided core 110. The deposition is continued on the front and back surfaces of the double-sided substrate 110. Next, it can be seen from Fig. 3 (2) that the substrate of the opening mask foil can be processed by the thickness of the substrate which can be subsequently plated using a single-sided copper-clad laminate | or an over-laminated film. A common mask of the core ΐ 1 1 1 -8 - 201146123 is used for laser processing, thereby forming stepped vias 1 1 3 A and vias L 1 1 3 B, 1 1 3 C. Next, as is clear from Fig. 3 (3), the copper foil on the single-sided copper-clad laminate 111, the inner wall of the stepped through-hole 113A, and the inner walls of the through-holes 113B and 113C are subjected to a conductive treatment and subsequent The electrolytic plating treatment is performed to form an electrolytic plating film. The thickness of the electrolytic plating film is formed to, for example, about 25 to 3 Ομηι to ensure the reliability of the interlayer connection. Thereby, the ore-layered through holes 11 4A, 1 1 4 , 114C for obtaining conduction between the core substrate and the layer of the buildup layer are formed. The ore deposit through hole 114A is plated to the inner wall of the stepped through hole U3A, and the plated through hole 1 14B is plated to the inner wall of the through hole 1 13B opposed to the stepped through hole 1 13A. The plated through hole 1 14C is applied to the inner wall of the through hole U3C. Next, as is clear from Fig. 3 (3), the copper foil of the single-sided copper clad laminates 111, 111 is etched in a predetermined pattern by a photolithography process, thereby forming an outer layer circuit pattern 1 1 5, 1 1 5. After that, a photoresist layer (not shown) is formed as needed, and surface treatment such as solder plating, ruthenium plating, or gold plating is applied to the terminals of the circuit pattern, and the outer shape is processed by drilling a hole by a mold or the like. . Through the above work, a laminated type multilayer printed wiring board 1 16 having a stacked via structure was obtained. As can be seen from Fig. 3 (3), the plated through-hole 1 1 4 A is formed directly above the plated bottomed through hole 106 of the double-sided core substrate 1 10 of the inner layer, and the plated through hole 106 is plated. The plated through holes 114A form a stacked via structure. In the laminated type multilayer printed wiring board 1 16 , the interlayer connection between the front surface and the back surface of the double-sided core substrate 110 is performed by plating the bottomed through hole 106 to 201146123, which is known from Fig. 3 (3). The multilayer printed wiring board 11 6 has a component mounting portion H 6a in which a build-up layer is laminated on the double-sided core substrate 110, and a flexible wire portion 6b extending from the component mounting portion 6b. The flexible wire portion 116b is not provided with a part of the double-sided core substrate no of the build-up layer. Through the above works, the plated through-holes 106 must be completely filled with the material. However, if the plating through hole is formed in the plating process by the plating process on the inner wall of the through hole of the double-sided copper clad laminate 104, the plated through hole 106 is less likely to be filled with the adhesive. This is based on the fact that the plating through hole system can be filled in the two directions of the front surface and the back surface. On the other hand, the bottom plating through hole can be filled only by one direction. Therefore, compared with the case where the interlayer connection of the double-sided core substrate 110 is performed by plating through the through holes, the case where the thickness of the subsequent layer 108 becomes thick is unavoidable. Therefore, the laminated via 1 1 3 becomes deep. As a result, as described above, the plating thickness for ensuring the reliability of the interlayer connection becomes large. For example, when forming the plated through holes 114A, 114B, and 114C as described above, it is necessary to perform electrolytic plating for forming a plating film of about 25 to 3 μm. It is assumed that the electrolytic plating of this degree is performed on the copper foil (the thickness of 2 μm thick) of the single-sided copper-clad laminate 111, and the conductor layer (copper foil + electrolytic plating film) on the single-sided copper-clad laminate 111 The total thickness is 37 to 42 μm. The patterning of the conductor layer is performed by wet etching, so that it is difficult to form a fine circuit pattern having a circuit pitch of about 1 〇〇μηι. As described above, in the past, there has been a problem that a laminated type multilayer printed wiring board that satisfies the requirements of high-density mounting -10-201146123 cannot be manufactured. In particular, this problem is the same even in the case of the multilayer printed wiring board which does not have the flexible wire 1 16b. [PRIOR ART DOCUMENT] [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-200260 [Patent Document 2] [Patent Document 3] Japanese Patent Laid-Open Publication No. Hei. No. 2008-258912 (Patent Document 4). The above problem of solving a multilayer printed wiring board capable of obtaining a high-density mounting due to difficulty in forming a fine outer layer circuit pattern is intended to provide a laminated type multilayer printed wiring board having a stacked via structure capable of high density mounting. Production method. (Means for Solving the Problem) According to one aspect of the present invention, a method for producing a multilayer printed wiring board is provided, which is characterized in that a double-sided conductive film layer having a first conductive film and a second conductive film on the front surface and the back surface is provided Forming a plated through hole and a plated through hole for electrically connecting the second conductive film and the second conductive film, -11 - 201146123, the first conductive film and the second conductive film Etching according to a predetermined pattern to produce a double-sided flexible substrate having an inner layer circuit pattern, and preparing a cover film having an insulating film and an adhesive layer formed on one surface of the insulating film, The adhesive agent after the melting of the adhesive layer of the cover film completely fills the inside of the through hole, and allows the inside of the plated bottomed through hole to be filled without being filled by the adhesive. a double-sided core substrate is formed by adhering the cover film to both surfaces of the double-sided flexible substrate under air void conditions, at least in front of the double-sided core substrate The opening surface side on which the bottom via hole is plated is laminated, and then a buildup layer having a third conductive film formed on one surface is laminated; and the above-mentioned adhesive inside the plated bottomed via hole is removed by laser processing The air gap is eliminated, whereby the plated bottomed through hole is exposed at the bottom portion, and the stepped through hole in which the plated bottomed through hole is a lower hole is formed, and the inside of the third conductive film and the stepped through hole are formed The plating treatment is performed to form a plating via hole for electrically connecting the third conductive film and the inner layer circuit pattern, and the third conductive film subjected to the plating treatment is etched in a predetermined pattern. This forms an outer circuit pattern. (Effects of the Invention) With the above features, the present invention achieves the effects as described below. In a laminated type multilayer printed wiring board having a stacked via structure according to an embodiment of the present invention, the stacked via structure is electrically connected to the surface and the back surface of the double-sided flexible base-12-201146123 board. A plated through hole is formed; and a plated through hole disposed on the plated bottomed through hole is formed. The plated through hole is formed by electrically connecting the outer layer circuit pattern and the inner layer circuit pattern, and forms an inner wall of the stepped through hole formed in the bottomed through hole formed in the double-sided flexible substrate as a small diameter hole. Those who have a plating film. Thereby, a stepped via structure composed of a plated bottomed via and a plated through via formed thereon is formed, and by the above-described embodiment, an embodiment of the present invention is used to cover When the film is laminated, it is not necessary to completely fill the inside of the plated through-hole formed in the double-sided flexible substrate. This is based on the fact that the adhesive in the plated bottomed via is removed when the stepped via is formed. Therefore, the thickness of the adhesive layer can be made as small as possible within the range in which the adhesive can be filled in the through-hole of the double-sided flexible substrate. As a result, the stepped via holes can be made shallower than in the prior art. Therefore, in the electrolytic plating treatment for forming the plated through-holes, the ease of electrodeposition is improved, and the influence on the plated through-holes due to the thermal expansion of the constituent members is alleviated. Therefore, with the present invention, the yield can be improved, and the plating thickness required for ensuring the connection reliability of the via wiring can be minimized. Therefore, with the present invention, the outer layer circuit pattern formed in the buildup layer can be made finer. Further, according to the present invention, when the plating via hole is formed, an electrolytic plating film is formed on the plated bottom via hole of the double-sided flexible substrate. Thereby, due to the asymmetrical shape, the plated through-holes which are more easily concentrated than the plating through-holes are reinforced, and the connection reliability can be improved -13-201146123. Further, since the plated through-holes are reinforced as described above, the plating of the plated through-holes can be made thick enough to ensure the reliability of the connection of the plating through the vias. As a result, the time required for the plating process can be shortened, and the cost can be reduced. Further, the inner layer circuit pattern formed on the double-sided flexible substrate can be made fine. As described above, by the present invention, there is provided a method of inexpensively and stably manufacturing a laminated type multilayer printed wiring board having a stacked via structure capable of high density mounting. [Embodiment] Hereinafter, a method of manufacturing a laminated type multilayer printed wiring board having a stacked via structure having an embodiment of the present invention will be described with reference to the drawings. Here, the same component symbols are denoted by the same components, and the detailed description is omitted. Further, the figure is shown as a mode indicator, and the display is centered on the feature portion of the embodiment, and the relationship between the thickness and the plane size, the thickness ratio of each layer, and the like are different from those of the actual person. First, a method of manufacturing a laminated type multilayer printed wiring board 3 2 having a stacking® via structure according to an embodiment of the present invention will be described with reference to Figs. 1A to 1C and Fig. 2 . Figs. 1A to 1C are structural sectional views for explaining a method of manufacturing the laminated type multilayer printed wiring board 32. Fig. 2 is a cross-sectional view showing a multilayer printed wiring board 32 of the present embodiment. -14 - 201146123 First, it can be seen from Fig. 1A (1) that the copper foil 2 and the copper foil 3 are provided on both sides of the flexible insulating base material 1 (for example, a polyimide of 25 μm thick) (first The double-sided copper clad laminate 4 of the conductive film and the second conductive film). The thickness of the copper foil 2 and the copper foil 3 is, for example, 5 μm. Then, the double-sided copper clad laminate 4' is formed by a laser processing method, a resin etching method, or the like, to form a through hole 5 penetrating through the double-sided copper clad laminate 4, and a bottomed through hole 6. As shown in Fig. 1 (1), the bottomed through hole 6 is a bottomed through hole in which the copper foil 3 is exposed on the bottom surface. Here, the through diameter of the through hole 5 and the bottomed through hole 6 is, for example, 70 μχ in diameter. When using the laser processing method in this project, the following two methods can be selected. The first method is called a method of the co-type laser processing method. In this method, openings of the same diameter as the diameter of the through holes are provided in the copper foils 2, 3 to form a common type of mask. Thereafter, the common mask is irradiated with the laser light to remove the insulating resin exposed at the opening. The second method is called a method of direct laser processing. In this method, a common mask is not formed, and laser light is directly irradiated onto the copper foil to remove the copper foil and the insulating resin therebelow. In the present embodiment, it is not necessary to perform a co-type laser processing method for etching a copper foil by a photolithography process, but a direct use of carbon dioxide laser is considered in consideration of productivity. Laser processing. Prior to the direct laser processing, the copper foils 2, 3 of the double-sided copper clad laminate 4 are subjected to surface treatment. That is, the copper foil surface on which the laser light is irradiated is formed into a roughening treatment of a low thickness. Thereby, when using a carbon dioxide laser (wavelength: about 9. 8 μιη ) When laser processing is performed, the absorption of the laser light of the copper foils 2 and 3 can be stably improved. In the present embodiment, Multi-bond 150 of Japan MacDermid Co., Ltd. is used for the roughening -15-201146123. Thereby, the adhesion to the electrolytic copper plating film 7 formed in the subsequent work can be ensured, and the absorption of the carbon dioxide laser light in the surface of the copper foil can be improved. It was confirmed that the absorption rate of carbon dioxide laser light was actually increased from about 20% to about 30% before and after the surface treatment. In the present embodiment, the through hole 5 and the bottomed through hole 6 are simultaneously processed. Therefore, the copper foil 2 can be easily processed on the surface of the copper box 2 by performing the above-described roughening treatment. At the same time, the copper foil surface is formed to have a low thickness so as not to penetrate the copper foil 3 when the bottomed through hole 6 is formed, and the back surface of the copper foil 3 is treated so that the absorption of the laser light is reduced to good. However, when the through hole 5 is to be formed efficiently, it is preferable to perform the roughening treatment as the back surface treatment of the copper foil 3. The thinner the copper foil 2'3 of the double-sided copper clad laminate 4, the more likely it is to penetrate the copper foils 2, 3 during laser processing. Therefore, when the thickness of the copper foil is as small as ΙΟμηι or less as described in the present embodiment, since the bottomed through hole 6' is easily formed, a low-thickness copper box which is treated as a back surface with almost no roughening treatment is used. 3 is better. Here, the laser processing method will be described in detail. First, the case where the bottomed through hole 6 is processed will be described. When the copper foil 2 is processed, the average 1 shot laser light energy (set to power ρ) is increased. Next, it is preferable to finish the processing of the copper foil 2 by one emission. Thereafter, when the resin of the flexible insulating base material 1 is processed until the copper foil 3 is exposed, the energy of the laser light emitted by the average one is reduced to (1/2) P 〜 (1/3) P, and 2 〜 3 launch complete resin processing. Next, the case of penetrating the through hole 5 will be described. At this time, -16-201146123, the double-sided copper foil and the resin are processed using laser light having an average light emission of laser light of the above-mentioned power P. Continuous irradiation of 3 to 4 shots is performed to complete the through-hole 5. When a thinner copper foil is used, in order to easily form the bottomed through hole 6, the back surface (the surface in contact with the base material) of the copper foil 3 which becomes the bottom of the bottomed through hole 6 is formed to have a low thickness. Along with this, the back surface of the copper foil 2 (the surface in contact with the base material) is roughened. Next, the through via 5 is formed by surface processing of the copper foil 3. According to this method, the through-holes 6 can be easily formed while forming the through-holes efficiently. Further, in other methods, the through hole 5 may be formed by laser processing from the surface of the copper case 2 and the surface of the copper plate 3. At this time, since the surfaces of the copper foils 2, 3 are subjected to the roughening treatment, they are easy to process from any direction, and there is no need to consider the back surface treatment state (the thickness of the copper foil) of the copper foil. Next, in order to remove the stain (resin residue) generated when the through hole 5 and the bottomed through hole 6 are formed, plasma treatment and wet etching (decontamination treatment) are performed. The optimum conditions for the plasma treatment of the through-hole 5 and the bottomed via 6 are substantially the same. On the other hand, regarding wet etching using sodium persulfate or the like, the optimum conditions are different between the two. That is, wet etching is almost unnecessary for the through via 5. It is not preferable to perform etching so that the copper foils 2 and 3 are retracted, which may adversely affect the subsequent conductive treatment. On the other hand, in order to remove the dissimilar metal such as ruthenium or ruthenium on the back surface of the copper poise 3 caused by the back surface treatment, it is necessary to carry out the plaque of 1 to 2 μm. In view of the influence on the through hole 5, it is preferable to complete the treatment with as little etching amount as possible. In the present embodiment, etching is performed at 1 μm. -17- 201146123 Next, it can be seen from Fig. 1A (2) that the copper foil 2, 3, the inner wall of the through hole 5 and the inner wall of the bottomed through hole 6 are subjected to a conductive treatment and subsequent electrolytic copper plating. The coating treatment is carried out to thereby form an electrolytic copper plating film 7 (about 8 μm thick). Thereby, the copper plating layer 8 on the copper foils 2, 3, the plating through-holes 9, and the plated through-holes 10 are formed. The plating penetrates the through-hole 9 through the interlayer conduction path, and the plated bottom via 10 is provided with a bottom type interlayer conduction circuit. Each of the plating vias electrically connects the copper foil 2 on the surface of the flexible insulating base material 1 to the copper foil 3 on the back surface. Among them, the liquid renewability of the treatment liquid in the above-described conductive treatment process and electrolytic copper plating project is not the same as that of the through-hole 5 and the bottomed through-hole 6. That is, the liquid renewability of the bottomed through hole 6 is inferior to that of the through hole 5. Therefore, the engineering flow under the condition that the bottomed through hole 6 can be processed is basically performed. Regarding the electrolytic copper plating process, the adhesion of the side wall near the bottom of the bottomed through hole 6 is likely to be deteriorated. Therefore, the electrolytic copper plating treatment is preferably carried out using a plating bath containing a high concentration of copper sulfate. Next, as is apparent from the first diagram (3), the resist layers 1 1 and 1 1 are formed on the copper plating layers 8 and 8. A dry film resist is used in forming the resist layer 11. The dry film resist is preferably a thickness (e.g., 20 μm) which can be used for tenting through both the through hole 9 and the plated through hole 10. Thereby, the resist is prevented from entering the plating through-hole 9 and the plated through-hole 1 ,, and the peeling of the resist layer 11 which is performed later can be easily performed. Among them, a liquid resist or an electrodeposition resist may be used instead of the dry film resist. Next, as is understood from the first drawing (4), the resist layer 11 is etched in a predetermined pattern by exposure and development of the resist layer 11 by a photosensitive etching process, and then patterned. The resist layer 11 is formed as a mask to etch the copper plating layer 8 and the copper foils 2, 3. Thereafter, the resist layer 11 is peeled off. Thereby, the inner layer circuit patterns 12A and 12B are formed on the front and back surfaces of the flexible insulating base material 1, respectively. The double-sided flexible substrate 13 shown in Fig. 1A (4) is obtained by the above-mentioned work. Next, it is understood from Fig. 1B (5) that the cover film 16 having the insulating film 14 (e.g., 12 μm thick) such as a polyimide film and the adhesive layer 15 formed on one side of the insulating film 14 is prepared. The subsequent layer 15 is composed of an adhesive such as acrylic or epoxy. Next, a lamination process of the double-sided adhesive cover film 16 on the double-sided flexible substrate 13 is carried out using a vacuum laminator or the like. Thereby, the inner layer circuit patterns 12A, 12A and the plating through holes 9 are filled by the adhesive layer 15. In the present laminating process, it is not necessary to completely fill the inside of the plated bottomed through hole 10 by using an adhesive. In other words, in the lamination process, the inside of the through-hole 9 is completely filled by the adhesive which is melted by the adhesive layer 15 of the cover film 16, and the inside of the plated through-hole 10 is allowed to occur. It is not carried out under the condition of an air gap of 1 5 a which is not filled by the adhesive which has been melted by the adhesive layer 15 . As described above, the thickness of the adhesive layer i 5 in the present embodiment can be completely filled with the plating through-holes 9, and it is not necessary to consider the state of the inside of the plated through-holes 10. Therefore, the adhesive layer 5 is as thin as possible within a range in which the plating can be completely filled through the through holes 9. In the present embodiment, the thickness of the adhesive layer 15 is formed as! 5μηι. As shown in Fig. 1b, 201146123 (5), there is a case where the air gap 15a is generated inside the plated bottomed through hole 10. However, in the post-engineering process, the adhesive in the plated through-hole 10 is completely removed by laser processing, so that the air void 15a does not become a problem. In the above-mentioned work, the double-sided core substrate 17 which becomes the core substrate of the multi-layer printed wiring board shown in Fig. 1B (5) is obtained. Next, as shown in FIG. 1B (6), a copper foil 18 (third conductive film) having a thickness of, for example, 12 μm is provided on one surface of the flexible insulating base material 19 (for example, a polyimide having a thickness of 25 μm). Single-sided copper clad laminate 20. Next, the opening portion 18a is formed in the copper foil 18 of the single-sided copper clad laminate 20 by the photosensitive etching method. More specifically, a resist layer (not shown) is formed over the copper foil 18, and the resist layer is patterned by exposure and development. Next, the patterned resist layer is formed into a mask, and the copper foil 18 is etched. Thereby, the common type mask 2 1 is formed to form a through hole by laser processing to remove the resin of the base material in the post-engineering process. Next, it is understood from Fig. 1B (6) that the single-sided copper clad laminates 20 and 20 on which the common mask 21 is formed are laminated through the adhesive layers 22 and 22 by using an adhesive for laminating. On both sides of the double-sided core substrate 17. In the case of the backing material used herein, it is preferred that the low flow type (pre-impregnated body) or the bonding sheet or the like has a small outflow. Alternatively, the single-sided copper-clad laminate 20 having the unprocessed copper foil 18 may be passed through the subsequent material layer 22 and then the double-sided core substrate 17 may be followed by etching the copper foil 18 in a predetermined pattern. To form a common mask 2 1 . Next, as is understood from Fig. 1(c), the common mask 21 is used to perform the -20-201146123 laser processing to form the stepped through holes 23 and the through holes 24A and 24B. The stepped through hole 23 penetrates through the flexible insulating base member 19, the adhesive layer 22, the insulating film 14, and the adhesive layer 15, and the plated bottomed through hole 10 is exposed at the bottom. In the laser processing, the resin inside the plated through-hole 10 is completely removed, and the air gap 15a is extinguished. The through holes 24A, 24B penetrate the flexible insulating base material 19, the adhesive layer 22, the insulating film I4, and the adhesive layer I5, and the inner layer circuit patterns 12A, 12B are exposed at the bottom. Among them, in order to form the stepped through hole 23, it is necessary to remove the resin which is inside the plated bottomed through hole 1 . Therefore, the amount of the resin material to be removed is more than that of the through holes 23A, 24B. Therefore, it is preferable to increase the number of shots of the laser processing or to increase the pulse width of the laser light when forming the stepped through holes 23. For the laser used in the laser processing, a UV-YAG laser, a carbonic acid laser, an excimer laser, or the like can be selected. Next, as is understood from FIG. 1C (8), the inner wall of the stepped through hole 23 and the inner walls of the through holes 24A and 24B are subjected to a conductive treatment and an electrolytic plating treatment to form an electrolysis. The coating film 25 is applied. Thereby, the copper plating layer 26 on the copper foil 18 and the plating via holes 27, 28, 29 are formed. The plated through holes are electrically connected to the inner layer circuit patterns 12A and 12B and the copper foil 18 and the copper plating layer 26 (the outer layer circuit pattern 30 thereafter). The plated through hole 27 is formed by forming an ore layer on the inner wall of the stepped through hole 23. The plated through hole 28 is formed with a plating layer on the inner wall of the through hole 24A opposed to the stepped through hole 23. The plated through hole 29 is formed by forming a plating layer on the inner wall of the through hole 24B. The thickness of the electrolytic coating film 25 is formed to ensure the connection of the crucible required for reliable performance. In the present embodiment, the thickness of the adhesive layer 15 is further reduced as compared with the prior art, whereby the thickness of the electrolytic plating film 25 is also thinner than the conventional technique (for example, 25 to 30 μm). To the extent of, for example, 15 μm to 2 0 μm. As can be seen from Fig. 1C (8), the stacked via structure in which the plated through-holes 27 are formed in the plated bottomed via 10 is completed by the above-mentioned process. Next, it can be seen from Fig. 2 that the photosensitive layer is used. In the etching processing method, the copper foil 18 and the electrolytic plating film 25 are etched in a predetermined pattern, thereby forming the outer layer circuit pattern 30. After that, a photoresist layer (not shown) is formed as necessary, and a surface treatment such as solder plating, nickel plating, or gold plating is applied to the terminals of the circuit pattern, and the outer shape processing is performed by drilling using a mold or the like. . Through the above work, the laminated type multilayer printed wiring board 3 2 having the stacked via structure of the present embodiment shown in Fig. 2 can be obtained. The multilayer printed wiring board 32 of the present embodiment is a single-sided copper-clad laminate 20 or 20 which is formed on the front and back surfaces of the double-sided core substrate 17 which is an inner layer and which is formed by laminating the outer layers 22 and 22 . The present embodiment is not limited thereto, and may be laminated on the surface of the double-sided core substrate 17, that is, on the opening surface side of the plated through-hole 1〇 of the double-sided core substrate 17, through the adhesive layer 22. A single-sided copper clad laminate 20 of the outer layer. By this, it is possible to provide a multilayer printed wiring board having a buildup layer on only one side. The inner layer circuit patterns 12A, 12B are electrically connected to the outer layer circuit pattern 30 by plating the via holes 27, 28, and 29. The laminated multilayer -22-201146123 printed wiring board 32 obtained by the manufacturing method of the present embodiment has a component mounting portion 32a in which the buildup layer 31 is laminated on the double-sided core substrate 17 belonging to the flexible printed wiring board. And a layered flexible wire portion 32b is not laminated on the double-sided core substrate 17. That is, the flexible wire portion 32b is configured to extend from the component mounting portion 32a. The present embodiment is not limited to this. It is also possible to manufacture a multilayer printed wiring board in which the double-sided core substrate 17 does not constitute the flexible wire member 3 2b. Further, in the present embodiment, a method of manufacturing a flexible multilayer printed wiring board will be described, but the present invention is not limited thereto. Further, in the laser processing method, in addition to the aforementioned common-type laser processing method or direct laser processing method, there is also a case where the copper foil 18 is formed with a larger opening than the upper hole of the stepped through hole 23. A large window method of irradiating laser light having the same beam diameter as that of the upper hole of the stepped through hole 23 is irradiated. The optional laser processing method is not limited to the user in the description of the above embodiment, and the common method, the direct laser method, and the large window method can be arbitrarily selected for each project. The thickness of the copper foil as shown in the present embodiment is preferably 15 μm or less. Further, in the present embodiment, after the cover film 16 is laminated on both surfaces of the double-sided flexible substrate 13 to form the double-sided core substrate 17, the double-sided core substrate 17 is laminated, but the present invention is not To be limited thereto, a single-sided copper-clad laminate with an adhesive may be used instead of the cover film 16, and a double-layer flexible substrate 13 may be directly provided with a build-up layer. At this time, a multilayer printed wiring board was produced as follows. First, as described above, the double-sided flexible substrate 13 on which the plating through-hole 9, the plated through-hole 10 and the inner layer circuit patterns 12A, 12A are formed is formed. Thereafter, it is prepared to have an insulating base material, a conductive film (third conductive film) formed on the surface of the insulating base-23-201146123 substrate, and an adhesive layer formed on the adhesive layer on the back surface of the insulating base material. Single-sided conductive film laminated board. Next, a lamination process in which the single-sided conductive film laminate of the adhesive layer is adhered to both surfaces of the double-sided flexible substrate 13 is performed. In the lamination process, the inside of the plating through-hole 9 is completely filled by the adhesive which is melted by the adhesive layer of the single-layer conductive film laminated plate of the adhesive layer, and the plating is bottomed. The inside of the through hole 10 is allowed to occur under the condition that an air gap which is not filled by the adhesive after the adhesive layer is melted occurs. The multilayer printed wiring board obtained as described above is subjected to laser processing to remove the adhesive inside the underlying through hole 10 to eliminate the air void, thereby exposing the mineralized bottomed through hole 10 at the bottom to form The plated through hole 10 is formed as a stepped through hole of the lower hole. Thereafter, a plating process is performed on the inner walls of the third conductive film and the stepped via holes to form a plated via hole for electrically connecting the third conductive film and the inner layer circuit pattern 12A. Then, the third conductive film which has been subjected to the plating treatment is etched in a predetermined pattern to form an outer layer circuit pattern, thereby obtaining a laminated type multilayer printed wiring board. As described above, the double-sided core substrate 17 has plating through-holes 9 and plated through-holes 10 for electrically connecting the inner layer circuit pattern 12A and the inner layer circuit pattern 12B. The stacked via structure is composed of a plated bottomed through hole 10 and a plated through hole 27 disposed on the plated bottomed through hole 10. The plated through-hole 27 is formed by forming an electrolytic plating film on the inner wall of the stepped through hole 23 formed in the plated through-hole 1 formed on the double-sided core substrate 17 as a small-diameter hole. Further, the plating through-via 10 is configured to conduct only the interlayer between the front and back surfaces of the double-sided core substrate 17, and the interlayer conduction between the outer layer circuit pattern 30 and the inner-24-201146123 layer circuit patterns 12A and 12B is not performed. According to the above feature, the following effects can be obtained by the present embodiment. When the cover film 16 is laminated, it becomes unnecessary to completely fill the inside of the bottomed through hole 10 by means of the backing material. That is, the inner portion of the plated through-hole 1〇 may be in an incompletely filled state by the adhesive, and the air void 15a may not be present. Therefore, the thickness of the adhesive layer 15 of the cover film 16 is made as small as possible within the range in which the inside of the plating through-hole 9 can be completely filled. As a result, the stepped through holes 23 can be made shallower (e.g., about ημηι) as much as possible, so that the electrodeposition ease at the time of performing the electrolytic plating treatment on the inner walls of the stepped through holes 23 and the through holes 24 Α, 24 。 is improved. Further, the plated through-holes 27, 28, and 29 are formed to be advantageous in that they are not easily affected by thermal expansion of the constituent members of the printed wiring board. Among the constituent members, in particular, the adhesive agent constituting the adhesive layer 15 has a large thermal expansion coefficient, and therefore the effect of the thinner adhesive layer 15 is large. Therefore, the yield can be improved and the thickness of the electrolytic plating film 25 required for ensuring the connection reliability can be reduced. As a result, according to this embodiment, the fine outer layer circuit pattern 30 can be formed. Further, according to the present embodiment, when the mineralized bed through hole 27 is formed, the electrolytic mineral coating film 26 is formed on the plated bottomed through hole 10. Thereby, the plated through-hole 1 is more reinforced than the plating through-hole 9 by the asymmetric through-hole 9, and the connection reliability can be improved, and the present embodiment can be improved by the present embodiment. Since the plated bottomed through hole 10 is reinforced, the plating thickness of the plated through hole 10 (the thickness of the electrolytic copper plating film 7) can be made thin to ensure the connection of the plating through the through hole 9. The degree of reliability -25, 201146123. As a result, the time required for the plating process can be shortened, and the cost can be reduced. Further, since the copper plating layer 8 is also made thinner by the plating thickness of the plated through hole 1〇, the inner layer circuit pattern 12 of the double-sided core substrate 17 can be made fine. In the description of the embodiment, the wiring pattern and the plating film are made of copper. However, the present invention is not limited thereto, and may be other metals such as aluminum or silver. According to the above description, the present invention is not limited to the above embodiment, and the additional effects or various modifications of the present invention are contemplated by those skilled in the art. Various additions, modifications, and partial deletions may be made without departing from the spirit and scope of the invention as set forth in the appended claims. 1 is a sectional view showing a method of manufacturing a laminated type multilayer printed wiring board according to an embodiment of the present invention. Fig. 1 is a cross-sectional view showing the construction of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. Fig. 1C is a cross-sectional view showing the construction of a method of manufacturing a multilayer printed wiring board according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing a laminated type multilayer printed wiring board according to an embodiment of the present invention. Fig. 3 is an engineering sectional view showing a method of manufacturing a laminated type multilayer printed wiring board having a stacked via structure obtained by a conventional technique. -26- 201146123 [Explanation of main component symbols] 1, 1 9, 1 0 1 : Flexible insulating base material 2, 3, 18, 102, 103: Copper foil 4, 104: Double-sided copper clad laminate 5: Through-holes 6, 105: bottomed vias 7: electrolytic copper plating film 8, 26: copper plating layer 9: plated through vias 10, 106: plated through-holes 1 1 : resist layer 1 2A, 1 2B : inner layer circuit pattern 1 3 : double-sided flexible substrate 14 , 107 : insulating film 15 , 22 , 108 ' 112 : adhesive layer 1 5 a : air gap 16 , 1 0 9 : covering Film 1 7 , 1 1 0 : double-sided core substrate 18 : copper foil 1 8 a : opening portion 20, 111: single-sided copper-clad laminate 21 : common type mask 23, 1 13A : stepped through hole -27- 201146123 24A, 24B > 113B, 1 1 3 C : through hole 2 5 : electrolytic plating film 27, 28' 29, 114A, 114B, 114C: plated through hole 30, 115: outer circuit pattern 3 1 : laminated Through hole 3 2, 1 1 6 : Multilayer printed wiring board 3 2 a, 1 1 6 a : Part mounting portion 3 2b, 1 16b : Flexible wire portion -28-