200847886 九、發明說明 【發明所屬之技術領域】 本發明係關於一種增建型多層印刷配線板之製造方法 及配線板之構造，特別是關於在層間連接部包含階狀通孔 構造之多層可撓性印刷配線板之製造方法及配線板之構造 【先前技術】 近年來，電子機器特別是行動電話之小型化/高功能 化極爲驚人，構裝於多層可撓性印刷配線板之零件亦隨之 置換成CSP(晶片尺寸封裝），而有封裝成高密度並在不增 加基板尺寸下附加高功能之演變。 因此，爲了實現高密度構裝，以雙面或多層可撓性印 刷配線板爲核心基板，並於雙面或單面具有1〜2層左右增 建層之增建型多層印刷配線板亦已逐漸實用化。 此無須增加步驟可進行高密度層間連接者，專利文獻 1中，已有提案一種將段狀之通孔與階狀通孔加以組合者 〇 此係可一倂進行多層構造之層間連接的方法，其同時 考量到位置偏移等，使雷射加工用之金屬光罩（Metal Mask)、共型光罩（Conformal Mask)之直徑愈往內層逐漸 變小，藉由雷射加工形成導通用孔，並藉由鍍敷等獲得層 間連接。 然而，在形成該階狀通孔上會有幾項問題。首先，如 -4- 200847886 以上所述，必須考量到位置偏移而將外層側之共型光罩形 成爲較大，有時會因積層等之位置精度而未必能成爲高密 度層間連接。又，在各層共型光罩之中心未一致的情況下 ，外層側之共型光罩會變成如屋簷般，而變成內層側之雷 射加工之不良原因，或當形成導通用孔後進行鍍敷時，造 成鍍敷周圍不穩定。 因此，便容易產生鍍敷孔隙等不良，以鍍敷所製得之 階狀通孔會呈不對稱構造，在溫度循環測試等於階狀通孔 所產生之熱應力會局部變大，而亦成爲層間連接之可靠性 降低的原因。 由於此種原因，結果爲了獲得通孔之可靠性，即必須 增加鍍敷厚度，但若增加鍍敷厚度則導體層厚度亦會變厚 ，結果便難以形成微細電路。 爲了確保用以電氣連接增建層與內層之雙面核心基板 之通孔的連接可靠性，則增建層之通孔壁面的鍍敷厚度亦 必須增加。因此，難以形成微細電路，而無法滿足高密度 構裝之要求。因此，已提案有一種以增加層數來彌補微細 電路形成能力之不足，而進一步進行第2段增建之方法。 [專利文獻1 ]日本專利第2 5 6 2 3 7 3號公報 [專利文獻2]日本特開2001-177248號公報 【發明內容】 [發明欲解決之課題] 然而，欲使用該方法以製作2段增建型多層多層印刷 200847886 配線板時，由於反覆逐次積層，因此會有隨著層數之增加 使得步驟變繁雜，而造成良率降低之問題。 針對上述問題，藉由圖3來說明。如圖3所示，在將增 建層122組合於內層核心基板121以構成具有纜線部12 3之 多層印刷基板1 24時，會產生下述問題點。 使用預先製作之雷射加工時之共型光罩1 1 1及形成於 內層之雙面核心基板1 2 1的雷射加工用共型光罩1 1 2進行雷 射加工，之後施以鍍敷以形成構成通孔之導通用孔1 〇 1 a、 1 0 1 b ° 針對導通用孔l〇la，考量共型光罩111與共型光罩112 之位置偏移，將共型光罩1 1 1之直徑設爲25 0 μηι，並將共 型光罩112之直徑設爲50μιη。 此時，如圖3所示，由於積層時會產生位置偏移，因 此共型光罩111與共型光罩112之中心位置不會一致。由於 會產生最大約1〇〇 μιη左右之位置偏移，因此難以進行導通 用孔1 0 1 a下側之孔的穩定雷射加工。 其次，於具有導通用孔1 〇 1 a、1 0 1 b之多層電路基材 ，進行25〜30μιη左右之電鍍，形成藉由導通用孔101a所 製得之階狀通孔1 〇2a、及藉由導通用孔1 0 1 b所製得通孔 102b，並使用此等以取得層間導通。 此時，如以上所述，由於共型光罩1 1 1與共型光罩1 1 2 之中心位置會產生最大約1〇〇 μιη左右之位置偏移，因此對 導通用孔1 〇 1 a下側之孔的鍍敷周圍會變得不穩定。 因此，容易產生鍍敷孔隙等1 〇3之不良，由於經鍍敷 -6 - 200847886 所得到之階狀通孔構造上呈不對稱，因此在溫度循環測試 等於階狀通孔1 02a所產生之熱應力會局部變大，而亦成 爲層間連接可靠性降低之原因。 由於該等問題，因此期望出現一種方法，其可廉價且 穩定製造具有能高密度構裝之纜線部的多層印刷配線板的 〇 本發明係考量到上述各點所構成，目的在於提供一種 可廉價且穩定製造多層印刷配線板之方法，該配線板係在 層間連接部包含階狀通孔構造之多層印刷配線板中，將層 間連接用之階狀通孔之上孔與下孔的中心配置於大致相同 之位置。 爲達成上述目的，本申請案提供以下各發明。 根據第1發明，可提供一種多層印刷配線板之製造方 法，其係包含：a)準備於由樹脂膜構成之絕緣底材上至少 具有1層導電層之內層核心基板的步驟；b)透過接著材料 ，將以至少於一面具有導電層之貼銅疊層板構成之外層增 建層，積層於前述內層核心基板的步驟；c)在積層前或後 ，在位於前述貼銅疊層板之導電層之導通用孔之形成部位 的銅箔形成開□，以形成積層電路基材的步驟；d)對前述 積層電路基材，形成階狀通孔用之導通用孔的步驟；以及 e)對前述導通用孔進行導電化處理，並藉由電鍍形成包含 前述階狀通孔之層間連接的步驟，其特徵爲：形成前述導 通用孔之步驟d)，係對前述積層電路基材，於前述外層 側之導通用孔之形成部位，形成與前述階狀通孔之下孔徑 200847886 大致相等直徑之銅箔的開口；對前述銅箔之開口的大致中 心，以與前述階狀通孔之上孔徑大致相等之束徑’照射可 將銅除去之雷射光，以於前述外層增建層之銅箔、層間絕 緣樹脂、及前述接著材料形成穿孔；進一步於前述內層核 心基板之前述雷射光之照射面側的導電層，藉由不使用穿 孔用銅箔之開口的直接加工照射前述雷射光’以於前述外 層側之導通用孔的形成部位，形成與前述階狀通孔之下孔 徑大致相等直徑的貫通孔。 又，第2發明可提供一種印刷配線板’其係將外層增 建層積層於內層核心基板之構造，並將前述外層增建層與 前述內層核心基板之層間連接，藉由進行愈外層側則導通 用孔之直徑愈大之3層以上之配線層之層間連接的階狀通 孔、及僅進行最外層與其下1層之配線層之層間連接的盲 孔來進行，其特徵爲：相對於前述階狀通孔之前述內層核 心基板之承墊的導體厚，係較前述盲孔之承墊的導體厚薄 [用以解決課題之手段] [發明效果] 根據此等特徵，本發明可發揮以下之效果。 本發明之具有纜線部之多層印刷配線板，藉由將連接· 3層配線層之階狀通孔之承墊的銅厚，設成較僅進行最外 層與其下1層之配線層之層間連接之盲孔之承墊的銅厚薄 ，在形成階狀通孔時，由於可僅形成最外層共型光罩，並 -8- 200847886 於其中心藉由直接雷射加工適當形成階狀通孔之下孔，因 此可謀求提升良率或降低用以確保可靠性所須之鍍敷厚度 〇 其結果，根據本發明即可提供可廉價且穩定製造多層 印刷配線板之方法，該配線板係以習知方法所難以製造， 在層間連接部包含階狀通孔構造之多層印刷配線板中，將 階狀通孔之上孔與下孔的中心配置於大致相同之位置。 【實施方式】 以下，參照所附圖式說明本發明之實施例。 實施例1 圖1係表示本發明之多層印刷配線板之製造方法的截 面步驟圖。該多層印刷配線板係於層間連接部包含階狀通 孔構造，並具有纜線部之4層型多層多層印刷配線板。 首先，如圖1A(1)所示，準備於聚醯亞胺等可撓性絕 緣底材1(此處爲厚度25 μπα之聚醯亞胺）之兩面，具有厚度 7 μιη之銅箔2及3的雙面貼銅疊層板4，並於該雙面貼銅疊 層板4以NC鑽孔機等形成導通用孔5。此時之銅箔2及3係 以彎曲性優異之輥軋銅箔或特殊電解銅箔較佳。 之後，進行導電化處理，以不在纜線等配線圖案上施 以鍍敷而僅在位於內壁部分進行選擇性電鍍的方式，形成 局部鍍敷用光阻層6。 此時，亦包含考量到曝光之位置偏移、基板之尺寸偏 -9- 200847886 差、NC鑽孔機之加工位置偏移等尺寸的貫通孔焊墊，在 位於導通用孔5之內壁及與增建層之層間連接用孔之承墊 的部分，進行選擇性電鍍，以形成光阻層6。然而，由於 對增建後以雷射貫通之焊墊不留下電鍍，因此亦在與此相 當之部位形成局部鍍敷用光阻層6。 接著，如圖1A(2)所示，對導通用孔5及位於上述承墊 之部分8，進行1 Ομηι左右之電鍍，以取得層間導通。以至 此之步驟形成貫通孔7。又，對於位於上述承墊之部分8亦 賦予鍍敷厚度。 接著，如圖1Α(3)所示，形成用以藉由感光蝕刻加工 方法來形成兩面之電路圖案的光阻層。使用光阻層並藉由 感光蝕刻加工方法以形成電路圖案9及焊墊10a、10b後， 再將光阻層剝離。以至此之步驟，製得構成多層印刷配線 板之核心基板的雙面核心基板1 1。 該實施例1中，雖使用貫通孔型雙面核心基板，但亦 可使用通孔型雙面核心基板。又，該實施例1中，先在導 通用孔內及承墊進行局部鍍敷，之後再進行纜線等電路圖 案之形成，但亦可先進行導通用孔之開孔以形成纜線等電 路圖案，之後再藉由部鍍敷在導通用孔及承墊上施以鍍敷 〇 此後，對雙面核心基板11之銅表面進行粗化處理’以 提升後續覆蓋層形成時之密合性，並在增建後實施雷射加 工時穩定提升雷射光之吸收。 此處係使用曰本MacDermid公司之MultiBondl50。 -10- 200847886 已確認在處理前後二氧化碳氣體雷射光（波長：約 之吸收由約2 0 %提升至約3 0 %。又’藉由該粗化處 箔之厚度約變薄1 μιη。 此後，如圖1Α(4)所示，準備例如在12Km厚之 胺膜12上具有厚度爲2μιη之丙烯酸/環氧樹脂等接 13的覆蓋層14，並以真空壓合、層壓等將該覆蓋層 於雙面核心基板1 1之兩面。以至此之步驟’製得附 層之雙面核心基板1 5。 其次，如圖1 Β (5 )所示，準備於聚醯亞胺等可 緣底材16(此處爲厚度25μηι之聚醯亞胺）之一面， 度7μιη之銅箔17a的單面貼銅疊層板18a，再將單 疊層板1 8 a脫模，並於該單面貼銅疊層板1 8 a之銅耗 形成用以形成雷射加工時之共型光罩的光阻層（未圖 藉由使用該光阻層之感光蝕刻加工方法，形成 工時之共型光罩1 7 b、1 7 c後，再將光阻層剝離。 預先將接著材料1 9脫模，以進行對準。該接著 係用以將增建層1 8b增建於附有覆蓋層之雙面核心 。接著材料1 9，係以低流量型預浸體或黏結片等流 者較佳。此處，由於無須塡充導體層，因此接著材 厚度可選擇15 μιη左右或更薄者。 透過接著材料19，以真空壓合等來積層增建層 附有覆蓋層之雙面核心基板1 5。以至此之步驟，製 電路基材2 0。此外，此後對多層電路基材2 0之增_ 的銅箔表面進行粗化處理，以穩定提升增建後實施 9.8 μιη) 理，銅 聚醯亞 著材料 14黏貼 有覆蓋 撓性絕 具有厚 面貼銅 | 1 7a， 示）。 雷射加 材料1 9 基板15 出較少 料19之 18b與 得多層 g 層 1 8 b 雷射加 -11 - 200847886 工時雷射光之吸收。該粗化處理之內容、效果係如先前所 述。 此外，於該銅箔表面進行粗化處理之步驟順序，有以 下3種形態：（a)於單面貼銅疊層板首先進行粗化處理，以 形成共型光罩，再積層於雙面核心基板、（b)形成共型光 罩，其次進行粗化處理，再積層於雙面核心基板、（c)形 成共型光罩，積層於雙面核心基板後，再進行粗化處理， 實施例1係依（c)之步驟順序進行。 此原因在於，若如上述（a)、（b)般在積層前進行粗化 處理時，除了會因積層之熱或壓力等經歷造成粗化面之形 狀或色調等與雷射光吸收相關之表面狀態改變之外，在 (a)中粗化處理後，藉由感光蝕刻加工方法形成共型光罩 時，蝕刻光阻與銅之密合性亦會提升至所須程度以上，導 致難以在共型光罩形成步驟將蝕刻光阻剝離。 又，另外一種提高共型光罩與內層核心基板之焊墊之 位置精度的方法，有以下所述方法。若將單面貼銅疊層板 積層於雙面核心基板’並直接辨識預先形成於雙面核心基 板之目標標記或形成導通用孔之焊墊’且藉由直接曝光法 形成共型光罩時，便能在位置偏移最小之狀態下形成共型 光罩。之後，再進一步進行前述粗化處理。 其次，如圖1B(6)所示’使用預先所製作之雷射加工 時之共型光罩1 7 b、1 7 c進行雷射加工’以形成階狀通孔 用導通用孔2 1 a、及導通孔用導通用孔2 1 b °由於必須進行 貫通銅箔之加工，因此雷射加工法必須是能將銅除去之準 -12- 200847886 分子雷射、UV-YAG雷射、YAG雷射、二氧化碳氣體雷射 等之加工。本實施例中，係使用加工速度快速且生產性優 異之二氧化碳氣體雷射。 共型光罩1 7b之直徑，係以大致等於所形成之階狀通 孔下側之孔的直徑，共型光罩1 7 c之直徑，係以大致等於 所形成之通孔的直徑的方式分別形成。對此進行雷射加工 ，對形成階狀通孔之共型光罩1 7 b，係以影像處理之方法 等瞄準共型光罩1 7b之中心，照射與階狀通孔之上孔徑大 致相等之束徑的雷射束。藉此，如圖1 B所示，以與共型 光罩17b直徑大致相等之直徑，此處係以200 μιη束徑照射 ，藉此首先除去至焊墊1 〇a爲止之樹脂。 此外，如圖1B所示，在導通用孔21a、21c與導通用 孔2 1 b係配置於相對向之位置的情況下，以考量不貫通焊 墊l〇b，先形成包含貫通加工之導通用孔21a、21c，之後 再形成導通用孔2 1 b較佳。 因此，圖1 B中，對圖中上側之導通用孔2 1 a、2 1 c先 進行加工，再對下側之導通用孔2 1 a、2 1 c與導通用孔2 1 b 加工。因此，實施例1中，在導通用孔21a、21c與導通用 孔2 1 b係相對向之情況下’若將導通用孔2 1 a、2 1 c設計成 全部位於上側，則可首先從上側之所有導通用孔進行雷射 加工，其次再對下側之所有導通用孔進行雷射加工’效率 最佳。 其次，如圖1C(7)所示，對形成階狀通孔之共型光罩 17b，進一步以200μπι束徑照射雷射’將共型光罩17b之 -13- 200847886 銅箔貫通成200 μηι之直徑，並亦除去其下之樹脂。 此時，如圖1Β(6)所示般，共型光罩17b延長線上之 樹脂亦被除去，焊墊1 〇 a係呈雷射束可選擇性照射於焊墊 1 〇a之銅箔上的狀態。其結果，焊墊1 〇a亦在共型光罩1 7b 延長線上之位置貫通成與共型光罩17b之直徑大致相等大 小0 此時，最後之1、2次照射係以影像處理之方法等在瞄 準階狀通孔中心下，以既定孔徑等將束徑會聚至1 ΟΟμηι以 進行加工，藉此即可使導通用孔2 1 a之下側孔2 1 c之形狀 形成爲更好之形狀。 針對所形成之導通用孔2 1 a的形狀加以整理時，導通 用孔2 1 a之上側孔之直徑爲2 0 0 μηι，導通用孔2 1 a之下側 孔21c之直徑係10 0 μηι之孔徑，已穩定形成在焊墊l〇a上 之導通用孔2 1 a上側的大致中心。此外，導通用孔2 1 b係 藉由不產生貫通之共型雷射加工所形成。 圖1B(6)至圖1C(7)係表示一系列雷射加工之一例。此 時，使用 ML605 GTXIII-5100U2(三菱電機公司製）作爲二 氧化碳氣體雷射加工機，藉由影像處理或讀取基板上複數 點之目標標記，進一步個別讀取多層電路基材2 0之尺寸伸 縮，或加以修正等以進行與共型光罩1 7 b中心之對準。 接著’首先藉由束徑2〇〇μιη、脈衝寬度15psec、15mJ 、3次照射進行加工，再以既定孔徑等將束徑會聚至 ΙΟΟμιη，進一步施加脈衝寬度15pSec、10mj、1次照射， 藉此將共型光罩1 7b之銅箔開口成200 μηι之直徑。接著， -14- 200847886 已形成銅厚較薄並呈二氧化碳氣體雷射光吸收良好之表面 狀態的焊墊l〇a，係以ΙΟΟμηι直徑貫通，並以其他鍍敷墊 厚之焊墊1 Ob，即使是呈二氧化碳氣體雷射光吸收良好之 表面狀態，亦不貫通而形成導通用孔2 1 a。 爲了以穩定之直徑貫通共型光罩17b及焊墊10a之銅 箔的既定部位，必須是雷射光中心爲能量密度較高且具有 高斯分布等雷射束剖面的雷射光學系統。 共型光罩17b及焊墊10a之銅厚度，已確認只要在 ΙΟμιη以下，即使是上述雷射加工條件之±30%的能量，亦 能以良好再現性貫通。若在5 μιη以下之厚度時，因上述粗 化步驟、及此後鍍敷前處理之蝕刻等，造成本應留下之焊 墊的銅會有局部消失之情況，因此銅厚以5〜1 0 μιη較佳。 焊墊1 0 b之銅厚度，藉由預先增加位於下側孔2 1 c之 雷射照射面之相反面之焊墊1 〇b的銅厚度，即可獲得對焊 墊l〇b之貫通的裕度。具體而言，已確認只要在14μιη以 上，貫通所須之雷射能量會在3倍以上，已具有充分之裕 度。因此，以14μιη以上之銅厚較佳。 再著，藉由電鍍進行用以取得層間連接的去膠渣處理 、導電化處理。然而，要預先除去導通用孔2 1 a下側孔 2 1 c周緣之焊墊1 0a的銅箔。由於有時該銅箔會熔化而在 後續之鍍敷步驟中成爲產生鍍敷孔隙等不良之原因，因此 在去膠渣處理步驟中，以過硫酸銨水溶液等鈾刻液進行 2 μιη左右鈾刻來除去。 如圖1C所示，在將導通用孔21a、21c與導通用孔21b -15- 200847886 配置成相對向位置的情況下，雖從焊墊1 〇b之上下面兩側 進行鈾刻，但如以上所述，由於已使焊墊1 Ob之銅厚度增 厚，因此在此触刻步驟或後續鍍敷前處理步驟等亦不會發 生貫通。 其次，如圖ic(8)所示，對具有導通用孔21a、21b之 多層電路基材22進行10〜15μπι左右之電鍍，形成得自導 通用孔21a之階狀通孔23a、及得自導通用孔21b之通孔 23b，以取得層間導通。由於在階狀通孔23a之上孔及下 孔的中心不會產生位置偏移，因此對導通用孔之下側孔周 圍的鍍敷即爲穩定。 其結果，由於不易產生鍍敷孔隙等不良，以鍍敷所製 得之階狀通孔會呈對稱構造，在溫度循環測試等於階狀通 孔23a所產生之熱應力會均勻分散，因此可提升層間連接 之可靠性。藉此，如以上所述電解厚度以1 〇〜1 5 μπι左右 便可確保良好層間連接之可靠性。 以至此之步驟，製得完成層間導通之多層電路基材24 。又，在須要有插入零件等構裝用貫通孔之情況下，在形 成導通用孔時，可以NC鑽孔機等形成貫通孔，並在進行 上述通孔之電鍍時，同時形成貫通孔。 其次，如圖1D(9)所示，藉由通常之感光蝕刻加工方 法，形成外層電路圖案2 5。此時，若有析出於核心基板1 5 之覆蓋膜1 2上的鍍敷層，則亦將其除去。 此後，視須要對基板表面實施鍍焊料、鍍鎳、鍍金等 表面處理，並進行光敏抗焊劑之形成及外形加工，藉此製 -16- 200847886 得內層具有纜線部之4層型多層印刷配線板26。 高密度構裝基板所要求之圖案形成能力，若以構裝 0.5 m m間距C S P之焊墊的大小爲3 0 0 μ m時，爲了使1條圖 案穿過焊墊間，則必須形成線/空間二50μιη/50μΓη、間距 爲ΙΟΟμιη之構造。 然而，如以上所述，由於若在7μηι厚之銅箔上進行厚 度1 0〜1 5 μηι左右之電鍍時，外層總導體厚會變成1 7〜 2 2 μ m，充分能以良好良率形成間距爲1 0 〇 μ m之微細圖案 ，因此可滿足高密度構裝之要求。 又，由於纜線係配置於第2層，因此爲了以最短距離 連接零件構裝部，可將連接第1層與第2層之通孔配置成窄 間距，且第2層配線必須微細。 通孔之配置，由於通孔23a、23b可形成爲通孔直徑 在200μιη以下，因此可配置成間距0.4mm以下。由於本發 明之具有纜線部之多層印刷配線板的層間連接構造，係採 用通孔直徑爲200μιη以下之通孔23a，因此對高密度化係 有利之構造。 圖2 A、B係表示本發明之6層型多層印刷配線板之製 造方法的截面步驟圖。首先，藉由與圖1A(1)〜（4)相同方 法，準備在導通用孔內及承墊已進行局部鍍敷墊厚之附有 覆蓋層的雙面核心基板1 5。 其次，如圖2 A (1 )所示，準備於聚醯亞胺等可撓性絕 緣底材46(此處爲厚度25 μιη之聚醯亞胺）之兩面，具有厚 度7μιη之銅箱47a及48a的雙面貼銅疊層板49a，再將雙面 -17- 200847886 貼銅疊層板49a脫模，並將用以藉由感光蝕刻加工方法對 雙面貼銅疊層板49a形成雷射加工時之共型光罩，及對銅 箔48a形成構成階狀通孔之第2層之焊墊48b與內層配線的 光阻層形成於兩面。 使用該光阻層，藉由感光蝕刻加工方法形成雷射加工 時之共型光罩47b、47c、47d後，再將光阻層剝離。以至 此之步驟，製得多層印刷配線板之增建層49b。 預先將接著材料50脫模，以進行對準。該接著材50料 係用以將增建層49b增建於附有覆蓋層之雙面核心基板15 。接著材料5 0，係以低流量型預浸體或黏結片等流出較少 者較佳。 此處，由於無須塡充導體層，因此接著材料50之厚度 可選擇15 μιη左右或更薄者。透過接著材料50，以真空壓 合等來積層增建層49b與附有覆蓋層之雙面核心基板15。 以至此之步驟，製得多層電路基材2 1。再者，此後對多層 電路基材51之增建層49b的銅箔表面進行粗化處理，以穩 定提升增建後實施雷射加工時雷射光之吸收。該粗化處理 之內容、效果係如先前所述。 又，另外一種提高共型光罩與內層核心基板之焊墊之 位置精度的方法，有以下所述方法。若將單面貼銅疊層板 積層於雙面核心基板，直接辨識預先形成於雙面核心基板 之目標標記或形成導通用孔之焊墊，並藉由直接曝光法形 成共型光罩時，便能在位置偏移最小之狀態下形成共型光 罩。此後，進一步進行前述粗化處理。 -18- 200847886 其次，如圖2A(2)所示’使用預先所製作之雷射加工 時之共型光罩47a、17c、47d進行雷射加工，以形成階狀 通孔用導通用孔52a、不與第2層導體層取得導通而直接對 第3層進行電氣連接之跨越通孔用導通用孔52b、及通孔用 導通用孔52d。由於必須進行銅箔之貫通加工，因此雷射 加工法必須是耢由雷射照射㊆將銅除去之準分子雷射、 UV-YAG雷射、YAG雷射、二氧化碳氣體雷射等之力日工。 本實施例中，係使用加工速度快速且生產性優異之二氧化 碳氣體雷射。 共型光罩47b之直徑係以大致等於所形成之階狀通孔 下側之孔的直徑，共型光罩47c、4 7d之直徑係以大致等 於所形成之跨越通孔及通孔的直徑的方式分別形成。 對此進行雷射加工，對形成階狀通孔之共型光罩47b ，以影像處理之方法等瞄準共型光罩1 7b之中心，並照射 與階狀通孔之上孔徑大致相等之束徑的雷射束。如圖2A 所示，藉由以與共型光罩47b直徑大致相等之直徑，此處 係以200μιη束徑照射，首先除去至焊墊48b爲止之樹脂。 其次，如圖2B (3)所示，對形成階狀通孔之共型光罩 47b，進一步以200 μιη束徑照射雷射，將共型光罩47b之 銅箔貫通成200 μιη之直徑，並亦除去其下之樹脂。此時， 如圖2Α(2)所示般，共型光罩47b延長線上之樹脂亦被除 去，而呈雷射束可選擇性照射於焊墊48b之銅箔上的狀態 。因此，焊墊48b亦在共型光罩47b之延長線上之位置， 以與共型光罩47b之直徑大致相等大小貫通而形成通孔。 -19- 200847886 此時，最後之1、2次照射係在以影像處理之方法等來 瞄準階狀通孔中心下，以既定孔徑等將束徑會聚至1 ΟΟμιη 以進行加工，藉此即可使導通用孔52a之下側孔52d之形 狀形成爲更好之形狀。 針對所形成之導通用孔52a的形狀加以整理時，導通 用孔52a之上側孔之直徑爲200μιη，導通用孔52a之下側 孔5 2d之直徑，係100 μιη之孔徑且穩定形成在焊墊48b之 導通用孔52a上側的大致中心。此外，導通用孔52b及52c 係藉由不產生貫通之共型雷射加工所形成。 圖2 A(2)及圖2B (3)之一系列雷射加工之條件例，係如 以下方式進行。使用ML605 GTXIII-5100U2(三菱電機公司 製）作爲二氧化碳氣體雷射加工機，藉由影像處理方法或 讀取基板上複數點之目標標記，或進一步個別讀取多層電 路基材5 1之尺寸伸縮而加以修正等，以對準於共型光罩 4 7 b之中心。200847886 IX. Description of the Invention The present invention relates to a method for manufacturing a multi-layer printed wiring board and a structure of a wiring board, and more particularly to a multilayer flexible structure including a stepped through-hole structure at an interlayer connection portion. Manufacturing method of printed wiring board and structure of wiring board [Prior Art] In recent years, the miniaturization and high functionality of electronic equipment, especially mobile phones, have been extremely remarkable, and the components mounted on the multilayer flexible printed wiring board have followed Replaced with CSP (Chip Size Package), with the evolution of high density and high functionality without increasing substrate size. Therefore, in order to realize a high-density package, an additional-type multilayer printed wiring board having a double-sided or multi-layer flexible printed wiring board as a core substrate and having an additional layer of about 1 to 2 layers on both sides or on one side has also been used. Gradually practical. There is no need to add a step to perform a high-density interlayer connection. In Patent Document 1, a method of combining a segment-shaped through hole and a stepped through hole has been proposed, and the layer connection between the layers can be performed in a single layer. At the same time, the positional offset is considered, so that the diameter of the metal mask and the conformal mask for laser processing is gradually reduced toward the inner layer, and the conductive hole is formed by laser processing. And obtaining an interlayer connection by plating or the like. However, there are several problems in forming the stepped through holes. First, as described in -4-200847886, it is necessary to consider the positional shift to make the shape of the common-type mask on the outer layer side large, and it may not necessarily be a high-density interlayer connection due to the positional accuracy of the laminate or the like. Moreover, in the case where the centers of the common-type masks of the respective layers are not identical, the common-type mask on the outer layer side becomes like an eaves, and becomes a bad cause of laser processing on the inner layer side, or is performed after forming a general-purpose hole. When plating, it causes instability around the plating. Therefore, it is easy to cause defects such as plating pores, and the stepped through holes formed by the plating may have an asymmetrical structure, and the thermal stress generated by the temperature cycle test equal to the stepped through holes may locally become larger, and become The reason for the reduced reliability of the interlayer connection. For this reason, in order to obtain the reliability of the through hole, it is necessary to increase the plating thickness, but if the plating thickness is increased, the thickness of the conductor layer is also thick, and as a result, it is difficult to form a fine circuit. In order to secure the connection reliability for electrically connecting the vias of the build-up layer and the inner layer to the double-sided core substrate, the plating thickness of the via hole wall of the build-up layer must also be increased. Therefore, it is difficult to form a fine circuit, and it is not possible to satisfy the requirements of a high-density package. Therefore, a method of increasing the number of layers to compensate for the formation of the fine circuit has been proposed, and the method of the second paragraph is further developed. [Patent Document 1] Japanese Patent No. 2 5 6 2 3 3 3 [Patent Document 2] JP-A-2001-177248 SUMMARY OF INVENTION [Problems to be Solved by the Invention] However, this method is used to produce 2 When the multi-layer multi-layer printing of the 200847886 wiring board is repeated, the layers are successively stacked, so that the steps become complicated as the number of layers increases, resulting in a problem of a decrease in yield. The above problem is explained by FIG. As shown in Fig. 3, when the build-up layer 122 is combined with the inner core substrate 121 to constitute the multilayer printed substrate 1 24 having the cable portion 12 3, the following problems occur. Laser processing is performed using a common-type photomask 1 1 1 for laser processing in advance and a common-type photomask 1 1 2 for laser processing formed on the inner core double-sided core substrate 1 2 1 , followed by plating Applying to form a common hole 1 、 1 a, 1 0 1 b ° constituting the through hole, for the common hole l 〇 la, considering the positional deviation of the common reticle 111 and the common reticle 112, the common mask The diameter of 1 1 1 is set to 25 0 μηι, and the diameter of the common mask 112 is set to 50 μm. At this time, as shown in Fig. 3, since the positional shift occurs during lamination, the center position of the common-type mask 111 and the common-type mask 112 does not match. Since a positional shift of up to about 1 μm is generated, it is difficult to perform stable laser processing of the hole on the lower side of the hole 1 0 1 a. Next, in a multilayer circuit substrate having a conductive hole 1 〇1 a, 1 0 1 b, plating is performed at about 25 to 30 μm to form a stepped through hole 1 〇 2a made by the conductive hole 101a, and The via hole 102b is formed by guiding the general-purpose hole 1 0 1 b, and is used to obtain interlayer conduction. At this time, as described above, since the center position of the common mask 1 1 1 and the common mask 1 1 2 generates a positional shift of up to about 1 μm, the common hole 1 〇 1 a The plating around the hole on the lower side becomes unstable. Therefore, it is easy to cause a defect of 1 〇3 such as plating porosity, and since the stepped via hole obtained by plating -6 - 200847886 is structurally asymmetrical, the temperature cycle test is equal to that produced by the stepped via hole 102a. The thermal stress locally becomes large, which also becomes a cause of a decrease in the reliability of the interlayer connection. Due to such problems, it is desirable to have a method for inexpensively and stably manufacturing a multilayer printed wiring board having a cable portion capable of high-density construction. The present invention has been made in view of the above points, and aims to provide a A method for producing a multilayer printed wiring board in an inexpensive and stable manner, wherein the wiring board is disposed in a multilayer printed wiring board having a stepped via structure in an interlayer connection portion, and a center of the upper and lower holes of the stepped through hole for interlayer connection In roughly the same position. In order to achieve the above object, the present application provides the following inventions. According to the first aspect of the invention, there is provided a method of manufacturing a multilayer printed wiring board comprising: a) a step of preparing an inner core substrate having at least one conductive layer on an insulating substrate made of a resin film; b) Next, the material is a step of forming an outer layer build-up layer with a copper-clad laminate having a conductive layer on at least one side, and laminating on the inner core substrate; c) before or after the build-up, on the copper-clad laminate a step of forming a copper foil on a portion where the conductive hole of the conductive layer is formed to form a laminated circuit substrate; d) a step of forming a conductive hole for the stepped via hole; and a step of conducting a conductive treatment on the conductive via hole and forming an interlayer connection including the stepped via hole by electroplating, wherein the step d) of forming the conductive via hole is performed on the laminated circuit substrate Forming an opening of a copper foil having a diameter substantially equal to a diameter of the bottom hole of the stepped through hole 200847886 at a portion where the conductive hole of the outer layer side is formed; and substantially the center of the opening of the copper foil a beam diameter that is substantially equal to the aperture above the through-holes illuminates the laser light that removes copper to form a perforation in the copper foil of the outer layer build-up layer, the interlayer insulating resin, and the bonding material; further to the inner core substrate The conductive layer on the irradiation surface side of the laser light is irradiated with the laser light without direct processing of the opening of the copper foil for perforation to form a portion of the conductive hole formed on the outer layer side, and the stepped through hole is formed. A through hole having a substantially equal diameter in the lower diameter. Further, the second invention can provide a printed wiring board having a structure in which an outer layer is additionally laminated on an inner core substrate, and the outer layer additional layer and the inner core substrate are connected to each other by the outer layer. The side is formed by a stepped through hole connecting the interlayers of the wiring layers of three or more layers having a larger diameter, and a blind hole connecting only the layers of the outermost layer and the wiring layer of the lower one of the layers, and is characterized by: The conductor thickness of the pad of the inner core substrate of the stepped through hole is thicker than the conductor of the pad of the blind hole [means for solving the problem] [effect of the invention] According to these features, the present invention The following effects can be achieved. In the multilayer printed wiring board having the cable portion of the present invention, the copper thickness of the spacer of the stepped via hole connecting the three wiring layers is set to be more than the interlayer between the outermost layer and the lower wiring layer. The thickness of the copper of the padding of the connected blind hole is such that only the outermost conformal mask can be formed when the stepped through hole is formed, and the stepped through hole is appropriately formed by direct laser processing at the center thereof at -8-200847886 The lower hole can be used to improve the yield or reduce the plating thickness required to ensure reliability. As a result, according to the present invention, it is possible to provide a method for inexpensively and stably manufacturing a multilayer printed wiring board. In the multilayer printed wiring board in which the interlayer connection portion includes the stepped via structure, the center of the stepped via hole and the center of the lower hole are disposed at substantially the same position. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. [First Embodiment] Fig. 1 is a cross-sectional view showing a method of manufacturing a multilayer printed wiring board of the present invention. This multilayer printed wiring board is a four-layer type multilayer multilayer printed wiring board having a stepped through-hole structure in the interlayer connection portion and having a cable portion. First, as shown in FIG. 1A (1), the copper foil 2 having a thickness of 7 μm is prepared on both sides of a flexible insulating substrate 1 (here, a polyimide having a thickness of 25 μπα) such as polyimide. The double-sided copper-clad laminate 4 of 3 is formed, and the common-purpose hole 5 is formed in the double-sided copper-clad laminate 4 by an NC drill or the like. In this case, the copper foils 2 and 3 are preferably rolled copper foil or special electrolytic copper foil which is excellent in flexibility. Thereafter, the conductive treatment is performed, and the partial plating resist layer 6 is formed so as not to be plated on the wiring pattern such as a cable, and selective plating is performed only on the inner wall portion. At this time, it also includes a through-hole pad which is sized to the positional deviation of the exposure, the size of the substrate -9-200847886, and the processing position offset of the NC boring machine, and is located on the inner wall of the common hole 5 and A portion of the pad which is connected to the interlayer of the build-up layer is selectively plated to form the photoresist layer 6. However, since the pad which is laser-penetrated after the build-up is not left with plating, a partial plating resist layer 6 is formed at a portion corresponding thereto. Next, as shown in Fig. 1A (2), the conductive via 5 and the portion 8 located on the spacer are plated at about 1 Ο μηι to obtain interlayer conduction. The step thus formed forms the through hole 7. Further, the plating thickness is also applied to the portion 8 located on the ferrule. Next, as shown in Fig. 1 (3), a photoresist layer for forming a circuit pattern on both sides by a photolithography process is formed. After the circuit pattern 9 and the pads 10a and 10b are formed by a photosensitive etching process using a photoresist layer, the photoresist layer is peeled off. Thus, the double-sided core substrate 11 constituting the core substrate of the multilayer printed wiring board is obtained. In the first embodiment, a through-hole type double-sided core substrate is used, but a through-hole type double-sided core substrate can also be used. Further, in the first embodiment, the partial plating is performed in the conductive hole and the spacer first, and then the circuit pattern such as the cable is formed. However, the opening of the common hole may be first formed to form a circuit such as a cable. The pattern is then plated on the conductive holes and the shims by partial plating, and then the copper surface of the double-sided core substrate 11 is roughened to improve the adhesion of the subsequent cover layer, and Stabilize the absorption of laser light when performing laser processing after the addition. The MultiBondl50 from MacDermid is used here. -10- 200847886 It has been confirmed that carbon dioxide gas laser light before and after treatment (wavelength: about absorption increased from about 20% to about 30%. In turn, the thickness of the foil by the roughening is about 1 μιη thinner. Thereafter, As shown in Fig. 1 (4), for example, a cover layer 14 having an acrylic/epoxy resin or the like having a thickness of 2 μm on a 12 Km thick amine film 12 is prepared, and the cover layer is vacuum-bonded, laminated, or the like. On both sides of the double-sided core substrate 1 1 , the double-sided core substrate 15 of the attached layer is prepared in the following step. Next, as shown in FIG. 1 (5), it is prepared for a polyimide substrate such as polyimide. 16 (one is a polyimide of a thickness of 25 μηι), a single-sided copper-clad laminate 18a of a copper foil 17a having a degree of 7 μm, and then demolded the single-layered laminate 18 a, and attached to the single-sided sheet The copper loss of the copper laminate 18 8 a forms a photoresist layer for forming a common mask during laser processing (not shown by the photosensitive etching processing method using the photoresist layer to form a common mode light of working hours) After the cover 1 7 b, 1 7 c, the photoresist layer is peeled off. The subsequent material 19 is demolded in advance for alignment. The adhesion is used to build the layer 1 8b is added to the double-sided core with the cover layer. Then, the material 197 is preferably a low-flow type prepreg or a bonded sheet. Here, since the conductor layer is not required to be filled, the thickness of the subsequent material can be A thickness of about 15 μm or less is selected. The double-sided core substrate 15 with a cover layer is laminated by vacuum bonding or the like through the bonding material 19. The circuit substrate 20 is formed by the step of this. Thereafter, the surface of the copper foil of the multi-layer circuit substrate 20 is coarsened to achieve 9.8 μm η after the stability enhancement and the addition, and the copper poly-ply material 14 is adhered with a flexible cover and has a thick surface copper paste. | 1 7a, shown). Laser plus material 1 9 substrate 15 out of material 19 18b and many layers g layer 1 8 b laser plus -11 - 200847886 working hours laser light absorption. The content and effect of the roughening process are as previously described. In addition, the steps of the roughening treatment on the surface of the copper foil are as follows: (a) The single-sided copper-clad laminate is first roughened to form a common mask, and then laminated on both sides. The core substrate and (b) a common mask are formed, followed by roughening, layering on the double-sided core substrate, (c) forming a common mask, laminating on the double-sided core substrate, and then performing roughening treatment. Example 1 was carried out in the order of steps (c). The reason for this is that when the roughening treatment is performed before the lamination as in the above (a) and (b), the surface associated with the absorption of the laser light such as the shape or color tone of the roughened surface is experienced due to the heat or pressure of the laminate. In addition to the state change, after the roughening treatment in (a), when the common mask is formed by the photosensitive etching processing method, the adhesion between the etching photoresist and the copper is also raised to the required level, resulting in difficulty in common The reticle forming step peels off the etch photoresist. Further, another method of improving the positional accuracy of the pads of the common type photomask and the inner core substrate has the following method. If a single-sided copper-clad laminate is laminated on the double-sided core substrate 'and directly identifies a target mark formed on the double-sided core substrate or a pad forming a common hole' and forms a common mask by direct exposure The common mask can be formed in a state where the positional deviation is the smallest. Thereafter, the above roughening treatment is further performed. Next, as shown in FIG. 1B (6), 'the laser processing is performed using the common-type masks 1 7 b and 1 7 c in the laser processing prepared in advance to form the conductive vias 2 1 a for the stepped through holes. And the general purpose hole for the via hole 2 1 b ° Since the copper foil must be processed, the laser processing method must be a quasi--12-200847886 molecular laser, UV-YAG laser, YAG mine that can remove copper. Processing of shots, carbon dioxide gas lasers, etc. In this embodiment, a carbon dioxide gas laser having a fast processing speed and excellent productivity is used. The diameter of the common mask 17b is substantially equal to the diameter of the hole on the lower side of the stepped through hole formed, and the diameter of the common mask 17c is substantially equal to the diameter of the through hole formed. Formed separately. Laser processing is performed on this, and the common-type mask 17b, which forms the stepped through-hole, is aimed at the center of the common-type mask 17b by image processing, and the illumination is substantially equal to the aperture above the stepped through-hole. The beam of the beam of the beam. Thereby, as shown in Fig. 1B, the resin having a diameter substantially equal to the diameter of the common-type mask 17b is irradiated with a beam diameter of 200 μm, whereby the resin to the pad 1 〇a is first removed. Further, as shown in FIG. 1B, when the general-purpose holes 21a and 21c and the common-purpose hole 2 1 b are disposed at positions facing each other, it is considered that the through-holes are not penetrated, and the guide including the through-process is formed first. It is preferable to form the common holes 21a, 21c and then to form the common holes 2 1 b. Therefore, in Fig. 1B, the upper common holes 2 1 a, 2 1 c of the upper side are processed first, and the lower common holes 2 1 a, 2 1 c and the common holes 2 1 b are processed. Therefore, in the first embodiment, when the common holes 21a, 21c and the common holes 2 1 b are opposed to each other, if the common holes 2 1 a, 2 1 c are designed to be all located on the upper side, the first All the common holes on the upper side are laser processed, and then the laser processing is performed on all the common holes on the lower side. Next, as shown in FIG. 1C (7), the common-type mask 17b forming the stepped through-hole is further irradiated with a laser beam of 200 μm beam diameter to pass through the common mask 17b-13-200847886 copper foil into 200 μηι. The diameter of the resin is also removed. At this time, as shown in Fig. 1 (6), the resin on the extension line of the common mask 17b is also removed, and the pad 1 〇a is a laser beam which can be selectively irradiated onto the copper foil of the pad 1 〇a. status. As a result, the pad 1 〇a is also penetrated at a position on the extension line of the common mask 17b to be substantially equal to the diameter of the common mask 17b. At this time, the last one or two illuminations are processed by image processing. Waiting at the center of the stepped through hole, the beam diameter is concentrated to 1 ΟΟμηι with a predetermined aperture or the like for processing, thereby forming the shape of the lower side hole 2 1 c of the common hole 2 1 a to be better. shape. When the shape of the formed common hole 2 1 a is arranged, the diameter of the hole on the upper side of the common hole 2 1 a is 2 0 0 μη, and the diameter of the hole 21c below the common hole 2 1 a is 10 0 μηι. The aperture is stably formed at the approximate center of the upper side of the conductive hole 2 1 a on the pad 10a. Further, the common hole 2 1 b is formed by conformal laser processing which does not cause penetration. 1B(6) to 1C(7) show an example of a series of laser processing. In this case, ML605 GTXIII-5100U2 (manufactured by Mitsubishi Electric Corporation) is used as a carbon dioxide gas laser processing machine, and the size of the multilayer circuit substrate 20 is further individually read and reproduced by image processing or reading of a target mark of a plurality of points on the substrate. , or modified or the like to align with the center of the common mask 17b. Then, first, the beam diameter is 2 〇〇μηη, the pulse width is 15 psec, 15 mJ, and 3 times of irradiation, and the beam diameter is concentrated to ΙΟΟμιη with a predetermined aperture or the like, and a pulse width of 15 pSec, 10 mj, and 1 irradiation are further applied. The copper foil of the common mask 17b is opened to a diameter of 200 μm. Then, -14- 200847886 has formed a solder pad l〇a with a thin copper thickness and a surface state of good absorption of carbon dioxide gas, which is penetrated by a diameter of ΙΟΟμηι, and is padded with other padding pads, 1 Ob, even It is a surface state in which the carbon dioxide gas laser light absorbs well, and does not penetrate to form a common hole 2 1 a. In order to penetrate a predetermined portion of the copper foil of the common-type mask 17b and the pad 10a with a stable diameter, it is necessary to have a laser optical system having a laser beam center having a high energy density and a laser beam profile such as a Gaussian distribution. It is confirmed that the thickness of the copper of the common-type mask 17b and the pad 10a can be penetrated with good reproducibility even if it is less than or equal to 30% of the laser processing conditions. If the thickness is less than 5 μηη, due to the above-mentioned roughening step and etching after the pre-plating treatment, the copper of the solder pad which should be left partially disappears, so the copper thickness is 5 to 1 0. Μιη is preferred. The thickness of the copper pad 10b can be obtained by increasing the copper thickness of the pad 1 〇b on the opposite side of the laser irradiation surface of the lower hole 2 1 c in advance. Margin. Specifically, it has been confirmed that as long as the laser energy required to penetrate above 14 μm is more than three times, there is sufficient margin. Therefore, it is preferable to use a copper thickness of 14 μm or more. Further, desmear treatment and conductivity treatment for obtaining interlayer connection are performed by electroplating. However, the copper foil of the pad 10a of the periphery of the lower hole 2 1 c of the common hole 2 1 a is removed in advance. Since the copper foil sometimes melts and becomes a cause of plating voids in the subsequent plating step, in the desmearing treatment step, an uranium engraving solution such as an ammonium persulfate aqueous solution is used to carry out an uranium engraving of about 2 μηη. To remove. As shown in FIG. 1C, in the case where the common holes 21a, 21c and the common holes 21b -15 - 200847886 are disposed in opposite positions, although uranium engraving is performed from both the upper and lower sides of the pad 1 〇b, As described above, since the thickness of the copper of the pad 1 Ob has been increased, the etching step or the subsequent pre-plating treatment step or the like does not occur. Next, as shown in FIG. ic (8), the multilayer circuit substrate 22 having the conductive holes 21a and 21b is plated at about 10 to 15 μm to form a stepped through hole 23a obtained from the conductive common hole 21a, and is obtained from The through hole 23b of the common hole 21b is guided to achieve interlayer conduction. Since the position of the hole and the center of the lower hole is not displaced at the center of the stepped through hole 23a, the plating around the side of the hole below the common hole is stabilized. As a result, since the plating holes and the like are less likely to be generated, the stepped through holes formed by the plating may have a symmetrical structure, and the thermal stress generated by the temperature cycle test equal to the stepped through holes 23a is uniformly dispersed, thereby improving The reliability of the connection between the layers. Thereby, as described above, the electrolytic thickness is about 1 〇 to 1 5 μπι to ensure the reliability of good interlayer connection. Throughout this step, a multilayer circuit substrate 24 that completes interlayer conduction is obtained. Further, when it is necessary to have a through hole for inserting a component or the like, a through hole can be formed by an NC drill or the like when the conductive hole is formed, and a through hole can be simultaneously formed when the through hole is plated. Next, as shown in Fig. 1D (9), the outer layer circuit pattern 25 is formed by a usual photosensitive etching processing method. At this time, if there is a plating layer deposited on the cover film 12 of the core substrate 15, it is also removed. After that, it is necessary to perform surface treatment such as soldering, nickel plating, gold plating, etc. on the surface of the substrate, and to form and shape the photosensitive solder resist, thereby making a 4-layer multi-layer printing having a cable portion in the inner layer. Wiring board 26. The pattern forming capability required for a high-density package substrate is such that if the size of the pad having a 0.5 mm pitch CSP is 300 μm, in order to pass a pattern through the pads, a line/space must be formed. Two 50 μm η / 50 μ Γ η, the pitch is ΙΟΟ μιη structure. However, as described above, when plating is performed on a copper foil having a thickness of 7 μm thick for about 10 to 15 μm, the total thickness of the outer layer becomes 1 7 to 2 2 μm, which is sufficient to form a good yield. The fine pattern with a pitch of 10 μm is suitable for high-density construction. Further, since the cable is disposed on the second layer, in order to connect the component mounting portion at the shortest distance, the through holes connecting the first layer and the second layer can be arranged at a narrow pitch, and the second layer wiring must be fine. Since the through holes 23a and 23b can be formed to have a through hole diameter of 200 μm or less, the through holes 23a and 23b can be arranged at a pitch of 0.4 mm or less. In the interlayer connection structure of the multilayer printed wiring board having the cable portion of the present invention, the through hole 23a having a through hole diameter of 200 μm or less is used, which is advantageous for the high density system. Fig. 2 is a cross-sectional view showing a method of manufacturing a six-layer type multilayer printed wiring board of the present invention. First, in the same manner as in Figs. 1A (1) to (4), a double-sided core substrate 15 having a coating layer having a partial plating thickness in the conductive hole and the spacer is prepared. Next, as shown in Fig. 2 A (1), it is prepared on both sides of a flexible insulating substrate 46 (here, a polyimide having a thickness of 25 μm) such as polyimine, and has a copper box 47a having a thickness of 7 μm and 48a double-sided copper-clad laminate 49a, and then double-sided -17-200847886 copper-clad laminate 49a is demolded, and used to form a laser on the double-sided copper-clad laminate 49a by a photosensitive etching process The common-type photomask at the time of processing, and the photoresist layer 48b which forms the 2nd layer which consists of a stepped via hole in the copper foil 48a, and the photoresist layer of an inner layer wiring are formed in both surfaces. Using the photoresist layer, the common-type masks 47b, 47c, and 47d at the time of laser processing are formed by a photolithography process, and then the photoresist layer is peeled off. In this way, an additional layer 49b of a multi-layer printed wiring board is produced. The adhesive material 50 is previously demolded for alignment. The backing material 50 is used to build the build-up layer 49b to the double-sided core substrate 15 with the cover layer. Next, the material 50 is preferably a low flow type prepreg or a bonded sheet, and the like. Here, since the conductor layer is not required to be filled, the thickness of the material 50 can be selected to be about 15 μm or less. The build-up layer 49b and the double-sided core substrate 15 with the cover layer are laminated by vacuum bonding or the like through the bonding material 50. In this way, a multi-layer circuit substrate 21 is fabricated. Further, thereafter, the surface of the copper foil of the build-up layer 49b of the multilayer circuit substrate 51 is roughened to stably enhance the absorption of the laser light during laser processing after the addition and construction. The content and effect of this roughening process are as previously described. Further, another method of improving the positional accuracy of the pads of the common type photomask and the inner core substrate has the following method. When the single-sided copper-clad laminate is laminated on the double-sided core substrate, the target mark formed on the double-sided core substrate or the pad forming the common hole is directly recognized, and the common mask is formed by the direct exposure method. The common mask can be formed in a state where the positional deviation is the smallest. Thereafter, the aforementioned roughening treatment is further performed. -18- 200847886 Next, as shown in Fig. 2A (2), laser processing is performed using the common-type masks 47a, 17c, and 47d in the laser processing prepared in advance to form the stepped via hole 52a. The conductive via hole 52b for the via hole and the via hole 52d for the via hole are electrically connected to the third layer without directly contacting the second layer conductor layer. Since the copper foil must be processed through the process, the laser processing method must be a laser for excimer laser, UV-YAG laser, YAG laser, carbon dioxide gas laser, etc., which are removed by laser irradiation. . In the present embodiment, a carbon dioxide gas laser which is fast in processing speed and excellent in productivity is used. The diameter of the common type mask 47b is substantially equal to the diameter of the hole on the lower side of the stepped through hole formed, and the diameters of the common masks 47c, 47d are substantially equal to the diameter of the formed through holes and through holes. The way is formed separately. Laser processing is performed on the common-type mask 47b forming the stepped through-hole, aiming at the center of the common-type mask 17b by image processing, and irradiating a beam substantially equal to the aperture above the stepped through-hole. The laser beam of the trail. As shown in Fig. 2A, by a diameter substantially equal to the diameter of the common-type mask 47b, it is irradiated with a beam diameter of 200 μm, and the resin up to the pad 48b is first removed. Next, as shown in FIG. 2B (3), the common-type mask 47b forming the stepped through-hole is further irradiated with a laser beam having a beam diameter of 200 μm, and the copper foil of the common-type mask 47b is penetrated to a diameter of 200 μm. The resin underneath is also removed. At this time, as shown in Fig. 2 (2), the resin on the extension line of the common mask 47b is also removed, and the laser beam is selectively irradiated onto the copper foil of the pad 48b. Therefore, the pad 48b is also formed at a position on the extension line of the common mask 47b so as to penetrate substantially the same size as the diameter of the common mask 47b to form a through hole. -19- 200847886 At this time, the last one or two illuminations are aimed at the center of the stepped through hole by image processing, etc., and the beam diameter is concentrated to 1 ΟΟμιη with a predetermined aperture or the like for processing. The shape of the lower side hole 52d of the guide hole 52a is formed into a better shape. When the shape of the formed common hole 52a is arranged, the diameter of the upper side hole of the common hole 52a is 200 μm, and the diameter of the side hole 5 2d of the common hole 52a is 100 μm of the aperture and is stably formed on the pad. The approximate center of the upper side of the common hole 52a of 48b. Further, the common holes 52b and 52c are formed by conformal laser processing which does not cause penetration. An example of the conditions of laser processing in one of the series of A (2) and Fig. 2B (3) is as follows. Using ML605 GTXIII-5100U2 (manufactured by Mitsubishi Electric Corporation) as a carbon dioxide gas laser processing machine, by image processing method or reading a target mark of a plurality of points on a substrate, or further individually reading the size expansion and contraction of the multilayer circuit substrate 51 Corrected, etc., to align with the center of the common mask 4 7 b.
接著，首先藉由束徑200μιη、脈衝寬度15pSeC、15mJ 、3次照射進行加工，並以既定孔徑等將束徑會聚至 1 0 0 μ m，進一步施加脈衝寬度1 5 μ s e c、1 0 m J、1次照射’ 藉此在共型光罩47b之銅箔形成200 μιη直徑之開口，已形 成銅厚較薄而呈二氧化碳氣體雷射光吸收良好之表面狀態 的焊墊48a，則以1〇〇 μηι直徑貫通，以其他鍍敷墊厚之焊 墊1 〇b，即使是呈二氧化碳氣體雷射光吸收良好之表面狀 態，但亦不貫通而形成導通用孔5 2 a。 爲了以穩定之直徑貫通共型光罩47b及焊墊48a之銅 -20- 200847886 箔的既定部位，必須是雷射光中心爲能量密度較高且具有 高斯分布等雷射束剖面的雷射光學系統。 共型光罩47b及焊墊48a之銅厚度，已確認只要在 ΙΟμιη以下，即使是上述雷射加工條件之±30%的能量，亦 能以良好再現性貫通。若在5 μηι以下之厚度，因上述粗化 步驟、及後續鍍敷前處理之蝕刻等，造成本應留下之焊墊 的銅會有局部消失之情況，因此銅厚以5〜1 Ομιη較佳。 焊墊l〇b之銅厚度，藉由預先增加位於下側孔52c之 雷射照射面之焊墊1 0 b的銅厚度，即可獲得對焊墊1 0 b之 貫通的裕度。具體而言，已確認只要在14 μιη以上，貫通 所須之雷射能量會在3倍以上，已具有充分之裕度。因此 ，以14μπι以上之銅厚較佳。 再者’藉由電鍍進行用以取得層間連接的去膠渣處理 、導電化處理。然而，由於導通用孔5 2 a之下側孔5 2 c周 緣之焊墊4 8 a的銅箔已熔化，而在後續之鍍敷步驟中可能 成爲產生鍍敷孔隙等不良之原因，因此在去膠渣處理步驟 中以過硫酸銨水溶液等鈾刻液進行2 μιη左右鈾刻，以除去 熔化之銅箔。 其次’如圖2Β(4)所示，對具有導通用孔52a、52b、 52d之多層電路基材23進行10〜15μιη左右之電鍍，而形 成得自導通用孔52a之階狀通孔54a、得自導通用孔52b之 跨越通孔54b、及得自導通用孔52d之階狀通孔54(:，以取 得層間導通。 由於階狀通孔5 4 a之上孔及下孔不會產生中心之位置 -21 - 200847886 偏移，因此可對導通用孔之下側孔周圍之鍍敷爲穩定。其 結果，由於不易產生鍍敷孔隙等不良’以鍍敷所製得之階 狀通孔會呈對稱構造，在溫度循環測試等於階狀通孔5 4 a 所產生之熱應力會均勻分散，因此可提升層間連接之可靠 性。藉此，如以上所述，電解厚度以1 〇〜15μη左右便可 確保良好層間連接可靠性。 以至此之步驟，製得完成層間導通之多層電路基材5 5 。又，在須要有插入零件等構裝用貫通孔之情況下，則可 在形成導通用孔時，以NC鑽孔機等形成貫通孔，並在進 行上述通孔電鍍敷時，同時形成貫通孔。 再者，藉由通常之感光蝕刻加工方法，形成外層圖案 5 6。此時，若有析出於核心基板1 5之覆蓋膜1 2上的鍍敷層 時’則亦將其除去。此後，視須要對基板表面實施鍍焊料 、鍍鎳、鍍金等表面處理，並進行光敏抗焊劑層之形成及 外形加工，藉此製得內層具有纜線部之6層型多層印刷配 線板5 7。 【圖式簡單說明】 [圖1 Α]係表示本發明之4層型多層印刷配線板之製造 方法中部分步驟的槪念性截面圖。 [圖1Β]係表示本發明之4層型多層印刷配線板之製造 方法中部分步驟的槪念性截面圖。 [圖1 C]係表示本發明之4層型多層印刷配線板之製造 方法中邰分步驟的槪念性截面圖。 -22- 200847886 [圖1 D ]係表示本發明之4層型多層印刷配線板之製造 方法中部分步驟的槪念性截面圖。 [圖2 A]係表示本發明之6層型多層印刷配線板之製造 方法中部分步驟的槪念性截面圖。 [圖2B]係表示本發明之6層型多層印刷配線板之製造 方法中部分步驟的槪念性截面圖。 [圖3 ]係表示習知增建型多層印刷配線板中與形成導 通孔相關之不良的說明圖。 【主要元件符號說明】 I :可撓性絕緣底材 2，3 :銅箔 4 :雙面貼銅疊層板 5 :導通用孔 6 :局部鍍敷用光阻層 7 :貫通孔 8 :位於承墊之部分 9 :電路圖案 10a， 10b ：焊墊 II :雙面核心基板 1 2 :聚醯亞胺膜 1 3 :接著材料 14 =覆蓋層 1 5 :雙面核心基板 23- 200847886 1 6 :可撓性絕緣底材 17a :銅箔 1 7b，1 7c :共型光罩 18a :單面貼銅疊層板 1 8b :增建層 1 9 :接著材料 2 0 :多層電路基材 2 1a，2 1b :導通用孔 2 1 c :導通用孔2 1 a之下側孔 2 2 :多層電路基材 2 3 a :階狀通孔 2 3 b :通孔 24 :完成層間導通之多層電路基材 2 5 :外層電路圖案 26 : 4層型多層印刷配線板 46 :可撓性絕緣底材 4 7 a :銅箔 47b，47c，47d :共型光罩 4 8 a :銅箔 4 8 b :焊墊 4 9 a :單面貼銅疊層扳 49b :增建層 50 :接著材料 5 1 :多層電路基材 -24- 200847886 52a, 52b :導通用孔 52c :導通用孔52a之下側孔 5 2d :導通用孔 5 3 :多層電路基材 54a, 54b :階狀通孔 5 4 c :通孔 5 5 :完成層間導通之多層電路基材 5 6 :外層電路圖案 57 : 6層型多層印刷配線板 10 1a，10 1b :導通用孔 l〇2a :階狀通孔 1 02b :通孔 103 :鍍敷孔隙等 111, 112:共型光罩 1 2 1 :內層核心基板 1 22 :增建層 1 2 3 :纜線部 124 :多層印刷基板 -25-Next, first, it is processed by a beam diameter of 200 μm, a pulse width of 15 pSeC, 15 mJ, and three times of irradiation, and the beam diameter is concentrated to 100 μm with a predetermined aperture or the like, and a pulse width of 15 μsec and 10 m J is further applied. By the first irradiation, a copper pad having a diameter of 200 μm is formed in the copper foil of the common mask 47b, and a pad 48a having a thin copper thickness and a surface state in which the carbon dioxide gas is absorbed by the laser light is formed. The diameter of μηι is penetrated, and the pad 1 〇b of other plating pads is thick, and even if it is a surface state in which the carbon dioxide gas laser light absorbs well, the conductive hole 5 2 a is not formed. In order to penetrate the predetermined portion of the copper-20-200847886 foil of the common mask 47b and the pad 48a with a stable diameter, it is necessary to have a laser optical system with a laser beam center and a laser beam profile having a high energy density and a Gaussian distribution. . The thickness of the copper of the common-type mask 47b and the pad 48a has been confirmed to be excellent in reproducibility even under ΙΟμηη, even if it is ±30% of the laser processing conditions. If the thickness is less than 5 μηι, the copper of the solder pad which should be left partially disappears due to the above-mentioned roughening step and etching of the subsequent pre-plating treatment, so the copper thickness is 5~1 Ομηη. good. The copper thickness of the pad l〇b can be obtained by increasing the copper thickness of the pad 10b of the laser irradiation surface of the lower hole 52c in advance, thereby obtaining a margin for the penetration of the pad 10b. Specifically, it has been confirmed that as long as it is 14 μmη or more, the required laser energy is more than three times, and it has sufficient margin. Therefore, it is preferable to use a copper thickness of 14 μm or more. Further, the desmear treatment and the electroconductive treatment for obtaining the interlayer connection are performed by electroplating. However, since the copper foil of the pad 48 8 a peripheral edge of the side hole 5 2 c under the common hole 5 2 a has been melted, it may become a cause of poor plating, etc. in the subsequent plating step. In the desmear treatment step, an uranium engraving solution such as an aqueous solution of ammonium persulfate is used to carry out uranium engraving of about 2 μm to remove the molten copper foil. Next, as shown in Fig. 2 (4), the multilayer circuit substrate 23 having the conductive holes 52a, 52b, and 52d is plated to a thickness of about 10 to 15 μm to form a stepped through hole 54a from the conductive hole 52a. The stepped through hole 54b of the conductive common hole 52b and the stepped through hole 54 obtained from the conductive common hole 52d are obtained to obtain interlayer conduction. Since the upper hole and the lower hole of the stepped through hole 5 4 a are not generated The position of the center is -21,087,886 offset, so it is stable to the plating around the side hole below the general-purpose hole. As a result, it is not easy to cause poor plating such as plating, and the stepped through hole is made by plating. It will have a symmetrical structure, and the thermal stress generated by the temperature cycle test equal to the stepped through hole 5 4 a will be uniformly dispersed, thereby improving the reliability of the interlayer connection. Thus, as described above, the electrolytic thickness is 1 〇 15 15 μη. The right and left connection reliability can be ensured. In this way, the multilayer circuit substrate 5 5 that completes the interlayer conduction is obtained. Further, in the case where a through hole for inserting a component or the like is required, the guide can be formed. For the general hole, the through hole is formed by an NC drill or the like. Further, when the through-hole plating is performed, the through holes are simultaneously formed. Further, the outer layer pattern 56 is formed by a usual photosensitive etching processing method. At this time, if the core film 15 is deposited on the cover film 1 2 The plating layer is also removed. Thereafter, the surface of the substrate is subjected to surface treatment such as soldering, nickel plating, gold plating, etc., and the formation and shape processing of the photosensitive solder resist layer are performed, thereby obtaining the inner layer. [Brief Description of the Drawings] [Fig. 1 Α] is a phantom cross-sectional view showing a part of steps in the method of manufacturing a four-layer type multilayer printed wiring board of the present invention. [Fig. 1A] is a phantom cross-sectional view showing a part of steps in a method of manufacturing a four-layer type multilayer printed wiring board of the present invention. [Fig. 1C] shows a method of manufacturing a four-layer type multilayer printed wiring board of the present invention. Fig. 1D is a perspective view showing a part of the steps in the method of manufacturing the 4-layer type multilayer printed wiring board of the present invention. [Fig. 2 A] 6-layer type multilayer printed wiring showing the present invention Fig. 2B is a sacred cross-sectional view showing a part of steps in a method of manufacturing a six-layer type multilayer printed wiring board of the present invention. [Fig. 3] shows a conventional increase. Description of the defects associated with the formation of via holes in the built-in multilayer printed wiring board. [Description of main components] I: Flexible insulating substrate 2, 3: Copper foil 4: Double-sided copper laminated board 5: Guide General hole 6: Photoresist layer 7 for partial plating: Through hole 8: Part 9 of the pad: Circuit pattern 10a, 10b: Pad II: Double-sided core substrate 1 2: Polyimine film 13: Next Material 14 = cover layer 15: double-sided core substrate 23 - 200847886 1 6 : flexible insulating substrate 17a: copper foil 1 7b, 1 7c: common mask 18a: single-sided copper laminated board 1 8b: Additive layer 19: Subsequent material 20: multilayer circuit substrate 2 1a, 2 1b: conductive hole 2 1 c : common hole 2 1 a lower side hole 2 2 : multilayer circuit substrate 2 3 a : order Through hole 2 3 b : through hole 24 : multilayer circuit substrate 25 that completes interlayer conduction: outer circuit pattern 26 : 4-layer type multilayer printed wiring board 46 : flexible insulating bottom 4 7 a : Copper foil 47b, 47c, 47d: Common mask 4 8 a : Copper foil 4 8 b : Solder pad 4 9 a : Single-sided copper laminated plate 49b: Additive layer 50: Next material 5 1 :Multilayer circuit substrate-24- 200847886 52a, 52b: general purpose hole 52c: lower side hole 5b of conductive common hole 52a: common hole 5 3 : multilayer circuit substrate 54a, 54b: stepped through hole 5 4 c : via hole 5 5 : multilayer circuit substrate 5 6 for completing interlayer conduction: outer layer circuit pattern 57 : 6-layer type multilayer printed wiring board 10 1a, 10 1b : general purpose hole l〇2a : stepped through hole 1 02b : pass Hole 103: plated pores, etc. 111, 112: common type mask 1 2 1 : inner layer core substrate 1 22 : build-up layer 1 2 3 : cable portion 124 : multilayer printed substrate - 25 -