JP2023083009A - Wiring board and method for manufacturing wiring board - Google Patents

Abstract

To improve the connection reliability of wiring boards.SOLUTION: A wiring board of the embodiment includes a first conductor pattern 111 and a second conductor pattern 121 facing each other, an insulating layer 22 interposed between the first conductor pattern 111 and the second conductor pattern 121, and a via conductor 42 penetrating the insulating layer 22 and connecting the first conductor pattern 111 and the second conductor pattern 121. The first conductor pattern 111 has a recess 11b in the surface 11a on the second conductor pattern 121 side, and a portion of the side 42a of the via conductor 42 is in contact with the recess 11b.SELECTED DRAWING: Figure 2A

Description

The present invention relates to a wiring board and a method for manufacturing the wiring board.

Patent Document 1 discloses a multilayer wiring board having a stacked via structure. In a series of vertically adjacent via pads, the lowermost portion of the upper via pad is arranged on the bottom surface of a recess formed in the center of the upper surface of the lower via pad.

JP 2008-270531 A

In the connection structure between the upper and lower via pads in the multilayer wiring board disclosed in Patent Document 1, the connection area of both via pads is limited to the area of the bottom surface of the upper via pad. Therefore, the connection strength between the via pads is insufficient, and sufficient connection reliability may not be obtained.

The wiring board of the present invention comprises a first conductor pattern and a second conductor pattern facing each other, an insulating layer interposed between the first conductor pattern and the second conductor pattern, and a conductor penetrating through the insulating layer. a via conductor connecting the first conductor pattern and the second conductor pattern. The first conductor pattern has a recess on the surface on the second conductor pattern side, and a part of the side surface of the via conductor is in contact with the recess.

A method of manufacturing a wiring board according to the present invention includes forming a first conductor pattern, forming an insulating layer covering the first conductor pattern, and forming a through hole penetrating the insulating layer by irradiating a laser beam. forming a second conductor pattern on the insulating layer; and forming a via conductor connecting the first conductor pattern and the second conductor pattern in the through hole. . Forming the through-hole includes forming a recess continuously connected to the through-hole on the surface of the first conductor pattern by irradiating the laser beam.

According to the embodiments of the present invention, it may be possible to improve the reliability of connection between via conductors and conductor patterns.

1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention; FIG. The enlarged view of the IIA part of FIG. FIG. 2 is a plan view showing an example of a conductor pattern on the wiring board of FIG. 1; FIG. 4 is a cross-sectional view showing another example of the wiring board according to one embodiment of the present invention; 1 is a cross-sectional view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; FIG. 1 is a cross-sectional view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; FIG. 1 is a cross-sectional view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; FIG. FIG. 4 is an enlarged view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; FIG. 2 is a schematic diagram showing an example of intensity distribution of laser light used in the manufacturing method of one embodiment of the present invention. FIG. 4 is an enlarged view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; 1 is a cross-sectional view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; FIG. 1 is a cross-sectional view showing an example of a wiring board being manufactured by a manufacturing method according to an embodiment of the present invention; FIG.

A wiring board according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 100 that is an example of a wiring board according to one embodiment, and FIG. 2A is an enlarged view of the IIA portion of FIG. FIG. 2B shows a plan view of conductor pattern 111 shown in FIG. 2A together with via conductors 42 . Note that the wiring board 100 is merely an example of the wiring board of the present embodiment. The laminated structure of the wiring board of the embodiment and the number of conductor layers and insulating layers are not limited to the laminated structure of the wiring board 100 in FIG.

As shown in FIG. 1, the wiring board 100 includes a core substrate 3, and conductor layers and insulating layers laminated on both sides of the core substrate 3, respectively. Specifically, the wiring board 100 includes conductor layers 11-16, an insulating layer 30, and insulating layers 21-24. An insulating layer 21 , a conductor layer 11 , an insulating layer 22 , and a conductor layer 12 are laminated in this order on the first surface 3 a of the core substrate 3 . On the other hand, on the second surface 3b of the core substrate 3, an insulating layer 23, a conductor layer 13, an insulating layer 24, and a conductor layer 14 are laminated in this order. The core substrate 3 includes an insulating layer 30 and conductor layers 15 and 16 . The conductor layer 15 and the conductor layer 16 are formed on the first surface 3a side surface and the second surface 3b side surface of the insulating layer 30, respectively. A through-hole conductor 33 that connects the conductor layer 15 and the conductor layer 16 is formed in the insulating layer 30 . The wiring board of the embodiment may include one or more sets of two conductor layers facing each other and one or more insulating layers interposed between the two conductor layers facing each other.

In the description of the embodiments, the side farther from the insulating layer 30 in the thickness direction of the wiring board 100 is also referred to as "outer", "upper" or "upper", or simply "upper", and is closer to the insulating layer 30. The sides are also referred to as "inner", "lower" or "lower", or simply "lower". Furthermore, in each conductor layer, the conductor pattern included in each conductor layer, and each insulating layer, the surface facing away from the insulating layer 30 is also referred to as the "upper surface", and the surface facing the insulating layer 30 is also referred to as the "lower surface". is called The thickness direction of the wiring board 100 is also referred to as the "Z direction".

A solder resist 5 is formed on the conductor layer 12 and the insulating layer 22 . A solder resist 5 is also formed on the conductor layer 14 and the insulating layer 24 . Each solder resist 5 is provided with an opening that exposes a portion of the conductor layer 12 or a portion of the conductor layer 14 .

Wiring board 100 further includes via conductors 41 to 44 . Via conductors 41, 42, 43 and 44 penetrate insulating layers 21, 22, 23 and 24, respectively. The insulating layers 21 to 24 have a through hole 6 or a through hole 61 that penetrates each insulating layer, and each via conductor is formed in the through hole 6 or through hole 61 that penetrates each insulating layer. A through hole 61 penetrating the insulating layer 21 is filled with a via conductor 41 , and a through hole 6 penetrating the insulating layer 22 is filled with a via conductor 42 . A through-hole 61 passing through the insulating layer 23 or the insulating layer 24 is filled with a via conductor 43 or a via conductor 44 .

Via conductors 41 to 44 each protrude from one of two conductor layers facing each other and are in contact with the other. Via conductor 41 is formed integrally with conductor layer 11 and connects conductor layer 11 and conductor layer 15 . Via conductors 42 are formed integrally with conductor layer 12 and connect conductor layers 12 and 11 . Via conductors 43 are formed integrally with conductor layer 13 and connect conductor layers 13 and 16 . Via conductors 44 are formed integrally with conductor layer 14 and connect conductor layer 14 and conductor layer 13 .

The insulating layer 30 and the insulating layers 21 to 24 are made of any insulating resin. Examples of the insulating resin include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. In the example of FIG. 1, the insulating layer 30 includes a core material (reinforcing material) 34 made of glass fiber, aramid fiber, or the like. Each insulating layer may further include a filler (not shown) consisting of particles such as silicon dioxide or alumina.

Conductor layers 11-16, through-hole conductors 33, and via conductors 41-44 may be formed using any metal such as copper or nickel. In the example of FIG. 1, each of the conductor layers 11 to 14 and the via conductors 41 to 44 is a two-layer structure including a first metal film 4a and a second metal film 4b formed on the first metal film 4a. have a structure. The first metal film 4 a forming the via conductor 42 is formed directly on the inner wall of the through hole 6 , and the first metal film 4 a forming each of the via conductors 41 , 43 and 44 is formed on the inner wall of the through hole 61 . is formed directly on the

The first metal film 4a is formed by electroless plating, sputtering, or the like, for example. The second metal film 4b is, for example, an electrolytic plated film formed by electrolytic plating using the first metal film 4a as a power supply layer. The through-hole conductor 33 also has a two-layer structure including an electroless plated film and an electrolytic plated film. On the other hand, the conductor layers 15 and 16 have a three-layer structure further including metal foil.

Each of the conductor layers 11-16 includes arbitrary conductor patterns. For example, conductor layer 11 includes conductor pattern 111 (first conductor pattern) and conductor pattern 112 , and conductor layer 12 includes conductor pattern 121 (second conductor pattern) and conductor pattern 122 . The conductor layer 13 and the conductor layer 14 respectively include conductor patterns 131 and conductor patterns 141 .

Conductive patterns 111 and 121 are at least partially opposed to each other, and conductive patterns 112 and 122 are at least partially opposed to each other. The conductor pattern 131 and the conductor pattern 141 are at least partially opposed to each other. The insulating layer 22 is interposed between the conductor patterns 111 and 121 and between the conductor patterns 112 and 122 . An insulating layer 24 is interposed between the conductor pattern 131 and the conductor pattern 141 .

Conductive patterns 121 and 122 each include so-called via lands (via pads) for via conductors 42 , and conductive patterns 111 and 112 each include so-called receiving pads for via conductors 42 . Similarly, the conductor pattern 141 includes so-called via lands for the via conductors 44 , and the conductor pattern 131 includes so-called receiving pads for the via conductors 44 .

That is, via conductors 42 are integrally formed with conductor pattern 121 or conductor pattern 122 , protrude from conductor pattern 121 or conductor pattern 122 , and are in contact with conductor pattern 111 or conductor pattern 112 . Via conductors 42 projecting from conductor pattern 121 connect conductor pattern 111 and conductor pattern 121 . Via conductors 42 projecting from conductor pattern 122 connect conductor pattern 112 and conductor pattern 122 . Similarly, via conductors 44 connect conductive patterns 131 and 141 .

In the example of FIG. 1, via conductors 41 to 44 all have a shape that tapers toward the receiving pad side. For example, a via conductor 42 connecting conductive pattern 111 and conductive pattern 121 has a shape that tapers toward conductive pattern 111 . However, the taper angle TA1 (see FIG. 2A) of via conductor 42 is smaller than the taper angle TA2 (see FIG. 2A) of each of via conductors 41, 43, and 44. FIG. Therefore, the via conductors 42 are sometimes more advantageous than the via conductors 41, 43, and 44 in forming fine wiring patterns. The "taper angle" of each via conductor is the angle of the side surface of each via conductor with respect to the Z direction.

The via conductors 41 connecting the conductor pattern 111 and the conductor layer 15 and the via conductors 42 connecting the conductor pattern 111 and the conductor pattern 121 are stacked in the Z direction and overlap in plan view. That is, these via conductors 41 and via conductors 42 constitute stack via conductors. Note that “planar view” means viewing the wiring board 100 with a line of sight along the Z direction.

In the wiring board 100 of FIG. 1 , the tips of the plurality of via conductors 42 penetrating the insulating layer 22 on the side of the conductor layer 11 are all inside the receiving pads (conductor patterns 111, 112, etc.) of the via conductors 42. getting into Details of this point will be described below with reference to FIGS. 2A and 2B, using via conductors 42 that enter conductor pattern 111 as an example.

As shown in FIG. 2A, the conductor pattern 111 has a concave portion 11b on the surface 11a on the conductor pattern 121 side. The surface 11 a is the surface of the conductor pattern 111 that faces the conductor layer 12 and is in contact with the insulating layer 22 . The recess 11b is recessed from the surface 11a in a direction opposite to the conductor pattern 121, that is, toward the insulating layer 21 and the conductor layer 15 side. In the example of FIG. 2A, the recess 11b has a bottom surface 11b1 that extends along the surface 11a, and an inner wall surface (inner surface) 11b2 that intersects with the bottom surface 11b1 and surrounds the space inside the recess 11b. The concave portion 11b in the example of FIG. 2A has a tapered shape that tapers toward the insulating layer 21 side. Therefore, the inner wall surface 11b2 is inclined with respect to the Z direction so that the bottom surface 11b1 approaches the center of the recess 11b, and is also inclined with respect to the normal line of the bottom surface 11b1.

In this embodiment, a part of the side surface 42a of the via conductor 42 is in contact with the recess 11b. That is, in the example of FIG. 2A, the via conductor 42 is inserted into the recess 11b at the end on the conductor pattern 111 side, and the side surface 42a is in contact with the inner wall surface 11b2 of the recess 11b at the end on the conductor pattern 111 side. there is On the other hand, the end surface 42b of the via conductor 42 on the conductor pattern 111 side is in contact with the bottom surface 11b1 of the recess 11b.

In this embodiment, not only the end surface 42b of the via conductor 42 but also the side surface 42a of the via conductor 42 are in contact with the recess 11b at the end on the conductor pattern 111 side. Therefore, the contact area between the conductor pattern 111 and the via conductor 42 is larger than in the case where only the end face 42b is in contact with the conductor pattern 111, for example. Therefore, it is considered that the adhesion strength between the conductor pattern 111 and the via conductor 42 is higher than when only the end face 42b is in contact with the conductor pattern 111, for example. That is, it is considered that the connection reliability between the via conductors 42 and the conductor patterns 111 is higher than in the conventional art.

Between the via conductors such as the via conductors 42 and the conductor pattern 111 and the conductor patterns (so-called receiving pads) connected to the via conductors, for example, expansion and contraction due to changes in temperature of the insulating layer penetrated by the via conductors may occur. , a stress in the direction of separating the two can occur. Therefore, peeling or cracking may occur at the interface between the two. In particular, wiring substrates are required to have higher wiring densities as electronic devices become smaller. In order to achieve this, it is sometimes required to reduce the diameter of via conductors. However, in a structure in which a via conductor is in contact with a receiving pad only at its end surface, a reduction in the diameter of the via conductor directly leads to a decrease in the contact area between the via conductor and the receiving pad, and the reduction in contact area corresponds to a decrease in adhesion. can lead to decline. Therefore, interfacial peeling between the via conductor and its receiving pad may occur more easily.

In contrast, in the present embodiment, not only the end surface 42b of the via conductor 42 but also the side surface 42a are in contact with the conductor pattern 111 in the recess 11b. Therefore, a larger contact area is obtained between the via conductor 42 and the conductor pattern 111 than when only the end surface 42b is in contact with the conductor pattern 111 . Therefore, it is considered that the adhesion between the two is increased.

In addition, even if the diameter of the via conductor 42 is reduced, for example, by increasing the depth of the recess 11b and inserting the via conductor 42 deeper into the recess 11b, the contact area between the side surface 42a and the recess 11b can be increased. be able to. That is, the decrease in the contact area at the end surface 42b may be compensated for by the increase in the contact area due to the side surface 42a. A decrease in adhesion between the via conductor 42 and the conductor pattern 111 may be suppressed. Alternatively, the adhesion between the via conductor 42 and the conductor pattern 111 may be maintained or improved. Therefore, it is possible to suppress the occurrence of problems related to connection, such as interfacial peeling, caused by a decrease in adhesion.

As described above, according to this embodiment, the connection reliability between the via conductors 42 and the conductor patterns 111 may be improved. In the example of FIG. 1, the reliability of connection with receiving pads such as conductor patterns 111 and 112 to which each via conductor 42 is connected may be improved in all of the via conductors 42 penetrating the insulating layer 22. .

Via conductor 42 has a portion inside through hole 6 penetrating insulating layer 22 and a portion inside recess 11 b of conductor pattern 111 . However, in each of the first metal film 4a and the second metal film 4b forming the via conductor 42, the portion inside the through-hole 6 and the portion inside the recess 11b are integrally formed. For example, the side surface 42a of the via conductor 42 continuously extends from the portion inside the through hole 6 to the portion inside the recess 11b. In the cross section shown in FIG. 2A, the side surface 42a extends linearly without bending near the point of contact with the surface 11a of the conductor pattern 111. As shown in FIG. That is, as shown in FIG. 2B, on the surface 11a of the conductor pattern 111, the peripheral edges of the recesses 11b and the peripheral edges of the through holes 6 overlap. Preferably, side surface 42 a of via conductor 42 does not have a step near surface 11 a of conductive pattern 111 . For example, even if shear stress occurs between the conductor pattern 111 and the insulating layer 22, cracks that extend the interface between the conductor pattern 111 and the insulating layer 22 into the via conductor 42 are unlikely to occur in the via conductor 42. .

As shown in FIG. 2A, the thickness of first metal film 4a forming via conductor 42 is smaller than the depth of recess 11b. Therefore, the surface 4aa of the first metal film 4a covering the bottom surface 11b1 of the recess 11b (the surface opposite to the bottom surface 11b1) is located closer to the insulating layer 21 than the surface 11a of the conductive pattern 111 is. The second metal film 4b and the first metal film 4a cross the surface 11a in the Z direction. As compared with the case where the surface 11a of the conductor pattern 111 and the surface 4aa of the first metal film 4a are flush with each other, it is considered that the interfacial separation between the first metal film 4a and the second metal film 4b is less likely to occur.

The depth D of the recess 11b, that is, the insertion length of the via conductor 42 into the recess 11b is, for example, 2 μm or more and 8 μm or less. It is considered that the effect of improving the adhesion strength between the via conductor 42 and the conductor pattern 111 as described above can be obtained, and the formation of the concave portion 11b is easy. Also, the depth D of the concave portion 11b is, for example, 10% or more and 50% or less of the thickness of the conductor pattern 111 . However, the depth of the concave portion 11b is not limited to the above range, and may be, for example, greater than 8 μm.

As described above, the taper angle TA1 of via conductor 42 is smaller than the taper angle TA2 of via conductor 41 . The taper angle TA1 is, for example, 80° or more and 88° or less. A via conductor 42 having a relatively small taper angle TA1 can have an end surface on the conductor pattern 121 side that has a relatively small enlargement ratio with respect to the end surface 42b on the conductor pattern 111 side. For example, the width W of the via conductor 42 at the end face on the conductor pattern 121 side is 15 μm or more and 30 μm or less. In that case, the thickness of the insulating layer 22 (the distance between the conductor pattern 111 and the conductor pattern 121) may be 15 to 30 μm.

The "width" of the via conductor 42 and the "width" of the recess 11b, which will be described later, are the longest distances between arbitrary two points on the peripheries of the via conductor 42 and the recess 11b, respectively, in plan view. Here, the planar shapes of via conductors 42 and recesses 11b may be, for example, circular or rectangular. When the planar shape of via conductor 42 and recess 11b is circular, the width of via conductor 42 and recess 11b is the diameter of the circular planar shape of via conductor 42 and recess 11b.

In the wiring board 100, as shown in FIGS. 2A and 2B, the width of the recess 11b is substantially the same as the width of the via conductor 42 in the recess 11b. As described above, the concave portion 11b has a shape that tapers toward the insulating layer 21 side. The via conductor 42 has a shape that tapers toward the conductor pattern 111 within the through hole 6, and is tapered to the insulating layer 21 at a taper angle TA1 that is substantially the same as the taper angle TA1 within the through hole 6 also within the recess 11b. It has a tapered shape. In the example of FIG. 2A, the recess 11b and the via conductor 42 in the recess 11b have approximately the same taper angle TA1. Therefore, in the example of FIG. 2A, the width of the recess 11b and the width of the via conductor 42 in the recess 11b are substantially the same over the entire Z direction.

Furthermore, as shown in FIGS. 2A and 2B, in wiring board 100, side surface 42a of via conductor 42 is in contact with recess 11b over the entire circumference at the end on the conductor pattern 111 side. Specifically, the side surface 42a is in contact with the recess 11b over the entire circumference within the recess 11b. As described above, since the width of the recess 11b and the width of the via conductor 42 in the recess 11b are substantially the same over the entire Z direction, substantially the entire inner wall surface 11b2 of the recess 11b is in contact with the side surface 42a of the via conductor 42. ing. Therefore, it is considered that the adhesion strength between the via conductor 42 and the conductor pattern 111 is higher than when the inner wall surface 11b2 and the side surface 42a are partially in contact with each other.

Also, the recess 11 b is filled with the via conductor 42 . In the example of FIG. 2A , the entire bottom surface 11 b 1 of the recess 11 b is in contact with the end surface 42 b of the via conductor 42 . That is, the entire recess 11 b is filled with the via conductor 42 . It is considered that problems due to thermal expansion and thermal contraction are less likely to occur than in the case where voids or the like are present in the concave portion 11b.

FIG. 3 shows a cross-sectional view of a wiring board 101 that is another example of the wiring board of the embodiment. The wiring board 101 has the same structure as the wiring board 100 in the example of FIG. However, the wiring substrate 101 includes via conductors 42 whose tips do not enter inside the conductor pattern 111 , and via conductors 421 whose tips do not substantially enter inside the conductor pattern 112 in the insulating layer 22 . Thus, the wiring board of the embodiment includes via conductors (for example, the via conductors 42) whose tips are inserted into so-called receiving pads such as the conductor patterns 111 and the conductor patterns 112, and via conductors (for example, the via conductors) whose tips are not inserted. 421) may be included in one insulating layer. For example, a wiring pattern arranged at a fine pitch and a power supply pattern or GND pattern having a large width may be mixed in a conductor layer adjacent to one insulating layer.

In the wiring board 101 of FIG. 3, the insulating layer 24 as well as the insulating layer 22 include via conductors (via conductors 421) whose tips are inserted into the insides of so-called receiving pads. The via conductors 421 connect the conductor pattern 132 included in the conductor layer 13 and the conductor pattern 142 included in the conductor layer 14 . Conductive pattern 132 includes so-called receiving pads for via conductors 421 , and conductive pattern 142 includes so-called via lands for via conductors 421 . The conductor pattern 132 has a concave portion 13b on the surface 13a on the conductor pattern 142 side. The end of the via conductor 421 on the conductor pattern 132 side is inserted into the recess 13b, and the side surface of the via conductor 421 is in contact with the recess 13b. The entire recess 13 b is filled with the via conductor 421 , and substantially the entire inner wall surface of the recess 13 b is in contact with the side surface of the via conductor 421 .

Like the wiring board 101 in FIG. 3, the wiring board according to the embodiment may include via conductors whose ends are inserted into so-called receiving pads on both insulating layers laminated on both sides of the core board. good. In the wiring board of the embodiment, via conductors whose tips are recessed into receiving pads like the via conductors 42 shown in FIGS. 1 and 2 can be provided in any insulating layer.

Next, a method for manufacturing a wiring board according to one embodiment will be described with reference to FIGS. 4A to 4H using the wiring board 100 of FIG. 1 as an example.

As shown in FIG. 4A, a core substrate 3 is prepared, an insulating layer 21 is formed on the first surface 3a of the core substrate 3, and an insulating layer 23 is formed on the second surface 3b. In preparation of the core substrate 3, for example, an insulating layer to be the insulating layer 30 of the core substrate 3 and a starting substrate (for example, a double-sided copper-clad laminate) including metal foil laminated on both surfaces of the insulating layer are prepared. be. Then, the conductor layers 15 and 16 having desired conductor patterns and the through-hole conductors 33 are formed by patterning using the subtractive method following the formation of through-holes and panel plating.

In forming the insulating layer 21 and the insulating layer 23, for example, a film-like epoxy resin is laminated on the first surface 3a and the second surface 3b of the core substrate 3, and heated and pressurized. As a result, insulating layers 21 and 23 are formed. Through holes 61 for forming via conductors 41 or via conductors 43 are formed in each insulating layer by, for example, carbon dioxide laser light irradiation.

A conductor layer 11 including a conductor pattern 111 is formed on the insulating layer 21 , and a conductor layer 13 is formed on the insulating layer 23 . Via conductors 41 are formed in through holes 61 penetrating insulating layer 21 , and via conductors 43 are formed in through holes 61 penetrating insulating layer 23 . The conductor layers 11 and 13 and the via conductors 41 and 43 are formed using any metal such as copper or nickel by, for example, a semi-additive method. First, the first metal film 4a is formed on the surfaces of the insulating layers 21 and 23 and in the through holes 61 by electroless plating or sputtering. Then, on the first metal film 4a on the insulating layer 21, a plating resist (not shown) having openings corresponding to formation regions of conductor patterns to be included in the conductor layer 11 such as the conductor pattern 111 is provided. . Similarly, a plating resist (not shown) is provided on the first metal film 4a on the insulating layer 23 as well. Then, the second metal film 4b is formed in the opening of each plating resist by pattern plating including electrolytic plating using the first metal film 4a as a power supply layer. As a result, via conductors 41 or via conductors 43 are formed in through holes 61 .

After the plating resist is removed, unnecessary portions of the first metal film 4a exposed by the removal of the plating resist are removed, for example, by etching. As a result, the conductor layer 11 including the conductor pattern 111 and other predetermined conductor patterns is formed. As described above, the wiring board manufacturing method of the present embodiment includes forming the conductor pattern 111 (first conductor pattern). A conductor layer 13 including a predetermined conductor pattern such as a conductor pattern 131 is formed on the insulating layer 23 .

As shown in FIG. 4B, an insulating layer 22 covering the conductor layer 11 including the conductor pattern 111 and an insulating layer 24 covering the conductor layer 13 are formed. The wiring board manufacturing method of the present embodiment includes forming the insulating layer 22 covering the conductor pattern 111 in this manner. The insulating layer 22 and the insulating layer 24 are formed by, for example, the same method as the method for forming the insulating layer 21 and the insulating layer 23 described above. For example, the insulating layer 22 is formed by laminating a film-like epoxy resin on the insulating layer 21 and the conductor layer 11 and thermally compressing them.

As shown in FIGS. 4C and 4D, the wiring board manufacturing method of the present embodiment further includes forming through holes 6 penetrating the insulating layer 22 . FIG. 4D shows an enlarged view of the IVD section shown in FIG. 4C. Through holes 6 are formed in regions where via conductors 42 (see FIG. 4G) are to be formed. The through hole 6 is formed by irradiating the insulating layer 22 with the laser beam L. As shown in FIG. By forming the through hole 6 in the insulating layer 22 , a part of the predetermined conductor pattern such as the conductor pattern 111 included in the conductor layer 11 is exposed in the through hole 6 . Through holes 61 are formed in insulating layer 24 in regions where via conductors 44 (see FIG. 4G) are to be formed. The through hole 61 is also formed by laser light irradiation or the like. The formation of the through-holes 6 and the formation of the through-holes 61 may be performed continuously in the same process using the same laser processing machine, or may be performed in separate processes in sequence using different processing machines. may be done.

As shown in FIG. 4D, forming the through hole 6 includes forming a recess 11b on the surface 11a of the conductor pattern 111 facing away from the insulating layer 21 by irradiation with the laser beam L. That is, along with the formation of the through hole 6, the recess 11b continuously connected to the through hole 6 is formed on the surface 11a. Preferably, recess 11b having a peripheral edge overlapping the peripheral edge of through hole 6 on surface 11a and having no step at the boundary between the inner wall surface of through hole 6 and the inner wall surface of recess 11b is formed.

The through-hole 6 and the concave portion 11b are formed substantially simultaneously or continuously by a series of irradiation with the laser light L, for example. That is, the irradiation of the laser beam L to form the through hole 6 may be continued without being stopped even after the through hole 6 is formed. Then, the recess 11b may be formed by irradiating the surface 11a of the conductor pattern 111 exposed in the through hole 6 with the laser light L that continues. Alternatively, before the formation of the through hole 6 is completed, a part of the surface 11a of the conductor pattern 111 exposed in the through hole 6 being formed is irradiated with the laser beam L, and the recess is formed in parallel with the formation of the through hole 6. A part or all of 11b may be formed. Since the recesses 11b are formed continuously or simultaneously with the formation of the through holes 6 by the irradiation of the laser light L, the recesses 11b can be formed efficiently.

Examples of the laser used to form the through holes 6 and 61 (see FIG. 4C) include a carbon dioxide laser and a YAG laser, but the laser used to form each through hole is not particularly limited. For example, the through holes 6 may be formed using an ultraviolet (UV) laser having a wavelength in the ultraviolet region, which is superior in straightness. It may be advantageous to form through holes 6 suitable for forming via conductors 42 having a width of less than 30 μm, as described above.

FIG. 4E shows an example of the intensity distribution (beam profile) of the laser light used for forming the through holes 6. As shown in FIG. In FIG. 4E, the center of the laser light L1 and the laser light L2 is indicated by the 0 point on the horizontal axis, and the intensity of the laser light L1 and L2 with respect to the radial distance from the center (horizontal axis) is indicated on the vertical axis. there is

In FIG. 4E, the laser beam L1 has a so-called Gaussian intensity distribution in which the intensity increases toward the center of the laser beam like a Gaussian distribution. On the other hand, the laser beam L2 has a so-called top-hat intensity distribution in which the intensity is substantially uniform within a predetermined range with respect to the distance from the center of the laser beam. The laser light L used for forming the through hole 6 and the recess 11b can have any intensity distribution including the intensity distribution of the laser lights L1 and L2 shown in FIG. 4E. For example, using a laser beam L having a top-hat intensity distribution such as the laser beam L2 may be beneficial in forming the through hole 6 and the recess 11b. Since the entire laser beam is concentrated in a region of desired size, it may be possible to form small-diameter through holes 6 and recesses 11b. In addition, since the light concentrated in the region of the desired size has a substantially uniform intensity distribution within that region, it is believed that the recesses 11b having the desired area are likely to be formed following the formation of the through-holes 6. be done.

Even when the laser beam L having a top-hat intensity distribution is used to form the through hole 6, a light source having a Gaussian intensity distribution, for example, is used as a light source (not shown) that emits the laser beam L. may In that case, for example, laser light having a Gaussian intensity distribution may be shaped into laser light L having a top-hat intensity distribution using, for example, a beam shaper (not shown) including suitable optical elements. .

After forming the through holes 6 and 61 and the recesses 11b, a desmear process may be performed to remove resin residue (smear) caused by forming the through holes 6 and 61. FIG. Smear in the through-holes 6, 61 is removed by exposing the inner walls of the through-holes 6, 61 to a processing liquid such as, for example, an alkaline permanganate solution. This desmearing process may remove smears that have fallen into the recesses 11b of the conductor pattern 111 .

As shown in FIGS. 4F and 4G, the wiring board manufacturing method of the present embodiment further includes forming via conductors 42 in the through holes 6 . A via conductor 44 is formed in the through hole 61 of the insulating layer 24 . A conductor layer 12 is formed on the insulating layer 22 and a conductor layer 14 is formed on the insulating layer 24 . FIG. 4F shows a state in the process of forming via conductors 42 in a portion corresponding to the portion shown in FIG. 4D.

The via conductors 42 and 44 are formed together with the conductor layer 12 or the conductor layer 14 by using, for example, a semi-additive method similar to the method of forming the via conductors 41 and 43 described above. For example, in forming the via conductors 42 and the conductor layer 12, as shown in FIG. 4F, a first metal film 4a is formed on the inner wall surface of the through hole 6 and the entire surface of the insulating layer 22 by, for example, electroless plating or sputtering. is formed. Since the recess 11b connected to the through hole 6 is formed on the surface 11a of the conductor pattern 111, the first metal film 4a is also formed on the inner wall surface 11b2 of the recess 11b. The first metal film 4a may be formed on the entire surface of the inner wall surface 11b2 (see FIG. 4F) of the recess 11b. The first metal film 4a may also be formed on part or all of the bottom surface 11b1 (see FIG. 4F) of the recess 11b. Thus, forming the via conductor 42 in the present embodiment can include forming the first metal film 4a on the inner wall surface 11b2 of the recess 11b.

As shown in FIG. 4G, a plating resist R having an opening R1 is provided on the first metal film 4a. The opening R1 is provided in a formation region of a conductor pattern to be included in the conductor layer 12 such as the conductor pattern 121 or in a formation region of a conductor pattern to be included in the conductor layer 14 such as the conductor pattern 141 . Then, the second metal film 4b is formed in the opening R1 by electroplating using the first metal film 4a as a power supply layer. As a result, a conductor pattern such as the conductor pattern 121 that should be included in the conductor layer 12 or a conductor pattern that should be included in the conductor layer 14 such as the conductor pattern 141 is formed. As described above, the wiring board manufacturing method of the present embodiment includes forming the conductor pattern 121 (second conductor pattern) on the insulating layer 22 .

A via conductor 42 that connects the conductor pattern 111 and the conductor pattern 121 is formed in the through hole 6 . A via conductor 44 that connects the conductor pattern 131 and the conductor pattern 141 is formed in the through hole 61 . Since the recess 11b connected to the through hole 6 is formed on the surface 11a of the conductor pattern 111, the via conductor 42 is also formed inside the recess 11b. As a result, recess 11 b is filled with via conductor 42 . Thus, forming the via conductors 42 in this embodiment may include filling the recesses 11 b with the via conductors 42 . A via conductor 42 having a portion formed integrally with the portion in through hole 6 in recess 11b is formed. Preferably, a via conductor 42 is formed that fills substantially the entire recess 11b and is in contact with the entire inner wall surface of the recess 11b.

After forming the second metal film 4b, the plating resist R is removed using, for example, a suitable stripping solution. Furthermore, the portion of the first metal film 4a exposed by the removal of the plating resist R is removed by short-time etching such as flash etching. As a result, conductor layers 12 and 14 are formed which include desired conductor patterns, such as conductor pattern 121 or conductor pattern 141, which are separated from each other.

When the wiring board 100 is manufactured, the solder resist 5 is formed on the insulating layer 22 and the conductor layer 12, and the solder resist 5 is also formed on the insulating layer 24 and the conductor layer 14, as shown in FIG. 4H. be done. For example, the solder resist 5 is formed by supplying a photosensitive epoxy resin, polyimide resin, or the like to the surface of the wiring board 100 during the process by spraying, laminating, printing, or the like. Openings are formed in the solder resist 5 by, for example, exposure and development using a mask having an appropriate opening pattern. The wiring substrate 100 shown in FIG. 1 is completed through the above steps.

According to the wiring board manufacturing method of the present embodiment, as shown in FIG. 4D , the laser light L is irradiated to form the recesses 11 b continuously connected to the through holes 6 on the surface 11 a of the conductor pattern 111 . Therefore, via conductors 42 (see FIG. 4G) formed in through-holes 6 can be in contact with conductor pattern 111 (recesses 11b) on their side surfaces as well. Therefore, a via conductor 42 having a high adhesion strength to the conductor pattern 111 can be formed. That is, according to the manufacturing method of the present embodiment, it is considered that a wiring board having high reliability in connection between via conductors and conductor layers can be obtained.

The wiring substrates of the embodiments are not limited to those having the structures illustrated in each drawing, and the structures, shapes, and materials illustrated in this specification. As described above, the wiring board of the embodiment can have any laminated structure. A wiring substrate of embodiments may include any number of conductor layers and insulating layers. For example, the wiring board of the embodiment may be a so-called coreless board that does not include a core board. In the wiring board of the embodiment, one of a set of arbitrary conductor patterns facing each other via an insulating layer can be a conductor pattern 111 (first conductor pattern) including a so-called receiving pad, and the other can be a so-called via land. It may be a conductor pattern 121 (second conductor pattern) including Via conductors, such as the via conductor 42, may be stacked such that the tip of the via conductor is inserted into the receiving pad.

Each of the conductor pattern 111 and the conductor pattern 121 may be formed integrally with the wiring pattern of each conductor layer. Also, the conductor pattern 111 may be formed integrally with a via land or a receiving pad of a via conductor connected to a conductor pattern other than the conductor pattern 121. It may be formed integrally with the via land of the connected via conductor or the component mounting pad.

The method for manufacturing the wiring board of the embodiment is not limited to the method described with reference to each drawing. For example, each conductor layer may be formed by a method other than the semi-additive method. Each insulating layer can be formed by any method. The laser light L used for forming the through holes 6 can have any intensity distribution. Arbitrary steps may be added to the wiring board manufacturing method of the embodiment in addition to the steps described above, and some of the steps described above may be omitted.

100, 101 wiring substrates 11 to 16 conductor layer 111 conductor pattern (first conductor pattern)
11a Surface 11b of conductor pattern Recess 11b1 Bottom surface 11b2 Inner wall surface 121 Conductor pattern (second conductor pattern)
21 to 24 insulating layers 41 to 44 via conductor 42a side surface 42b of via conductor end surface 4a of via conductor metal film (first metal film)
4b second metal films 6, 61 through hole L laser beam W width of via conductor

Claims (11)

a first conductor pattern and a second conductor pattern facing each other;
an insulating layer interposed between the first conductor pattern and the second conductor pattern;
a via conductor penetrating the insulating layer and connecting the first conductor pattern and the second conductor pattern;
A wiring board comprising
The first conductor pattern has a concave portion on the surface on the second conductor pattern side,
A part of the side surface of the via conductor is in contact with the recess. The wiring board according to claim 1,
the via conductor is inserted into the recess at an end on the first conductor pattern side,
The width of the recess and the width of the via conductor in the recess are substantially the same. 2. The wiring board according to claim 1, wherein the side surface of the via conductor is in contact with the recess over the entire circumference at the end on the first conductor pattern side. 4. The wiring board according to claim 3, wherein substantially the entire inner wall surface of said recess is in contact with said side surface of said via conductor. The wiring board according to claim 1,
the insulating layer has a through hole filled with the via conductor;
A peripheral edge of the recess and a peripheral edge of the through hole overlap on the surface of the first conductor pattern. 2. The wiring board according to claim 1, wherein the entire recess is filled with the via conductor. 2. The wiring board according to claim 1, wherein the width of the via conductor on the end surface on the side of the second conductor pattern is 15 [mu]m or more and 30 [mu]m or less. forming a first conductor pattern;
forming an insulating layer covering the first conductor pattern;
Forming a through-hole penetrating the insulating layer by irradiating a laser beam;
forming a second conductor pattern on the insulating layer;
forming a via conductor that connects the first conductor pattern and the second conductor pattern in the through hole;
A wiring board manufacturing method comprising
Forming the through-hole includes forming a recess continuously connected to the through-hole on the surface of the first conductor pattern by irradiating the laser beam. 9. The method of manufacturing a wiring board according to claim 8, wherein forming the via conductor includes forming a metal film on an inner wall surface of the recess. 9. The method of manufacturing a wiring board according to claim 8, wherein forming the via conductor includes filling substantially the entire recess with the via conductor. 9. The method of manufacturing a wiring board according to claim 8, wherein the through hole and the recess are formed substantially simultaneously or continuously by a series of irradiation with the laser beam.

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