JP2020188072A - Wiring board and manufacturing method thereof - Google Patents

Abstract

To achieve power supply enhancement of a wiring board.SOLUTION: A wiring board 1 according to an embodiment includes a first build-up layer 11 in which a core substrate 10, a first interlayer insulating layer 32, and a first conductor layer 31 are alternately laminated, a second build-up layer 12 in which a second interlayer insulating layer 42 and a second conductor layer 41 are alternately laminated, and a first via conductor 52a and a second via conductor 52b that connect the conductor layers to each other through the second interlayer insulating layer 42, and the second conductor layer 41 has a recess of less than 10 μm on the first via conductor 52a and the second via conductor 52b, and the first via conductor 52a is formed by filling a hole having a predetermined top diameter with plating, and the second via conductor 52b is formed by filling a groove having a predetermined width which is 0.8 times or more and 1.3 times or less a predetermined top diameter with plating.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

Patent Document 1 discloses a wiring board for mounting a semiconductor integrated circuit element in which build-up insulating layers and build-up wiring layers are alternately laminated on the upper and lower surfaces of a core substrate having through holes for power supply. ing. The power supply plane on the lower surface side of the core board connected to the through hole for power supply is arranged in the build-up wiring layer, and the parts corresponding to multiple sets of vias are connected to one via land. , Are connected via a pair of vias.

Japanese Unexamined Patent Publication No. 2013-115062

In the wiring board of Patent Document 1, via lands corresponding to a set of four vias are provided in the build-up wiring layer, from through holes for power supply via the via lands to external connection pads for power supply corresponding thereto. However, four vias are connected by a pair of vias. Power may not be supplied sufficiently.

The wiring substrate of the present invention has a first surface and a second surface opposite to the first surface, and has a core insulating layer, a first surface side conductor layer, a second surface side conductor layer, and the core insulating layer. A core substrate including a through-hole conductor that penetrates the first surface side conductor layer and connects the second surface side conductor layer, and a first interlayer insulating layer provided on the first surface of the core substrate. The first build-up layer in which the first conductor layers on the first interlayer insulating layer are alternately laminated, and the second interlayer insulating layer and the second interlayer insulation provided on the second surface of the core substrate are provided. A first via conductor that penetrates the second interlayer insulating layer and connects the conductor layers on both sides of the second interlayer insulating layer to the second build-up layer in which the second conductor layers on the layer are alternately laminated. And a second via conductor. The first via conductor is formed by penetrating the second interlayer insulating layer and filling holes having a predetermined top diameter with plating, and the second via conductor is the second interlayer insulating layer. It is formed by filling a groove having a predetermined width of 0.8 times or more and 1.3 times or less the top diameter of the hole through which the first via conductor is formed by plating. The second conductor layer does not have a recess or has a recess of less than 10 μm on the first via conductor and the second via conductor on the surface facing the opposite side of the core substrate. ing.

The method for manufacturing a wiring board of the present invention has a first surface and a second surface opposite to the first surface, and has a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer. A core substrate including the core substrate is provided, and a first build-up layer formed by alternately laminating a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer is provided on the first surface of the core substrate. A second build-up layer in which a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated is provided on the second surface of the core substrate. Includes. Then, providing the second build-up layer connects the second conductor layers on both sides of the second interlayer insulating layer in the same second interlayer insulating layer in the second build-up layer. It includes forming a via conductor and a second via conductor at the same time, and forming the first via conductor means filling a hole having a predetermined top diameter through the second interlayer insulating layer with plating. To form the second via conductor is 0.8 times or more and 1.3 times the top diameter of the hole through which the first via conductor is formed through the second interlayer insulating layer. It involves filling a groove having the following predetermined width with plating.

According to the embodiment of the present invention, it is considered that the power supply of the wiring board can be strengthened. In addition, a wiring board having high power supply characteristics can be manufactured.

The cross-sectional view which shows an example of the wiring board of one Embodiment of this invention. The plan view which shows the 2nd surface side of the wiring board of FIG. It is a graph which shows the relationship between the thickness of a conductor layer and the dent of the surface of a conductor layer. The enlarged view which shows an example of the recess of the conductor layer surface on the 1st via conductor in the wiring board of one Embodiment. The enlarged view which shows an example of the recess of the conductor layer surface on the 2nd via conductor in the wiring board of one Embodiment. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention.

A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1 having a first surface 1F and a second surface 1B opposite to the first surface 1F, which is an example of the wiring board of one embodiment. A plan view of the wiring board 1 on the second surface 1B side is shown in FIG.

As shown in FIG. 1, the wiring board 1 includes a core substrate 10 having a first surface 10F and a second surface 10B opposite to the first surface 10F, and a first surface 10F of the core substrate 10. One build-up layer 11 and a second build-up layer 12 on the second surface 10B of the core substrate 10 are included. In the example of FIG. 1, the two build-up layers (first build-up layer 11 and second build-up layer 12) include the same number of conductor layers as each other. The first build-up layer 11 is formed by alternately laminating the first interlayer insulating layer 32 and the first conductor layer 31 on the first interlayer insulating layer 32. In the example of FIG. 1, the first build-up layer 11 includes two first conductor layers 31 and two first interlayer insulating layers 32. The second build-up layer 12 is formed by alternately laminating a second interlayer insulating layer 42 and a second conductor layer 41 on the second interlayer insulating layer 42. In the example of FIG. 1, the second build-up layer 12 includes two second conductor layers 41 and two second interlayer insulating layers 42. The number of conductor layers and interlayer insulating layers in the first and second build-up layers is not limited to two, and any number of conductor layers, for example, one, three or more, can be used. And an interlayer insulating layer may be provided.

The core substrate 10 is formed on both sides of the core insulating layer 5 and the core insulating layer 5, that is, on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively, the first surface side conductor layers 3 and the second. The surface side conductor layer 4 is included. Through-hole through holes 55 penetrating the core insulating layer 5 are formed in the core insulating layer 5, and by filling each through-hole through hole 55 with a conductor, the first surface side conductor layer 3 and the first surface side conductor layer 5 are formed. A through-hole conductor 50 that connects the two-sided conductor layer 4 is formed.

A desired conductor pattern is formed in each of the conductor layers (first surface side conductor layer 3, second surface side conductor layer 4, first conductor layer 31, and second conductor layer 41). In the example of FIG. 1, the first surface side conductor layer 3 and the second surface side conductor layer 4 are formed of three layers. The first conductor layer 31 and the second conductor layer 41 are formed of two layers. However, the number of layers forming each of the conductor layers is not limited to the example of FIG. 1, and for example, the first conductor layer 31 and the second conductor layer 41 may be formed of three layers. The first surface side conductor layer 3 and the second surface side conductor layer 4 may have, for example, a metal foil layer, an electroless plating film layer, and an electrolytic plating film layer. The first conductor layer 31 and the second conductor layer 41 may have, for example, an electroless plating film layer and an electrolytic plating film layer. Each conductor layer can be formed, for example, with any metal such as copper, nickel, silver, palladium, alone or in combination. The thickness of each of the first surface side conductor layer 3, the second surface side conductor layer 4, and the first conductor layer 31 is, for example, 5 μm or more and 30 μm or less.

The core insulating layer 5, the first interlayer insulating layer 32, and the second interlayer insulating layer 42 are formed by using an arbitrary insulating material. Examples of the insulating material include resin materials such as epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. Each insulating layer formed using these resin materials may contain a reinforcing material such as glass fiber or aramid fiber and / or an inorganic filler such as silica. When each build-up layer includes a plurality of interlayer insulating layers as in the example of FIG. 1, each interlayer insulating layer in each build-up layer may be formed by using the same resin material. Detachment between each interlayer insulation layer may be prevented. Further, for example, all the interlayer insulating layers, that is, the first interlayer insulating layer 32 in the first build-up layer 11 and the second interlayer insulating layer 42 in the second build-up layer 12 are made of the same insulating resin material. May be formed using. However, different resin materials may be used. The thickness of the interlayer insulating layer is, for example, 10 μm or more and 50 μm or less.

Each interlayer insulating layer includes via conductors 51 and 52 that connect the conductor layers formed on both sides of the interlayer insulating layers in the first build-up layer 11 and the second build-up layer 12. The first interlayer insulating layer 32 includes a via conductor 51, and the second interlayer insulating layer 42 includes a via conductor 52. The via conductors 51 and 52 are so-called filled vias formed by filling through holes penetrating each interlayer insulating layer with a conductor. The via conductors 51 and 52 are integrally formed with the conductor layer on the upper side (opposite side of the core substrate) of each. Therefore, the via conductors 51 and 52 and the first conductor layer 31 and the second conductor layer 41 are formed of the same plating film (electroless plating film and electrolytic plating film) made of, for example, copper or nickel. The through-hole conductor 50 formed through the core insulating layer 5 is also formed by an electroless plating film and an electrolytic plating film made of copper, nickel, or the like.

The wiring board 1 of the example of FIG. 1 further has a first solder resist layer 6 formed on the first build-up layer 11 and a second solder resist layer formed on the second build-up layer 12. 7 is included. The first solder resist layer 6 covers the first conductor layer 31 of the uppermost layer, and the second solder resist layer 7 covers the second conductor layer 41 of the uppermost layer. The first and second solder resist layers 6 and 7 are formed by using, for example, an epoxy resin or a polyimide resin.

An electronic component (not shown) such as a semiconductor element can be mounted on the first surface 1F of the wiring board 1 (that is, the upper surface side of the wiring board 1). The outermost first conductor layer 31 of the first build-up layer 11 of the wiring board 1 includes a plurality of connection pads 31a for being electrically connected to the terminals of such electronic components. The solder resist layer 6 has an opening for exposing the connection pad 31a.

FIG. 2 shows a bottom view of the wiring board 1 of FIG. FIG. 1 is a cross-sectional view including a cross section taken along the line II shown in FIG. In FIG. 2, the solder resist layer 7 in FIG. 1 is not shown. An external electric circuit board such as a motherboard, a package board, or the like can be connected on the second surface 1B of the wiring board 1 (that is, the lower surface side of the wiring board 1). In this case, as shown in FIG. 2, on the second surface 1B of the wiring board 1, for example, first connection pads 41a having two different shapes for connecting to such an external board or the like. And a second connection pad 41b may be formed. The second connection pad 41b may be separated (for example, into three) by the solder resist layer 7 which is omitted. Such first and second connection pads 41a and 41b are included in the outermost second conductor layer 41 of the second build-up layer 12 of the wiring board 1. As shown in FIG. 1, the solder resist layer 7 has an opening for exposing the connection pads 41a and 41b.

The first connection pad 41a and the second connection pad 41b are respectively arranged inside the outermost second conductor layer 41 by the via conductor 52 having a shape corresponding to the shape of each connection pad in the second build-up layer 12. It is connected to the second conductor layer 41 and / or the second surface side conductor layer 4 in the second build-up layer 12. As shown in FIG. 2, the first connection pad 41a may have a substantially circular shape in a plan view. Further, the second connection pad 41b may have a substantially oval shape in a plan view, for example. The "planar view" means that the wiring board 1 is viewed with a line of sight parallel to the thickness direction of the wiring board 1 with respect to the view when the wiring board 1 is viewed from the outside.

For example, the first connection pad 41a is a connection pad for signals, and is electrically connected to the first via conductor 52a for signals. The end surface of the first via conductor 52a on the second surface 1B side has a substantially circular shape in a plan view similar to the shape of the first connection pad 41a on the second surface 1B side. For example, the top diameter (diameter of the end surface on the second surface 1B side) d (hereinafter, also referred to as via diameter d, see FIG. 2) of the first via conductor 52a is about 55 μm or less. Here, the "top diameter" belongs to the outer circumference of the end surface on the second surface 1B side of the hole (first through hole 42a) in the second interlayer insulating layer 42 for forming the first via conductor 52a or the first via conductor 52a. It means the maximum value of the distance between two points.

On the other hand, for example, the second connection pad 41b is a connection pad for power supply. The second connection pad 41b is connected to the power supply layer 4b of the second surface side conductor layer 4 via the second via conductor 52b for power supply in the second build-up layer 12. The power supply layer 4b is connected to a through-hole conductor 50b for power supply. The end surface of the second via conductor 52b on the second surface 1B side has a substantially oval shape in a plan view similar to the shape of the second connection pad 41b on the second surface 1B side.

Therefore, the second build-up layer 12 of the wiring board 1 is arranged in the same second interlayer insulating layer 42 and is separated from each other, and has different shapes of via conductors 52 (first via conductors having a substantially circular shape in a plan view). A second via conductor 52b) having a substantially oval shape in a plan view is included. As described above, the via conductor 52 is formed by embedding a conductor such as a plating film in the through hole formed in the second interlayer insulating layer 42. For example, a first through hole 42a for the first via conductor 52a and a second through hole 42b for the second via conductor 52b are formed in the second interlayer insulating layer 421 (see FIG. 1) of the second build-up layer 12. Has been done. As shown in FIG. 2, for example, the second through hole 42b is a groove in which a plurality of through holes having substantially the same shape as the first through hole 42a having a substantially circular shape in a plan view are arranged so as to overlap each other in a row and communicate with each other. It has a similar structure. Therefore, the length w in the width direction (short direction) of the second through hole 42b in the plan view is 0.8 times or more and about 1.3 times or less the top diameter d of the first through hole 42a. is there. The top diameter d of the first through hole 42a is, for example, about 55 μm or less. Further, the length L in the longitudinal direction (length L in the direction orthogonal to the width) in the plan view of the second through hole 42b is, for example, 100 μm or more and 2000 μm or less. Therefore, the end surface of the second via conductor 52b formed by filling the groove-shaped second through hole 42b with plating on the second surface 1B side has a substantially oval shape in a plan view, and its width w is defined as. The top diameter d of the first via conductor 52a formed by filling the first through hole 42a with plating is about 0.8 times or more and 1.3 times or less, and the length L is 100 μm or more. , 2000 μm or less. When the second via conductor 52b for power supply has such a plan view shape, the amount of energization on the second surface 10B side of the core substrate 10 can be increased. It is considered that the power supply characteristics of the wiring board 1 can be improved and the power supply can be strengthened.

In the wiring board 1, the first via conductor 52a and the second via conductor 52b are simultaneously formed integrally with the electroless plating film layer and the electrolytic plating film layer constituting the second conductor layer 41. Therefore, when the shape of each through hole, especially the volume, is different, when the through hole is filled with plating, the through hole having a large volume is not completely filled with plating and a dent is formed in the through hole. It can happen. The flatness of the integrally formed second conductor layer 41 may decrease. Such dents in the second conductor layer 41 may affect the lamination of the next interlayer insulating layer and the conductor layer on the formed second conductor layer 41, resulting in a thickness imbalance or distortion in the process of manufacturing wiring. Can occur on the board. There is a possibility that a problem may occur in the patterning accuracy of the conductor layer laminated on the conductor layer. Alternatively, if a through hole having a large volume is sufficiently filled by plating so that such a dent does not occur, the amount of plating required for filling increases, so that the time required for the plating step becomes long. Therefore, the thickness of the second conductor layer 41 integrally formed at the same time as filling the through holes may increase. There is a risk that the thickness of the wiring board 1 as a whole in the stacking direction and the thickness of the first conductor layer 31 on the first build-up layer side that can be formed at the same time will increase.

In the present embodiment, the size of the first and second through holes 42a and 42b to be filled with plating, that is, the size of the diameter d or width w of the first and second via conductors 52a and 52b, and each through hole The thickness T (see FIGS. 4A and 4B) of the second conductor layer 41 integrally formed with the formed via conductor 52 (first via conductor 52a, second via conductor 52b) and the core of the second conductor layer 41. The depth D of the recess on the via conductor 52 (D1 and D2, see FIGS. 4A and 4B, respectively) on the surface facing away from the substrate (the surface on the second surface 1B side) is properly adjusted and selected. Has been done. As a result, even if via conductors 52 having different sizes are included in the same second interlayer insulating layer 42 in the second build-up layer 12, the increase in the layer thickness of the second build-up layer 12 can be suppressed. Can be done. Further, even if the second interlayer insulating layer 42 and the second conductor layer 41 are alternately laminated on the via conductor 52, and / or the number of layers of the second build-up layer 12 increases, the size is large. The second interlayer insulating layer 42 including the via conductors 52 having different characteristics can be formed so as to have good flatness. Therefore, it is possible to suppress deviation in patterning of the second conductor layer 41 formed on the second conductor layer 41. The correlation between the size of the diameter d or the width w of the via conductor 52, the thickness T of the second conductor layer 41, and the depth D of the recess obtained in the present embodiment is shown in FIG.

The depth D of the recess in the second conductor layer 41, which is acceptable to provide sufficient flatness in the lamination of the second build-up layer 12, is less than about 10 μm. As shown in FIG. 3, in the first via conductor 52a having a substantially circular shape in a plan view, the first through hole 42a is satisfactorily filled even if the second conductor layer 41 is thin, and the second conductor layer 41 is filled with the second conductor layer 41. Only dents with a small depth D occur. On the other hand, in the second via conductor 52b having a substantially oval shape in a plan view, in order to make the depth D of the recess in the second conductor layer 41 less than about 10 μm, the thickness T of the second conductor layer 41 of about 12 μm or more is set. It was necessary. Further, when the via diameter d of the first via conductor 52a having a substantially circular shape in a plan view is 49 μm, the width w in the lateral direction of the second via conductor 52b having a substantially circular shape in a plan view is 75 μm or more. Even if the thickness T of the second conductor layer 41 was adjusted, the depth D of the recess could not be less than 10 μm. On the other hand, unlike the width length w, even if the length L in the longitudinal direction of the second via conductor 52b having a substantially elliptical shape in a plan view changes, the depth D of the recess in the second conductor layer 41 changes significantly. Was not seen. It is considered that this is because the filling when the inside of the second through hole 42b is filled with plating is mainly performed from the direction parallel to the lateral direction.

When the width w in the lateral direction of the second via conductor 52b having a substantially oval shape in a plan view is made smaller than the via diameter d of the first via conductor 52a having a substantially circular shape in a plan view, the width length w. When w becomes smaller than 0.8 times the via diameter d, the dent in the second conductor layer 41 does not occur, but the amount of plating filled in the second through hole 42b becomes too large, and the second conductor A convex portion is formed on the layer 41. Therefore, together with the result shown in FIG. 3, the width w of the second via conductor 52b having a substantially circular shape in a plan view is 0.8 of the via diameter d of the first via conductor 52a having a substantially circular shape in a plan view. It is preferably more than double and 1.3 times or less. Further, the thickness T of the second conductor layer 41 is preferably about 12 μm or more. For example, preferably, the thickness T of the second conductor layer 41 is 12 μm or more and 30 μm or less.

4A and 4B show enlarged schematic views of the recessed portion when the surfaces of the second conductor layer 41 on the first via conductor 52a and the second via conductor 52b have recesses, respectively. It should be noted that FIGS. 4A and 4B are intended to explain the recessed portion on the surface of the second conductor layer 41 that may be caused by filling the inside of the first through hole 42a and the inside of the second through hole 42b with plating. The via conductor 52 on the second conductor layer 41 included in the wiring board 1 of FIG. 1 is not shown.

If a recess is formed on the first via conductor 52a and the second via conductor 52b on the surface of the second conductor layer 41 facing away from the core substrate (lower in FIGS. 4A and 4B), the recess is a wiring board. It is formed along the thickness direction Z of 1. The bottom surface of the recess is curved toward the second interlayer insulating layer 421 including the first via conductor 52a and the second via conductor 52b. The recess depths D1 and D2 are preferably less than 10 μm at the maximum. If it is 10 μm or more, good flatness in the lamination of each layer of the second build-up layer 12 laminated on it (lower in FIGS. 4A and 4B) may be lost. When the depths D1 and D2 of the respective recesses are less than 10 μm, for example, on the surface of the second conductor layer 41 facing the opposite side to the core substrate, the surface on the second via conductor 52b is formed substantially flat, and the first A dent may be formed on the surface of the 1 via conductor 52a. Further, of course, no dent is formed on either the first via conductor 52a or the second via conductor 52b on the surface of the second conductor layer 41 facing the opposite side to the core substrate (lower in FIGS. 4A and 4B). , The entire surface of the second conductor layer 41 facing the opposite side to the core substrate may be formed substantially flush with each other.

The cross-sectional shape of the recess is not limited to the shapes shown in FIGS. 4A and 4B, and any shape can be taken depending on the conditions for filling the through holes with plating, the shape of each through hole, and the like. For example, the recess may have a substantially conical or pyramidal shape with an apex angle rather than a surface at the deepest part of the recess. Further, the inner wall of the recess has a shape that is inclined with respect to the thickness direction Z of the wiring board 1 so as to be toward the center of the recess toward the second interlayer insulating layer 421 side as shown in FIGS. 4A and 4B. It does not have to be. However, in any case, the maximum depth D of the recessed portion is formed to be less than 10 μm.

As shown in FIG. 3, the thickness T of the second conductor layer 41 correlates with the recess depths D1 and D2 due to the manufacturing method of the second conductor layer 41 of the present embodiment. In the present embodiment, the thickness T of the second conductor layer 41 is 12 μm or more. Further, the thickness T of the second conductor layer 41 is preferably 30 μm or less from the viewpoint of suppressing an increase in the overall thickness of the wiring board 1. Further, the width w of the second via conductor 52b is formed so as to be 0.8 times or more and 1.3 times or less the via diameter d of the first via conductor 52a.

In the wiring board 1 of the present embodiment, the plurality of second interlayer insulating layers 42 in the second build-up layer 12 on the second surface 10B side of the core substrate 10 have a plurality of via conductors 52 having different shapes in the same layer (for example, It may be formed so as to include the first via conductor 52a and the second via conductor 52b). Further, the same second interlayer insulating layer 42 may contain three or more kinds of via conductors 52 having different shapes. Even in such a case, the diameter of the hole of the first via conductor 52a, the width of the groove of the second via conductor 52b, and the thickness T of the second conductor layer 41 are appropriately selected based on the correlation shown in FIG. The second conductor layer 41 having good flatness can be formed by combining the two conductor layers 41.

Next, using the wiring board 1 shown in FIG. 1 as an example, a method for manufacturing the wiring board of one embodiment will be described below with reference to FIGS. 5A to 5D.

As shown in FIG. 5A, a laminated plate having a core insulating layer 5 constituting the core substrate 10 and metal foils 3e provided on both sides of the core insulating layer 5 is prepared. For example, a double-sided copper-clad laminate having a metal foil 3e made of copper is prepared.

As shown in FIG. 5B, the through hole 55 is formed by irradiation with carbon dioxide gas laser light or the like, and includes, for example, a copper foil, a copper electroless plating film, and an electrolytic plating film by using a subtractive method. The first surface side conductor layer 3 and the second surface side conductor layer 4 having a desired conductor pattern are formed on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively. Further, the through-hole conductor 50 is formed by embedding the electroless plating film and the electrolytic plating film in the through hole 55. The through-hole conductor 50 includes a through-hole conductor 50b for a power source, and a through-hole conductor 50b for a power source is also formed at the same time as another through-hole conductor 50.

As shown in FIG. 5C, the first interlayer insulating layer 32 and the second interlayer insulating layer 42 are formed. Further, the first conductor layer 31 is formed on the first interlayer insulating layer 32. Along with the formation of the first conductor layer 31, the second conductor layer 41 is formed on the second interlayer insulating layer 42. In the formation of the first conductor layer 31, the via conductor 51 is formed in the first interlayer insulating layer 32. Further, in the formation of the second conductor layer 41, the via conductor 52 is formed in the second interlayer insulating layer 42.

For the first and second interlayer insulating layers 32 and 42, for example, a prepreg containing a semi-cured epoxy resin and a reinforcing material such as glass fiber, or a film-shaped epoxy resin is laminated on both sides of the core substrate 10. It is formed by heat crimping. When laminating the prepreg, a metal foil made of, for example, copper may be laminated on the prepreg and crimped together with the prepreg. After that, for example, by irradiating carbon dioxide laser light, a through hole 32a for forming the via conductor 51 is formed in the first interlayer insulating layer 32.

In the wiring board 1 of the example of FIG. 1, among the second interlayer insulating layers 42 of the second build-up layer 12, the first vias having different shapes are contained in the second interlayer insulating layer 421 that is most laminated on the core substrate side. A conductor 52a and a second via conductor 52b are formed. Therefore, in the present embodiment, the second interlayer insulating layer 42 formed on the second surface 10B of the core substrate 10 is the second interlayer insulating layer 421. The first via conductor 52a for the first via conductor 52a is irradiated with, for example, CO ₂ laser light, on the second interlayer insulating layer 421 at a position corresponding to the place where the via conductor 52 (first via conductor 52a and second via conductor 52b) is formed. A through hole 42a and a second through hole 42b for the second via conductor 52b are formed, respectively. The second through hole 42b is formed by perforating a plurality of through holes having substantially the same shape as the first through hole 42a laterally and vertically. At this time, the through holes are arranged so that a part of the adjacent through holes overlap each other, and as a result, a groove-shaped second through hole 42b having a substantially oval shape in a plan view is formed in which the through holes communicate with each other. To.

Then, for example, using a semi-additive method, a metal film obtained by electroless copper plating or the like and an electrolytic plating film formed on the metal film using this metal film as a seed layer are formed, and the first and first one having a desired conductor pattern. The second conductor layers 31, 41, and the via conductor 51 and the via conductor 52 (the first via conductor 52a having a substantially circular shape in a plan view and the second via conductor 52b having a substantially oval shape in a plan view) are formed. The conductor layer integrally formed with the first via conductor 52a and the second via conductor 52b is formed so as to have a thickness of 12 μm or more.

For example, by applying a general method for manufacturing a build-up wiring board using a semi-additive method, on the first conductor layer 31 and the second conductor layer 41 of FIG. 5C, the first interlayer insulating layer 32 and the first interlayer insulating layer 32 and the second conductor layer 41 are further applied. The first conductor layer 31, the second interlayer insulating layer 42, and the second conductor layer 41 are formed, and the first build-up layer 11 and the second build-up are formed on the first surface 10F and the second surface 10B of the core substrate 10. Layers 12 are formed respectively (FIG. 5D). A via conductor 51 is formed on the laminated first interlayer insulating layer 32. A via conductor 52 is formed on the laminated second interlayer insulating layer 42. The via conductor 52 may also include via conductors 52 having different shapes (for example, the first via conductor 52a and the second via conductor 52b). For example, the second via conductor 52b having a substantially oval shape in a plan view may be formed by performing the same process as the process of FIG. 5C. Also in this case, the conductor layer integrally formed with the second via conductor 52b is formed so as to have a thickness of 12 μm or more. Further, a via conductor 52 having the same substantially oval shape in a plan view is formed on the second via conductor 52b having a substantially oval shape in a plan view formed in the second interlayer insulating layer 421 so as to overlap in a plan view. You may. That is, the wiring board 1 may be formed so as to include a stack via conductor of the second via conductor 52b that connects the second connection pad 41b and the power supply layer 4b. Power enhancement may be better.

In FIG. 5D, the first and second build-up layers 11 and 12, which are composed of two interlayer insulating layers and a conductor layer, respectively, are formed on the first surface 10F side and the second surface 10B side of the core substrate. However, the number of layers of the interlayer insulating layer and the conductor layer in the buildup layers 11 and 12 is not limited to this example, and the buildup includes a larger number of layers by repeating the above buildup process. Layers may be formed.

After that, the solder resist layer 6 is formed on the first build-up layer 11, and the solder resist layer 7 is formed on the second build-up layer 12. The solder resist layers 6 and 7 are formed by, for example, forming a resin layer containing a photosensitive epoxy resin, a polyimide resin, or the like, exposure using a mask having an appropriate pattern, and development.

The connection pads 31a, 41a, 41b exposed to the openings of the solder resist layers 6 and 7 may be subjected to electroless plating, solder leveler, spray coating or the like, if necessary, to Au, Ni / Au, Ni / Pd / Au. A surface protective film (not shown) made of solder, heat-resistant preflux, or the like may be formed. By going through the above steps, the wiring board 1 of the example of FIG. 1 is completed.

The wiring board of the embodiment is not limited to the structure exemplified in each drawing and the structure, shape, and material exemplified in this specification. For example, the via conductors 51, 52 and the like do not have to have a shape in which the diameter is reduced toward the core substrate 10. Further, the solder resist layers 6 and 7 may not be provided.

Further, the method for manufacturing the wiring board of the embodiment is not limited to the method described above with reference to each drawing. For example, the core substrate 10 may be formed by using a semi-additive method using a copper foil. Each conductor layer in the first and second build-up layers 11 and 12 may be formed by using a subtractive method. The conditions and order of the manufacturing method described above can be changed as appropriate. Depending on the structure of the wiring board actually manufactured, some steps may be omitted or another step may be added.

1 Wiring board 1F First side of wiring board 1B Second side of wiring board 5 Core insulating layer 10 Core board 10F First side of core board 10B Second side of core board 11 First build-up layer 12 Second build-up layer 3 1st surface side conductor layer 4 2nd surface side conductor layer 4b Power supply layer 31 1st conductor layer 32 1st interlayer insulating layer 41 2nd conductor layer 41a 1st connection pad 41b 2nd connection pad 42 2nd interlayer insulating layer 50 Through-hole conductors 51 and 52 Via conductors 52a First via conductor 52b Second via conductors 6, 7 Solder resist layer

Claims (12)

The first surface has a first surface and a second surface opposite to the first surface, and penetrates the core insulating layer, the first surface side conductor layer, the second surface side conductor layer, and the core insulating layer. A core substrate including a surface-side conductor layer and a through-hole conductor connecting the second surface-side conductor layer, and
A first build-up layer provided on the first surface of the core substrate and having a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer alternately laminated.
A second build-up layer provided on the second surface of the core substrate and having a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer alternately laminated.
The first via conductor and the second via conductor that penetrate the second interlayer insulating layer and connect the conductor layers on both sides of the second interlayer insulating layer,
It is a wiring board equipped with
The first via conductor is formed by penetrating the second interlayer insulating layer and filling holes having a predetermined top diameter with plating.
The second via conductor has a predetermined width that is 0.8 times or more and 1.3 times or less the top diameter of the hole through which the first via conductor is formed and penetrates the second interlayer insulating layer. It is formed by filling the groove with plating with plating.
The second conductor layer has no recess or has a recess of less than 10 μm on the first via conductor and the second via conductor on the surface facing the opposite side of the core substrate. There is. The wiring board according to claim 1, wherein the top diameter of the hole on which the first via conductor is formed is 55 μm or less. The wiring board according to claim 1, wherein the groove on which the second via conductor is formed has a predetermined length of 100 μm or more and 2000 μm or less in a direction orthogonal to the width. The thickness of the conductor layer on the side opposite to the core substrate of the conductor layers on both sides of the second interlayer insulating layer including the first via conductor and the second via conductor in the wiring board according to claim 1. It is 12 μm or more. The conductor layer on the core substrate side of the conductor layers on both sides of the second interlayer insulating layer including the first via conductor and the second via conductor in the wiring board according to claim 1 is a power supply layer. is there. The wiring board according to claim 1, wherein the first via conductor has a substantially circular shape in a plan view, and the second via conductor has a substantially oval shape in a plan view. In the wiring board according to claim 1, the groove in which the second via conductor is formed has a plurality of holes having substantially the same shape as the hole in which the first via conductor is formed so as to overlap in a row. It has a structure formed by being arranged in. The wiring board according to claim 1, wherein the first via conductor is a signal via conductor, and the second via conductor is a power supply via conductor. A core substrate having a first surface and a second surface opposite to the first surface and including a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer is provided.
A first build-up layer in which the first interlayer insulating layer and the first conductor layer on the first interlayer insulating layer are alternately laminated is provided on the first surface of the core substrate.
A second build-up layer in which a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated is provided on the second surface of the core substrate.
It is a manufacturing method of a wiring board including
Providing the second build-up layer is a first via conductor that connects the second conductor layers on both sides of the second interlayer insulating layer into the same second interlayer insulating layer in the second build-up layer. And the formation of the second via conductor at the same time
Forming the first via conductor includes filling a hole having a predetermined top diameter through the second interlayer insulating layer with plating.
Forming the second via conductor is predetermined to be 0.8 times or more and 1.3 times or less the top diameter of the hole through which the first via conductor is formed through the second interlayer insulating layer. Includes filling a groove with a width of. The method for manufacturing a wiring board according to claim 9, wherein forming the first via conductor includes filling the holes having a top diameter of 55 μm or less with plating. The method for manufacturing a wiring board according to claim 9, wherein the second via conductor is formed by plating the groove having a predetermined length of 100 μm or more and 2000 μm or less in a direction orthogonal to the width. Includes filling. The method for manufacturing a wiring board according to claim 9, wherein the second build-up layer is provided with the core substrate of the second conductor layer on the first via conductor and the second via conductor. It involves forming the second conductor layer so that the opposite surface is substantially flat or has a recess of less than 10 μm.

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