JP2017084843A - Circuit board and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board capable of suppressing a trouble caused by heat generation of an electronic component mounted on the circuit board, and a method for manufacturing the same.SOLUTION: A circuit board 10 comprises a core substrate 11 incorporating a metal block 17, and a build-up layer 20 laminated on both surfaces of the core substrate 11 and including a via conductor 51. A diameter of a small via conductor 51FS on the F surface side connected from the 11F side of the F surface of the core substrate 11 to the metal block 17 is smaller than a diameter of a large via conductor 51BL on the B surface side connected from the 11B side of the B surface of the core substrate 11 to the metal block 17. The number of small via conductors 51FS on the F surface side connected to the metal block 17 is greater than the number of large via conductors 51BL on the B surface side connected to the metal block 17.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a circuit board in which a buildup layer is laminated on a core substrate having a cavity, and a method for manufacturing the circuit board.

  Conventionally, as this type of circuit board, an electronic component housed in a cavity is connected to an electronic component (for example, a semiconductor element) mounted on the circuit board via a via conductor or the like. (For example, refer to Patent Document 1).

JP2013-135168A (paragraphs [0028] to [0030], FIG. 3B)

  However, in the above-described conventional circuit board, when the heat generated by the electronic components mounted on the circuit board is accumulated, the circuit board is warped by heat, and it is considered that problems such as disconnection occur.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board capable of suppressing problems caused by heat generation of electronic components mounted on the circuit board and a method for manufacturing the circuit board.

  The circuit board according to the present invention made to achieve the above object is laminated on a core board having a cavity in which a metal block is accommodated, a first surface and a second surface, which are both surfaces of the core board, and A build-up layer having via conductors, a mounting portion provided on the outermost side of the first build-up layer stacked on the first surface side of the build-up layer, and mounted with an electronic component; and the build-up layer A circuit board having a board connection portion provided on the outermost side of the second buildup layer laminated on the second surface side of the layers and connected to another circuit board, and serving as the via conductor A first via conductor provided in the first buildup layer and connected to the metal block; and a second via conductor provided in the second buildup layer and connected to the metal block. The first via Smaller than the diameter of the diameter of the body the second via conductor, and the number of the first via conductor is larger than the number of the second via conductor.

  The method for manufacturing a circuit board according to the present invention includes preparing a core substrate having a cavity in which a metal block is accommodated, and providing build-up layers on the first surface and the second surface that are both surfaces of the core substrate. Stacking, forming a via conductor in the build-up layer, and providing a mounting portion on which an electronic component is mounted on the outermost part of the build-up layer stacked on the first surface side; A circuit board manufacturing method comprising: providing a board connection portion connected to another circuit board on the outermost part of the buildup layer laminated on the second surface side, wherein the via conductor is formed. In doing so, the first via conductor on the first surface side and the second via conductor on the second surface side are formed, and the diameter of the first via conductor is smaller than the diameter of the second via conductor. And before the number of the second via conductors. Increasing the number of first via conductors.

The top view of the circuit board concerning a 1st embodiment of the present invention. Plan view of product area on circuit board FIG. 2 is a side sectional view of the circuit board taken along the line AA of FIG. Enlarged view around the metal block in FIG. (A) The figure which shows arrangement | positioning of the metal block and via conductor when seen from the F surface side, (B) The figure which shows arrangement of the metal block and via conductor when seen from the B surface side Enlarged side sectional view around the edge of the metal block Side view showing the manufacturing process of electrolytic copper foil Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view showing circuit board manufacturing process Side sectional view of PoP including circuit board Side sectional view of the circuit board of the second embodiment Side sectional view of circuit board according to modification Side sectional view of circuit board according to modification Side sectional view of circuit board according to modification

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. As shown in the plan view of FIG. 1, the circuit board 10 according to the present embodiment has, for example, a frame-shaped discarding region R1 along the outer edge, and the inside of the discarding region R1 is a plurality of squares. It is partitioned into product areas R2. FIG. 2 shows an enlarged view of one product region R2, and FIG. 3 shows an enlarged cross-sectional structure of the circuit board 10 obtained by cutting the product region R2 along the line AA shown in FIG. ing.

  As shown in FIG. 3, the circuit board 10 has a structure having build-up layers 20 and 20 on both front and back surfaces of the core board 11. The core substrate 11 includes an F surface 11F (corresponding to the “first surface” of the present invention) that is the front surface of the insulating base 11K and a B surface 11B (the “second surface” of the present invention) that is the back surface. And the conductor circuit layers 12 and 12 are formed. The insulating base 11K is formed with a cavity 16 and a plurality of conductive through holes 14. Hereinafter, the F surface 11F and the B surface 11B of the insulating base material 11K will be referred to as the F surface 11F and the B surface 11B of the core substrate 11 as appropriate.

  The conductive through-hole 14 communicates with the small diameter side ends of the tapered holes 14A and 14A, which are perforated from both the F surface 11F and the B surface 11B of the insulating base material 11K and gradually reduce in diameter toward the back side. It has an intermediate constricted shape. A plurality of through-hole conductive conductors 15 are formed in each through-hole 14 for conduction to form a plurality of through-hole conductive conductors 15, and the conductive circuit layer 12 on the F surface 11 F and the conductive circuit layer 12 on the B surface 11 B are formed by these through-hole conductive conductors 15. Is connected.

  The cavity 16 has a shape having a rectangular parallelepiped space. A metal block 17 is accommodated in the cavity 16. The metal block 17 is a rectangular parallelepiped made of copper, for example, and the planar shape of the metal block 17 is slightly smaller than the planar shape of the cavity 16. Further, the thickness of the metal block 17, that is, the distance between the first main surface 17 </ b> F that is one surface of the metal block 17 and the second main surface 17 </ b> B that is the other surface of the metal block 17. Is slightly larger than the thickness of the core substrate 11. The metal block 17 slightly protrudes from the F surface 11F and the B surface 11B of the core substrate 11, and the first main surface 17F of the metal block 17 is the outermost surface of the conductor circuit layer 12 on the F surface 11F of the core substrate 11. On the other hand, the second main surface 17B of the metal block 17 is substantially flush with the outermost surface of the conductor circuit layer 12 on the B surface 11B of the core substrate 11. A gap between the metal block 17 and the inner surface of the cavity 16 is filled with a filling resin 16J. The cavity 16 may have a shape having a tapered space.

  The first main surface 17F and the second main surface 17B of the metal block 17 have substantially the same area and are parallel to each other. The four side surfaces between the outer edge portion of the first main surface 17F and the outer edge portion of the second main surface 17B in the metal block 17 are deeper toward the center between the first main surface 17F and the second main surface 17B. The groove side surface 17A is curved so as to be.

  FIG. 6 shows an enlarged view of a part of the metal block 17. As shown in the figure, the first main surface 17F and the second main surface 17B of the metal block 17 (that is, both the front and back surfaces of the metal block 17) are rough surfaces. Specifically, the arithmetic average roughness Ra of the first main surface 17F of the metal block 17 is, for example, 0.16 [μm], while the arithmetic average roughness Ra of the second main surface 17B is, for example, 2.1. [Μm], and the roughness of the first main surface 17F of the metal block 17 is smaller than the roughness of the second main surface 17B (as defined in JIS B 0601-1994).

  In addition, the manufacturing method of the metal block 17 is as follows. That is, first, copper is attached to the electrode 91 having a rough surface to produce the electric field copper foil 60 (see FIG. 7). Next, after roughening treatment is performed on both the front and back surfaces of the electrolytic copper foil 60, the electrolytic copper foil 60 is cut by sequentially subjecting the electric field copper foil 60 to half-etching treatment and etching treatment, whereby the metal block 17 is cut. Is obtained. In this method of manufacturing the metal block 17, the surface of the electrolytic copper foil 60 that is in contact with the electrode 91 becomes a rough surface by transferring the shape of the rough surface of the electrode 91, while the opposite surface is relatively smooth. It becomes.

  As shown in FIG. 3, the build-up layer 20 on the F surface 11F side of the core substrate 11 (corresponding to the “first build-up layer” in the present invention) is also the build-up layer 20 on the B surface 11B side (in the present invention). The first insulating resin layer 21, the first conductor layer 22, the second insulating resin layer 23, and the second conductor layer 24 are also sequentially formed from the core substrate 11 side. A solder resist layer 25 is laminated on the second conductor layer 24. A plurality of via holes 52 and 54 are formed in the first insulating resin layer 21 and the second insulating resin layer 23, respectively. Further, the via holes 52 and 54 are filled with plating to form a plurality of via conductors 51 and 53. The via conductor 51 of the first insulating resin layer 21 connects between the conductor circuit layer 12 and the first conductor layer 22 and between the metal block 17 and the first conductor layer 22, and the second insulating resin. The first conductor layer 22 and the second conductor layer 24 are connected by the via conductor 53 of the layer 23. Hereinafter, the via conductors 51 and 53 and the via holes 52 and 54 formed in the buildup layer 20 on the F surface 11F side of the core substrate 11 are appropriately referred to as “F surface side via conductors 51F and 53F” and “F surface side via hole 52F,” The via conductors 51 and 53 and the via holes 52 and 54 formed in the buildup layer 20 on the B surface 11B side are referred to as “B side via conductors 51B and 53B” and “B side via holes 52B and 54B”. .

  The F-side via conductor 51F has a larger diameter than the F-side via conductor 51FS (hereinafter referred to as “F-side small via conductor 51FS”) connected to the metal block 17 and the F-side via conductor 51FS. F-side via conductors 51FL connected to the conductor circuit layer 12 (hereinafter referred to as “F-side large via conductors 51FL”). On the other hand, the F-plane side via conductor 53F includes only an F-plane side via conductor 53FL (hereinafter referred to as “F-plane side large via conductor 53FL”) having substantially the same diameter as the F-plane side large via conductor 51FL. The F-side large via conductors 51FL and 53FL have a tapered shape in which the diameter of the core substrate 11 is reduced. Also, as shown in FIG. 4, the F-side small via conductor 51FS is tapered or cylindrical with a smaller taper angle than the F-side large via conductors 51FL and 53FL (FIG. 4 shows the cylindrical F-side side). A small via conductor 51FS is shown). Further, in the circuit board 10 of the present embodiment, at least a part of the plurality of F-plane side small via conductors 51FS includes one F-plane side large via conductor 51FS via the first conductor layer 22. It is connected to the via conductor 53FL. The F-plane side small via conductor 51FS corresponds to the “first via conductor” of the present invention, and the F-plane side large via conductor 51FL corresponds to the “third via conductor” of the present invention.

  The B-side via conductors 51B and 53B are B-side via conductors 51BL and 53BL (hereinafter referred to as “B-side large via conductors 51BL and 53BL”) having substantially the same diameter as the F-side large via conductors 51FL and 53FL. It is configured. Among the plurality of B-side large via conductors 51BL, some of the B-side large via conductors 51BL (corresponding to the “second via conductor” of the present invention) are connected to the metal block 17 (see FIG. 4). The remaining B-side large via conductor 51BL is connected to the conductor circuit layer 12. The B-side large via conductors 51BL and 53BL have a tapered shape in which the diameter of the core substrate 11 is reduced, like the F-side large via conductors 51FL and 53FL.

  That is, in the circuit board 10 of the present embodiment, the F-side small via conductor 51FS connected to the metal block 17 from the F-side 11F side of the core board 11 is connected to the B-side large via conductor connected from the B-side 11B side. The diameter is smaller than 51BL. Specifically, the diameter φ2 of the B-side large via conductor 51BL is 40 to 70 μm (top diameter) on the side far from the core substrate 11 and 30 to 60 μm (bottom diameter) on the side close to the core substrate 11. . Further, the diameter φ1 of the F-side small via conductor 51FS is 10 to 30 μm.

  FIGS. 5A and 5B show the arrangement of the F-side small via conductor 51FS and the B-side large via conductor 51BL connected to the metal block 17. FIG. For example, the F-side small via conductors 51FS are arranged in 4 rows and 3 columns and connected to the first main surface 17F of the metal block 17 (see FIG. 5A). On the other hand, the B-side large via conductor 51BL is, for example, arranged in 2 rows and 2 columns and connected to the second main surface 17B of the metal block 17 (see FIG. 5B). Thus, in this embodiment, the number (for example, twelve) of the F-side small via conductors 51FS connected to the metal block 17 from the F-side 11F side is larger than the B-side side connected from the B-side 11B side. More than the number of via conductors 51BL (for example, four).

  Further, as shown in FIGS. 5A and 5B, the distance between the F-side small via conductors 51FS and 51FS (the pitch of the F-side small via conductor 51FS) is the B-side large via conductor. It is narrower than the interval between 51BL and 51BL (pitch of the B-side large via conductor 51BL). Specifically, the pitch of the B-side large via conductor 51BL is 130 to 170 μm, and the pitch of the F-side small via conductor 51FS is 45 to 55 μm. And in the circuit board 10 of this embodiment, the sum total of the connection area of the metal block 17 and the some F surface side small via conductor 51FS is the connection area of the metal block 17 and the some B surface side large via conductor 51BL. It is larger than the total.

  As shown in FIG. 3, a plurality of openings for bumps are formed in the solder resist layer 25, and portions exposed from the openings in the second conductor layer 24 serve as pads 26. Note that a metal film 41 having a three-layer structure including a nickel layer, a palladium layer, and a gold layer is formed on each pad 26.

  As shown in FIGS. 2 and 3, the F surface 10F of the circuit board 10 that is the outermost surface of the buildup layer 20 on the F surface 11F of the core substrate 11 is large as the F surface side of the F surface 10F. Two types of pads 26FA and F-side small pads 26FB are provided. The F-side large pad 26FA group is arranged in two rows along the outer edge of the product region R2, and the F-side small pad 26FB group is arranged in an inner region surrounded by the F-side large pad 26FA group. Thus, the electronic component mounting portion 26J (corresponding to the “mounting portion” of the present invention) is configured. Further, as shown in FIG. 2, the metal block 17 is disposed at a position directly below the F-plane side small pads 26FB group. Then, as shown in FIG. 3, the F-side small pads 26FB group are connected to the metal block 17 via via conductors 51F and 53F (specifically, the F-side small via conductor 51FS and the F-side large via conductor 53FL). It is connected to the.

  As shown in FIG. 3, on the B surface 10B of the circuit board 10 that is the outermost surface of the buildup layer 20 on the B surface 11B side of the core substrate 11, the pads 26 are substantially the same as the F-side large pads 26FA described above. Only one type of large B-side large pad 26BA is provided. The B-side large pads 26BA group constitutes a board connecting portion according to the present invention. A part of the B-side large pad 26BA is connected to the metal block 17 via via conductors 51B and 53B (B-side large via conductors 51BL and 53BL).

The circuit board 10 of this embodiment is manufactured as follows.
(1) As shown in FIG. 8 (A), copper foil 11C is laminated on both front and back surfaces of an insulating base material 11K made of a reinforcing material such as epoxy resin or BT (bismaleimide triazine) resin and glass cloth. A copper-clad laminate 11Z is prepared.

  (2) As shown in FIG. 8 (B), for example, a CO2 laser is irradiated on the copper-clad laminate 11Z from the F surface 11F side of the insulating base material 11K to form a conductive through hole 14 (see FIG. 3). A taper hole 14A is formed.

  (3) As shown in FIG. 8C, the taper hole 14A is perforated by irradiating the CO2 laser to the position directly behind the taper hole 14A on the F surface 11F side in the copper clad laminate 11Z. A conductive through hole 14 is formed from the tapered holes 14A, 14A.

  (4) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 11 </ b> C and the inner surface of the conductive through hole 14.

  (5) As shown in FIG. 8D, a predetermined pattern of plating resist 33 is formed on the electroless plating film on the copper foil 11C.

  (6) The electrolytic plating process is performed, and as shown in FIG. 9A, the electrolytic plating is filled in the conductive through holes 14 to form the through-hole conductive conductors 15 and the copper foil 11C on the copper foil 11C. An electrolytic plating film 34 is formed on a portion of the electrolytic plating film (not shown) exposed from the plating resist 33.

  (7) While the plating resist 33 is peeled off, the electroless plating film (not shown) and the copper foil 11C below the plating resist 33 are removed, and the remaining electrolytic plating is performed as shown in FIG. 9B. The conductor circuit layer 12 is formed on the F surface 11F of the insulating substrate 11K and the conductor circuit layer 12 is formed on the B surface 11B of the insulating substrate 11K by the film 34, the electroless plating film, and the copper foil 11C. It is formed. Then, the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the B surface 11B are connected by the through-hole conductive conductor 15. Thereby, the core substrate 11 is obtained.

  (8) As shown in FIG. 9C, a cavity 16 is formed in the core substrate 11 by a router or a CO2 laser.

  (9) As shown in FIG. 9D, a tape 90 made of a PET film is stuck on the F surface 11 </ b> F of the core substrate 11 so that the cavity 16 is closed.

  (10) Metal blocks 17 having different roughness on the front and back surfaces manufactured by the method described above are prepared. At this time, the plurality of metal blocks 17 are arranged in advance in a state where, for example, the first main surface 17F (the surface with the lower roughness) is down.

  (11) As shown in FIG. 10A, the metal block 17 is stored in the cavity 16 with the first main surface 17F facing down by a mounter (not shown).

  (12) As shown in FIG. 10B, a prepreg containing an inorganic filler as the first insulating resin layer 21 on the conductor circuit layer 12 on the B surface 11B of the core substrate 11 (containing an inorganic filler in the core material) A B-stage resin sheet impregnated with a resin to be impregnated) and the copper foil 37 are laminated and then heated and pressed. At that time, the space between the conductor circuit layers 12 and 12 on the B surface 11B of the core substrate 11 is filled with the prepreg, and the thermosetting resin exuded from the prepreg is filled in the gap between the inner surface of the cavity 16 and the metal block 17. Is done.

  (13) As shown in FIG. 10C, the tape 90 is removed.

  (14) As shown in FIG. 10 (D), the prepreg as the first insulating resin layer 21 and the copper foil 37 are laminated on the conductor circuit layer 12 on the F surface 11F of the core substrate 11, and then heated and pressed. The At that time, the space between the conductor circuit layers 12 and 12 on the F surface 11F of the core substrate 11 is filled with the prepreg, and the thermosetting resin exuded from the prepreg is filled in the gap between the inner surface of the cavity 16 and the metal block 17. Is done. In addition, the above-described filling resin 16J is formed by the thermosetting resin that oozes out from the prepreg of the F surface 11F and the B surface 11B of the core substrate 11 and fills the gap between the inner surface of the cavity 16 and the metal block 17.

  Note that a resin film (not including a core material) containing an inorganic filler may be used as the first insulating resin layer 21 instead of the prepreg. In that case, a conductor circuit layer can be directly formed on the surface of the resin film by a semi-additive method without laminating a copper foil.

  (15) As shown in FIG. 11A, a plurality of via holes 52 are formed by irradiating the first insulating resin layers 21 and 21 on both sides of the core substrate 11 formed by the prepreg with laser. The The plurality of via holes 52 are disposed on the conductor circuit layer 12 and the metal block 17. At this time, the unevenness of the rough surface of the metal block 17 located on the back side of the via hole 52 may be eliminated by laser light irradiation or desmear processing after irradiation.

  In forming the F surface side via hole 52F disposed on the F surface 11F side of the core substrate 11 in the via hole 52, the F surface side via hole 52F disposed on the metal block 17 is formed as the other F surface side via hole 52F. It is formed using a laser having a shorter wavelength than the laser used in the above. Specifically, an ultraviolet laser (for example, YAG laser) is used to form the F-plane side via hole 52F on the metal block 17, and an infrared laser (for example, CO2 is used to form the other F-side via hole 52F. Laser). As a result, the F-surface side small via hole 52FS (corresponding to the “first via hole” of the present invention) disposed on the metal block 17 and the conductor circuit layer 12 are formed in the first insulating resin layer 21 on the F surface 11F side. The F-side large via hole 52FL disposed above is formed.

  In forming the B surface side via hole 52B disposed on the B surface 11B side of the core substrate 11 in the via hole 52, an infrared laser is used. Then, as the B-side via hole 52, a B-side large via hole 52BL having the same size as the F-side large via hole 52FL on the F-plane 11F side is formed. Of the plurality of B-side large via holes 52BL, a part of the B-side large via holes 52BL arranged on the metal block 17 corresponds to the “second via hole” of the present invention.

  Further, in forming the via holes 52 arranged on the metal block 17, the interval (pitch) between the F-side small via holes 52FS and 52FS on the F-side 11F side is set to the B-side large via hole 52BL on the B-side 11B side. It is narrower than the interval (pitch) between the 52BLs, and the number of F-side small via holes 52FS is made larger than the number of B-side large via holes 52BL.

  (16) When a plurality of via holes 52 are formed in the first insulating resin layers 21, 21, an electroless plating process is performed, and an electroless plating film is formed on the first insulating resin layers 21, 21 and in the via holes 52. (Not shown) is formed.

  (17) As shown in FIG. 11B, a predetermined pattern of plating resist 40 is formed on the electroless plating film on the copper foil 37.

  (18) An electrolytic plating process is performed, and as shown in FIG. 11C, the plating is filled in the via holes 52 to form the via conductors 51. Furthermore, there is no plating on the first insulating resin layers 21 and 21. Electrolytic plating films 39 and 39 are formed on portions of the electrolytic plating film (not shown) exposed from the plating resist 40. At this time, on the F surface 11 side of the core substrate 11, the F surface side small via conductor 51FS is formed in the F surface side small via hole 52FS, and the F surface side large via conductor 51FL is formed in the F surface side large via hole 52FL. The Further, on the B surface 11B side of the core substrate 11, the B surface side large via conductor 51BL is formed in the B surface side large via hole 52BL.

  (19) The plating resist 40 is peeled off, and the electroless plating film (not shown) and the copper foil 37 below the plating resist 40 are removed. As shown in FIG. The first conductor layer 22 is formed on the first insulating resin layers 21 on the front and back of the core substrate 11 by the film 39, the electroless plating film, and the copper foil 37. And while a part of each 1st conductor layer 22 of the front and back of the core board | substrate 11 and the conductor circuit layer 12 are connected by the via conductor 51, another part of each 1st conductor layer 22 and the metal block 17 are The via conductor 51 is connected.

  (20) By the same processing as the above (12) to (19), the second insulating resin layer 23 and the second insulating resin layer 23 are formed on the first conductor layers 22 on the front and back of the core substrate 11 as shown in FIG. The two conductor layers 24 are formed, and a part of each second conductor layer 24 and the first conductor layer 22 are connected by the via conductor 53. Here, the via holes 54 for forming the via conductors 53 are formed using an infrared laser, and all the via holes 54 have substantially the same size as the F-side large via holes 52FL and the B-side large via conductors 52BL. The via holes are 54FL and 54BL. As the via conductor 53, via conductors 53FL and 53BL having substantially the same size as the F-side large via conductor 51FL and the B-side large via conductor 51BL are formed. That is, all the F-side via holes 54F arranged on the F-plane 11F side become F-side large via holes 54FL, and all the B-side via holes 54B arranged on the B-side 11B side become B-side large via holes 54BL. . Further, all the F-side via conductors 53F arranged on the F-side 11F side become the F-side large via conductors 53FL, and all the B-side via conductors 53B arranged on the B-side 11B side become the B-side large vias. It becomes the conductor 53BL.

  (21) As shown in FIG. 12C, solder resist layers 25, 25 are laminated on the second conductor layers 24 on the front and back sides of the core substrate 11.

  (22) As shown in FIG. 13, bump openings are formed at predetermined positions of the solder resist layers 25, 25 on the front and back of the core substrate 11, and the openings of the second conductor layers 24 on the front and back of the core substrate 11 are opened. The portion exposed from the portion becomes the pad 26.

  (23) A nickel layer, a palladium layer, and a gold layer are laminated on the pad 26 in this order, and the metal film 41 shown in FIG. Thus, the circuit board 10 is completed. Instead of the metal film 41, surface treatment with OSP (preflux) may be performed.

  This completes the description of the structure and manufacturing method of the circuit board 10 of the present embodiment. Next, the effect of the circuit board 10 will be described together with an example of use of the circuit board 10. The circuit board 10 of this embodiment is used as follows, for example. That is, as shown in FIG. 14, on the F surface 10F side of the circuit board 10, on the F surface side large pad 26FA and the F surface side small pad 26FB, the F surface side large size that matches the size of each pad. Solder bumps 27FA and F-side small solder bumps 27FB are formed. Then, for example, a CPU 80 (corresponding to the “electronic component” of the present invention) having a pad group on the lower surface with the same arrangement as the F surface side small pad 26FB group is an F surface side small solder bump 27FB group in each product region R2. The first package substrate 10P is formed by being mounted thereon and soldered. At this time, for example, twelve pads for ground included in the CPU 80 are connected to the metal block 17 of the circuit board 10 via the via conductors 51 and 53.

  Next, a second package substrate 82P formed by mounting the memory 81 on the F surface 82F of the circuit board 82 is disposed on the first package substrate 10P from above the CPU 80, and the circuit board 82 in the second package substrate 82P is disposed. A large solder bump 27FA on the F surface side of the circuit board 10 in the first package substrate 10P is soldered to a pad provided on the B surface 82B to form a PoP 83 (Package on Package 83). Note that a resin (not shown) is filled between the circuit boards 10 and 82 in the PoP 83.

  Next, the B-side large solder bump 27BA is formed on the B-side large pad 26BA described above on the B-side 10B side of the circuit board 10 in PoP83. Then, the PoP 83 is disposed on the mother board 84, and the large solder bumps 27BA on the B surface side of the circuit board 10 in the PoP 83 are soldered to the pads included in the mother board 84. At this time, for example, a ground pad included in the motherboard 84 is soldered to the pad 26 connected to the metal block 17 in the circuit board 10. In the case where the CPU 80 and the motherboard 84 have pads dedicated for heat dissipation, the pads dedicated for heat dissipation and the metal block 17 of the circuit board 10 may be connected by via conductors 51 and 53.

  When the PoP 83 generates heat, the heat is transmitted to the metal block 17 through the via conductors 51 and 53 included in the buildup layer 20 on the F surface 10F side of the circuit board 10 on which the CPU 80 is mounted, and the B of the circuit board 10 is transferred. Heat is radiated from the metal block 17 to the mother board 84 via via conductors 51 and 53 included in the buildup layer 20 on the surface 10B side.

  Here, in the circuit board 10 of the present embodiment, the F-side via conductor 51F (F-side small via conductor 51FS) connected to the metal block 17 on the CPU 80 side (F-side 10F side) is connected to the motherboard 84 side (B On the surface 10B side), the diameter is smaller and larger than the B-side via conductor 51B (B-side large via conductor 51BL) connected to the metal block 17. Thus, in the circuit board 10 of the present embodiment, the CPU 80 mounted on the circuit board 10 is connected to the first main surface 17F side of the metal block 17 by connecting many small-diameter F-side small via conductors 51FS. Can be transferred to the motherboard 84 efficiently. That is, according to the circuit board 10 of the present embodiment, it is possible to secure a heat dissipation route that passes through the metal block 17 and to suppress deformation of the circuit board 10 due to heat generation. Further, according to the circuit board 10 of the present embodiment, the total connection area between the metal block 17 and the plurality of F-plane side via conductors 51F is equal to the connection area between the metal block 17 and the plurality of B-plane side via conductors 51B. It becomes possible to make it larger than the total, and heat transfer from the CPU 80 to the metal block 17 can be performed efficiently.

  The circuit board 10 repeats thermal expansion and contraction depending on whether or not the CPU 80 is used. Then, due to the difference in thermal expansion / contraction rate between the metal block 17 and the first insulating resin layer 21 of the buildup layer 20, a crack may occur and the via conductor 51 may be peeled off from the metal block 17 together with the first insulating resin layer 21. . However, in the circuit board 10 of the present embodiment, both the front and back surfaces (the first main surface 17F and the second main surface 17B) of the metal block 17 that are covered with the first insulating resin layers 21 and 21 are rough. Therefore, peeling between the metal block 17 and the first insulating resin layers 21 and 21 can be suppressed, and the fixing of the metal block 17 on the circuit board 10 is stabilized. Further, by making the surface of the metal block 17 rough, the contact area between the metal block 17 and the first insulating resin layers 21 and 21 and the filling resin 16J in the cavity 16 is increased, and the metal block 17 is transferred to the circuit board 10. Increases the heat dissipation efficiency.

  In the circuit board 10 of the present embodiment, the roughness of the second main surface 17B connected to the motherboard 84 is relatively large, while the roughness of the first main surface 17F connected to the CPU 80 is relatively high. Therefore, the total of the connection areas of the metal block 17 and the plurality of B-side large via conductors 51BL on the second main surface 17B side is equal to the first while stabilizing the fixing of the metal block 17 on the circuit board 10. When smaller than the total connection area of the metal block 17 and the plurality of F edge side small via conductors 51FS on the main surface 17F side (that is, when viewed from the thickness direction of the circuit board 10 and the first insulating resin layer) Even when the contact area with the second main surface 17B is larger on the second main surface 17B side than on the first main surface 17F side), the delamination risk of the metal block 17 and the first insulating resin layer 21 is reduced. There are believed to be reduced.

[Second Embodiment]
The circuit board 10V of this embodiment is shown in FIG. The circuit board 10 </ b> V is provided with a cavity 32 that houses a multilayer ceramic capacitor 18 (hereinafter referred to as “MLCC 18”) in the vicinity of the cavity 16 that houses the metal block 17. The MLCC 18 has a structure in which, for example, both ends of a ceramic prismatic body are covered with a pair of electrodes 31, 31. Similarly to the metal block 17, the MLCC 18 slightly protrudes from the F surface 11F and the B surface 11B of the core substrate 11, and the first plane 31F of each electrode 31 of the MLCC 18 is a conductor circuit on the F surface 11F side of the core substrate 11. The second planar surface 31B of each electrode 31 of the MLCC 18 is flush with the outermost surface of the conductor circuit layer 12 on the B surface 11B side of the core substrate 11, and is flush with the outermost surface of the layer 12. It is arranged below the portion 26J. The via conductors 51 and 53 included in the build-up layers 20 and 20 on the front and back surfaces of the core substrate 11 are connected to the electrodes 31 of each MLCC 18. Further, when the circuit board 10V is manufactured, the metal block 17 and the MLCC 18 are accommodated in the cavities 16 and 32 in the same process. Here, the diameter of the via conductor 51 (the F-side large via conductor 51FL and the B-side large via conductor 51BL) connecting the electrode 31 of the MLCC 18 and the first conductor layer 22 and the second main of the metal block 17 The diameter of the via conductor 51 (B-side large via conductor 51BL) connecting the surface 17B and the first conductor layer 22 is substantially the same.
[Other Embodiments]

  The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various modifications are possible within the scope of the invention other than the following. It can be changed and implemented.

  (1) The via conductor 51 of the above embodiment is connected to the pad 26 exposed on the outermost surface of the circuit boards 10 and 10V by the via conductor 53. For example, the via conductor 53 is not connected. The conductor connected to the via conductor 51 may not be connected to the portion exposed on the outermost surface of the circuit boards 10 and 10V, such as the pad 26 not being provided.

  (2) In the second embodiment, the MLCC 18 is housed in the cavity 32. However, in addition to the MLCC 18, other electronic components such as passive components such as capacitors, resistors, thermistors, and coils, It may be an active component such as an IC circuit.

  (3) In the above embodiment, the inner surface of the cavity 16 is a flat surface, but as shown in FIG. 16, it may be a bulging side surface 16A that bulges toward the groove-shaped side surface 17A.

  (4) The planar shape of the metal block 17 of the above embodiment is rectangular, but it may be other polygonal shapes, circular, oval or oval. Good.

  (5) The metal block 17 of the above embodiment is made of copper, but is not limited to this, and may be, for example, copper mixed with molybdenum or tungsten, aluminum, or the like.

  (6) In the above embodiment, the distance between the first main surface 17F and the second main surface 17B of the metal block 17 is larger than the plate thickness of the core substrate 11. It may be the same or smaller than the thickness of the core substrate 11.

  (7) In the above embodiment, when the metal block 17 is housed in the cavity 16 by the mounter, the plurality of metal blocks 17 have the first main surface 17F (the surface with the lower roughness) in advance. However, it is arranged in a state where the front and back surfaces are random, and the one with the lower roughness surface is selected from among them and accommodated, or the difference in roughness A configuration in which the surface with the lower roughness is on the bottom and the surface with the higher roughness on the bottom is turned upside down and the one with the surface with the lower roughness on the bottom is accommodated. In the latter case, for example, a mark such as coloring may be provided on one side of the copper plate 50, and the difference in roughness may be discriminated using the mark as a clue.

  (8) In the said embodiment, although the side surface of the metal block 17 was curving, the structure orthogonal to the 1st main surface 17F and the 2nd main surface 17B may be sufficient.

  (9) In the metal block 17 of the above embodiment, the roughness of the second major surface 17B connected to the motherboard 84 is relatively large, while the roughness of the first major surface 17F connected to the CPU 80 is compared. Although the roughness of the first main surface 17F is relatively large, the roughness of the second main surface 17B may be relatively small. According to this configuration, when the thermal stress increases on the first main surface 17F side, the reliability of the connection between the B-side via conductor 51B and the metal block 17 is prevented, and the metal block 17 and the motherboard 84 are prevented. Heat can be transferred more efficiently.

  (10) In the above embodiment, as shown in FIG. 17, the F-plane side via conductor 53F connected to the F-plane side small via conductor 51FS is substantially the same size as the F-plane side small via conductor 51FS. The small via conductor 53FS may be used. The F surface side small via conductor 53FS is formed by forming an F surface side small via hole 54FS in the second insulating resin layer 23 using, for example, an ultraviolet laser, and filling the F surface side small via hole 54FS with plating. It is formed. Note that at least some of the plurality of F-plane-side small via conductors 53FS are connected to the F-plane-side small pad 26FB via the second conductor layer 24.

  (11) In the above embodiment, as shown in FIG. 18, the build-up layer 20 may have a structure in which only the first insulating resin layer 21 and the first conductor layer 22 are laminated. In this case, a part of the first conductor layer 22 connected to the one or more F-plane-side small via conductors 51FS is exposed as the F-plane-side small pad 26FB. The circuit board 10 shown in FIG. 18 is obtained as follows. That is, in the manufacturing method of the first embodiment, after the process shown in FIG. 12A is performed, the solder is formed on the first conductor layer 22 in the same manner as the process shown in FIGS. A resist layer 25 is laminated, bump openings are formed at predetermined positions of the solder resist layer 25, and portions exposed from the openings become pads 26. Thereby, the circuit board 10 shown in FIG. 18 is completed.

10, 10V circuit board 11 core board 16 cavity 17 metal block 20 buildup layer 51, 53 via conductor 51FS F-side small via conductor (first via conductor)
51FL F-side large via conductor (third via conductor)
51BL B-side large via conductor (second via conductor)
26J electronic component mounting part (mounting part)
26B B side large pad

Claims (12)

A core substrate having a cavity in which a metal block is accommodated;
A build-up layer that is laminated on the first and second surfaces of the core substrate and has via conductors;
A mounting portion provided on the outermost portion of the first buildup layer stacked on the first surface side of the buildup layer, on which an electronic component is mounted;
A circuit board having a board connection portion provided on the outermost side of the second buildup layer stacked on the second surface side of the buildup layer and connected to another circuit board,
As the via conductor, a first via conductor provided in the first buildup layer and connected to the metal block; and a second via conductor provided in the second buildup layer and connected to the metal block; Have
The diameter of the first via conductor is smaller than the diameter of the second via conductor, and the number of the first via conductors is larger than the number of the second via conductors. The circuit board according to claim 1,
The diameter of the first via conductor is 10 to 30 μm, and the diameter of the second via conductor is 40 to 70 μm. The circuit board according to claim 1 or 2,
The pitch of the first via conductor is narrower than the pitch of the second via conductor. The circuit board according to claim 3,
The pitch of the first via conductor is 45 to 55 μm, and the pitch of the second via conductor is 130 to 170 μm. A circuit board according to any one of claims 1 to 4,
The total connection area between the metal block and the plurality of first via conductors is larger than the total connection area between the metal block and the plurality of second via conductors. A circuit board according to any one of claims 1 to 5,
The first via conductor has a cylindrical shape, and the second via conductor has a tapered shape that is reduced in diameter toward the core substrate side. A circuit board according to any one of claims 1 to 6,
Of the metal block, the connection surface with the resin on both the front and back surfaces covered with the buildup layer is a rough surface, and the surface roughness on the second surface side of the both surfaces of the front and back surfaces is the first surface side. It is larger than the surface roughness. The circuit board according to claim 7,
The arithmetic mean roughness of the surface on the first surface side of the metal block is 0.1 to 1.0 μm, and the arithmetic mean roughness of the surface on the second surface side is 1.0 to 3.0 μm. . The circuit board according to claim 1, wherein
The via conductor further includes a third via conductor provided in the first buildup layer and connected to a conductor circuit layer formed on the first surface of the core substrate;
The diameter of the first via conductor is smaller than the diameter of the third via conductor. Providing a core substrate having a cavity in which a metal block is accommodated;
Laminating build-up layers on the first and second surfaces of the core substrate;
Forming via conductors in the build-up layer;
Providing a mounting part on which an electronic component is mounted on the outermost part of the buildup layer laminated on the first surface side;
A circuit board manufacturing method for performing, on the outermost part of the build-up layer laminated on the second surface side, providing a board connecting portion to be connected to another circuit board,
In forming the via conductor, the first via conductor on the first surface side and the second via conductor on the second surface side are formed, and the first via is larger than the diameter of the second via conductor. The diameter of the conductor is reduced, and the number of the first via conductors is made larger than the number of the second via conductors. It is a manufacturing method of the circuit board according to claim 10,
In forming the via conductor, the first via hole is formed in the build-up layer on the first surface side by laser processing, and the first via hole is filled with plating to form the first via conductor, Forming a second via hole in the build-up layer on the second surface side by laser processing, filling the second via hole with plating, and forming the second via conductor;
The wavelength of the laser for forming the first via hole is shorter than the wavelength of the laser for forming the second via hole. It is a manufacturing method of the circuit board according to claim 11,
The first via hole is formed with an ultraviolet laser, and the second via hole is formed with an infrared laser.

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