JP7288339B2 - Wiring board and method for manufacturing wiring board - Google Patents

Description

The present invention relates to a wiring board and a method for manufacturing the wiring board.

In Patent Document 1, on the upper and lower surfaces of a core substrate, an upper buildup layer including a first conductor layer and a top conductor layer including pads for mounting an IC chip, and a second conductor layer and a motherboard. A printed wiring board is disclosed in which a lower buildup layer including a bottom conductor layer and a lower buildup layer including pads for connecting to the wiring are formed. The sum of the thickness of the first conductor layer and the thickness of the uppermost conductor layer is greater than the sum of the thickness of the second conductor layer and the thickness of the lowermost conductor layer.

JP 2014-45019 A

In the printed wiring board of Patent Document 1, the sum of the thicknesses of the conductor layers formed on the side closer to the IC chip than the center line of the printed wiring board is greater than the sum of the thicknesses of the conductor layers formed on the far side. . It may be difficult to form the conductor layer on the side closer to the IC chip with a fine pitch. Also, the power supply may not be sufficient.

A wiring board of the present invention has a first surface and a second surface opposite to the first surface, and includes a core substrate including an insulating layer, a first surface-side conductor layer, and a second surface-side conductor layer. a first buildup layer provided on the first surface of the core substrate and formed by alternately laminating first interlayer insulating layers and first conductor layers on the first interlayer insulating layers; A second buildup layer is provided on the second surface and is formed by alternately stacking second interlayer insulating layers and second conductor layers on the second interlayer insulating layers. Then, in the conductor layers positioned at the same order from the core substrate, among the first conductor layer and the second conductor layer, the area of the conductor layer in the second buildup layer is the area of the conductor layer in the first buildup layer. The area of the conductor layer is larger than that of the conductor layer, and the thickness of the conductor layer in the second buildup layer is larger than the thickness of the conductor layer in the first buildup layer.

A wiring board manufacturing method of the present invention has a first surface and a second surface opposite to the first surface, and includes an insulating layer, a first surface-side conductor layer, and a second surface-side conductor layer. providing a core substrate; and forming a first interlayer insulating layer and a first conductive layer on the first interlayer insulating layer alternately laminated on the first surface and the second surface of the core substrate. providing a buildup layer and a second buildup layer formed by alternately laminating a second interlayer insulation layer and a second conductor layer on the second interlayer insulation layer. In addition, providing the first buildup layer and the second buildup layer means that the conductor layer on the second surface side is thicker than the conductor layer of the same order from the core substrate on the first surface side, and , including forming to have a large area.

According to the embodiment of the present invention, it is considered that the power supply of the wiring board can be strengthened. Also, a wiring board with high power supply capability can be manufactured.

1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view showing another example of the wiring board according to one embodiment of the present invention; FIG. 2 is an enlarged view showing an example of the shape of the surface of a conductor layer on via conductors in a wiring board according to one embodiment; 4A to 4C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 4A to 4C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 4A to 4C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; 4A to 4C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention;

A wiring board according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1 having a first surface 1F and a second surface 1B opposite to the first surface 1F, which is an example of a wiring board according to one embodiment. As shown in FIG. 1, the wiring board 1 includes a core substrate 10 having a first surface 10F and a second surface 10B opposite to the first surface 10F; 1 buildup layer 11 and a second buildup layer 12 on the second surface 10B of the core substrate 10 . In the example of FIG. 1, the two buildup layers (the first buildup layer 11 and the second buildup layer 12) each contain the same number of conductor layers. The first buildup layer 11 is formed by alternately laminating the first interlayer insulating layers 32 and the first conductor layers 31 on the first interlayer insulating layers 32 . In the example of FIG. 1 , the first buildup layer 11 includes three first conductor layers 31 and three first interlayer insulating layers 32 . The second buildup layer 12 is formed by alternately laminating the second interlayer insulating layers 42 and the second conductor layers 41 on the second interlayer insulating layers 42 . In the example of FIG. 1 , the second buildup layer 12 includes three second conductor layers 41 and three second interlayer insulating layers 42 . In addition, the number of conductor layers and interlayer insulating layers in the first and second buildup layers is not limited to three, respectively, and any number, for example, two or less, or four or more conductors Layers and interlayer insulating layers may be provided.

The core substrate 10 includes a core insulating layer 5 and a first surface side conductor layer 3 and a second surface conductor layer 3 formed on both surfaces of the core insulating layer 5, that is, on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively. A face-side conductor layer 4 is included. Through-holes 55 for through-holes penetrating the core insulating layer 5 are formed in the core insulating layer 5 . By filling each through-hole through-hole 55 with a conductor, the first surface side conductor layer 3 and the second surface conductor layer 3 are connected. A through-hole conductor 50 is formed to connect to the two-side conductor layer 4 .

A desired conductor pattern is formed on each conductor layer (the first surface-side conductor layer 3, the second surface-side conductor layer 4, the first conductor layer 31, and the second conductor layer 41). In the example of FIG. 1, the first-surface-side conductor layer 3 and the second-surface-side conductor layer 4 are formed of three layers. The first conductor layer 31 and the second conductor layer 41 are formed of two layers. However, the number of layers forming each conductor layer is not limited to the example of FIG. 1, and for example, the first conductor layer 31 and the second conductor layer 41 may be formed of three layers. The first-side conductor layer 3 and the second-side conductor layer 4 can have, for example, a metal foil layer, an electroless plated film layer, and an electrolytic plated film layer. The first conductor layer 31 and the second conductor layer 41 can have, for example, an electroless plated film layer and an electrolytic plated film layer. Each conductor layer can be formed using any metal, such as copper, nickel, silver, palladium, alone or in combination.

The core insulating layer 5, the first interlayer insulating layer 32, and the second interlayer insulating layer 42 are formed using any insulating material. Examples of insulating materials include resin materials such as epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. Each insulating layer formed using these resin materials may contain a reinforcing material such as glass fiber or aramid fiber and/or an inorganic filler such as silica. When each buildup layer includes a plurality of interlayer insulation layers as in the example of FIG. 1, each interlayer insulation layer in each buildup layer may be formed using the same resin material. Separation between each interlayer insulating layer may be prevented. Further, for example, all the interlayer insulating layers, that is, the first interlayer insulating layer 32 in the first buildup layer 11 and the second interlayer insulating layer 42 in the second buildup layer 12 are made of the same insulating resin material. may be formed using However, different resin materials may be used.

Each interlayer insulating layer includes first and second via conductors 51 and 52 that connect the conductor layers formed on both sides of each interlayer insulating layer in the first buildup layer 11 and the second buildup layer 12. contains. First interlayer insulating layer 32 includes first via conductors 51 , and second interlayer insulating layer 42 includes second via conductors 52 . The first and second via conductors 51 and 52 are so-called filled vias formed by filling through-holes penetrating through the respective interlayer insulating layers with conductors. The first and second via conductors 51 and 52 are formed integrally with their upper (opposite to the core substrate) conductor layers. Therefore, the first and second via conductors 51 and 52 and the first conductor layer 31 and the second conductor layer 41 are formed of the same plated film (electroless plated film and electrolytic plated film) made of, for example, copper or nickel. formed by Through-hole conductors 50 penetrating through core insulating layer 5 are also formed of electroless plated films and electrolytic plated films made of copper, nickel, or the like.

The wiring board 1 in the example of FIG. 1 further includes a first solder-resist layer 6 formed on the first buildup layer 11 and a second solder-resist layer formed on the second buildup layer 12. contains 7. The first solder-resist layer 6 covers the uppermost first conductor layer 31 , and the second solder-resist layer 7 covers the uppermost second conductor layer 41 . The first and second solder resist layers 6 and 7 are formed using, for example, epoxy resin or polyimide resin.

An electronic component (not shown) such as a semiconductor element may be mounted on the first surface 1F of the wiring board 1 (that is, the upper surface side of the wiring board 1). The outermost first conductor layer 31 of the first buildup layer 11 of the wiring board 1 includes a plurality of connection pads 31a for electrically connecting to terminals of such electronic components. The solder resist layer 6 has openings that expose the connection pads 31a. On the other hand, on the second surface 1B of the wiring board 1 (that is, on the lower surface side of the wiring board 1), an external electric circuit board such as a motherboard can be connected. The outermost second conductor layer 41 of the second buildup layer 12 of the wiring board 1 includes a plurality of connection pads 41a for electrically connecting to terminals of such an external board. The solder resist layer 7 has openings that expose the connection pads 41a.

In the wiring board 1, the area of the first conductor layer 31 in the first buildup layer 11 on the first surface 10F side of the core substrate 10 (here, the area of the conductor layer means the area occupied by the conductor in the conductor layer). ) and the area of the second conductor layer 41 in the second buildup layer 12 on the second surface 10B side of the core substrate 10 is different (hereinafter, the material of each conductor layer is not limited to copper, The ratio of the total area of the conductor patterns in each conductor layer to the area of the wiring board 1 is called the residual copper ratio). In the example shown in FIG. 1, among the conductor layers positioned at the same level from the core substrate 10, the residual copper ratio of the conductor layer on the side of the second surface 10B, that is, the residual copper ratio of the second conductor layer 41 is the same as that of the first surface 10F. It is larger than the residual copper rate of the conductor layer on the side, that is, the residual copper rate of the first conductor layer 31 . Here, "the conductor layers positioned in the same order from the core substrate 10" means that the conductor layers in each buildup layer are arranged in order from the core substrate 10 toward the outside of the first surface 10F side or the outside of the second surface 10B side. It means the conductor layers that have the same order when attached.

In the example shown in FIG. 1, furthermore, in the first conductor layer 31 and the second conductor layer 41 positioned at the same order from the core substrate 10, the conductor thickness of the second conductor layer 41 is equal to the conductor thickness of the first conductor layer 31. It is formed to be thicker than the thickness. For example, the conductor thickness of the second conductor layer 41 laminated on the second interlayer insulating layer 42 located closest to the core substrate 10 side among the second buildup layers 12 is the thickness of the first buildup It is thicker than the conductor thickness of the first conductor layer 31 laminated on the first interlayer insulating layer 32 located closest to the core substrate 10 side among the layers 11 . In addition, the conductor thickness of the outermost second conductor layer 41 of the second buildup layer 12 is thicker than the conductor thickness of the outermost first conductor layer 31 of the first buildup layer 11 . Therefore, the allowable current amount on the second surface 1B side of the wiring board 1 can be increased. Voltage drop and heat generation in the power supply line on the second surface 1B side can be suppressed. Therefore, it is considered that the power supply on the second surface 1B of the wiring board 1 can be strengthened.

Each thickness of each first conductor layer 31 in the first buildup layer 11 may be equal or may be different. For example, each thickness of the first conductor layer 31 is 5 μm or more and 20 μm or less. Also, the thickness of each of the second conductor layers 41 in the second buildup layer 12 may be equal or different. For example, the thickness of each of the second conductor layers 41 is 15 μm or more and 30 μm or less. As described above, in the present embodiment, in the first conductor layer 31 and the second conductor layer 41 positioned at the same level from the core substrate 10, the thickness of the second conductor layer 41 is greater than the thickness of the first conductor layer 31. thick. In the example shown in FIG. 1, in the first conductor layer 31 and the second conductor layer 41 positioned at the same level from the core substrate 10, the thickness of the second conductor layer 41 is approximately the thickness of the first conductor layer 31. It is formed to be 1.25 times or more and about 2.0 times or less.

Each thickness of the first surface-side conductor layer 3 and the second surface-side conductor layer 4 of the core substrate 10 is, for example, 5 μm or more and 30 μm or less. In the example of FIG. 1, the conductor thickness of the first surface-side conductor layer 3 and the conductor thickness of the second surface-side conductor layer 4 are substantially equal. However, the conductor thicknesses of the first-surface-side conductor layer 3 and the second-surface-side conductor layer 4 may be different. Also in this case, preferably, the sum of the areas of the conductor layers on the second surface 10B side of the core insulating layer 5 in the wiring board 1, that is, the sum of the areas of the second surface-side conductor layers 4 and the areas of the second conductor layers 41 ( The residual copper ratio on the second surface 10B side) is the sum of the areas of the conductor layers on the first surface 10F side of the core insulating layer 5, that is, the sum of the areas of the first surface-side conductor layer 3 and the area of the first conductor layer 31. (residual copper ratio on the first surface 10F side). For example, the residual copper rate on the second surface 10B side is about 1.1 to 1.3 times the residual copper rate on the first surface 10F side. It is considered that the power supply enhancement on the second surface 10B side can be favorably achieved.

In the example shown in FIG. 1 , the first conductor layer 31 in the first buildup layer 11 and the second conductor layer 41 in the second buildup layer 12 are positioned in the same order from the core substrate 10 . Among the first conductor layer 31 and the second conductor layer 41, the conductor area of the second conductor layer 41 is larger than the conductor area of the first conductor layer 31, and the conductor thickness of the second conductor layer 41 is greater than that of the first conductor layer 31. is formed to be thicker than the conductor thickness of However, the conductor areas of all the second conductor layers 41 are larger than the conductor areas of the corresponding first conductor layers 31, and the conductor thicknesses of all the second conductor layers 41 are greater than the conductor thicknesses of the corresponding first conductor layers 31. It need not be thicker than each of the conductor thicknesses. The conductor area of at least one second conductor layer 41 is larger than the conductor area of the first conductor layer 31 positioned at the same level from the core substrate 10, and the conductor thickness is greater than that of the corresponding first conductor layer 31. It suffices if it is formed so as to be thicker than the conductor thickness. An example of such a wiring board is shown in FIG. In the wiring board 1a of the example of FIG. 2, the second interlayer insulating layer 42 positioned closest to the core substrate 10 side among the second conductor layers 41 in the second buildup layer 12 is laminated thereon. The conductor area of the second conductor layer 411 is located at the same order from the core substrate 10, that is, among the first conductor layers 31 in the first buildup layer 11, it is located closest to the core substrate 10 side. It is formed larger than the conductor area of the first conductor layer 311 laminated on the first interlayer insulating layer 32 . Furthermore, the conductor thickness of the second conductor layer 411 is formed thicker than the conductor thickness of the first conductor layer 311 .

In the example shown in FIGS. 1 and 2, the thickness of each interlayer insulating layer in first buildup layer 11 and second buildup layer 12 is, for example, 15 μm or more and 100 μm or less. First interlayer insulating layers 32 in first buildup layer 11 may be formed with the same thickness, or may be formed with different thicknesses. Similarly, each of second interlayer insulating layers 42 in second buildup layer 12 may be formed with the same thickness, or may be formed with different thicknesses. For example, in the first interlayer insulating layer 32 and the second interlayer insulating layer 42 positioned in the same order from the core substrate 10, the second interlayer insulating layer 42 is formed to be thicker than the first interlayer insulating layer 32. may be Warpage that may occur due to a difference in residual copper ratio between the first surface 10F side and the second surface 10B side of the core substrate 10 may be suppressed. Here, the interlayer insulating layers positioned at the same level from the core substrate 10 mean the interlayer insulating layers in each buildup layer extending from the core substrate 10 toward the outside of the first surface 10F side or the outside of the second surface 10B side. means interlayer insulating layers having the same order when the order is assigned to the layers.

The first conductor layer 31 and the second conductor layer 41 positioned at the same level from the core substrate 10 are simultaneously formed of plated films (electroless plated film and electrolytic plated film). In order to form the second conductor layer 41 having a thicker conductor thickness than the first conductor layer 31, in the present embodiment, on the electroless plating film for forming the first conductor layer 31 and the second conductor layer 41, When forming the electrolytic plating film, a voltage is applied such that the current density on the second surface 10B side of the core substrate 10 is higher than the current density on the first surface 10F side. As a result, the electrolytic plated film on the second surface 10B side can be formed to be thicker than the electrolytic plated film on the first surface 10F side. As described above, the first via conductors 51 are formed simultaneously and integrally with the first conductor layer 31, which is the conductor layer on the upper side (the side opposite to the core substrate). The second via conductors 52 are formed simultaneously and integrally with the second conductor layer 41, which is the conductor layer on the upper side (the side opposite to the core substrate). The speed at which the through holes are filled with the electroplated film and the speed at which the electroplated film is stacked on the electroless plated film on the flat interlayer insulating layer can be controlled by selecting the electroplating conditions and the components of the plating solution. . Therefore, the surface of each conductor layer facing away from the core substrate 10 can be convexly curved toward the opposite side of the core substrate 10 . The raised portions of an embodiment in which the conductor layer includes such raised portions are shown enlarged in FIG. If the current density is increased to increase the film thickness of the electrolytic plated film, the formation rate of the plated film can be increased both in the through-hole and on the electroless plated film on the flat interlayer insulating layer. Therefore, the protrusion amount of the convex portion on the surface of the conductor layer can be increased. In FIG. 3, since the purpose is to explain the convex portion of the conductor layer, the via conductors on the convex portion of the conductor layer, which are included in the wiring board 1 of FIG. 1, are omitted. there is

In the example of FIG. 3, the conductor layer 600 is formed from an electroless plated film 601 and an electrolytic plated film 602 . Electrolytic plated film 602 on electroless plated film 601 fills through holes 700 a formed in interlayer insulating layer 700 to form electroless plated film 601 and via conductors 800 and to form the core substrate of interlayer insulating layer 700 . is formed on the surface facing away from (upward in FIG. 3). Electroplated film 602 on via conductor 800 includes a convex portion curved upward from surface 600S of conductor layer 600 (the surface of the portion of conductor layer 600 above interlayer insulating layer 700). The height h of the convex portion from the surface 600s can be increased by increasing the thickness of the electrolytic plated film 602, that is, the thickness of the conductor layer 600, as described above. Therefore, when a thick conductor layer and a thin conductor layer are simultaneously formed, the height h increases in the thick conductor layer to which a large current density is applied. That is, as the conductor thickness D of the conductor layer 600 including the electroplated film 602 increases, the height h of the convex portion from the surface 600S of the conductor layer 600 can increase. Therefore, as shown in FIG. 1, the conductor thickness of the second conductor layer 41 on the second surface 10B side of the core substrate 10 is formed thicker than the first conductor layer 31 on the first surface 10F side. In the wiring board, the height h of the convex portion in the thicker second conductor layer 41 is equal to or greater than the height h of the convex portion in the thinner first conductor layer 31 .

A convex portion as shown in FIG. 3 can be formed along the thickness direction Z of the wiring board 1 . However, the cross-sectional shape of the convex portion is not limited to the shape shown in FIG. can take

The height h of the convex portion is, for example, about 3 μm or less. For example, when the first conductor layer 31 of the wiring board 1 includes a convex portion, the height h (h1) of the convex portion of the first conductor layer 31 is about 1.5 μm or less, that is, the first conductor layer 31 is about 1/10 or less of the conductor thickness D of . When the second conductor layer 41 includes a convex portion, the height h (h2) of the convex portion of the second conductor layer 41 is about 2.5 μm or less, that is, the thickness D of the conductor thickness D of the second conductor layer 41. It is about 1/10 or less. If the height h of the convex portion of the conductor layer is made higher than about 3 μm, problems may arise in laminating the next interlayer insulating layer and conductor layer on the formed conductor layer. Thickness imbalance and warping can occur in the printed circuit board during manufacture. In addition, there is a possibility that a problem may arise in the accuracy of patterning of the conductor layer laminated thereon. It is considered that such a problem can be conspicuous on the second surface 10B side where the second conductor layer 41 having the thicker conductor thickness D is formed. Preferably, the height h2 of the convex portion in the second conductor layer 41 having the thicker thickness D is greater than the height h1 of the convex portion in the first conductor layer 31 having the thinner thickness D, but The height h2 is approximately 1.7 times or less the height h1. However, the first conductor layer 31 on the first via conductor 51 or both the first conductor layer 31 on the first via conductor 51 and the second conductor layer 41 on the second via conductor 52 have a convex shape. The entire surface of the first conductor layer 31 facing away from the core substrate or the entire surfaces of the first conductor layer 31 and the second conductor layer 41 facing away from the core substrate are formed substantially flat. may

Using the wiring board 1 shown in FIG. 1 as an example, a method for manufacturing a wiring board according to one embodiment will now be described with reference to FIGS. 4A to 4D.

As shown in FIG. 4A, a laminate having a core insulating layer 5 forming a core substrate 10 and metal foils 3e provided on both sides of the core insulating layer 5 is prepared. For example, a double-sided copper-clad laminate having metal foil 3e made of copper is prepared.

As shown in FIG. 4B, through-holes 55 are formed by, for example, irradiating carbon dioxide laser light, and include copper foil, electroless copper film, and electrolytic plated film using, for example, a subtractive method. A first surface-side conductor layer 3 and a second surface-side conductor layer 4 having desired conductor patterns are formed on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively. The through-hole conductor 50 is formed by filling the through hole 55 with the electroless plated film and the electrolytic plated film.

As shown in FIG. 4C, a first interlayer insulating layer 32 and a second interlayer insulating layer 42 are formed. Also, the first conductor layer 31 is formed on the first interlayer insulating layer 32 . Along with the formation of the first conductor layer 31 , the second conductor layer 41 is formed on the second interlayer insulating layer 42 . In forming the first conductor layer 31 , the first via conductors 51 are formed in the first interlayer insulating layer 32 . Also, in forming the second conductor layer 41 , the second via conductors 52 are formed in the second interlayer insulating layer 42 .

The first and second interlayer insulating layers 32 and 42 are formed by laminating a prepreg containing reinforcing material such as semi-cured epoxy resin and glass fiber, or a film-like epoxy resin on both sides of the core substrate 10. It is formed by thermocompression bonding. When laminating the prepregs, a metal foil made of copper, for example, may be overlaid on the prepregs and pressed together with the prepregs. After that, through holes 32a for forming first via conductors 51 are formed in the first interlayer insulating layer 32 by, for example, carbon dioxide laser light irradiation. Similarly, through holes 42 a for forming second via conductors 52 are formed in the second interlayer insulating layer 42 .

Then, for example, using a semi-additive method, a metal film is formed by electroless copper plating or the like, and this metal film is used as a seed layer to form an electroplating film on the metal film, thereby forming first and second conductive patterns having desired conductor patterns. Second conductor layers 31 and 41, and first and second via conductors 51 and 52 are formed. In the wiring board 1 in the example of FIG. 1, the second conductor layer 41 has a conductor thickness greater than that of the first conductor layer 31 . Therefore, when the electrolytic plated film is formed such that the thickness of the electrolytic plated film on the side of the second surface 10B is thicker than the thickness of the electrolytic plated film on the side of the first surface 10F, the thickness of the electrolytic plated film on the side of the second surface 10B of the core substrate 10 is increased. is higher than the current density on the first surface 10F side. The thickness of the conductor layer of the second conductor layer 41 integrally formed with the second via conductors 52 is about 1.5 times the thickness of the conductor layer of the first conductor layer 31 integrally formed with the first via conductors 51 . It is about 25 times or more and about 2.0 times or less.

For example, by applying a general build-up wiring board manufacturing method using a semi-additive method, on the first conductor layer 31 and the second conductor layer 41 in FIG. 1 conductor layer 31 and second interlayer insulating layer 42 and second conductor layer 41 are formed to form first buildup layer 11 and second buildup layer 11 on first surface 10F and second surface 10B of core substrate 10. A layer 12 is formed respectively (FIG. 4D). A first via conductor 51 is formed in the laminated first interlayer insulating layer 32 . Second via conductors 52 are formed in the laminated second interlayer insulating layer 42 .

In FIG. 4D, first and second buildup layers 11 and 12 each composed of three interlayer insulating layers and three conductor layers are formed on the first surface 10F side and the second surface 10B side of core substrate 10 . However, the number of layers of each of the interlayer insulating layers and conductor layers in the buildup layers 11 and 12 is not limited to this example. Layers may be formed. However, regardless of the number of interlayer insulating layers and conductor layers laminated on both sides of core substrate 10, the formation of conductor layers in a wiring substrate in the middle of manufacturing causes the current density on the second surface 10B side of core substrate 10 to be It includes applying a voltage so as to be higher than the current density on the first surface 10F side. Therefore, in at least one pair of conductor layers (the first conductor layer 31 and the second conductor layer 41) positioned in the same order from the core substrate 10, the second conductor layer 41 formed on the second surface 10B side of the core substrate 10 is formed to be larger than the thickness of the first conductor layer 31 formed on the first surface 10F side. In FIG. 4D, voltage is applied so that the current density on the second surface 10B side of the core substrate 10 is higher than the current density on the first surface 10F side when the first and second conductor layers are formed. Therefore, among the first conductor layer 31 and the second conductor layer 41, the conductor layer positioned at the same level from the core substrate 10 has the thickness of the second conductor layer 41 formed on the second surface 10B side of the core substrate 10. is formed to be larger than the thickness of the first conductor layer 31 formed on the first surface 10F side.

After that, a solder-resist layer 6 is formed on the first buildup layer 11 and a solder-resist layer 7 is formed on the second buildup layer 12 . The solder resist layers 6 and 7 are formed by, for example, forming a resin layer containing a photosensitive epoxy resin or polyimide resin, and exposing and developing using a mask having an appropriate pattern.

Au, Ni/Au, Ni/Pd/Au, Ni/Pd/Au, Ni/Pd/Au, Ni/Pd/Au, etc. are applied to the connection pads 31a, 41a exposed in the openings of the solder resist layers 6, 7, respectively, by electroless plating, solder leveler, or spray coating, if necessary. A surface protective film (not shown) made of solder, heat-resistant preflux, or the like may be formed. The wiring board 1 shown in FIG. 1 is completed through the above steps.

The wiring substrates of the embodiments are not limited to those having the structures illustrated in each drawing, and the structures, shapes, and materials illustrated in this specification. For example, first and second via conductors 51 and 52 may not have a shape that decreases in diameter toward core substrate 10 . Also, the solder resist layers 6 and 7 may not be provided.

Moreover, the method for manufacturing the wiring board of the embodiment is not limited to the method described above with reference to each drawing. For example, the core substrate 10 may be formed using a semi-additive method using copper foil. Each conductor layer in the first and second buildup layers 11, 12 may be formed using a subtractive method. The conditions, order, etc. of the manufacturing method described above may be changed as appropriate. Some steps may be omitted or other steps may be added depending on the structure of the wiring board to be actually manufactured.

1 Wiring board 1a Wiring board 1F Wiring board first surface 1B Wiring board second surface 5 Core insulating layer 10 Core substrate 10F Core substrate first surface 10B Core substrate second surface 11 First buildup layer 12 Second second Buildup layer 3 First surface conductor layer 4 Second surface conductor layer 31 First conductor layer 32 First interlayer insulating layer 41 Second conductor layer 42 Second interlayer insulating layer 50 Through-hole conductor 51 First via conductor 52 Second 2 via conductors 6, 7 solder resist layer

Claims (8)

a core substrate having a first surface and a second surface opposite to the first surface, and including a core insulating layer, a first surface-side conductor layer, and a second surface-side conductor layer;
a first buildup layer provided on the first surface of the core substrate and formed by alternately stacking a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer;
a second buildup layer provided on the second surface of the core substrate and formed by alternately stacking a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer;
A wiring board comprising
Among the first conductor layer and the second conductor layer, the area of the conductor layer in the second buildup layer is equal to the area of the conductor layer in the first buildup layer in the conductor layers positioned in the same order from the core substrate. and the thickness of the conductor layer in the second buildup layer is greater than the thickness of the conductor layer in the first buildup layer,
The outermost first conductor layer of the first buildup layer includes a plurality of connection pads for mounting a semiconductor element, and the outermost second conductor layer of the second buildup layer is for connection with a motherboard. Contains multiple connection pads . 2. The wiring board according to claim 1, wherein the sum of areas of said second surface side conductor layer and said second conductor layer is larger than the sum of areas of said first surface side conductor layer and said first conductor layer. . 2. The wiring board according to claim 1, wherein, of the first conductor layer and the second conductor layer, the conductor layer positioned in the same order from the core substrate includes the conductor layer in the second buildup layer. The thickness is 1.25 times or more and 2.0 times or less the thickness of the conductor layer in the first buildup layer. 2. The wiring board according to claim 1, wherein all the conductor layers of the first conductor layer and the second conductor layer located in the same order from the core board have conductor layers in the second buildup layer. is larger than the area of the conductor layer in the first buildup layer, and the thickness of the conductor layer in the second buildup layer is larger than the thickness of the conductor layer in the first buildup layer. The wiring board according to claim 1,
a first via conductor that penetrates the first interlayer insulating layer and connects the conductor layers on both sides of the first interlayer insulating layer;
a second via conductor that penetrates the second interlayer insulating layer and connects the conductor layers on both sides of the second interlayer insulating layer;
the first via conductor on the surface of the first conductor layer facing away from the core substrate is convexly curved from the surface of the first conductor layer toward the opposite side of the core substrate;
The second via conductors on the surface of the second conductor layer facing away from the core substrate are convexly curved from the surface of the second conductor layer toward the opposite side of the core substrate. 6. The wiring board according to claim 5, wherein the height of said convex portion of said second conductor layer from said surface of said second conductor layer is equal to the height of said convex portion of said first conductor layer. , equal to or greater than the height of the first conductor layer from the surface. providing a core substrate having a first surface and a second surface opposite to the first surface, and including a core insulating layer, a first surface-side conductor layer, and a second surface-side conductor layer;
a first buildup layer formed by alternately laminating first interlayer insulating layers and first conductor layers on the first interlayer insulating layers on the first surface and the second surface of the core substrate; providing second build-up layers in which two interlayer insulating layers and second conductor layers on the second interlayer insulating layers are alternately laminated;
A wiring board manufacturing method comprising
Providing the first buildup layer and the second buildup layer includes:
forming the conductor layer on the side of the second surface so as to be thicker and have a larger area than the conductor layer of the same rank from the core substrate on the side of the first surface;
forming a plurality of connection pads for mounting a semiconductor element on the outermost first conductor layer of the first buildup layer;
forming a plurality of connection pads for connecting to a motherboard on the outermost second conductor layer of the second buildup layer;
contains. 8. The method of manufacturing a wiring board according to claim 7, wherein the provision of the first buildup layer and the second buildup layer is such that the current density on the second surface side of the core substrate is higher than that on the first surface side. electroplating by applying a voltage higher than the current density of .

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