JP2003332716A - Wiring board and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which is equipped with connection terminals formed on the filled via conductors and can be improved in reliability by preventing voids from occurring in solder and to provide a method of manufacturing the same. <P>SOLUTION: The wiring board 101 is equipped with a second insulating layer 124 provided with viaholes 125 and formed on its main surface, the filled via conductors 128 filling the viaholes 125, and a main-surface side Ni plating layer 136 deposited on the surface of the filled via conductors 128. The filled via conductor 128 is formed into the shape provided with an convex expanded part, and the main-surface side Ni plating layer 136 has a convex surface as following the surface of the filled via conductor 128. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board having a connection terminal connected to an electronic component or a terminal of another board, and a method for manufacturing the wiring board, and more particularly to a connection terminal formed on a via conductor. Alternatively, the present invention relates to a wiring board in which the via conductor itself is a connection terminal and a method for manufacturing the wiring board.

[0002]

2. Description of the Related Art Conventionally, there has been known a wiring board having a connection terminal formed on a via conductor. For example, FIG. 18 is a wiring substrate 9 showing a partially enlarged cross-sectional view of the main part on the substrate main surface 902 side.
01 is mentioned. The wiring board 901 includes a board main surface 902 on which an IC chip is mounted and a board back surface (not shown).
And a substantially plate shape having. The wiring board 901 is shown in FIG.
As shown in, the first resin insulation layer 905 is provided. A second resin insulation layer 907 having a via hole 908 at a predetermined position is laminated thereon. Further thereon, a solder resist layer 90 having an opening 910 at a predetermined position.
9 are stacked.

First resin insulation layer 905 and second resin insulation layer 9
A plate-shaped pad 911 is formed between the layer 07 and 07. The via hole 908 of the second resin insulating layer 907 is located on the central portion of the pad 911.
The filled via conductor 913 connected to the pad 911.
(Via conductor whose via hole 908 is filled with a conductor) is formed. An opening 910 of the solder resist layer 909 is located on the center of the surface of the filled via conductor 913, and a plate-shaped Ni plating layer (metal layer) 915 connected to the filled via conductor 913 is formed in the opening 910. ing. Further, a solder bump 916 is welded to the Ni plating layer 915 and protrudes from inside the opening 910 over the surface of the solder resist layer 909. These N
The i-plated layer 915 and the solder bumps 916 are the connection terminals 917 connected to the terminals of the IC chip.

Such a wiring board 901 is manufactured as follows. That is, the first resin insulation layer 905 and the pad 911.
A substrate on which a second resin insulation layer 907 having a via hole 908 is formed is prepared. Then, this substrate is subjected to Cu plating by using an electrolytic plating solution for forming a filled via conductor, and the via hole 908 is filled with the plating to form a filled via conductor 913. At this time, the surface of the filled via conductor 913 is usually slightly concave or flat. Next, a solder resist layer 909 having an opening 910 is formed on the second resin insulating layer 907. After that, Ni plating is applied to the filled via conductor 9 exposed in the opening 910.
A Ni plating layer 915 is deposited on the surface of 13. At this time, the surface of the Ni plating layer 915 also covers the filled via conductor 9
Following the surface of 13, it becomes slightly concave or flat. After that, Au plating is further applied, and Au is plated on the Ni plating layer 915.
Apply the plating layer. Next, a solder paste is applied to the openings 910 using a print mask having a predetermined pattern corresponding to the openings 910, or using a dispenser or the like, and then the solder paste is reflowed to form solder bumps 916. At that time, since the Au plating diffuses into the solder, the solder bump 916 is formed on the Ni plating layer 915 as described above. Note that, as a document related to such a technique, for example, Patent Document 1 can be cited.

[0005]

[Patent Document 1] Japanese Patent Laid-Open No. 2002-134862

[0006]

However, the opening 9
When reflowing the solder paste applied to 10,
As shown by the broken line in FIG. 18, air bubbles (voids) BD may occur in the solder bump 916. This is because air is easily trapped when applying the solder paste.
It is also considered that the flux does not escape during reflow and remains in the solder. When the void BD is included in the solder bump 916, the wiring board 901 is
When heat stress is applied to the cracks, cracks starting from the void BD are likely to occur. That is, electrical connection failure is likely to occur in the connection terminal 917, and the wiring board 90
1 is inferior in reliability.

The present invention has been made in view of the above circumstances, and a wiring board in which a connection terminal is formed on a filled via conductor or a wiring board in which the filled via conductor itself serves as a connection terminal has voids in solder. It is an object of the present invention to provide a wiring board and a method for manufacturing the wiring board, which can prevent the occurrence and improve the reliability.

[0008]

Means for Solving the Problems, Actions and Effects The solution is provided with an insulating layer having a via hole, a filled via conductor formed in the via hole, and a metal layer deposited on the surface of the filled via conductor. In the wiring board, the filled via conductor has a shape having a bulging portion in which the surface bulges in a convex shape, and the metal layer also bulges in a convex shape along the surface of the filled via conductor. The wiring board has a shape.

This wiring board is provided on the surface of the filled via conductor as a connection terminal to be connected to terminals of electronic parts such as IC chips and terminals of other boards such as a mother board (hereinafter also referred to as external terminals). A formed metal layer is provided. Then, in the present invention, the filled via conductor has a shape having a bulging portion in which the surface is bulged in a convex shape, and the metal layer adhered to the surface also follows the surface of the filled via conductor and its surface is It has a convex shape. In such a wiring board, voids are unlikely to occur in the solder when forming the solder on the metal layer. The reason is,
It is considered that since the surface of the metal layer is bulged in a convex shape, entrapment of air is reduced when the solder paste is applied. Also, during reflow, where flux components tend to collect at the center of gravity of the solder, and because the surface of the metal layer swells, the distance from the center of gravity of the solder to the surface of the solder becomes shorter, making it easier for flux components to move to the surface. It is considered that this is because the inclusion as voids is reduced. Therefore, even when thermal stress is applied to the wiring board, the stress is not locally concentrated in the void portion, and the crack resistance of the solder is improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the metal layer is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

The filled via conductor may have any shape as long as it has a convex bulge on its surface, and may be a bulge on the entire surface or a bulge on a part of the surface (for example, the central portion). Good. Further, the metal layer may be any one as long as it satisfies the above requirements, for example, N
Examples thereof include an i layer, a Sn layer, a Cu layer, a Pd layer, an Au layer, and a metal layer containing these as a main component. In addition to the metal layer formed of one layer, a metal layer formed of two or more layers such as a Ni / Au layer in which an Au layer is formed on a Ni layer may be used. The insulating layer may be made of ceramic or resin. That is, the insulator may be a ceramic such as alumina, aluminum nitride, glass ceramic, low temperature fired ceramic,
It may be a resin such as an epoxy resin or a BT resin, or a composite material such as a glass-epoxy resin composite material or a ceramic-resin composite material.

Another solution is a wiring board including an insulating layer having a via hole and a filled via conductor formed in the via hole, wherein the filled via conductor has a convex surface swelling. It is a wiring board having a shape having a projecting portion.

This wiring board includes a filled via conductor as a connection terminal connected to an external terminal or the like. Further, in the present invention, the filled via conductor has a shape having a bulged portion whose surface bulges in a convex shape. In such a wiring board, when the solder is formed on the filled via conductor, the surface of the filled via conductor swells in a convex shape, and thus voids are less likely to occur in the solder. Therefore, the crack resistance of the solder can be improved. Therefore,
Electrical connection failure is unlikely to occur at the connection terminals, and the reliability of the wiring board can be improved. Furthermore, since the surface of the filled via conductor is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

Another solution is to provide an insulating layer having a via hole, a filled via conductor formed in the via hole, a metal layer deposited on the surface of the filled via conductor, and a solder bump welded to the surface of the metal layer. And the filled via conductor is formed into a shape having a bulge portion in which the surface bulges in a convex shape, and the metal layer also follows the surface of the filled via conductor and has a convex surface. The wiring board has a bulging shape.

The wiring board includes a metal layer formed on the surface of the filled via conductor and a solder bump welded to the metal layer as a connection terminal connected to an external terminal or the like.
Then, in the present invention, the filled via conductor has a shape having a bulging portion in which the surface is bulged in a convex shape, and the metal layer adhered to the surface also follows the surface of the filled via conductor and its surface is It has a convex shape. In manufacturing such a wiring board, when forming the solder bumps on the metal layer, the surface of the metal layer swells in a convex shape, so that voids are less likely to occur in the solder bumps. Therefore, the crack resistance of the solder bump can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the metal layer is swollen, the joint area with the solder bump is increased, so that the joint strength of the solder bump can be improved.

Another solution is a wiring board comprising an insulating layer having a via hole, a filled via conductor formed in the via hole, and a solder bump welded to the surface of the filled via conductor. Is a wiring board whose surface has a bulging portion that bulges in a convex shape.

This wiring board is provided with solder bumps welded to the surface of the filled via conductor as connection terminals connected to external terminals and the like. Further, in the present invention, the filled via conductor has a shape having a bulging portion in which the surface thereof bulges in a convex shape. In manufacturing such a wiring board, when the solder bumps are formed on the filled via conductors, the surface of the filled via conductors bulges in a convex shape, so that voids are less likely to occur in the solder bumps. Therefore,
The crack resistance of the solder bump can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the filled via conductor is swollen, the joint area with the solder bump is increased, so that the joint strength of the solder bump can be improved.

Another solution is that an insulating layer having a via hole, a filled via conductor formed in the via hole, and an insulating layer are laminated on the insulating layer, and at least a part of the filled via conductor is arranged inside thereof. A wiring board comprising: a solder resist layer having an opening; and a metal layer deposited on the surface of the filled via conductor in the opening, wherein the filled via conductor has a convex surface swelled in the opening. The wiring board is formed to have a bulge portion, and the metal layer is also a wiring board whose surface bulges in a convex shape following the surface of the filled via conductor.

This wiring board has a metal layer formed on the surface of the filled via conductor in the opening of the solder resist layer as a connection terminal connected to an external terminal or the like. Then, in the present invention, the filled via conductor has a shape having a bulging portion whose surface bulges in a convex shape in the opening of the solder resist layer, and the metal layer adhered to the surface is also the surface of the filled via conductor. In accordance with the above, the surface has a convex shape. In such a wiring board, when the solder is formed on the metal layer, the surface of the metal layer bulges in a convex shape, and thus voids are less likely to occur in the solder. Therefore, the crack resistance of the solder can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved.
Furthermore, because the surface of the metal layer is swollen,
Since the joint area with the solder increases, the joint strength of the solder can be improved.

Another solution is that an insulating layer having a via hole, a filled via conductor formed in the via hole, and an insulating layer are laminated on the insulating layer, and at least a part of the filled via conductor is arranged inside thereof. A wiring board comprising a solder resist layer having an opening, a metal layer deposited on the surface of the filled via conductor in the opening, and a solder bump welded on the surface of the metal layer, wherein the filled via conductor is In the wiring board, the surface of which has a bulging portion that bulges in a convex shape in the opening, and the metal layer also has a shape in which the surface thereof bulges in a convex shape following the surface of the filled via conductor. is there.

This wiring board is provided with a metal layer formed on the surface of the filled via conductor in the opening of the solder resist layer and a solder bump welded to the metal layer as a connection terminal connected to an external terminal or the like. Then, in the present invention, the filled via conductor has a shape having a bulging portion whose surface bulges in a convex shape in the opening of the solder resist layer, and the metal layer adhered to the surface is also the surface of the filled via conductor. In accordance with the above, the surface has a convex shape. In manufacturing such a wiring board, when forming the solder bumps on the metal layer, the surface of the metal layer swells in a convex shape, so that voids are less likely to occur in the solder bumps. Therefore, the crack resistance of the solder bump can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the metal layer is swollen, the joint area with the solder bump is increased, so that the joint strength of the solder bump can be improved.

In any one of the above wiring boards, the surface of the metal layer may be lower than the surface of the solder resist layer.

As described above, in order to suppress the occurrence of voids in the solder, it is preferable to swell the surface of the filled via conductor and the surface of the metal layer. However, when the surface of the metal layer exceeds the surface of the solder resist layer, it comes into contact with the terminals of electronic components such as IC chips and chip capacitors to be mounted, which may adversely affect the mounting state of the electronic components. On the other hand, in the present invention, the surface of the metal layer is lower than the surface of the solder resist layer. You can
On the other hand, since the surface of the metal layer is swollen, it is possible to suppress the occurrence of voids in the solder, as described above.

Another solution is that the insulating layer having a via hole, the filled via conductor formed in the via hole, and the insulating layer are laminated, and at least a part of the filled via conductor is arranged inside thereof. A wiring board comprising: a solder resist layer having an opening,
The filled via conductor is a wiring board having a shape in which the surface has a convex bulge in the opening.

This wiring board has a filled via conductor as a connection terminal connected to an external terminal or the like. Further, in the present invention, the filled via conductor is formed in a shape having a bulging portion whose surface bulges in a convex shape in the opening of the solder resist layer. In such a wiring board, when the solder is formed on the filled via conductor, the surface of the filled via conductor swells in a convex shape, and thus voids are less likely to occur in the solder. Therefore, the crack resistance of the solder can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the filled via conductor is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

Another solution is that an insulating layer having a via hole, a filled via conductor formed in the via hole, and an insulating layer are laminated on the insulating layer, and at least a part of the filled via conductor is arranged inside thereof. A wiring board comprising a solder resist layer having an opening and a solder bump welded to the surface of the filled via conductor, wherein the filled via conductor has a shape having a bulging portion whose surface bulges in a convex shape in the opening. This is a wiring board.

This wiring board is provided with solder bumps welded to the surface of the filled via conductor as connection terminals connected to external terminals and the like. Further, in the present invention, the filled via conductor is formed in a shape having a bulging portion whose surface bulges in a convex shape in the opening of the solder resist layer. In manufacturing such a wiring board, when the solder bumps are formed on the filled via conductors, the surface of the filled via conductors bulges in a convex shape, so that voids are less likely to occur in the solder bumps. Therefore, the crack resistance of the solder bump can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the filled via conductor is swollen, the joint area with the solder bump is increased, so that the joint strength of the solder bump can be improved.

In the wiring board according to any one of the above, it is preferable that the surface of the filled via conductor is lower than the surface of the solder resist layer.

In the present invention, the surface of the filled via conductor is lower than the surface of the solder resist layer. For this reason,
When the terminal of the electronic component or the like is connected to the connection terminal, the electronic component or the like can be mounted in a good state. On the other hand, since the surface of the filled via conductor is swollen, it is possible to suppress the occurrence of voids in the solder, as described above.

Another solution is an insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, and a second filled via conductor formed in the second via hole. And a solder resist layer which is laminated on the insulating layer and has an opening in which at least a part of the first filled via conductor is arranged, and which covers the second filled via conductor, and the first resist in the opening. A wiring board comprising: a metal layer deposited on the surface of a filled via conductor, wherein the first filled via conductor has a shape having a convex bulge on the surface in the opening, The layer also has a shape in which its surface bulges in a convex shape following the surface of the first filled via conductor, and the surface of the second filled via conductor bulges in a convex shape. A wiring substrate has a shape having a bulging portion I.

This wiring board includes a metal layer formed on the surface of the first filled via conductor in the opening of the solder resist layer as a connection terminal connected to an external terminal or the like. Further, in the present invention, the first filled via conductor has a shape having a bulging portion in which the surface is bulged in a convex shape in the opening of the solder resist layer, and the metal layer deposited on the surface is also the first Following the surface of the filled via conductor, the surface has a convex shape.
In such a wiring board, when the solder is formed on the metal layer, the surface of the metal layer bulges in a convex shape, and thus voids are less likely to occur in the solder. Therefore, the crack resistance of the solder can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the metal layer is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

On the other hand, this wiring board has a second filled via conductor covered with a solder resist layer. A wiring board having such a via conductor may have a void on the via conductor when a solder resist layer is formed in manufacturing the wiring board. When a void is generated, the solder resist layer is easily peeled off from that portion. On the other hand, according to the present invention, the second filled via conductor has a shape in which the surface thereof has a convex bulge. Therefore, when the solder resist layer is formed, voids are unlikely to occur on the second filled via conductor. Therefore, the reliability of the wiring board can be improved.

Another solution is an insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, and a second filled via conductor formed in the second via hole. And a solder resist layer which is laminated on the insulating layer and has an opening in which at least a part of the first filled via conductor is arranged, and which covers the second filled via conductor, and the first resist in the opening. A metal layer deposited on the surface of the filled via conductor, and a solder bump deposited on the surface of the metal layer,
A wiring board comprising: a first filled via conductor having a bulging portion whose surface bulges in a convex shape in the opening; and the metal layer also follows the surface of the first filled via conductor. The surface of the second filled via conductor is bulged in a convex shape, and the second filled via conductor has a bulge in which the surface is bulged in a convex shape.

This wiring board is provided with a metal layer formed on the surface of the first filled via conductor in the opening of the solder resist layer and a solder bump welded to the metal layer as a connection terminal connected to an external terminal or the like. Then, in the present invention, the first filled via conductor has a shape having a bulging portion whose surface is convexly bulged in the opening of the solder resist layer, and the metal layer adhered to the surface is also
Following the surface of the first filled via conductor, the surface has a convex shape. Such a wiring board
At the time of manufacturing, when forming the solder bump on the metal layer, since the surface of the metal layer is bulged in a convex shape, voids are less likely to occur in the solder bump. Therefore, the crack resistance of the solder bump can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the metal layer is swollen, the joint area with the solder bump is increased, so that the joint strength of the solder bump can be improved.

On the other hand, in the present invention, the second filled via conductor covered with the solder resist layer is provided, and the second filled via conductor is formed in a shape having a bulged portion whose surface bulges in a convex shape. Therefore, when the solder resist layer is formed during manufacturing, voids are unlikely to occur on the second filled via conductor. Therefore, the reliability of the wiring board can be improved.

Further, in the wiring board according to any one of the above, it is preferable that the surface of the metal layer is lower than the surface of the solder resist layer.

In the present invention, the surface of the metal layer is lower than the surface of the solder resist layer. Therefore, when the terminal of the electronic component or the like is connected to the connection terminal, the electronic component or the like can be mounted in a good state. On the other hand, since the surface of the metal layer is swollen, it is possible to suppress the occurrence of voids in the solder, as described above.

Another solution is to provide an insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, and a second filled via conductor formed in the second via hole. And a solder resist layer that is laminated on the insulating layer and has an opening in which at least a part of the first filled via conductor is arranged, and a solder resist layer that covers the second filled via conductor. The first filled via conductor has a shape in which the surface has a convex bulge in the opening, and the second filled via conductor has a shape in which the surface has a convex bulge. This is a wiring board.

This wiring board has a first filled via conductor as a connection terminal connected to an external terminal or the like.
Further, in the present invention, the first filled via conductor has a shape having a bulging portion whose surface bulges in a convex shape in the opening of the solder resist layer. In such a wiring board, when the solder is formed on the first filled via conductor, the surface of the first filled via conductor bulges in a convex shape, and thus voids are less likely to occur in the solder. Therefore, the crack resistance of the solder can be improved. Therefore,
Electrical connection failure is unlikely to occur at the connection terminals, and the reliability of the wiring board can be improved. Furthermore, since the surface of the first filled via conductor is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

On the other hand, according to the present invention, the second filled via conductor covered with the solder resist layer is provided, and the second filled via conductor has a shape in which the surface thereof has a convex bulge. Therefore, when the solder resist layer is formed during manufacturing, voids are unlikely to occur on the second filled via conductor. Therefore, the reliability of the wiring board can be improved.

Another solution is to provide an insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, and a second filled via conductor formed in the second via hole. And a solder resist layer laminated on the insulating layer, having an opening in which at least a part of the first filled via conductor is arranged, and covering the second filled via conductor, and a surface of the first filled via conductor. And a solder bump welded to the wiring board, wherein the first filled via conductor is
The surface of the second filled via conductor is formed into a shape having a convex bulge in the opening, and the second filled via conductor is a wiring board having a surface having a convex bulge. .

This wiring board is provided with solder bumps welded to the surface of the first filled via conductor as connection terminals to be connected to external terminals and the like. Further, in the present invention, the first filled via conductor has a shape having a bulging portion whose surface bulges in a convex shape in the opening of the solder resist layer. In manufacturing such a wiring board, when the solder bump is formed on the first filled via conductor, the surface of the first filled via conductor bulges in a convex shape, and thus the void does not easily occur in the solder bump. Therefore, the crack resistance of the solder bump can be improved. Therefore, electrical connection failure is unlikely to occur in the connection terminal, and the reliability of the wiring board can be improved. Furthermore, since the surface of the first filled via conductor swells, the bonding area with the solder bump increases,
The bonding strength of the solder bump can be improved.

On the other hand, in the present invention, the second filled via conductor covered with the solder resist layer is provided, and the second filled via conductor has a shape having a bulging portion whose surface bulges in a convex shape. Therefore, when the solder resist layer is formed during manufacturing, voids are unlikely to occur on the second filled via conductor. Therefore, the reliability of the wiring board can be improved.

Further, in the wiring board according to any one of the above, it is preferable that the surface of the first filled via conductor is lower than the surface of the solder resist layer.

In the present invention, the surface of the first filled via conductor is lower than the surface of the solder resist layer. Therefore, when the terminal of the electronic component or the like is connected to the connection terminal, the electronic component or the like can be mounted in a good state. on the other hand,
Since the surface of the first filled via conductor is swollen, it is possible to suppress the occurrence of voids in the solder, as described above.

Further, in the wiring board according to any one of the above, the thickness of the portion of the solder resist layer laminated on the bulging portion of the second filled via conductor is:
A wiring board having a thickness of 5 μm or more is preferable.

By bulging the surface of the second filled via conductor in a convex shape, it is possible to prevent the occurrence of voids on the second filled via conductor. However, if the height of the bulging portion becomes high and the thickness of the solder resist layer on the bulging portion becomes too thin, the appearance of the wiring board is impaired. On the other hand, in the present invention, the thickness of the portion of the solder resist layer laminated on the bulging portion of the second filled via conductor is 5
Since it is at least μm, it is possible to prevent the occurrence of voids on the second filled via conductor, and it is possible to improve the appearance of the wiring board.

Furthermore, in the wiring board according to any one of the above, it is preferable that the second filled via conductor has a roughened surface on the entire surface thereof.

When the convex bulging portion of the surface of the second filled via conductor is not roughened, the solder resist layer is easily peeled from the bulging portion. On the other hand, in the present invention, the entire surface of the second filled via conductor including the bulging portion is a roughened surface. Therefore, the adhesion strength between the second filled via conductor and the solder resist layer can be improved.

Further, in the above wiring board, the solder resist layer is formed by vacuum lamination, and the height of the bulging portion of the second filled via conductor is 1
A wiring board having a thickness of 5 μm or less is preferable.

When the solder resist layer is formed by vacuum laminating, if the height of the bulging portion of the second filled via conductor is high, the bulging portion is rubbed and crushed by the conveying roller or the vacuum seal roller, and the roughened surface is crushed. The surface roughness of is reduced, resulting in a smooth surface. In this case, the solder resist layer easily peels off from the bulging portion. On the other hand, in the present invention, since the height of the bulging portion is 15 μm or less, when the solder resist layer is formed after the conductor is roughened, the bulging portion may be crushed to some extent by a vacuum seal roller or the like. However, the surface roughness is maintained to some extent. Therefore, the adhesion strength between the second filled via conductor and the solder resist layer can be improved, and the reliability of the wiring board can be improved.

Furthermore, it is preferable that the above-mentioned wiring board is such that the height of the bulging portion of the second filled via conductor is 5 μm or less.

According to the present invention, since the height of the bulging portion of the second filled via conductor is as low as 5 μm or less, the bulging portion itself is less likely to be crushed when the solder resist layer is formed, and the surface roughness thereof is reduced. Is maintained. Therefore, it is possible to further improve the adhesion strength between the second filled via conductor and the solder resist layer and further improve the reliability of the wiring board.

Another solution is an insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, and a second filled via conductor formed in the second via hole. And a solder resist layer which is laminated on the insulating layer and has an opening in which at least a part of the first filled via conductor is arranged, and which covers the second filled via conductor, and the first resist in the opening. A metal layer deposited on the surface of the filled via conductor, and solder bumps deposited on the surface of the metal layer,
And the first filled via conductor has a shape having a bulge in which the surface bulges in a convex shape in the opening, and the surface of the metal layer also follows the surface of the first filled via conductor. A method of manufacturing a wiring board having a convex bulge, wherein the second filled via conductor has a convex bulge on the surface thereof, wherein the bulge is formed by electrolytic plating. A filled via forming step of simultaneously forming a first filled via conductor having a portion and a second filled via conductor having the bulged portion, wherein the height of the bulged portion is 15 μm or less and the filled via is formed. Forming step, roughening step of roughening the entire surface of the second filled via conductor, and vacuum laminating to form the solder resist layer on the insulating layer. And over the resist layer forming step, a method of manufacturing a wiring board comprising a.

As described above, if the convexly bulged portion of the surface of the second filled via conductor is not roughened, the solder resist layer is easily peeled off from the bulged portion. It is preferable to roughen the entire surface of the conductor. However, when the solder resist layer is formed by vacuum lamination, if the height of the bulging portion is high,
The bulging portion is rubbed and crushed by the transport roller and the vacuum seal roller, and the surface roughness of the roughened surface is reduced, resulting in a smooth surface.
In this case, the solder resist layer easily peels off from the bulging portion.

On the other hand, in the present invention, the height of the bulging portion is increased in the filled via forming step in which the first filled via conductor having the bulging portion and the second filled via conductor having the bulging portion are simultaneously formed by electrolytic plating. Form a second filled via conductor having a thickness of 15 μm or less. Then, the entire surface of the second filled via conductor is roughened, and then a solder resist layer is formed on the insulating layer and the second filled via conductor by vacuum lamination. If the height of the bulging portion of the second filled via conductor is suppressed to 15 μm or less, the bulging portion may be crushed to some extent when the solder resist layer is formed after the conductor is roughened. The surface roughness is maintained to some extent. Therefore, the adhesion strength between the second filled via conductor and the solder resist layer can be improved, and the reliability can be improved.

Another solution is to provide an insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, and a second filled via conductor formed in the second via hole. And a solder resist layer laminated on the insulating layer, having an opening in which at least a part of the first filled via conductor is arranged, and covering the second filled via conductor, and a surface of the first filled via conductor. And a solder bump welded to
The second filled via conductor is a method of manufacturing a wiring board in which the surface has a bulging portion that bulges in a convex shape, and the first filled via conductor has the bulging portion by electrolytic plating.
A filled via forming step of simultaneously forming a filled via conductor and a second filled via conductor having the bulged portion, the filled via forming step of forming the second filled via conductor having a height of the bulged portion of 15 μm or less; A roughening step of roughening the entire surface of the second filled via conductor;
And a solder resist layer forming step of forming the solder resist layer on the insulating layer by vacuum lamination.

In the present invention, the height of the bulging portion is 15 μm or less in the filled via forming step in which the first filled via conductor having the bulging portion and the second filled via conductor having the bulging portion are simultaneously formed by electrolytic plating. A second filled via conductor is formed. Then, the entire surface of the second filled via conductor is roughened, and then a solder resist layer is formed on the insulating layer and the second filled via conductor by vacuum lamination. If the height of the bulging portion of the second filled via conductor is suppressed to 15 μm or less, the bulging portion may be crushed to some extent when the solder resist layer is formed after the conductor is roughened. The surface roughness is maintained to some extent.
Therefore, the adhesion strength between the second filled via conductor and the solder resist layer can be improved, and the reliability can be improved.

Further, it is preferable that in the method of manufacturing a wiring board described above, in the filled via forming step, the second filled via conductor having a height of the bulging portion of 5 μm or less is formed.

According to the present invention, the height of the bulging portion of the second filled via conductor is further reduced to 5 μm or less. By doing this, when the solder resist layer is formed,
The bulging portion itself is less likely to be crushed and its surface roughness is maintained. Therefore, it is possible to further improve the adhesion strength between the second filled via conductor and the solder resist layer and further improve the reliability.

[0060]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a partial cross-sectional view of the wiring board 101 of the present embodiment. Further, FIG. 2 is a partially enlarged cross-sectional view near the main surface side connection terminal 135, FIG. 3 is a partially enlarged cross sectional view near the second filled via conductor 130 of the main surface side second insulating layer 124, and FIG. The partial expanded sectional view of the terminal 155 vicinity is shown.

The wiring board 101 has a substantially rectangular plate shape having a substrate main surface 102 on which an IC chip IC indicated by a broken line in FIG. 1 is mounted and a substrate back surface 103 connected to a mother board (not shown). . The wiring board 101 is made of glass-epoxy resin and has a thickness of about 800 μm at its center.
Core substrate 111. The core main surface 112 of the core substrate 111 has a thickness of about 35 made of epoxy resin or the like.
A main surface side first insulating layer 121 having a thickness of μm is stacked, and a main surface side second insulating layer 124 having a thickness of about 35 μm, which is also made of an epoxy resin or the like, is stacked on the main surface side first insulating layer 121.
Similarly, a main surface side solder resist layer 133 having a thickness of about 25 μm and made of epoxy resin or the like is laminated. Similarly, on the core back surface 113 of the core substrate 111, a back surface side first insulating layer 14 made of epoxy resin or the like and having a thickness of about 35 μm is formed.
1 is laminated, and a back side second insulating layer 144 having a thickness of about 35 μm and also made of an epoxy resin or the like is laminated thereon. The side solder resist layer 153 is laminated.

The surface of the main surface side first insulating layer 121, the surface of the main surface side second insulating layer 124, and the back surface side first insulating layer 1
The surface of 41 and the surface of the back surface side second insulating layer 144 are roughened surfaces each having a surface roughness Ra of about 0.5 μm (see FIGS. 2 to 4). This is for improving the adhesion between the insulating layers, the adhesion between the insulating layer and the solder resist layer, and the adhesion between the insulating layer and a conductor layer described later.

A large number of through holes 115 having a diameter of about 350 μm are formed through the core substrate 111 at predetermined positions, and the inner peripheral surface of the through holes 115 is made of Cu and has a thickness of about 20 μm. The hole conductors 116 are formed respectively. In each through-hole conductor 116, a substantially columnar resin filling body 117 made of epoxy resin or the like is formed.

A large number of via holes 122 having an opening diameter of about 65 μm are formed through the main surface side first insulating layer 121 at predetermined positions, and a filled via conductor 123 made of Cu is formed inside and on the via holes 122. Each is formed. Specifically, each of the filled via conductors 123 has a substantially truncated cone-shaped truncated cone portion formed in the via hole 122, and a diameter of about 125 μm and a thickness of about 1 μm formed thereon.
And a disc-shaped disc portion of 4.5 μm. Furthermore, on the center of the disc, it bulges convexly and the diameter of the bottom surface is about 55μ.
m, and the height is about 5 μm. That is, the filled via conductor 123 has a shape having a bulging portion whose surface bulges in a convex shape. Also, filled via conductor 1
The entire surface of 23 is a roughened surface having a surface roughness Ra of about 0.5 μm in order to improve the adhesion with the main surface side second insulating layer 127.

Further, as shown in FIGS. 1 to 3, the main surface side second insulating layer 124 also has an opening diameter of about 65 μm penetrating therethrough.
A large number of via holes 125 are formed at predetermined positions, and filled via conductors 128 made of Cu are formed inside and on the via holes 125, respectively. Specifically, the via hole 125 can be classified into a first via hole 126 arranged under the region where the IC chip IC is mounted and a second via hole 127 arranged under the other region. The first filled via conductor 1 is provided in the first via hole 126.
29, a second filled via conductor 130 is formed in the second via hole 127. First filled via conductor 12
9 and the second filled via conductor 130, the first via hole 1
26 or substantially circular truncated cone-shaped truncated cone portions 129P and 130P formed in the second via hole 127, and disk-shaped disc portions 129Q and 130Q having a diameter of approximately 125 μm and a thickness of approximately 14.5 μm formed thereon. (See FIGS. 2 and 3). Further, on the centers of the disk portions 129Q and 130Q, there are bulged portions 129R and 130R that bulge in a convex shape and have a bottom diameter of approximately 55 μm and a height of approximately 5 μm. That is,
These first and second filled via conductors 129 and 130 are
The surface is formed to have bulging portions 129R and 130R bulging in a convex shape. In addition, the entire surface of the first and second filled via conductors 129 and 130 has surface roughness Ra in order to improve adhesion with the main surface side solder resist layer 133.
= About 0.5 μm roughened surface.

As shown in FIGS. 1 and 2, the main surface side solder resist layer 133 has a diameter of about 60 μ which penetrates it.
A large number of main surface side openings 134 of m are formed in a substantially lattice shape in a plan view in a region where the IC chip IC is mounted. Inside the main surface side opening 134, the central portion of the first filled via conductor 129 formed in the main surface side second insulating layer 124, specifically, the bulging portion 129R of the first filled via conductor 129 is located. ing. Then, in each main surface side opening 134, the first
IC connected to field via conductor 129 and mounted on the other side
Main surface side connection terminals 135 connected to the terminals of the chip IC are respectively formed. These main surface side connection terminals 13
5 is a main surface side Ni plating layer 136 having a thickness of about 7 μm deposited on the surface of the first filled via conductor 129 in the main surface side opening 134, and is welded to the surface of the main surface side Ni plating layer 136. The solder bumps 138 project beyond the surface of the surface-side solder resist layer 133.

Of these, since the main surface side Ni plating layer 136 has a substantially uniform thickness (about 7 μm), the surface thereof is made to be convex so as to follow the surface of the first filled via conductor 129. There is. The depth of the main surface side opening 134 (the thickness of the main surface side solder resist layer 133) is about 25 μm.
Since the height of the bulging portion 129R of the first filled via conductor 129 is about 5 μm and the thickness of the main surface side Ni plating layer 136 is about 7 μm, the surface of the main surface side Ni plating layer 136 is Is about 12 from the bottom surface of the main surface side opening 134.
It is at a height of μm. Therefore, the Ni plating layer 136 on the main surface side
Surface is lower than the surface of the main surface side solder resist layer 133. On the other hand, the entire surface of the second filled via conductor 130 formed on the main surface side second insulating layer 124 is covered with the main surface side solder resist layer 133 (see FIGS. 1 and 3). The thickness of the portion of the main surface side solder resist layer 133 that is stacked on the bulging portion 130R of the second filled via conductor 130 is approximately 5.5 μm.

As shown in FIG. 1, the back side first insulating layer 14
1, a number of via holes 142 having an opening diameter of about 65 μm are formed at predetermined positions, and filled via conductors 143 made of Cu are formed inside and on the via holes 142. Specifically, each of the filled via conductors 143, like the filled via conductors 123 and 128, includes a truncated cone portion, a disk portion, and a bulging portion, and has a shape having a bulging portion whose surface bulges in a convex shape. ing. In addition, the entire front surface is a roughened surface in order to improve the adhesion with the second back insulating layer 144.

Further, as shown in FIGS. 1 and 4, the back side second insulating layer 144 also has an opening diameter of about 65 μ which penetrates the second back side insulating layer 144.
a large number of m via holes 145 are formed at predetermined positions,
Filled via conductors 148 made of Cu are formed in and on the inside of the conductors. Specifically, each of the filled via conductors 148 corresponds to each of the filled via conductors 12.
Similar to 3,128,143, a substantially truncated cone-shaped truncated cone portion 148P formed in the via hole 145 and a disk-shaped disc portion 148Q having a diameter of about 800 μm and a thickness of about 14.5 μm formed thereon. And a bulging portion 148 that bulges convexly above the center and has a bottom surface diameter of approximately 55 μm and a height of approximately 5 μm.
And R (see FIG. 4). Therefore, the filled via conductor 148 also has a shape having a bulged portion 148R whose surface bulges in a convex shape. In addition, the filled via conductor 14
In order to improve the adhesion with the back side solder resist layer 153, the entire surface of No. 8 has a surface roughness Ra of about 0.5 μm.
It is said to be a roughened surface.

The rear surface side solder resist layer 153 has a large number of rear surface side openings 15 having a diameter of about 650 μm and penetrating therethrough.
4 are formed in a substantially lattice shape in a plan view (see FIGS. 1 and 4). Inside these rear surface side openings 154, the rear surface side second
The central portion of the filled via conductor 148 formed in the insulating layer 144, specifically, the bulging portion 1 of the filled via conductor 148.
48R and a part of the disk portion 148Q are located. Then, the filled via conductor 148 is provided in each back surface side opening 154.
And rear surface side connection terminals 155 which are connected to the terminals of the motherboard on the other side. These back side connection terminals 155 have a thickness of about 7 μm deposited on the surface of the filled via conductor 148 in the back side opening 154.
The back side Ni plating layer 156 and the back side Au plating layer 157 having a thickness of about 0.05 μm deposited on the surface of the back side Ni plating layer 156.

Of these, since the back surface side Ni plating layer 156 has a substantially uniform thickness (about 7 μm), the surface thereof is convexly bulged following the surface of the filled via conductor 148. The depth of the back surface side opening 154 (the thickness of the back surface side solder resist layer 153) is about 25 μm, the height of the bulging portion 148R of the filled via conductor 148 is about 5 μm, and the back surface side Ni plating layer 156 is formed. Is about 7 μm and the thickness of the back side Au plating layer 157 is about 0.05 μm, the surface of the metal layer (the surface of the back side Au plating layer 156) is about 12 μm from the bottom surface of the back side opening 154. At the height of. Therefore, the surface of the metal layer is lower than the surface of the backside solder resist layer 153.

Core substrate 111 and main surface side first insulating layer 121
As shown in FIG. 1, a main surface side first conductor layer 161 made of Cu and having a thickness of about 35 μm is formed between the layers and.
The main surface side first conductor layer 161 is a power plane layer that is at a power potential and is formed in a substantially solid shape. The main surface side first conductor layer 161 is connected to a part of the through-hole conductor 116 of the core substrate 111 and a part of the filled via conductor 123 of the main surface side first insulating layer 121. Further, between the main surface side first insulating layer 121 and the main surface side second insulating layer 124, a main surface side second conductor layer 163 of Cu having a thickness of about 14.5 μm is formed. This main surface side second conductor layer 16
Reference numeral 3 is a wiring layer having a predetermined pattern including wiring and the like. The main surface side second conductor layer 163 is connected to the filled via conductor 123 of the main surface side first insulating layer 121 and the filled via conductor 128 of the main surface side second insulating layer 124. Further, between the main surface side second insulating layer 124 and the main surface side solder resist layer 133, a main surface side third conductor layer 165 of Cu having a thickness of about 14.5 μm is formed. The main surface side third conductor layer 165 is a conductor layer having a predetermined pattern that partially includes wiring and the like. The main surface side third conductor layer 165 is connected to the filled via conductor 128 of the main surface side second insulating layer 124 and the main surface side connection terminal 135.

On the other hand, between the core substrate 111 and the backside first insulating layer 141, a backside first conductor layer 171 having a thickness of about 35 μm and made of Cu is formed. The back surface side first conductor layer 171 is a ground plane layer that is at a ground potential and is formed in a substantially solid shape. Back side first conductor layer 1
Reference numeral 71 denotes a part of the through-hole conductor 116 of the core substrate 111 and the filled via conductor 14 of the back-side first insulating layer 141.
It is connected to part of 3. In addition, the back side first insulating layer 14
A backside second conductor layer 173 having a thickness of about 14.5 μm and made of Cu is formed between the layer 1 and the backside second insulating layer 144. The back surface side second conductor layer 173 is a wiring layer having a predetermined pattern including wiring, and is connected to the filled via conductor 143 of the back surface side first insulating layer 141 and the filled via conductor 148 of the back surface side second insulating layer 144. . In addition, a thickness of about 14.5 μm made of Cu is provided between the back side second insulating layer 144 and the back side solder resist layer 153.
A third conductor layer 175 on the back side of m is formed. The back surface side third conductor layer 175 is a conductor layer having a predetermined pattern partially including wiring and the like, and is connected to the filled via conductor 148 and the back surface side connection terminal 155 of the back surface side second insulating layer 144.

In manufacturing the wiring board 101 as described above, the solder bumps 13 are formed on the Ni plating layer 136 on the main surface side.
Since the surface of the Ni plating layer 136 on the main surface side is convexly bulged when forming No. 8, voids are less likely to occur in the solder bump 138. Therefore, even when thermal stress is applied to the wiring board 101, the stress is not locally concentrated on the void portion, so that the crack resistance of the solder bump 138 is improved. Therefore, the main surface side connection terminal 135
The electrical connection failure is unlikely to occur, and the reliability can be improved. Furthermore, since the surface of the Ni plating layer 136 on the main surface side swells, the bonding area with the solder bump 138 increases, so that the bonding strength of the solder bump 138 can be improved.

When connecting the wiring board 101 to the mother board, when solder is applied to the back side Ni plating layer 156, the surface of the back side Ni plating layer 156 bulges in a convex shape, so that a void is formed in the solder. Unlikely to occur. Therefore, even when thermal stress is applied to the wiring board 101, the stress is not locally concentrated on the void portion, and the crack resistance of the solder is improved. Therefore, electrical connection failure is unlikely to occur in the back surface side connection terminal 155, and reliability can be improved. Further, since the surface of the back Ni plating layer 156 is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

Further, in the present embodiment, the surface of the main surface side Ni plating layer 136 (the surface of the metal layer) is lower than the surface of the main surface side solder resist layer 133, so that the main surface side Ni plating layer is formed. Although the surface of 136 is swollen, the IC chip IC can be mounted in a good state. Moreover, since the surface of the back side Au plating layer 157 (the surface of the metal layer) is lower than the surface of the back side solder resist layer 153, the surface of the back side Au plating layer 157 is swollen despite the fact that it is swollen. , When connected to the motherboard, the connection state with the motherboard can be improved.

Further, in this embodiment, the second filled via conductor 13 covered with the main surface side solder resist layer 133 is used.
Since the surface of No. 0 bulges in a convex shape, a void is unlikely to be formed on the second filled via conductor 130 when the main surface side solder resist layer 133 is formed in the manufacturing thereof. Therefore, the reliability of the wiring board 101 can be improved. Moreover, the principal surface side solder resist layer 1 laminated on the bulging portion 130R of the second filled via conductor 130
Since the thickness of 33 (about 5.5 μm) is 5 μm or more,
It is possible to prevent the occurrence of voids on the second filled via 130, and also to improve the appearance of the wiring board 101. In addition, the entire surface of the second filled via conductor 130 including the bulged portion 130R is a roughened surface. Therefore, the adhesion strength between the second filled via conductor 130 and the main surface side solder resist layer 133 can be improved.

Next, a method of manufacturing the wiring board 101 will be described with reference to the drawings. First, the core substrate 111
Is prepared, and through holes 115 are drilled at predetermined positions with a drill or the like (see FIG. 5).

Next, Cu electroless plating and Cu electrolytic plating are sequentially performed to form a substantially cylindrical through hole conductor 116 on the inner peripheral surface of the through hole 115, and the core main surface 11
2 and a solid conductor layer are formed on substantially the entire surface of the core back surface 113. After that, a resin paste is printed and filled in the through-hole conductor 116, and the resin paste is thermoset to form a resin filling body 117. Then, the end portion of this resin filling body 117 is removed by polishing, and the core main surface 112 and the core back surface 113
To make it flush. Further, Cu electroless plating and Cu electrolytic plating are sequentially performed to form a lid plating layer on the resin filling body 117. After that, an etching resist layer having a predetermined pattern is formed on each of the solid conductor layers on the core main surface 112 and the core back surface 113 by a known photolithography method. Then, the conductor layer exposed from the etching resist layer is removed by etching to form the main surface side first conductor layer 161 and the back surface side first conductor layer 171 from the solid conductor layer.

Next, in the first conductor roughening step, the main surface side first conductor layer 1 is roughened by a known chemical roughening treatment, for example, using a roughening treatment liquid containing CuCl 2 or the like.
The surface of 61 and the surface of the back side first conductor layer 171 are roughened to a surface roughness Ra = about 0.7 μm.

Next, in the first insulating layer forming step, the first main surface side having the via holes 122 at predetermined positions on the core main surface 112 and the main surface side first conductor layer 161 by a known photolithography method. The insulating layer 121 is formed. Similarly, the core back surface 113 and the back surface side first conductor layer 17 are similarly formed.
A first back surface side insulating layer 141 having a via hole 142 at a predetermined position is formed on the first surface.

Next, in the first insulating layer roughening step, the main surface side first insulating layer is roughened by using a known chemical roughening treatment, for example, a roughening treatment liquid containing KMnO4 or the like. The surface of 121 and the surface of the back surface side first insulating layer 141 are roughened to a surface roughness Ra = about 0.5 μm.

Next, in the first filled via forming step, the filled via conductor 123 is formed in the via hole 122 of the main surface side first insulating layer 121 by Cu plating, and the filled via conductor is formed in the via hole 142 of the back surface side first insulating layer 141. 143 is formed. Further, the main surface side second conductor layer 163 is formed on the main surface side first insulating layer 121, and the back surface side second conductor layer 173 is formed on the back surface side first insulating layer 141. Specifically, Cu electroless plating is applied to the first main surface side.
An electroless plating layer is formed on the insulating layer 121 and the via hole 122 thereof, and on the back side first insulating layer 141 and the via hole 142. Then, the main surface side first insulating layer 12
A plating resist layer having a predetermined pattern is formed on the electroless plating layer on 1 and the electroless plating layer on the back side first insulating layer 141 by a known photolithography method. next,
Cu electroplating is performed, and the filled via conductor 123, on the electroless plating layer exposed from each plating resist layer,
A predetermined pattern of electrolytic plating including 143 is formed. At that time, Cu electrolytic plating is performed until the surfaces of the filled via conductors 123 and 143 swell and bulges each having a height of about 5 μm are formed. After that, the plating resist layers are peeled off, and the exposed electroless plating layer is removed by etching to form a main surface side second conductor layer 163 and a back surface side second conductor layer 173 having a predetermined pattern. In addition, in the Cu electrolytic plating, a plating solution for forming a filled via conductor is used.

Next, in the second conductor roughening step, the filled via conductor 1 is roughened by a known chemical roughening treatment, for example, using a roughening treatment liquid containing CuCl 2 or the like.
The surface of 23, 143, the surface of the main surface side second conductor layer 163, and the surface of the back surface side second conductor layer 173 are roughened to a surface roughness Ra = about 0.5 μm.

Next, in the second insulating layer forming step, on the main surface side first insulating layer 121 and the main surface side second conductor layer 163,
Via hole 125 is formed by a known photolithography method.
The main surface side second insulating layer 124 having a predetermined position is formed. Similarly, the back surface side second insulating layer 144 having the via hole 145 at a predetermined position is formed on the back surface side first insulating layer 141 and the back surface side second conductor layer 173.

Next, in the second insulating layer roughening step, the main surface side second insulating layer is roughened by a known chemical roughening treatment, for example, using a roughening treatment liquid containing KMnO4 or the like. The surface of 124 and the surface of the back surface side second insulating layer 144 are roughened to a surface roughness Ra = about 0.5 μm. In this way
The substrate shown in FIG. 5 is produced.

Next, in the second filled via forming step, as shown in FIG.
The filled via conductor 1 is provided in the via hole 125 of the insulating layer 124.
28, the filled via conductor 148 is formed in the via hole 145 of the second back surface side insulating layer 144. In addition, the main surface side third conductor layer 16 is provided on the main surface side second insulating layer 124.
5 is formed, and the back surface side third conductor layer 175 is formed on the back surface side first insulating layer 144. Specifically, Cu electroless plating is performed, and the main surface side second insulating layer 124 and its via hole 125 (first via hole 126 and second via hole 12) are formed.
7), an electroless plating layer is formed on the second insulating layer 144 on the back surface side and in the via hole 145. After that, on the electroless plating layer on the main surface side second insulating layer 124 and on the back surface side second
A plating resist layer having a predetermined pattern is formed on the electroless plating layer on the insulating layer 144 by a known photolithography method. Next, Cu electrolytic plating is performed, and the filled via conductor 128 (the first filled via conductor 129 and the second filled via conductor 129 is formed on the electroless plating layer exposed from each plating resist layer).
Filled via conductor 130) and filled via conductor 14
Electrolytic plating of a predetermined pattern including 8 is formed. At that time, the filled via conductor 128 (the first filled via conductor 1
29 and the second filled via conductor 130) and the surface of the filled via conductor 148 are swollen to form swollen portions 129R, 130R, 148R having a height of about 5 μm, respectively.
u Electrolytic plating is performed. Next, the plating resist layers are peeled off, and the exposed electroless plating layer is removed by etching to form a main surface side third conductor layer 165 and a back surface side third conductor layer 175 having a predetermined pattern. In addition, in the Cu electrolytic plating, a plating solution for forming a filled via conductor is used.

Next, in the third conductor roughening step, the entire surface of the filled via conductor 128 (the first filled via conductor 129 and the second filled via conductor 130) and the entire surface of the filled via conductor 148, and the main surface side third conductor layer 165.
And the entire surface of the back side third conductor layer 175 are roughened. Specifically, these surfaces are roughened using a known chemical roughening treatment, for example, a roughening treatment liquid containing CuCl2 or the like, so that the surface roughness Ra is about 0.5 μm.
roughen to m.

Next, in the solder resist layer forming step, as shown in FIG. 7, on the main surface side second insulating layer 124 and the main surface side third conductor layer 165, a known vacuum laminating method and photolithography method are used. The main surface side solder resist layer 133 having the main surface side opening 134 at a predetermined position is formed. Similarly, the back surface side solder resist layer 153 having the back surface side opening 154 at a predetermined position is formed on the back surface side second insulating layer 144 and the back surface side third conductor layer 175. Specifically, by vacuum lamination, the main surface side second
An uncured main surface side solder resist layer is laminated on the insulating layer 124 and the main surface side third conductor layer 165, and an uncured back surface side is formed on the back surface side second insulating layer 144 and the back surface side third conductor layer 175. Laminate a solder resist layer. At that time, since the transport roller and the vacuum seal roller come into contact with the front and back surfaces of the substrate, they also come into contact with the tops of the filled via conductors 129, 130, 148, respectively, but the bulged portions 129R, 130R,
Since the height of 148R is suppressed to 5 μm or less, the bulged portions 129R, 130R, 148R are not crushed and the surface roughness is prevented from being lowered. Then, the main surface side solder resist layer 133 having a predetermined pattern having the main surface side opening 134 and the back surface side opening 154 are formed by photolithography.
Backside solder resist layer 15 having a predetermined pattern
3 is formed.

Next, as shown in FIG. 8, electroless Ni plating is applied to the filled via conductor 128 (first filled via conductor 129) exposed in the main surface side opening 134 of the main surface side solder resist layer 133. Ni plating layer 13 on the main surface side
6 is attached. At the same time, the back side Ni plating layer 156 is also deposited on the filled via conductor 148 exposed in the back side opening 154 of the back side solder resist layer 153. Then, Au plating is applied, and to prevent oxidation, a very thin film of about 0.0 is formed on the Ni plating layer 136 on the main surface side.
While forming the main surface side Au plating layer 137 of 5 μm,
On the back side Ni plating layer 156, very thin, about 0.05
A backside Au plated layer 157 having a thickness of μm is formed to serve as a backside connection terminal 155.

Next, solder bumps 138 are formed on the main surface side Ni plating layer 133 to form main surface side connection terminals 135 (see FIG. 1). Specifically, first, using a print mask having a predetermined pattern corresponding to the main surface side openings 134, solder paste is printed on each main surface side opening 134. afterwards,
This is reflowed to form solder bumps 138. At that time, since Au of the main surface side Au plating layer 137 diffuses into the solder, the solder bumps 135 are welded to the main surface side Ni plating layer 136 as described above. The wiring board 101 is completed as described above.

As described above, in this embodiment,
In the filled via forming process, the height (about 5 μm) of the bulging portion 130R of the second filled via conductor 130 is set to 5 μm.
It is kept below. Therefore, after the conductor is roughened, when the main surface side solder resist layer 133 is vacuum-laminated, the transport roller and the vacuum seal roller are connected to the second filled via 130.
Even if the bulging portion 130R comes into contact with the bulging portion 130R, the bulging portion 130R is less likely to be crushed and the surface roughness is maintained. Therefore, the second
Field via conductor 130 and main surface side solder resist layer 1
The adhesion strength with 33 can be improved, and the reliability can be improved.

(Results of Investigation) Wiring board 101 of this embodiment
For the above, the occurrence rate of voids in the solder bump 138 and the maximum size of the void in the solder bump 138 were investigated. Further, for comparison, the same investigation was conducted on the wiring board according to the conventional technique. Specifically, in the wiring board of the conventional form 1, the surface of the first filled via 129 is 5 to 20.
It is recessed by μm. In the wiring board of Comparative Example 2, the surface of the first filled via 129 is recessed by 0 to 5 μm. The results are summarized in Table 1.

[0094]

[Table 1]

As can be seen from Table 1, the wiring board of Comparative Example 1 had a void generation rate of 57.6% and the wiring board of Comparative Example 2 had a void generation rate of 50.0%. In the wiring board 101 of the present embodiment, the void occurrence rate is significantly suppressed to 20.0%. Also, regarding the size (maximum size) of the voids, the wiring board of Comparative Example 1 has a size of 13.0 μm, and the wiring board of Comparative Example 2 has a size of 1 μm.
The wiring board 1 according to the present embodiment has a thickness of 0.1 μm.
In No. 01, it was reduced to 4.6 μm. From the above results, by applying the present invention, the solder bump 13
It is possible to suppress the generation of voids inside the wiring board 8 and improve the reliability of the wiring board.

(Second Embodiment) Next, a second embodiment will be described. The description of the same parts as those in the first embodiment will be omitted or simplified. FIG. 9 shows a partial cross-sectional view of the wiring board 201 of the present embodiment. Further, FIG. 10 is a partially enlarged sectional view of the vicinity of the main surface side connection terminal 235,
FIG. 11 shows a partially enlarged sectional view of the second insulating layer 124 on the main surface side in the vicinity of the second filled via conductor 130, and FIG.

This wiring board 201 is similar to the first embodiment, and the main surface 102 of the board on which the IC chip IC is mounted.
And a substrate back surface 103 connected to the mother board, and has a substantially rectangular plate shape. The wiring board 201 is
A core substrate 111 is provided in the center, and a main surface side first insulating layer 121 and a main surface side second insulating layer 12 are provided on the core main surface 112 side.
4 and the main surface side solder resist layer 133 are laminated, and the core back surface 113 side is provided with a back surface side first insulating layer 141,
The back surface side second insulating layer 144 and the back surface side solder resist layer 153 are laminated.

A large number of through holes 115 are formed in the core substrate 111 at predetermined positions, through hole conductors 116 are formed on the inner peripheral surfaces of the through holes 115, and the through holes conductors 116 are formed in the through hole conductors 116. , Resin filling body 11
7 are formed. In addition, a large number of via holes 122 are formed at predetermined positions in the main surface side first insulating layer 121,
Filled via conductors 123 are formed inside and on the inside thereof, respectively. Specifically, each filled via conductor 123 has a substantially truncated cone-shaped truncated cone portion formed in the via hole 122, and a disk-shaped disc portion formed thereon. Further, a convex portion that bulges in a convex shape is provided on the center of the disc portion.

Further, as shown in FIGS. 9 to 11, a large number of via holes 125 are formed in predetermined positions in the main surface side second insulating layer 124, and filled via conductors 128 are formed inside and on the via holes 125. Each is formed. Specifically, the via hole 125 can be classified into a first via hole 126 arranged under the region where the IC chip IC is mounted and a second via hole 127 arranged under the other region. A first filled via conductor 129 is formed in the first via hole 126, and a second filled via conductor 130 is formed in the second via hole 127. Both the first filled via conductor 129 and the second filled via conductor 130 are substantially truncated cone-shaped truncated cone portions 129P and 130P formed in the first via hole 126 or the second via hole 127, and a disk-shaped disc formed thereon. And portions 129Q and 130Q (see FIGS. 10 and 11). Furthermore, the disk portion 129
A bulge portion 129R, 13 bulging in a convex shape on the center of Q, 130Q and having a bottom surface diameter of about 55 μm and a height of about 5 μm.
Has 0R. In addition, the first and second filled via conductors 12
The entire surface of 9,130 has a surface roughness Ra of about 0.5 μm.
It is said to be a roughened surface.

In the main surface side solder resist layer 133, as shown in FIGS. 9 and 10, a large number of main surface side openings 134 are formed in a region in which the IC chip IC is mounted in a substantially lattice shape in a plan view. Inside the main surface side opening 134, a central portion of the first filled via conductor 129 formed in the main surface side second insulating layer 124, specifically, the first filled via conductor 1 is formed.
The bulging part 129R of 29 is located. Then, main surface side connection terminals 235 connected to the first filled via conductor 129 and connected to the terminals of the IC chip IC mounted on the other side are formed in the respective main surface side openings 134, respectively. These main surface side connection terminals 235 are solder bumps 235 that are welded to the surface of the first filled via conductor 129 in the main surface side opening 134 and project beyond the surface of the main surface side solder resist layer 133.

The depth of the main surface side opening 134 (thickness of the main surface side solder resist layer 133) is about 25 μm,
Since the height of the bulging portion 129R of the first filled via conductor 129 is about 5 μm, the surface of the first filled via conductor 129 is lower than the surface of the main surface side solder resist layer 133. On the other hand, the entire surface of the second filled via conductor 130 formed on the main surface side second insulating layer 124 is covered with the main surface side solder resist layer 133 (see FIGS. 9 and 11). The thickness of the portion of the main surface side solder resist layer 133 that is stacked on the bulging portion 130R of the second filled via conductor 130 is approximately 5.5 μm.

As shown in FIG. 9, the back side first insulating layer 14
1, a large number of via holes 142 are formed at predetermined positions, and filled via conductors 143 are formed inside and on the via holes 142.
Are formed respectively. Specifically, each of the filled via conductors 143 has the filled via conductors 123, 128.
Similarly, it is composed of a truncated cone portion, a disk portion, and a bulging portion, and has a shape having a bulging portion whose surface bulges in a convex shape.

Further, as shown in FIGS. 9 and 12, a large number of via holes 145 are formed in predetermined positions in the second insulating layer 144 on the back surface side, and filled via conductors 148 are formed inside and on the via holes 145, respectively. Has been formed. Specifically, each filled via conductor 148 has a via hole 145, similar to the filled via conductors 123, 128, 143.
A truncated cone portion 148P having a substantially truncated cone shape formed therein, a disk portion 148Q formed on the truncated cone portion 148Q, and a convex bulge on the center thereof, the diameter of the bottom surface is about 55 μm, and the height is about 55 μm. 5
and a bulging portion 148R of μm (see FIG. 12). In addition, the entire surface of the filled via conductor 148 has a surface roughness R.
a = a roughened surface of about 0.5 μm.

A large number of rear surface-side openings 154 are formed in the rear surface-side solder resist layer 153 in a substantially lattice shape in plan view (see FIGS. 9 and 12). Inside the rear surface side opening 154, the central portion of the filled via conductor 148 formed in the second rear surface insulating layer 144, specifically, the bulging portion 148R of the filled via conductor 148 and a part of the disk portion 148Q are located. is doing. Then, in each back surface side opening 154, a back surface side connection terminal 255 is formed, which is connected to the filled via conductor 148 and is connected to the terminal of the motherboard on the other side. These back surface side connection terminals 255 are provided on the surface of the filled via conductor 148 in the back surface side opening 154 and have a thickness of about 0.05 μm on the back surface side Au plating layer 255.
Consists of.

Since the back surface side Au plating layer 255 has a substantially uniform thickness (about 0.05 μm), the surface thereof has a convex shape swelling following the surface of the filled via conductor 148. Further, the depth of the back surface side opening 154 (the thickness of the back surface side solder resist layer 153) is about 25 μm, and the bulged portion 148R of the filled via conductor 148 is
Is about 5 μm and the thickness of the back side Au plating layer 255 is about 0.05 μm, the surface of the metal layer (the surface of the back side Au plating layer 255) is from the bottom surface of the back side opening 154. It is at a height of about 5 μm. Therefore, the surface of the metal layer is lower than the surface of the backside solder resist layer 153.

As in the first embodiment, a main surface side first conductor layer 161 is formed between the core substrate 111 and the main surface side first insulating layer 121, as shown in FIG. A main surface side second conductor layer 163 is formed between the main surface side first insulating layer 121 and the main surface side second insulating layer 124, and the main surface side second insulating layer 124 and the main surface side solder are provided. Resist layer 133
A main surface side third conductor layer 165 is formed between the layers of and. Further, a back surface side first conductor layer 171 is formed between the core substrate 111 and the back surface side first insulating layer 141, and a back surface side first insulating layer 141 and a back surface side second insulating layer 144 are provided between the layers. , The back surface side second conductor layer 173 is formed, and the back surface side second insulating layer 144 and the back surface side solder resist layer 153 are formed.
A back side third conductor layer 175 is formed between the layers and.

In manufacturing the wiring board 201, the first filled via conductor 129 is formed when the solder bump 235 is formed on the first filled via conductor 129.
The surface of the solder bump 235 bulges in a convex shape.
Voids are unlikely to occur in the Therefore, the crack resistance of the solder bump 235 is improved. Therefore, the main surface side connection terminal 23
5. Electrical connection failure is unlikely to occur in 5, and reliability can be improved. Further, the first filled via conductor 129
Due to the bulging surface of the solder bump 235
Since the joint area with the solder bump 235 increases, the joint strength of the solder bump 235 can be improved.

Further, when connecting the wiring board 201 to the mother board, when soldering the back side Au plating layer 255, the surface of the back side Au plating layer 255 bulges in a convex shape, so that a void is formed in the solder. Unlikely to occur. Therefore, the crack resistance of the solder is improved. Therefore, electrical connection failure is unlikely to occur in the back surface side connection terminal 255, and reliability can be improved. Furthermore, since the surface of the back side Au plating layer 255 is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

Furthermore, in this embodiment, the surface of the first filled via conductor 129 is the main surface side solder resist layer 133.
Since it is lower than the surface of the IC chip, the IC chip IC can be mounted in a good state. Also, the back side Au
Since the surface of the plating layer 255 (the surface of the metal layer) is lower than the surface of the back side solder resist layer 153, the connection state with the motherboard can be improved when connected to the motherboard.

Further, in this embodiment, the second filled via conductor 13 covered with the main surface side solder resist layer 133 is used.
Since the surface of No. 0 bulges in a convex shape, a void is unlikely to be formed on the second filled via conductor 130 when the main surface side solder resist layer 133 is formed in the manufacturing thereof. Therefore, the reliability of the wiring board 201 can be improved. Moreover, the principal surface side solder resist layer 1 laminated on the bulging portion 130R of the second filled via conductor 130
Since the thickness of 33 (about 5.5 μm) is 5 μm or more,
It is possible to prevent the occurrence of voids on the second filled via 130, and also to improve the appearance of the wiring board 201. In addition, the entire surface of the second filled via conductor 130 including the bulged portion 130R is a roughened surface. Therefore, the adhesion strength between the second filled via conductor 130 and the main surface side solder resist layer 133 can be improved.

Next, a method of manufacturing this wiring board 201 will be described with reference to the drawings. First, the first embodiment
Similarly to the above, the substrate shown in FIG. 5 is manufactured. Next, as in the first embodiment, in the second filled via forming step, as shown in FIG. 6, the filled via conductor 128 is formed in the via hole 125 of the main surface side second insulating layer 124 and the back surface side second insulating layer is formed. Filled via conductors 148 are formed in via holes 145 in layer 144. Further, the main surface side third conductor layer 165 is formed on the main surface side second insulating layer 124, and the back surface side third conductor layer 175 is formed on the back surface side first insulating layer 144. At that time, the surfaces of the filled via conductor 128 (the first filled via conductor 129 and the second filled via conductor 130) and the filled via conductor 148 swell to a height of about 5 μm.
Cu electrolytic plating is performed until the bulged portions 129R, 130R, and 148R are formed. Next, in the third conductor roughening step, the entire surface of the filled via conductor 128 (the first filled via conductor 129 and the second filled via conductor 130) and the entire surface of the filled via conductor 148, and the entire surface of the main surface side third conductor layer 165. And the back side third conductor layer 17
The entire surface of 5 is roughened to a surface roughness Ra of about 0.5 μm.

Next, as in the first embodiment, in the solder resist layer forming step, as shown in FIG. 7, on the main surface side second insulating layer 124 and the main surface side third conductor layer 165,
The main surface side solder resist layer 133 having the main surface side opening 134 at a predetermined position is formed. Similarly, the back surface side solder resist layer 153 having the back surface side opening 154 at a predetermined position is formed on the back surface side second insulating layer 144 and the back surface side third conductor layer 175. Specifically, the uncured main surface side solder resist layer is laminated on the main surface side second insulating layer 124 and the main surface side third conductor layer 165 by vacuum lamination, and the back surface side second insulating layer 144 and An uncured back side solder resist layer is laminated on the back side third conductor layer 175. At that time, since the transport roller and the vacuum seal roller come into contact with the front and back surfaces of the substrate, the filled via conductor 129,
The bulging portions 129R, 130R, 148 are also in contact with the tops of the bulging portions 129R, 130R, 148R because the heights of the bulging portions 129R, 130R, 148R are suppressed to 5 μm or less.
R does not collapse and prevents the surface roughness from decreasing.

Next, in this embodiment, as shown in FIG. 13, Au plating is performed without Ni plating, and the filled via conductor 128 exposed in the main surface side opening 134 of the main surface side solder resist layer 133 is exposed. On the (first filled via conductor 129), a main surface side Au plating layer 237 having a thickness of about 0.05 μm is deposited. Along with this, a back side Au plating layer 255 having a thickness of about 0.05 μm is also deposited on the filled via conductor 148 exposed in the back side opening 154 of the back side solder resist layer 153, and this is connected to the back side connection terminal. It is set to 255.

Next, solder bumps 235 are formed on the first filled via conductors 129 to form main surface side connection terminals 235 (see FIG. 9). At that time, since the Au of the Au plating layer 237 on the main surface side diffuses into the solder, the solder bump 235.
Is welded to the first filled via conductor 129 as described above. The wiring board 201 is completed as described above.

As described above, also in this embodiment,
In the filled via forming process, the height (about 5 μm) of the bulging portion 130R of the second filled via conductor 130 is set to 5 μm.
It is kept below. Therefore, after the conductor is roughened, when the main surface side solder resist layer 133 is vacuum-laminated, the transport roller and the vacuum seal roller are connected to the second filled via 130.
Even if the bulging portion 130R comes into contact with the bulging portion 130R, the bulging portion 130R is less likely to be crushed and the surface roughness is maintained. Therefore, the second
Field via conductor 130 and main surface side solder resist layer 1
The adhesion strength with 33 can be improved, and the reliability can be improved.

(Third Embodiment) Next, a third embodiment will be described. The description of the same parts as those in the first or second embodiment will be omitted or simplified. FIG. 14 shows a partial cross-sectional view of the wiring board 301 of this embodiment. Further, FIG. 15 is a partially enlarged cross-sectional view near the main surface side connection terminal 335, and FIG. 16 is a partially enlarged cross sectional view near the second filled via conductor 130 of the main surface side second insulating layer 124.
FIG. 17 shows a partially enlarged cross-sectional view in the vicinity of the back surface side connection terminal 148.

This wiring board 301 is the same as that of the first embodiment.
Similar to 2, the substrate main surface 10 on which the IC chip IC is mounted
2 and a substrate back surface 103 connected to a mother board, which is a substantially rectangular plate shape. Also, the wiring board 301
Has a core substrate 111 at its center, and a core main surface 112
On the side, the main surface side first insulating layer 121, the main surface side second insulating layer 1
24 and a main surface side solder resist layer 133 are laminated, and the back surface side first insulating layer 141 is provided on the core back surface 113 side.
The back surface side second insulating layer 144 and the back surface side solder resist layer 153 are laminated.

Further, a large number of through holes 115 are formed at predetermined positions in the core substrate 111, through hole conductors 116 are formed on the inner peripheral surfaces thereof, and further, in each through hole conductor 116. , Resin filling body 11
7 are formed. In addition, a large number of via holes 122 are formed at predetermined positions in the main surface side first insulating layer 121,
Filled via conductors 123 are formed inside and on the inside thereof, respectively. Specifically, each filled via conductor 123 has a substantially truncated cone-shaped truncated cone portion formed in the via hole 122, and a disk-shaped disc portion formed thereon. Further, a convex portion that bulges in a convex shape is provided on the center of the disc portion.

Further, as shown in FIGS. 14 to 16, a large number of via holes 125 are formed at predetermined positions in the main surface side second insulating layer 124, and filled via conductors 128 are formed inside and on the via holes 125. Each is formed. Specifically, the via hole 125 can be classified into a first via hole 126 arranged under the region where the IC chip IC is mounted and a second via hole 127 arranged under the other region. A first filled via conductor 129 is formed in the first via hole 126, and a second filled via conductor 130 is formed in the second via hole 127. Both the first filled via conductor 129 and the second filled via conductor 130 are substantially truncated cone-shaped truncated cone portions 129P and 130P formed in the first via hole 126 or the second via hole 127, and a disk-shaped disc formed thereon. And portions 129Q and 130Q (see FIGS. 15 and 16). Furthermore, the disk portion 129
A bulge portion 129R, 13 bulging in a convex shape on the center of Q, 130Q and having a bottom surface diameter of about 55 μm and a height of about 5 μm.
Has 0R. In addition, the first and second filled via conductors 12
The entire surface of 9,130 has a surface roughness Ra of about 0.5 μm.
It is said to be a roughened surface.

As shown in FIGS. 14 and 15, the main surface side solder resist layer 133 has a large number of main surface side openings 134.
Are formed in a substantially lattice shape in a plan view in a region where the IC chip IC is mounted. Inside the main surface side opening 134, the central portion of the first filled via conductor 129 formed in the main surface side second insulating layer 124, specifically, the bulging portion 129R of the first filled via conductor 129 is located. ing. Then, each main surface side opening 134 is formed with a main surface side connection terminal 335 which is connected to the first filled via conductor 129 and is connected to the terminal of the IC chip IC mounted on the other side. These main surface side connection terminals 335 are solder bumps 335 that are welded to the surface of the first filled via conductor 129 in the main surface side opening 134 and project beyond the surface of the main surface side solder resist layer 133.

The depth of the main surface side opening 134 (thickness of the main surface side solder resist layer 133) is about 25 μm,
Since the height of the bulging portion 129R of the first filled via conductor 129 is about 5 μm, the surface of the first filled via conductor 129 is lower than the surface of the main surface side solder resist layer 133. On the other hand, the entire surface of the second filled via conductor 130 formed on the main surface side second insulating layer 124 is covered with the main surface side solder resist layer 133 (FIG. 14).
And FIG. 16). The thickness of the portion of the main surface side solder resist layer 133 that is stacked on the bulging portion 130R of the second filled via conductor 130 is approximately 5.5 μm.

As shown in FIG. 14, the back side first insulating layer 1
41, a large number of via holes 142 are formed at predetermined positions, and the filled via conductors 14 are formed in and on the via holes 142.
3 are formed respectively. Specifically, each of the filled via conductors 143 has the filled via conductors 123, 12
Like No. 8, it has a shape including a truncated cone portion, a disk portion, and a bulging portion, and the surface has a bulging portion bulging in a convex shape.

Also, as shown in FIGS. 14 and 17, a large number of via holes 145 are formed in predetermined positions in the second insulating layer 144 on the back surface side, and filled via conductors 148 are formed inside and on the via holes 145, respectively. Has been formed. Specifically, each of the filled via conductors 148 is similar to the filled via conductors 123, 128, 143 in the via hole 14.
5, a truncated cone portion 148P having a substantially truncated cone shape, a disk portion 148Q formed on the truncated cone portion 148Q, and a convex bulge on the center thereof, and the bottom surface has a diameter of about 55 μm and a height of The bulging portion 148R is about 5 μm (see FIG. 17). In addition, the entire surface of the filled via conductor 148 has a surface roughness R.
a = a roughened surface of about 0.5 μm.

A large number of rear surface-side openings 154 are formed in the rear surface-side solder resist layer 153 in a substantially lattice pattern in plan view (see FIGS. 14 and 17). These back side openings 154
Inside, the central portion of the filled via conductor 148 formed on the back side second insulating layer 144, specifically, the bulging portion 148R of the filled via conductor 148 and a part of the disk portion 148Q are located. And this filled via conductor 148
The terminal itself is the back surface connection terminal 148 connected to the terminal of the motherboard. The depth of the back surface side opening 154 (the thickness of the back surface side solder resist layer 153) is about 25 μm, and the height of the bulging portion 148R of the filled via conductor 148 is about 5 μm. Therefore, the surface of the filled via conductor 148 is It is lower than the surface of the backside solder resist layer 153.

As in the first and second embodiments, a main surface side first conductor layer 161 is formed between the core substrate 111 and the main surface side first insulating layer 121 as shown in FIG. The main surface side first insulating layer 121 and the main surface side second insulating layer 124
A main surface side second conductor layer 163 is formed between the main surface side second conductor layer 163 and the main surface side second insulating layer 124 and the main surface side solder resist layer 133. Are formed. A backside first conductor layer 171 is formed between the core substrate 111 and the backside first insulating layer 141, and the backside first insulating layer 141 and the backside second insulating layer 144 are formed.
And a back surface side second conductor layer 173 is formed between the back surface side second conductor layer 173 and the back surface side second insulating layer 144 and the back surface side solder resist layer 153. There is.

In manufacturing the wiring board 301, the first filled via conductor 129 is formed when the solder bump 335 is formed on the first filled via conductor 129.
The surface of the solder bump 335 bulges in a convex shape.
Voids are unlikely to occur in the Therefore, the crack resistance of the solder bump 335 is improved. Therefore, the main surface side connection terminal 33
5. Electrical connection failure is unlikely to occur in 5, and reliability can be improved. Further, the first filled via conductor 129
The solder bump 335 due to the swollen surface of the
Since the joint area with the solder bump 235 increases, the joint strength of the solder bump 235 can be improved.

When connecting the wiring board 301 to the mother board, when the filled via conductor 148 is soldered, since the surface of the filled via conductor 148 bulges in a convex shape, voids are unlikely to occur in the solder. Therefore, the crack resistance of the solder is improved. Therefore, electrical connection failure is unlikely to occur, and reliability can be improved. Further, since the surface of the filled via conductor 148 is swollen, the joint area with the solder is increased, so that the joint strength of the solder can be improved.

Further, in this embodiment, the surface of the first filled via conductor 129 is the main surface side solder resist layer 133.
Since it is lower than the surface of the IC chip, the IC chip IC can be mounted in a good state. In addition, the front surface of the filled via conductor 148 is the back side solder resist layer 153.
Since it is lower than the surface of, the connection state with the motherboard can be improved when the motherboard is connected.

Further, in this embodiment, the second filled via conductor 13 covered with the main surface side solder resist layer 133 is used.
Since the surface of No. 0 bulges in a convex shape, a void is unlikely to be formed on the second filled via conductor 130 when the main surface side solder resist layer 133 is formed in the manufacturing thereof. Therefore, the reliability of the wiring board 301 can be improved. Moreover, the principal surface side solder resist layer 1 laminated on the bulging portion 130R of the second filled via conductor 130
Since the thickness of 33 (about 5.5 μm) is 5 μm or more,
A void can be prevented from being formed on the second filled via 130, and the appearance of the wiring board 301 can be improved. In addition, the entire surface of the second filled via conductor 130 including the bulged portion 130R is a roughened surface. Therefore, the adhesion strength between the second filled via conductor 130 and the main surface side solder resist layer 133 can be improved.

Next, a method of manufacturing the wiring board 301 will be described with reference to the drawings. First, the substrate shown in FIG. 5 is manufactured in the same manner as in the first and second embodiments. Next, as in Embodiments 1 and 2, in the second filled via forming step, as shown in FIG. 6, the filled via conductor 128 is formed in the via hole 125 of the main surface side second insulating layer 124, and the back surface side first insulating layer 124 is formed. The filled via conductor 148 is formed in the via hole 145 of the second insulating layer 144. Further, the main surface side third conductor layer 165 is formed on the main surface side second insulating layer 124, and the back surface side third conductor layer 1 is formed on the back surface side first insulating layer 144.
Forming 75. At that time, the filled via conductor 128 (the first filled via conductor 129 and the second filled via conductor 1
30) and the surface of the filled via conductor 148 swells,
Cu electrolytic plating is performed until bulges 129R, 130R, and 148R having a height of about 5 μm are formed. Next, the third
In the conductor roughening step, the filled via conductor 128 (first
Filled via conductor 129 and second filled via conductor 13
0) and the entire surface of the filled via conductor 148, and the entire surface of the main surface side third conductor layer 165 and the back surface side third conductor layer 175 have a surface roughness Ra of about 0.
Coarse to 5 μm.

Next, as in Embodiments 1 and 2, in the solder resist layer forming step, as shown in FIG.
A main surface side solder resist layer 133 having a main surface side opening 134 at a predetermined position is formed on the main surface side second insulating layer 124 and the main surface side third conductor layer 165. Similarly, the back surface side solder resist layer 153 having the back surface side opening 154 at a predetermined position is formed on the back surface side second insulating layer 144 and the back surface side third conductor layer 175. Specifically, the uncured main surface side solder resist layer is laminated on the main surface side second insulating layer 124 and the main surface side third conductor layer 165 by vacuum lamination, and the back surface side second insulating layer 144 and An uncured back side solder resist layer is laminated on the back side third conductor layer 175. At that time, since the transport roller and the vacuum seal roller contact the front and back surfaces of the substrate, the filled via conductor 1
It also touches the tops of 29, 130 and 148, respectively.
Since the height of the bulging portions 129R, 130R, 148R is suppressed to 5 μm or less, the bulging portions 129R, 130R,
148R is not crushed and prevents the surface roughness from decreasing.

Next, in this embodiment, Ni plating or Au is used.
The solder bump 335 is formed on the first filled via conductor 129 without plating, and the main surface side connection terminal 335 is formed.
(See FIG. 15). As described above, the wiring board 3
01 is completed.

As described above, also in this embodiment,
In the filled via forming process, the height (about 5 μm) of the bulging portion 130R of the second filled via conductor 130 is set to 5 μm.
It is kept below. Therefore, after the conductor is roughened, when the main surface side solder resist layer 133 is vacuum-laminated, the transport roller and the vacuum seal roller are connected to the second filled via 130.
Even if the bulging portion 130R comes into contact with the bulging portion 130R, the bulging portion 130R is less likely to be crushed and the surface roughness is maintained. Therefore, the second
Field via conductor 130 and main surface side solder resist layer 1
The adhesion strength with 33 can be improved, and the reliability can be improved.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-described first to third embodiments, and is appropriately modified and applied without departing from the scope of the invention. It goes without saying that you can do it. For example, in the first embodiment, the solder bumps 138 are formed on the Ni plating layer 136 on the main surface side, but a wiring board without the solder bumps 138 can be used as a product. That is, the wiring board in the state shown in FIG. 8 can also be used. In such a wiring board, when solder is applied to the main surface side Ni plating layer 136, the surface of the main surface side Ni plating layer 136 swells in a convex shape, so that voids are unlikely to occur in the solder. Therefore,
The crack resistance of the solder can be improved. Therefore, electrical connection failure is unlikely to occur in the main surface side connection terminal,
The reliability of the wiring board can be improved. further,
Since the surface of the Ni plating layer 136 on the main surface side swells, the joint area with the solder increases, so that the joint strength of the solder can be improved. In addition, other parts similar to those of the above-described embodiment have similar effects. In addition,
Similarly, in the second and third embodiments, the wiring board without the solder bumps 235 and 335 may be used as a product.

In each of the first to third embodiments described above, the wiring board 101, 201, 301 for connecting the back surface side connection terminals 155, 255, 148 and the mother board via the solder has been described, but the back surface side connection terminal 155 and the like. It is also possible to erected the pin via solder.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a wiring board according to a first embodiment.

FIG. 2 is a partially enlarged cross-sectional view showing the vicinity of the main surface side connection terminal of the wiring board according to the first embodiment.

FIG. 3 is a partial enlarged cross-sectional view showing the vicinity of a second filled via conductor of the second insulating layer on the main surface side of the wiring board according to the first embodiment.

FIG. 4 is a partially enlarged cross-sectional view showing the vicinity of the back surface side connection terminal of the wiring board according to the first embodiment.

FIG. 5 relates to a method for manufacturing a wiring board according to the first embodiment,
It is explanatory drawing which shows the board | substrate which formed the main surface side 2nd insulating layer and the back surface side 2nd insulating layer.

FIG. 6 relates to a method for manufacturing a wiring board according to the first embodiment,
It is explanatory drawing which shows a mode that the filled via conductor of the main surface side 2nd insulating layer, the filled via conductor of the back surface side 2nd insulating layer, etc. were formed.

FIG. 7 relates to a method for manufacturing a wiring board according to the first embodiment,
It is explanatory drawing which shows a mode that the main surface side solder resist layer and the back surface side solder resist layer were formed.

FIG. 8 relates to a method for manufacturing a wiring board according to the first embodiment,
Main surface side Ni plating layer, main surface side Au plating layer, back surface side Ni plating layer
It is explanatory drawing which shows a mode that the plating layer and the back surface side Au plating layer were formed.

FIG. 9 is a partial cross-sectional view of a wiring board according to a second embodiment.

FIG. 10 is a partial enlarged cross-sectional view showing the vicinity of the main surface side connection terminal of the wiring board according to the second embodiment.

FIG. 11 is a second main surface side of the wiring board according to the second embodiment.
It is a partial expanded sectional view which shows the 2nd filled via conductor vicinity of an insulating layer.

FIG. 12 is a partially enlarged cross-sectional view showing the vicinity of the back surface side connection terminal of the wiring board according to the second embodiment.

FIG. 13 is an explanatory diagram showing a state in which a main surface side Au plating layer and a back surface side Au plating layer are formed in the method for manufacturing a wiring board according to the second embodiment.

FIG. 14 is a partial cross-sectional view of a wiring board according to a third embodiment.

FIG. 15 is a partially enlarged cross-sectional view showing the vicinity of the main surface side connection terminal of the wiring board according to the third embodiment.

FIG. 16 is a second main surface side of the wiring board according to the third embodiment.
It is a partial expanded sectional view which shows the 2nd filled via conductor vicinity of an insulating layer.

FIG. 17 is a partially enlarged cross-sectional view showing the vicinity of the back surface side connection terminal of the wiring board according to the third embodiment.

FIG. 18 is a partial enlarged cross-sectional view of a main part of a wiring board according to a conventional form.

[Explanation of symbols]

101, 201, 301 wiring board 121 First surface first insulating layer 122,125,142,145 via holes 123,128,143,148 filled via conductors 124 Main surface side second insulating layer 126 First via hole 127 Second via hole 129 First filled via conductor 130 Second filled via conductor 133 main surface side solder resist layer 134 Main surface side opening 135,235,335 Main surface side connection terminal 136 Ni plating layer on main surface 138, 235, 335 solder bumps 141 Backside First Insulating Layer 144 Backside second insulating layer 153 Backside solder resist layer 154 Back side opening 155, 255, 148 Rear side connection terminals 156 Back side Ni plating layer 157,255 Au plating layer on the back side

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Noritaka             14-18 Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture             Inside this special ceramics company (72) Inventor Kozo Yamazaki             14-18 Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture             Inside this special ceramics company F-term (reference) 5E319 AA03 AB05 AC02 AC11 BB04                       CC33 CD26 GG03 GG11                 5E343 AA17 BB17 BB23 BB24 BB44                       DD33 DD43 EE53 GG02 GG18                 5E346 AA15 AA32 AA43 BB16 CC09                       CC32 CC37 CC38 DD13 DD25                       DD47 EE18 FF07 FF09 FF10                       FF15 FF18 FF22 FF45 GG06                       GG15 GG17 GG25 HH07 HH11                       HH33

Claims (21)

[Claims] 1. A wiring board comprising an insulating layer having a via hole, a filled via conductor formed in the via hole, and a metal layer deposited on the surface of the filled via conductor, wherein the filled via conductor has a surface thereof. Is a shape having a convex bulge, and the metal layer also follows the surface of the filled via conductor,
A wiring board whose surface is convex. 2. A wiring board comprising: an insulating layer having a via hole; and a filled via conductor formed in the via hole, wherein the filled via conductor has a shape having a bulged portion whose surface bulges in a convex shape. Wiring board. 3. A wiring board comprising: an insulating layer having a via hole; a filled via conductor formed in the via hole; a metal layer deposited on the surface of the filled via conductor; and solder bumps deposited on the surface of the metal layer. In the filled via conductor, the surface thereof has a shape having a bulging portion that bulges in a convex shape, and the metal layer also follows the surface of the filled via conductor,
A wiring board whose surface is convex. 4. A wiring board comprising an insulating layer having a via hole, a filled via conductor formed in the via hole, and a solder bump welded to the surface of the filled via conductor, wherein the filled via conductor has a convex surface. A wiring board having a shape that has a bulging portion that bulges like a circle. 5. A solder resist layer having an insulating layer having a via hole, a filled via conductor formed in the via hole, laminated on the insulating layer, and having an opening in which at least a part of the filled via conductor is arranged. And a metal layer deposited on the surface of the filled via conductor in the opening, wherein the filled via conductor has a bulged portion whose surface bulges convexly in the opening. And the metal layer also follows the surface of the filled via conductor,
A wiring board whose surface is convex. 6. A solder resist layer having an insulating layer having a via hole, a filled via conductor formed in the via hole, laminated on the insulating layer, and having an opening in which at least a part of the filled via conductor is arranged. And a metal layer deposited on the surface of the filled via conductor in the opening, and a solder bump welded to the surface of the metal layer, wherein the filled via conductor has a surface in the opening. It has a shape having a convex bulge, and the metal layer also follows the surface of the filled via conductor,
A wiring board whose surface is convex. 7. The wiring board according to claim 5, wherein the surface of the metal layer is lower than the surface of the solder resist layer. 8. A solder resist layer having an insulating layer having a via hole, a filled via conductor formed in the via hole, laminated on the insulating layer, and having an opening in which at least a part of the filled via conductor is arranged. And a filled via conductor having a bulging portion whose surface is convexly bulged in the opening. 9. A solder resist layer having an insulating layer having a via hole, a filled via conductor formed in the via hole, laminated on the insulating layer, and having an opening in which at least a part of the filled via conductor is arranged. And a solder bump welded to the surface of the filled via conductor, wherein the filled via conductor has a shape in which the surface has a convex bulge in the opening. . 10. The wiring board according to claim 8 or 9, wherein the surface of the filled via conductor is lower than the surface of the solder resist layer. 11. An insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, a second filled via conductor formed in the second via hole, and an insulating layer on the insulating layer. And a solder resist layer that has an opening in which at least a part of the first filled via conductor is disposed inside and that covers the second filled via conductor, and a surface of the first filled via conductor in the opening. And a metal layer attached to the first filled via conductor, wherein the first filled via conductor has a shape having a bulged portion whose surface bulges in a convex shape in the opening. According to the surface of the filled via conductor, the surface has a shape that bulges in a convex shape, and the second filled via conductor has a bulging portion whose surface bulges in a convex shape. A wiring board that has a shape. 12. An insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, a second filled via conductor formed in the second via hole, and an insulating layer on the insulating layer. And a solder resist layer that has an opening in which at least a part of the first filled via conductor is disposed inside and that covers the second filled via conductor, and a surface of the first filled via conductor in the opening. A wiring board comprising a deposited metal layer and a solder bump welded to the surface of the metal layer, wherein the first filled via conductor has a bulging portion in which the surface bulges in a convex shape in the opening. And the metal layer also has a shape in which the surface bulges in a convex shape following the surface of the first filled via conductor. Conductor wiring the surface is a shape having a bulging portion bulging convex substrate. 13. The wiring board according to claim 11, wherein the surface of the metal layer is lower than the surface of the solder resist layer. 14. An insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, a second filled via conductor formed in the second via hole, and an insulating layer on the insulating layer. A solder resist layer that is laminated on the second filled via conductor and has an opening in which at least a part of the first filled via conductor is arranged.
A wiring board comprising: the first filled via conductor having a bulging portion whose surface bulges convexly in the opening; and the surface of the second filled via conductor bulges convexly. A wiring board having a shape with a bulge. 15. An insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, a second filled via conductor formed in the second via hole, and an insulating layer on the insulating layer. And a solder resist layer having an opening in which at least a part of the first filled via conductor is arranged, the solder resist layer covering the second filled via conductor, and a solder bump welded to the surface of the first filled via conductor. A wiring board comprising: the first filled via conductor having a bulging portion whose surface bulges convexly in the opening; and the surface of the second filled via conductor bulges convexly. A wiring board having a shape with a bulge. 16. The wiring board according to claim 14 or 15, wherein the surface of the first filled via conductor is lower than the surface of the solder resist layer. 17. The wiring board according to claim 11, wherein a thickness of a portion of the solder resist layer laminated on the bulging portion of the second filled via conductor. The wiring board is 5 μm or more. 18. The wiring board according to claim 11, wherein the entire surface of the second filled via conductor is a roughened surface. 19. An insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, a second filled via conductor formed in the second via hole, and an insulating layer on the insulating layer. And a solder resist layer that has an opening in which at least a part of the first filled via conductor is disposed inside and that covers the second filled via conductor, and a surface of the first filled via conductor in the opening. And a solder bump welded to the surface of the metal layer, wherein the first filled via conductor has a shape having a bulged portion whose surface bulges in a convex shape in the opening. The layer also has a shape in which the surface thereof bulges in a convex shape following the surface of the first filled via conductor, and the second filled via conductor has a surface thereof. A method of manufacturing a wiring board having a shape having a convex bulge, comprising: a first filled via conductor having the bulge and a second filled via conductor having the bulge by electroplating; And a filled via forming step of forming the second filled via conductor having a height of the bulging portion of 15 μm or less, and a roughening step of roughening the entire surface of the second filled via conductor. And a solder resist layer forming step of forming the solder resist layer on the insulating layer by vacuum lamination. 20. An insulating layer having a first via hole and a second via hole, a first filled via conductor formed in the first via hole, a second filled via conductor formed in the second via hole, and an insulating layer on the insulating layer. And a solder resist layer having an opening in which at least a part of the first filled via conductor is arranged, the solder resist layer covering the second filled via conductor, and a solder bump welded to the surface of the first filled via conductor. The first filled via conductor has a shape in which the surface has a bulging portion in which a convex shape bulges in the opening, and the second filled via conductor has a bulging portion in which a surface thereof bulges in a convex shape. A method of manufacturing a wiring board having a shape, comprising: forming a first filled via conductor having the bulged portion and the bulged portion by electrolytic plating. A filled via forming step of simultaneously forming a second filled via conductor for forming the second filled via conductor and a filled via forming step of forming the second filled via conductor having a height of the bulging portion of 15 μm or less; A method of manufacturing a wiring board, comprising: a roughening step of roughening; and a solder resist layer forming step of forming the solder resist layer on the insulating layer by vacuum lamination. 21. The method of manufacturing a wiring board according to claim 19 or 20, wherein in the filled via forming step, the second filled via conductor having a height of the bulging portion of 5 μm or less is formed. Substrate manufacturing method.