JP2016039158A - Wiring board manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board manufacturing method which can inhibit generation of a resin residue on a connection terminal.SOLUTION: A wiring board manufacturing method according to the present embodiment comprises: a process of forming a first via hole in a first insulation layer and a second via hole in a second insulation layer; a process of forming a first via conductor in the first via hole and a second via conductor in the second via hole and forming a first connection terminal on the first via conductor and the first insulation layer and a second connection terminal on the second via conductor and the second insulation layer; and a process of forming a conductive salient having an outer diameter larger than an outer diameter of the second via conductor.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a wiring board.

  Terminals for connection to the semiconductor chip (hereinafter referred to as connection terminals) are formed on the surface side of the wiring board for mounting the semiconductor chip. In recent years, the density of the connection terminals has been increased, and the interval (pitch) between the connection terminals to be arranged has been reduced. For this reason, a wiring board adopting an NSMD (non-solder mask-defined) shape in which a plurality of connection terminals are arranged in the same opening of the solder resist layer has been proposed.

  However, when a plurality of connection terminals are arranged in the same opening at a narrow pitch, there is a possibility that the solder coated on the surface of the connection terminal flows out to the adjacent connection terminal side and the connection terminals are short-circuited. Thus, it has been proposed to fill a filling member between connection terminals (see, for example, Patent Document 1). According to the proposal, since the space between the connection terminals is filled with the filling member, underfill or NCP (Non-Conductive) which is filled in the gap between the semiconductor chip and the wiring board when connected to the semiconductor chip. Paste) and voids between connection terminals of NCF (Non-Conductive Film) can be prevented. For this reason, at the time of reflow, it can be prevented that the solder flows out to the void and the connection terminals are short-circuited.

Japanese Patent No. 5415632

  However, in the above proposal, after laminating a resist layer on the connection terminal, development is performed so as not to penetrate the resist layer, and an opening for exposing the plurality of connection terminals and filling between the plurality of connection terminals are filled. Forming a member.

  Usually, in the wiring board, connection terminals are formed not only on the front surface side but also on the back surface side for connection with a mother board or the like. Similarly to the front surface side, a resist layer (resin layer) is also formed on the back surface side, and an opening for exposing each connection terminal is formed in the resist layer so as to penetrate the resist layer. . The front-side opening and the back-side opening are formed in the same development process.

  Usually, the development time for forming the opening is determined in accordance with the depth of the opening on the surface side to be formed. For this reason, by performing development with a development time determined in accordance with the depth of the opening on the front surface side to be formed, an opening that does not penetrate the resist layer on the front surface side and an opening that penetrates the resist layer on the back surface side And are formed. However, if there is a depression on the surface of the connection terminal on the back side, the resist material buried in the depression may not be removed by development, and a resin such as a resist material may remain in the depression. If the resin residue is generated, there is a possibility that a contact failure may occur in connection with the mother board or the like, or sufficient solder may not be coated when solder is applied to the connection terminals.

  The present invention has been made in response to the above-described circumstances, and an object of the present invention is to provide a method for manufacturing a wiring board capable of suppressing the occurrence of a resin residue on a connection terminal.

  In order to achieve the above object, the present invention has a laminate in which at least one conductor layer and a plurality of insulating layers are alternately laminated, and the first main surface and the opposite side of the first main surface of the laminate. And a second main surface located at a surface of the first insulating layer and the surface of the second insulating layer forming a plurality of insulating layers, wherein the thickness of the first insulating layer is Forming a first via hole penetrating in the direction and a second via hole penetrating the second insulating layer in the thickness direction, and a first via conductor and a second via filling the first via hole Forming a second via conductor filling the hole, forming a first connection terminal on the first via conductor and the first insulating layer, and on the second via conductor and the second insulating layer; Forming a second connecting terminal, and forming a conductive convex portion having an outer diameter larger than the outer diameter of the second via conductor on the second connecting terminal; And after the step of forming the convex portion, a first resist layer having photosensitivity is formed on the first insulating layer and the first connection terminal, and the second insulating layer and the second connection are formed. A step of forming a photosensitive second resist layer on the terminal, and a step of performing exposure for forming an opening for exposing the first connection terminal and the convex portion in the first and second resist layers. And developing the first and second resist layers to form a first opening that exposes the first connection terminal, the first resist layer forming a bottom surface, and a second resist layer. And a step of collectively forming a second opening that penetrates in the thickness direction and exposes the convex portion.

  According to the present invention, since the conductive convex portion having an outer diameter larger than the outer diameter of the second via conductor is formed on the second connection terminal, a depression is generated on the second connection terminal. This can suppress the occurrence of resin residue such as the second resist layer on the second connection terminal.

  In one aspect of the present invention, in the step of forming the first and second connection terminals, the first metal layer to be the first and second via conductors and the first and second connection terminals is formed by electrolytic plating. The projecting portion is formed by electrolytic plating when forming the first metal layer.

  According to one aspect of the present invention, when the first metal layer to be the first and second via conductors and the first and second connection terminals is formed by electrolytic plating, the convex portion is also formed. That is, it is not necessary to add a separate process for forming the convex portion, and the manufacturing process can be simplified.

  In another aspect of the present invention, the step of forming the convex portion includes a step of forming a third resist layer having an opening for forming the convex portion on the second connection terminal, and electrolytic plating. It has the process of forming the 2nd metal layer used as a convex part in the opening part of a 3rd resist layer, and the process of removing a 3rd resist layer, It is characterized by the above-mentioned.

  According to another aspect of the present invention, after the third resist layer having an opening is formed on the second connection terminal, the first resist that becomes a convex portion is formed in the opening of the third resist layer by electrolytic plating. 2 metal layers are formed. For this reason, a convex part can be reliably formed on the 2nd connecting terminal. Moreover, the outer diameter and height of a convex part can be changed easily.

  As described above, according to the present invention, it is possible to provide a method for manufacturing a wiring board capable of suppressing the occurrence of resin residue on a connection terminal.

Sectional drawing of the wiring board which concerns on embodiment. The enlarged plan view of the connecting terminal of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board concerning an embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board concerning an embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on embodiment. The manufacturing process figure of the wiring board which concerns on other embodiment. The manufacturing process figure of the wiring board which concerns on other embodiment. The manufacturing process figure of the wiring board which concerns on other embodiment. The manufacturing process figure of the wiring board which concerns on other embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The wiring board according to the embodiment described below is merely an example, and the present invention is not limited to the following embodiment. For example, in the following description, the embodiment has been described by taking a wiring substrate having a core substrate as an example, but a so-called coreless substrate having no core substrate may be used.

(Embodiment)
FIG. 1 is a cross-sectional view of a wiring board 100 according to an embodiment. FIG. 2 is an enlarged plan view of the connection terminals 24 </ b> A and the protrusions T included in the wiring board 100. Hereinafter, the configuration of the wiring board 100 will be described with reference to FIGS. 1 and 2.

  The wiring substrate 100 includes a core substrate 11, insulating layers 12 and 13, conductor layers 21 to 24, via conductors 31 and 32, and resist layers 41 and 42. The core substrate 11, the insulating layers 12 and 13, and the conductor layers 21 and 22 constitute a laminated body, a semiconductor chip is mounted on the front surface (first main surface) side, and the back surface (second main surface) side. A motherboard etc. are connected to

  The core substrate 11 is a plate-shaped resin substrate made of a heat-resistant resin plate (for example, a bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin), or the like.

(Structure on the front side)
The conductor layer 21 is formed on the surface of the core substrate 11. The conductor layer 21 includes a via land 21 </ b> A that is in electrical contact with the via conductor 31 and a wiring 21 </ b> B that is not in contact with the via conductor 31. The conductor layer 21 is made of a metal having excellent conductivity, for example, copper.

  The insulating layer 12 (first insulating layer) is formed by thermosetting a thermosetting resin composition on the surfaces of the conductor layer 21 and the core substrate 11. A via hole (first via hole) 12A penetrating in the thickness direction is formed in the insulating layer 12 by a laser or the like. A via conductor 31 (first via conductor) is filled in the via hole 12A. The via conductor 31 electrically connects the conductor layer 21 and the conductor layer 23.

  The conductor layer 23 is formed on the insulating layer 12. The conductor layer 23 includes a via land 23A that is in electrical contact with the via conductor 31, a wiring 23B that is not in contact with the via conductor 31, and a connection terminal 23C (first connection terminal). The conductor layer 23 is made of a metal having excellent conductivity, for example, copper.

  The connection terminal 23 </ b> C is a terminal for connection with a semiconductor chip mounted on the surface side of the wiring substrate 100. The exposed portion of the connection terminal 23C may be coated with a metal plating layer. As the metal plating layer, for example, a single layer or a plurality of layers (for example, Ni layer / Au layer, Ni layer / Pd layer) selected from metal layers such as Ni layer, Sn layer, Ag layer, Pd layer, Au layer, etc. / Au layer). Further, an OSP (Organic Solderability Preservative) treatment for rust prevention may be performed instead of the metal plating layer. In addition, solder may be coated, and after coating a metal plating layer, the metal plating layer may be coated with solder.

  The resist layer 41 (first resist layer) is formed on the conductor layer 23 and the insulating layer 12. The resist layer 41 is formed of a photosensitive resist material. The resist layer 41 is formed with an opening 41A in which at least a part of the connection terminal 23C is exposed and the resist layer 41 itself forms the bottom surface 41S.

  As shown in FIG. 1, the thickness T1 of the resist layer 41 on the bottom surface 41S is thinner than the thickness (height) T2 of the connection terminal 23C. Further, the resist layer 41 on the bottom surface 41S is filled between the connection terminals 23C in a state of being in close contact with the side surface S of the connection terminals 23C.

  In FIG. 1, the NSMD shape has a plurality of connection terminals 23 </ b> C arranged in one opening 41 </ b> A, but the number of connection terminals 23 </ b> C exposed in one opening 41 </ b> A is arbitrary. For example, only one connection terminal 23C may be exposed in one opening 41A.

(Configuration on the back side)
The conductor layer 22 is formed on the back surface of the core substrate 11. The conductor layer 22 includes a via land 22 </ b> A that is in electrical contact with the via conductor 32 and a wiring 22 </ b> B that is not in contact with the via conductor 32. The conductor layer 22 is made of a metal having excellent conductivity, for example, copper.

  The insulating layer 13 (second insulating layer) is formed by thermosetting a thermosetting resin composition on the conductor layer 22 and the back surface of the core substrate 11. In the insulating layer 13, a via hole (second via hole) 13A penetrating in the thickness direction is formed by a laser or the like. A via conductor 32 (second via conductor) is filled in the via hole 13A. The via conductor 32 electrically connects the conductor layer 22 and the conductor layer 24.

  The conductor layer 24 is formed on the insulating layer 13. The conductor layer 24 includes a connection terminal 24A (second connection terminal) that is in electrical contact with the via conductor 32, a connection terminal 24B that is not in contact with the via conductor 32, and a convex portion T formed on the connection terminal 24A. With. The conductor layer 24 is made of a metal having excellent conductivity, for example, copper. The conductor layer 24 may be provided with a wiring (not shown).

  The connection terminals 24 </ b> A and 24 </ b> B are terminals for connection with a motherboard or the like provided on the back side of the wiring board 100. In addition, you may coat the connection part 24A, 24B and the exposed part of the convex part T with a metal plating layer. As the metal plating layer, for example, a single layer or a plurality of layers (for example, Ni layer / Au layer, Ni layer / Pd layer) selected from metal layers such as Ni layer, Sn layer, Ag layer, Pd layer, Au layer, etc. / Au layer). Further, an OSP (Organic Solderability Preservative) treatment for rust prevention may be performed instead of the metal plating layer. In addition, solder may be coated, and after coating a metal plating layer, the metal plating layer may be coated with solder.

  As shown in FIG. 2, the outer diameter D1 of the convex portion T in plan view is larger than the outer diameter D2 of the via conductor 32 in plan view. Here, the outer diameter D1 of the convex portion T and the outer diameter D2 of the via conductor 32 both mean the maximum value of the outer diameter. In addition, in FIG. 2, although the shape of the convex part T in planar view is circular, it is not limited to this shape. For example, the shape of the convex portion T in plan view may be a polygon or an ellipse. In this case, the projection region obtained by projecting the projection T in the thickness direction of the insulating layer 13 may include the projection region of the via conductor 32 in the thickness direction of the insulating layer 13. The area of the convex portion T in plan view may be larger than S2 of the via conductor 32. By making the outer diameter D1 of the convex portion T in plan view larger than the outer diameter D2 of the via conductor 32 in plan view, the resin residue hardly occurs on the connection terminal 24A.

  The resist layer 42 (second resist layer) is formed on the conductor layer 24 and the insulating layer 13. The resist layer 42 is formed with an opening 42A that penetrates in the thickness direction and exposes the convex portion T and a part of the connection terminals 24A and 24B. That is, the opening 42A of the resist layer 42 has an SMD shape that exposes part of the connection terminals 24A and 24B.

(Method for manufacturing a wiring board)
3 to 8 are views showing a manufacturing process of the wiring substrate 100 according to the embodiment. Hereinafter, a method for manufacturing the wiring substrate 100 will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the structure same as the structure demonstrated with reference to FIG.1 and FIG.2, and the overlapping description is abbreviate | omitted.

  A plate-shaped resin substrate (core substrate 11) having a copper foil attached to the front and back surfaces is prepared. Next, electrolytic copper plating is performed according to a conventionally known method to form a copper plating layer having a desired shape on both surfaces of the core substrate 11. Thereafter, the copper foil and the copper plating layer on both surfaces of the core substrate 11 are etched into a desired shape to form via lands 21A and wirings 21B constituting the conductor layer 21 on the front surface side, and the conductor layer 22 is formed on the back surface side. Via lands 22A and wirings 22B are formed (see FIG. 3).

  Next, the surfaces of the conductor layer 21 and the conductor layer 22 are roughened with a copper surface roughening agent (for example, Meck Etien Bond CZ: manufactured by MEC). By roughening the surfaces of the conductor layers 21 and 22, the adhesion to the insulating layers 12 and 13 formed on the conductor layers 21 and 22, respectively, is improved.

Next, a thermosetting resin film is laminated on the front surface side and the back surface side of the core substrate 11 on which the conductor layers 21 and 22 are formed, and cured by pressurizing and heating under vacuum to form the insulating layers 12 and 13. Each is formed (see FIG. 4). Thereby, the front surface and the back surface of the core substrate 11 are covered with the insulating layers 12 and 13, respectively. Next, the insulating layers 12 and 13 are irradiated with laser light having a predetermined intensity from, for example, a CO ₂ gas laser or a YAG laser to form via holes 12A and 13A, respectively (see FIG. 5).

  Thereafter, a roughening process is performed on the insulating layers 12 and 13 including the via holes 12A and 13A. In addition, when the insulating layers 12 and 13 contain a filler, when the roughening treatment is performed, the filler is released and remains on the insulating layers 12 and 13, so that washing is performed as appropriate. Next, desmear processing and outline etching are performed on the via holes 12A and 13A to clean the inside of the via holes 12A and 13A. In addition, you may perform an air blow process between the said water washing and a desmear process. Even when the filler released by washing with water is not completely removed, the remaining of the filler can be more reliably suppressed by the air blowing process.

  Next, seed layers M1 and M2 for electrolytic plating are formed on the insulating layers 12 and 13, respectively. The seed layers M1 and M2 can be formed by a conventionally known method such as electroless copper plating, sputtering (PVD), vacuum deposition, or the like. Thereafter, dry films R1 and R2 made of a photosensitive resin having openings having a desired pattern are formed on the seed layers M1 and M2 on the insulating layers 12 and 13 (see FIG. 6).

  Next, electrolytic copper plating is performed on the non-formed portions of the dry films R1 and R2 to form the via conductors 31 and 32, the conductor layer 23, and the metal layer (first metal layer) to be the conductor layer 24. Then, even after the connection terminal 24A constituting the conductor layer 24 is formed, a convex portion T is formed on the connection terminal 24A by further performing electrolytic copper plating (see FIG. 7).

  Next, after the dry films R1 and R2 are peeled using a stripping solution such as KOH, the seed layers M1 and M2 under the dry films R1 and R2 are removed by etching (see FIG. 8).

  Next, the surfaces of the conductor layer 23 and the conductor layer 24 are roughened with a copper surface roughening agent (for example, Meck Etien Bond CZ: manufactured by MEC). By roughening the surfaces of the conductor layers 23 and 24, adhesion with the resist layers 41 and 42 formed on the conductor layers 23 and 24, respectively, is improved.

  Next, a photosensitive resist material (photosensitive resin) is applied on the conductor layers 23 and 24 and the insulating layers 12 and 13 to form resist layers 41 and 42, respectively, and then the connection terminals 23C, 24A, 24B and Exposure is performed to form openings 41A and 42A that expose the convex portions T, respectively.

  Thereafter, the connection terminal 23C is exposed by development, and the resist layer 41 penetrates the resist layer 42 in the thickness direction and the opening 41A in which the bottom surface 41S is formed. An opening 42 that exposes a part of the surface of the terminal 24B is formed at a time to obtain the wiring substrate 100 of the present embodiment (see FIG. 1).

  When developing the resist layer 41, the wiring substrate 100 being manufactured is immersed in an aqueous solution of sodium carbonate (concentration of 1% by weight) for a short time (a time that the photosensitive resin surface of the unexposed part is slightly swollen). Then, the photosensitive resin swollen by washing with water is emulsified, and the swollen and emulsified photosensitive resin is removed from the wiring substrate 100 in the process of manufacturing, so that the resist layer 41 is filled between the connection terminals 23C and the bottom surface of the resist layer 41. An opening 41A for forming 41S is formed.

  As described above, in the wiring substrate 100 according to the present embodiment, the via conductor 32 in the via hole 13 is a so-called filled via, and therefore a depression is likely to be formed on the surface of the connection terminal 24A formed on the via conductor 32. For this reason, a resin such as a resist material may remain in this recess. However, according to the method for manufacturing the wiring board 100 according to the present embodiment, the conductive convex portion T having an outer diameter larger than the outer diameter of the via conductor 32 is formed on the connection terminal 24A. For this reason, it can suppress that a hollow is formed on 24 A of connection terminals, and can suppress that resin residues, such as a resist material, arise in this hollow.

  Furthermore, in the present embodiment, in the step of forming the connection terminal 23C and the connection terminal 24A, the via conductors 31 and 32 and the connection terminals 23C and 24A are formed by electrolytic plating, and the convex portion T is formed of the via conductors 31 and 32 and It is formed by electrolytic plating when forming the connection terminals 23C and 24A. For this reason, it is not necessary to add a separate process for forming the convex part T, and the manufacturing process can be simplified. Moreover, the manufacturing cost of the wiring board 100 can be reduced.

(Other embodiments)
9 to 12 are views for explaining a method of manufacturing the wiring board 100 according to another embodiment. Here, an embodiment in which the convex portion T is formed by a method different from the above-described embodiment will be described. Hereinafter, a method of manufacturing the wiring board 100 according to another embodiment will be described with reference to FIGS. 1 to 6 and FIGS. 9 to 12. In addition, the same code | symbol is attached | subjected to the structure same as the structure demonstrated in embodiment, and the overlapping description is abbreviate | omitted.

  First, the wiring substrate 100 is manufactured as described with reference to FIGS. 3 to 6, and a photosensitive resin having openings of desired patterns on the seed layers M <b> 1 and M <b> 2 on the insulating layers 12 and 13 is manufactured. The resulting dry films R1 and R2 are formed (see FIG. 6).

  Next, electrolytic copper plating is performed on portions where the dry films R1 and R2 are not formed to form via conductors 31 and 32 in the via holes 12A and 13A, and via lands 23A, wirings 23B, and connection terminals 23C constituting the conductor layer 23. Then, connection terminals 24A and 24B constituting the conductor layer 24 are formed (see FIG. 9). Since the via conductor 32 is a filled via, the recess 24R is likely to be formed in the connection terminal 24A formed on the via conductor 32.

  Next, the dry film R3 is formed on the dry film R1, and the dry film R4 (third resist layer) having the opening AP for forming the convex portion T is formed on the dry film R2 (see FIG. 10). ).

  Next, a metal layer (second metal layer) to be the convex portion T is formed in the opening AP of the dry film R4 by electrolytic copper plating (see FIG. 11).

  Next, after the dry films R1 to R4 are peeled using a stripping solution such as KOH, the seed layers M1 and M2 under the dry films R1 to R4 are removed by etching (see FIG. 12).

  Next, the surfaces of the conductor layer 23 and the conductor layer 24 are roughened with a copper surface roughening agent (for example, Meck Etien Bond CZ: manufactured by MEC). By roughening the surfaces of the conductor layers 23 and 24, adhesion with the resist layers 41 and 42 formed on the conductor layers 23 and 24, respectively, is improved.

  Next, a photosensitive resist material is applied on the conductor layers 23 and 24 and the insulating layers 12 and 13 to form resist layers 41 and 42, respectively, and then the connection terminals 23C, 24A and 24B and the projections T are exposed. Exposure for forming the openings 41A and 42A to be performed is performed. Thereafter, the connection terminal 23C is exposed by development, and the resist layer 41 penetrates the resist layer 42 in the thickness direction and the opening 41A in which the bottom surface 41S is formed, and a part of the surface of the convex portion T and the connection terminals 24A and 24B. Are formed in a lump to obtain the wiring substrate 100 of the present embodiment (see FIG. 1).

  As described above, according to the method for manufacturing the wiring substrate 100 according to the other embodiment, the conductive convex portion T having an outer diameter larger than the outer diameter of the via conductor 32 is formed on the connection terminal 24A. . For this reason, it can suppress that a hollow is formed on 24 A of connection terminals, and can suppress that resin residues, such as a resist material, arise in this hollow.

  Furthermore, the step of forming the convex portion T includes a step of forming a dry film R4 (third resist layer) having an opening AP for forming the convex portion T on the connection terminal 24A, and is dry by electrolytic plating. The dry film R4 is removed after the metal layer to be the convex portion T is formed in the opening AP of the film R4. For this reason, the convex part T can be reliably formed on the connection terminal 24A. Moreover, the outer diameter and height of the convex part T can be changed easily.

DESCRIPTION OF SYMBOLS 100 ... Wiring board 11 ... Core board | substrate 12, 13 ... Insulating layer 12A, 13A ... Via hole 21-24 ... Conductor layer 31, 32 ... Via conductor 41, 42 ... Resist layer 41A, 42A ... Opening part

Claims (3)

A laminated body in which at least one conductor layer and a plurality of insulating layers are alternately laminated; and a first main surface of the laminated body and a second main surface located on the opposite side of the first main surface. A method of manufacturing a wiring board formed by the surfaces of the first insulating layer and the second insulating layer constituting the plurality of insulating layers,
Forming a first via hole penetrating the first insulating layer in the thickness direction and a second via hole penetrating the second insulating layer in the thickness direction;
Forming a first via conductor filling the first via hole and a second via conductor filling the second via hole; and on the first via conductor and the first insulating layer. Forming a first connection terminal and forming a second connection terminal on the second via conductor and the second insulating layer;
Forming a conductive convex portion having an outer diameter larger than the outer diameter of the second via conductor on the second connection terminal;
After the step of forming the convex portion, a photosensitive first resist layer is formed on the first insulating layer and the first connection terminal, and the second insulating layer and the second insulating layer are formed. Forming a photosensitive second resist layer on the connection terminal;
Exposing the first and second resist layers to form openings for exposing the first connection terminals and the protrusions; and
A first opening that exposes the first connection terminal by the development of the first and second resist layers and the first resist layer forms a bottom surface; and the second resist Forming a second opening that penetrates the layer in the thickness direction and exposes the protrusion, and a method for manufacturing a wiring board. In the step of forming the first and second connection terminals,
Forming a first metal layer to be the first and second via conductors and the first and second connection terminals by electrolytic plating;
The convex portion is
The method of manufacturing a wiring board according to claim 1, wherein the wiring board is formed by the electrolytic plating when forming the first metal layer. The step of forming the convex portion includes
Forming a third resist layer having an opening for forming the convex portion on the second connection terminal;
Forming a second metal layer to be the protrusion in the opening of the third resist layer by electrolytic plating;
Removing the third resist layer;
The method for manufacturing a wiring board according to claim 1, wherein:

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