KR101792335B1

KR101792335B1 - Method for manufacturing wiring board

Info

Publication number: KR101792335B1
Application number: KR1020150108739A
Authority: KR
Inventors: 도모히로 니시다; 마코토 와카조노
Original assignee: 니혼도꾸슈도교 가부시키가이샤
Priority date: 2014-08-05
Filing date: 2015-07-31
Publication date: 2017-10-31
Also published as: JP6230971B2; TW201613438A; TWI569703B; KR20160016688A; JP2016039158A

Abstract

(PROBLEMS TO BE SOLVED BY THE INVENTION) A method of manufacturing a wiring board capable of suppressing the generation of resin debris on a connection terminal.
A method of manufacturing a wiring board according to the present invention includes the steps of forming a first via hole in a first insulating layer and a second via hole in a second insulating layer; A second via conductor is formed in the second via hole and a first connection terminal is formed on the first via conductor and the first insulation layer and a second connection terminal is formed on the second via conductor and the second insulation layer And a step of forming a conductive convex portion having a larger outer diameter than the outer diameter of the second via conductor on the second connection terminal.

Description

[0001] METHOD FOR MANUFACTURING WIRING BOARD [0002]

The present invention relates to a method of manufacturing a wiring board.

A terminal for connection with a semiconductor chip (hereinafter referred to as a connection terminal) is formed on the surface side of the wiring board for mounting the semiconductor chip. In recent years, the connection terminals are becoming higher in density, and the interval (pitch) of connection terminals to be arranged is narrowed. Therefore, a wiring board adopting the NSMD (non-solder mask / definded) shape in which a plurality of connection terminals are disposed in the same opening portion of the solder resist layer has been proposed.

However, when a plurality of connection terminals are disposed in the same opening with a narrow pitch, the solder coated on the surface of the connection terminal may flow out to the adjacent connection terminal side, which may short-circuit the connection terminals. Thus, it has been proposed to fill the filling member between the connection terminals (see, for example, Patent Document 1). According to the proposal, since the connection terminals are filled with the filling member, the connection between the semiconductor chip and the wiring substrate can be prevented by using underfill, non-conductive paste (NCP), or non-conductive film It is possible to prevent the generation of voids between the connection terminals of the semiconductor device. As a result, it is possible to prevent solder from flowing out to the voids during reflow, thereby preventing the connection terminals from being short-circuited.

Patent Document 1: Japanese Patent No. 5415632

However, in the above proposal, the resist layer is laminated on the connection terminal, and then developed so as not to penetrate the resist layer, thereby forming an opening for exposing the plurality of connection terminals and a filling member for filling the space between the plurality of connection terminals .

Normally, in the wiring board, connection terminals are formed not only on the front side but also on the back side for connection with a mother board or the like. As in the case of the front side, a resist layer (resin layer) is formed on the back side, and openings for exposing the respective connection terminals are formed in the resist layer through the resist layer. The opening on the front side and the opening on the back side are formed by the same developing process.

Generally, the development time for forming the openings is determined in accordance with the depth of the surface side openings to be formed. As a result, development is carried out at a development time determined according to the depth of the surface side opening to be formed, thereby forming an opening penetrating through the resist layer on the back side and the opening portion not penetrating the resist layer on the surface side. However, if there is a concave portion on the surface of the connection terminal on the back side, the resist material buried in the concave portion may not be removed by development, and a resin such as a resist material may remain on the concave portion. If resin debris is generated, contact failure may occur in connection with a mother board or the like, or sufficient solder may not be coated when the solder is coated on the connection terminal.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and it is an object of the present invention to provide a method of manufacturing a wiring board capable of suppressing the generation of resin debris on a connection terminal.

In order to achieve the above object, the present invention provides a laminated body including a laminated body in which at least one conductor layer and a plurality of insulating layers are alternately stacked, and the laminated body includes a first main surface and a second main surface, And the second main surface is formed by the surfaces of the first insulating layer and the second insulating layer constituting the plurality of insulating layers, wherein the first via hole penetrating the first insulating layer in the thickness direction, Forming a second via-hole through the insulating layer in a thickness direction; forming a first via conductor filling the first via-hole and a second via conductor filling the second via-hole, A step of forming a first connection terminal on the first via conductor and the first via conductor and forming a second connection terminal on the second via conductor and the second insulating layer; This large conductive convex portion is formed A first resist layer having photosensitivity is formed on the first insulating layer and the first connection terminal later than the step of forming the resist and the convex portion and a second resist layer having photosensitivity is formed on the second insulating layer and the second connection terminal A step of performing exposure for forming openings for exposing the first connection terminals and the convex portions to the first and second resist layers; and a step of developing the first and second resist layers, The first resist layer has a first opening that exposes the top and side surfaces of the first connection terminal and forms a bottom surface between the plurality of first connection terminals and a second opening through which the second resist layer penetrates in the thickness direction to expose the convex portion And a step of collectively forming the second openings.

According to the present invention, since the conductive convex portion having the larger outer diameter than the outer diameter of the second via conductor is formed on the second connection terminal, it is possible to suppress the occurrence of the concave portion on the second connection terminal, The generation of resin debris such as a resist layer can be suppressed.

In one embodiment of the present invention, in the step of forming the first and second connection terminals, the first and second via conductors and the first metal layer to be the first and second connection terminals are formed by electrolytic plating, And is formed by electrolytic plating at the time of forming the first metal layer.

According to one aspect of the present invention, convex portions are also formed when the first and second via conductors and the first metal layer to be the first and second connection terminals are formed by electrolytic plating. In other words, it is not necessary to add a separate step to form the convex portion, and the manufacturing process can be simplified.

According to another aspect of the present invention, in the step of forming the convex portion, a step of forming a third resist layer having an opening for forming a convex portion on the second connection terminal, a step of forming a convex portion in the opening of the third resist layer by electrolytic plating, A step of forming a second metal layer to be added, and a step of removing the third resist layer.

According to another aspect of the present invention, a third resist layer having an opening is formed on the second connection terminal, and then a second metal layer having a convexity is formed in the opening of the third resist layer by electrolytic plating. As a result, the convex portion can reliably be formed on the second connection terminal. In addition, the outer diameter and height of the convex portion can be easily changed.

INDUSTRIAL APPLICABILITY As described above, according to the present invention, it is possible to provide a method of manufacturing a wiring board capable of suppressing the generation of resin debris on a connection terminal.

1 is a cross-sectional view of a wiring board according to an embodiment;
2 is an enlarged plan view of a connection terminal of a wiring board according to the embodiment;
3 is a manufacturing process diagram of a wiring board according to the embodiment;
4 is a manufacturing process diagram of a wiring board according to the embodiment;
5 is a manufacturing process diagram of a wiring board according to the embodiment;
6 is a manufacturing process diagram of a wiring board according to the embodiment;
7 is a manufacturing process diagram of a wiring board according to the embodiment;
8 is a manufacturing process diagram of a wiring board according to the embodiment;
9 is a manufacturing process diagram of a wiring board according to another embodiment.
10 is a manufacturing process diagram of a wiring board according to another embodiment;
11 is a manufacturing process diagram of a wiring board according to another embodiment.
12 is a manufacturing process diagram of a wiring board according to another embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The wiring board according to the embodiment to be described below is merely an example, and the present invention is not limited to the following embodiments. For example, in the following description, a wiring board having a core substrate is described as an example, but a so-called coreless substrate not having a core substrate may be used.

(Embodiments)

1 is a cross-sectional view of a wiring board 100 according to an embodiment. Fig. 2 is an enlarged plan view of the connection terminal 24A and the convex portion T of the wiring board 100. Fig. Hereinafter, the configuration of the wiring board 100 will be described with reference to Figs. 1 and 2. Fig.

The wiring board 100 includes the core substrate 11, the insulating layers 12 and 13, the conductor layers 21 to 24, the via conductors 31 and 32 and the resist layers 41 and 42 have. The core substrate 11, the insulating layers 12 and 13 and the conductor layers 21 and 22 constitute a laminate and the semiconductor chip is mounted on the surface (first main surface) A mother board or the like is connected to the main surface side.

The core substrate 11 is a plate-shaped resin substrate composed of a heat resistant resin plate (for example, bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin).

(Configuration on the surface side)

The conductor layer 21 is formed on the surface of the core substrate 11. The conductor layer 21 includes a via land 21A which is in electrical contact with the via conductor 31 and a wiring 21B which is not in contact with the via conductor 31. [ The conductor layer 21 is formed of a metal having excellent conductivity, for example, copper.

The insulating layer 12 (first insulating layer) is formed by thermally curing a thermosetting resin composition on the surface of the conductor layer 21 and the core substrate 11. [ In the insulating layer 12, a via hole (first via hole) 12A penetrating in the thickness direction is formed by laser or the like. A via conductor (31, first via conductor) is filled in the via hole 12A. The via conductor (31) electrically connects the conductor layer (21) and the conductor layer (23).

The conductor layer 23 is formed on the insulating layer 12. The conductor layer 23 has a via land 23A electrically connected to the via conductor 31, a wiring 23B not in contact with the via conductor 31, and a connection terminal 23C (first connection terminal) Respectively. The conductor layer 23 is formed of a metal having excellent conductivity, for example, copper.

The connection terminal 23C is a terminal for connection with a semiconductor chip mounted on the front surface side of the wiring board 100. [ The exposed portion of the connection terminal 23C may be coated with a metal plating layer. Examples of the metal plating layer include a single or multiple layers selected from a metal layer such as a Ni (nickel) layer, a Sn (tin) layer, an Ag (silver) layer, a Pd For example, Ni layer / Au layer, Ni layer / Pd layer / Au layer). Instead of the metal plating layer, an OSP (Organic Solderability Preservative) treatment for preventing rust may be performed. The solder may be coated, or after the metal plating layer is coated, the metal plating layer may be coated with solder.

A resist layer 41 (first resist layer) is formed on the conductor layer 23 and the insulating layer 12. The resist layer 41 is formed of a photosensitive resist material. The resist layer 41 is formed with an opening 41A in which at least part of the connection terminal 23C is exposed and the resist layer 41 itself forms the bottom surface 41S.

As shown in Fig. 1, the thickness T1 of the resist layer 41 on the bottom surface 41S is thinner than the thickness (height, T2) of the connection terminal 23C. The resist layer 41 on the bottom surface 41S is filled between the connection terminals 23C in a state of being in tight contact with the side surface S of the connection terminal 23C.

1, an NSMD shape in which a plurality of connection terminals 23C are arranged in one opening 41A is provided, but the number of connection terminals 23C exposed in one opening 41A is arbitrary. For example, only one connection terminal 23C may be exposed in one opening 41A.

(Configuration on the back side)

The conductor layer 22 is formed on the back surface of the core substrate 11. The conductor layer 22 includes a via land 22A that is in electrical contact with the via conductor 32 and a wiring 22B that is not in contact with the via conductor 32. [ The conductor layer 22 is formed of a metal having excellent conductivity, for example, copper.

The insulating layer 13 (second insulating layer) is formed by thermosetting a thermosetting resin composition on the back surface of the conductor layer 22 and the core substrate 11. In the insulating layer 13, a via hole (second via hole) 13A penetrating in the thickness direction is formed by laser or the like. A via conductor (32, second via conductor) is filled in the via hole (13A). The via conductor 32 electrically connects the conductor layer 22 and the conductor layer 24.

The conductor layer 24 is formed on the insulating layer 13. The conductor layer 24 includes a connection terminal 24A (second connection terminal) that is in electrical contact with the via conductor 32, a connection terminal 24B that is not in contact with the via conductor 32, And has a convex portion T formed thereon. The conductor layer 24 is formed of a metal having excellent conductivity, for example, copper. The conductor layer 24 may also include wiring (not shown).

The connection terminals 24A and 24B are terminals for connection with a mother board or the like provided on the back side of the wiring board 100. [ The exposed portions of the connection terminals 24A, 24B and the convex portion T may be coated with a metal plating layer. Examples of the metal plating layer include single or plural layers (for example, Ni layer / Au layer, Ni layer / Pd layer / Ag layer) selected from metal layers such as Ni layer, Sn layer, Ag layer, Pd layer, Au layer, Au layer). Instead of the metal plating layer, an OSP (Organic Solderability Preservative) treatment for preventing rust may be performed. The solder may be coated, or after the metal plating layer is coated, the metal plating layer may be coated with solder.

As shown in Fig. 2, the outer diameter D1 of the convex portion T in a plan view (hereinafter sometimes referred to as " plan view (plan view) " Of the outer diameter D2. The outer diameter D1 of the convex portion T and the outer diameter D2 of the via conductor 32 mean the maximum value of the outer diameter. 2, the shape of the convex portion T in the plan view is circular, but the shape is not limited to this shape. For example, the shape of the convex portion T in a plan view may be polygonal or elliptical. In this case, it is sufficient that the projection region in which the convex portion T is projected in the thickness direction of the insulating layer 13 includes the projection region in the thickness direction of the insulating layer 13. It is preferable that the area of the convex portion T in the plan view is wider than the area of the via conductor 32. [ The outer diameter D1 of the convex portion T in the plan view is made larger than the outer diameter D2 of the via conductor 32 in the plan view so that resin debris hardly occurs on the connection terminal 24A .

A resist layer 42 (second resist layer) is formed on the conductor layer 24 and the insulating layer 13. The resist layer 42 is formed with an opening 42A penetrating in the thickness direction and exposing a part of the convex portion T and the connection terminals 24A and 24B. That is, the opening 42A of the resist layer 42 is formed in an SMD shape exposing a part of the connection terminals 24A and 24B.

(Manufacturing method of wiring board)

Figs. 3 to 8 are views showing the manufacturing steps of the wiring board 100 according to the embodiment. Fig. Hereinafter, a method of manufacturing the wiring board 100 will be described with reference to Figs. 1 and 3 to 8. Fig. The same components as those described with reference to Figs. 1 and 2 are denoted by the same reference numerals, and redundant explanations are omitted.

(The core substrate 11) is prepared by bonding a copper foil to the front and back surfaces of the resin substrate. Next, electrolytic copper plating is performed according to a conventionally known technique to form a copper plating layer having a desired shape on both sides of the core substrate 11. [ Thereafter, the copper foil and the copper plating layer on both sides of the core substrate 11 are etched in a desired shape to form the via land 21A and the wiring 21B constituting the conductor layer 21 on the front surface side, The via land 22A and the wiring 22B constituting the layer 22 are formed (see Fig. 3).

Next, the surfaces of the conductor layer 21 and the conductor layer 22 are roughened by a copper surface roughening agent (for example, MECetchBOND CZ manufactured by Mack Co.). By coarsening the surfaces of the conductor layers 21 and 22, the adhesion with the insulating layers 12 and 13 formed on the conductor layers 21 and 22 is improved.

Next, a thermosetting resin film is laminated on the front surface side and the back surface side of the core substrate 11 on which the conductor layers 21 and 22 are formed and is cured by heating under vacuum to form the insulating layers 12 and 13 (See Fig. 4). As a result, the front and back surfaces of the core substrate 11 are covered with the insulating layers 12 and 13, respectively. Next, the insulating layers 12 and 13 are irradiated with a laser beam of a predetermined intensity, for example, from a CO ₂ gas laser or a YAG laser to form via holes 12A and 13A, respectively (see FIG. 5).

Thereafter, the insulating layers 12 and 13 including the via holes 12A and 13A are roughened. When the insulating layers 12 and 13 include fillers, the filler is liberated and remains on the insulating layers 12 and 13 when the roughening treatment is performed, so that the water is washed appropriately. Next, the via holes 12A and 13A are subjected to a desmear treatment and an outline etching to clean the inside of the via holes 12A and 13A. Further, an air blow process may be performed between the water washing and the desmear process. Even if the filler favorable for flushing by water is not completely removed, the remaining filler can be more reliably suppressed by the air blow treatment.

Next, seed layers M1 and M2 for electroplating are formed on the insulating layers 12 and 13, respectively. The seed layers M1 and M2 can be formed by a conventionally known method, for example, electroless copper plating, sputtering (PVD), vacuum deposition, or the like. Thereafter, dry films R 1 and R 2 made of a photosensitive resin having openings of a desired pattern are formed on the seed layers M 1 and M 2 on the insulating layers 12 and 13 (see FIG. 6).

Next, electrolytic copper plating is performed on the non-formed portions of the dry films R1 and R2 to form a metal layer (first metal layer) to be the via conductors 31 and 32, the conductor layer 23, and the conductor layer 24 do. After the connection terminal 24A constituting the conductor layer 24 is formed, the convex portion T is formed on the connection terminal 24A by performing the electrolytic copper plating again (see FIG. 7).

Next, after the dry films R1 and R2 are peeled off using a peeling solution such as KOH, the seed layers M1 and M2 on the lower side of the dry films R1 and R2 are removed by etching (see FIG. 8) .

Next, the surfaces of the conductor layer 23 and the conductor layer 24 are surface-matched by a copper surface conditioner (for example, a Macitride bond CZ manufactured by Mackie). By coarsening the surfaces of the conductor layers 23 and 24, the adhesion with the resist layers 41 and 42 formed on the conductor layers 23 and 24 is improved.

Next, the resist layers 41 and 42 are formed by applying a photosensitive resist material (photosensitive resin) on the conductor layers 23 and 24 and the insulating layers 12 and 13, respectively, and then the connection terminals 23C and 24A And 24B, and the openings 41A and 42A for exposing the convex portion T, respectively.

Thereafter, the connection terminal 23C is exposed by the development, and the opening 41A in which the resist layer 41 forms the bottom surface 41S and the opening 41A penetrating the resist layer 42 in the thickness direction, T and a part of the surface of the connection terminal 24A and an opening 42 for exposing a part of the surface of the connection terminal 24B are collectively formed to obtain the wiring board 100 of the present embodiment (see FIG. 1) .

When the resist layer 41 is developed, the wiring board 100 is immersed in a sodium carbonate aqueous solution (density 1% by weight) for a short time (a time for the surface of the photosensitive resin of the non- The resist resin layer 41 is filled between the connection terminals 23C by removing the swollen and emulsified photosensitive resin from the wiring board 100 during the manufacturing process, And an opening 41A for forming the bottom surface 41S is formed.

As described above, in the wiring board 100 according to the present embodiment, since the via conductors 32 in the via holes 13 are so-called field vias, the connection terminals 24A formed on the via conductors 32 A concave portion is likely to occur on the surface. As a result, a resin such as a resist material may remain in the concave portion. However, according to the method of manufacturing the wiring board 100 according to the present embodiment, the conductive convex portion T having the outer diameter larger than the outer diameter of the via conductor 32 is formed on the connection terminal 24A. This can suppress the formation of recesses on the connection terminals 24A and suppress the generation of resin debris such as a resist material in the recesses.

In the present embodiment, in the step of forming the connection terminal 23C and the connection terminal 24A, the via conductors 31 and 32 and the connection terminals 23C and 24A are formed by electrolytic plating, T are formed by electrolytic plating when the via conductors 31 and 32 and the connection terminals 23C and 24A are formed. Thereby, it is not necessary to add a separate step to form the convex portion T, and the manufacturing process can be simplified. In addition, the manufacturing cost of the wiring board 100 can be reduced.

(Other Embodiments)

9 to 12 are views for explaining a manufacturing method of the wiring board 100 according to another embodiment. Here, an embodiment in which the convex portion T is formed by a method different from the above embodiment will be described. Hereinafter, a method of manufacturing the wiring board 100 according to another embodiment will be described with reference to Figs. 1 to 6 and Figs. 9 to 12. Fig. The same constituent elements as those described in the embodiment are denoted by the same reference numerals, and redundant description is omitted.

First, the wiring board 100 is manufactured as described with reference to Figs. 3 to 6, and a photosensitive resin having openings of a desired pattern is formed on the seed layers M1 and M2 on the insulating layers 12 and 13 Thereby forming the dry films R1 and R2 (see Fig. 6).

Next, electrolytic copper plating is performed on the non-formed portions of the dry films Rl and R2 to form the via conductors 31 and 32 in the via holes 12A and 13A and the via conductors 31 and 32 constituting the conductor layer 23 The land 23A, the wiring 23B and the connection terminal 23C and the connection terminals 24A and 24B constituting the conductor layer 24 are formed respectively (see FIG. 9). Since the via conductor 32 is a field via, the concave portion 24R is likely to be generated in the connection terminal 24A formed on the via conductor 32. [

Next, a dry film (R3) is formed on the dry film (R1), and a dry film (R4, third resist layer) having an opening (AP) for forming a convex portion (T) on the dry film (See Fig. 10).

Next, a metal layer (second metal layer) to be a convex portion T is formed in the opening AP of the dry film R4 by electrolytic copper plating (see Fig. 11).

Next, the dry films R1 to R4 are peeled off using a peeling solution such as KOH, and then the seed layers M1 and M2 on the lower side of the dry films R1 to R4 are removed by etching (see Fig. 12) .

Next, the surfaces of the conductor layer 23 and the conductor layer 24 are surface-matched by a copper surface conditioner (for example, a Macitride bond CZ manufactured by Mackie). The surfaces of the conductor layers 23 and 24 are roughened to improve the adhesion with the resist layers 41 and 42 formed on the conductor layers 23 and 24, respectively.

Next, the resist layers 41 and 42 are formed by applying a photosensitive resist material on the conductor layers 23 and 24 and the insulating layers 12 and 13, respectively, and then the connection terminals 23C, 24A, Exposure for forming the openings 41A and 42A for exposing the convex portion T is performed. Thereafter, the connection terminal 23C is exposed by the development and the opening 41A in which the resist layer 41 forms the bottom surface 41S and the opening 41A penetrating the resist layer 42 in the thickness direction to form the convex portion T And the openings 42 for exposing a part of the surfaces of the connection terminals 24A and 24B are collectively formed to obtain the wiring board 100 of the present embodiment (see FIG. 1).

As described above, according to the method for manufacturing the wiring board 100 according to the other embodiments, the conductive convex portion T having the outer diameter larger than the outer diameter of the via conductor 32 is formed on the connection terminal 24A have. This can suppress the formation of recesses on the connection terminals 24A and suppress the generation of resin debris such as a resist material in the recesses.

The step of forming the convex portion T is a step of forming a dry film R4 (third resist layer) having an opening AP for forming the convex portion T on the connection terminal 24A, A metal layer serving as a convex portion T is formed in the opening portion AP of the dry film R4 by electrolytic plating and then the dry film R4 is removed. As a result, the convex portion T can be reliably formed on the connection terminal 24A. In addition, the outer diameter and height of the convex portion T can be easily changed.

100: wiring substrate 11: core substrate
12, 13: insulating layer 12A, 13A:
21 to 24: conductor layer 31, 32: via conductor
41, 42: resist layer 41A, 42A:

Claims

And a second main surface located on a side opposite to the first main surface of the multilayer body, wherein the first main surface and the second main surface of the multilayer body are located on opposite sides of the first main surface, A method of manufacturing a wiring board formed by surfaces of a first insulating layer and a second insulating layer constituting an insulating layer,
Forming a first via hole penetrating the first insulating layer in the thickness direction and a second via hole penetrating the second insulating layer in the thickness direction;
A first via conductor that fills the first via hole and a second via conductor that fills the second via hole are formed, and a first connection terminal is formed on the first via conductor and the first insulation layer, A step of forming a second connection terminal on the second via conductor and the second insulating layer,
Forming a conductive convex portion having an outer diameter larger than the outer diameter of the second via conductor on the second connection terminal;
Forming a first resist layer having photosensitivity on the first insulating layer and the first connecting terminal after the step of forming the convex portion, and forming a second resist layer having photosensitivity on the second insulating layer and the second connecting terminal, ; A step
Performing exposure for forming openings for exposing the first connection terminals and the convex portions to the first and second resist layers;
Wherein the first resist layer is an opening for exposing the tops and side surfaces of the plurality of first connection terminals in the same opening by the development of the first and second resist layers, And forming a second opening through the second resist layer in the thickness direction so as to expose the convex portion in a collective manner.

The method according to claim 1,
In the step of forming the first and second connection terminals,
The first and second via conductors and the first metal layer serving as the first and second connection terminals are formed by electrolytic plating,
The convex portion
Wherein the first metal layer is formed by the electrolytic plating at the time of forming the first metal layer.

The method according to claim 1,
Wherein the step of forming the convex portion comprises:
Forming a third resist layer having an opening for forming the convex portion on the second connection terminal;
A step of forming a second metal layer as the convex portion in the opening of the third resist layer by electrolytic plating,
And removing the third resist layer.