TWI569703B - Wiring substrate manufacturing method - Google Patents

Description

Wiring substrate manufacturing method

The present invention relates to a method of manufacturing a wiring board.

A terminal for connection to a semiconductor wafer (hereinafter referred to as a connection terminal) is formed on the surface side of the wiring substrate on which the semiconductor wafer is mounted. In recent years, the density of the connection terminals has continued to increase, and the interval (pitch) of the connection terminals to be arranged has been narrowed. Therefore, a wiring board having an NSMD (Non-Solder-Mask Defined) shape in which a plurality of connection terminals are disposed in the same opening of the solder resist layer has been proposed.

However, when a plurality of connection terminals are arranged in the same opening at a narrow pitch, the solder applied to the surface of the connection terminal flows to the adjacent connection terminal side, and a short circuit occurs between the connection terminals. Then, it is proposed to fill the filling member between the connection terminals (for example, refer to Patent Document 1). According to this proposal, since the connection terminals are filled with the filling member, it is possible to prevent underfill or NCP (Non-Conductive Paste) or NCF from being filled in the gap between the semiconductor wafer and the wiring substrate when being connected to the semiconductor wafer. (Non-Conductive Film) The generation of voids between the connection terminals. Therefore, it is possible to prevent the solder from flowing to the pores during the reflow and short-circuiting between the connection terminals.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent No. 5415632

However, in the above proposal, after the resist layer is laminated on the connection terminal, the opening is formed by developing the plurality of connection terminals without developing the resist layer; and filling the plurality of connection terminals member.

In general, in the wiring board, a connection terminal for connection to a mother board or the like is formed not only on the front side but also on the back side. Further, similarly to the surface side, a resist layer (resin layer) is formed on the back side, and an opening for exposing each connection terminal on the resist layer is formed to penetrate the resist layer. Further, the opening on the front side and the opening on the back side are formed in the same development step.

Generally, the development time for forming the opening portion is determined in accordance with the depth of the opening on the surface side to be formed. Therefore, development is performed by the development time determined by the depth of the opening on the surface side to be formed, and the opening of the resist layer that does not penetrate the surface side and the opening of the resist layer that penetrates the back side can be formed. However, when the surface of the connection terminal on the back side has a pit, the resist material buried in the pit cannot be removed by development, and a resin such as a resist material remains in the pit. When resin residue occurs, contact failure occurs when it is connected to a mother board or the like, or sufficient solder cannot be applied when solder is applied to the connection terminal.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a wiring board capable of suppressing generation of resin residue at a connection terminal.

In order to achieve the above object, the present invention provides a method of manufacturing a wiring board having a laminated body in which a single conductor layer and a plurality of insulating layers are alternately laminated, and the first main surface of the laminated body and the opposite of the first main surface The second main surface of the side is formed by the surfaces of the first insulating layer and the second insulating layer constituting the plurality of insulating layers, and the method for manufacturing the wiring substrate is characterized in that the first insulating layer is formed to penetrate the thickness direction. a first via hole and a second via hole penetrating the second insulating layer in the thickness direction; forming a first via conductor filling the first via hole and a second via conductor filling the second via hole; a first connection terminal is formed on the first via conductor and the first insulating layer, a second connection terminal is formed on the second via conductor and the second insulating layer, and an outer diameter is formed on the second connection terminal than the second via conductor a step of forming a conductive protrusion having a large outer diameter; and after forming the protrusion, forming a photosensitive first resist layer on the first insulating layer and the first connection terminal, and the second insulating layer and the second insulating layer 2nd connection terminal is formed with photosensitive second a step of forming a resist layer; performing a step of exposing the opening portions for exposing the first connection terminal and the convex portion to the first and second resist layers; and developing the first and second resist layers a step of forming the first opening and the second opening at a time, wherein the first opening is an opening that exposes the first connection terminal, and the first resist layer forms a bottom surface, and the second opening forms a second resist The layer penetrates the thickness direction and exposes the convex portion.

According to the present invention, since the second connection terminal is formed Since the conductive convex portion having a larger diameter than the outer diameter of the second via conductor can prevent the occurrence of pits in the second connection terminal, it is possible to suppress the occurrence of resin residue such as the second resist layer on the second connection terminal.

According to an aspect of the present invention, in the step of forming the first and second connection terminals, the first and second via conductors and the first and second connection terminals are formed by electrolytic plating. The first metal layer and the convex portion are formed by electrolytic plating when the first metal layer is formed.

According to an aspect of the present invention, when the first metal layer which becomes the first and second via conductors and the first and second connection terminals is formed by electrolytic plating, a convex portion is also formed. That is to say, the manufacturing steps can be simplified without additionally adding a step for forming the convex portion.

In another aspect of the invention, the step of forming the convex portion has a step of forming a third resist layer having an opening portion for forming the convex portion on the second connection terminal; by electrolytic plating a step of forming a second metal layer that becomes a convex portion in the opening of the third resist layer; and a step of removing the third resist layer.

According to another aspect of the present invention, after the third resist layer having the opening is formed in the second connection terminal, the second portion which becomes the convex portion is formed in the opening portion of the third resist layer by electrolytic plating. Metal layer. Therefore, the convex portion can be surely formed on the second connection terminal. Moreover, the outer diameter or height of the convex portion can be easily changed.

As described above, according to the present invention, it is possible to provide a method of manufacturing a wiring board capable of suppressing generation of resin residue on a connection terminal.

11‧‧‧ core substrate

12, 13‧‧‧ insulation

12A, 13A‧‧‧ access hole

21~24‧‧‧ conductor layer

21A, 22A, 23A‧‧‧access end (via land)

21B, 22B, 23B‧‧‧ wiring

23C, 24A, 24B‧‧‧ connection terminals

24R‧‧‧ pit

31, 32‧‧‧ Path conductor

41, 42‧‧‧Resist layer

41A, 42A‧‧‧ openings

41S‧‧‧ bottom

100‧‧‧Wiring substrate

R1~R4‧‧‧ dry film

S‧‧‧ side

T‧‧‧ convex

AP‧‧‧ openings

M1, M2‧‧‧ seed layer

T1, T2‧‧‧ thickness

Fig. 1 is a cross-sectional view showing a wiring board of an embodiment.

Fig. 2 is an enlarged plan view showing a connection terminal of the wiring board of the embodiment.

Fig. 3 is a view showing a manufacturing step of the wiring board of the embodiment.

Fig. 4 is a view showing a manufacturing step of the wiring board of the embodiment.

Fig. 5 is a view showing a manufacturing step of the wiring board of the embodiment.

Fig. 6 is a view showing a manufacturing step of the wiring board of the embodiment.

Fig. 7 is a view showing a manufacturing step of the wiring board of the embodiment.

Fig. 8 is a view showing a manufacturing step of the wiring board of the embodiment.

Fig. 9 is a view showing a manufacturing step of a wiring board according to another embodiment.

Fig. 10 is a view showing a manufacturing step of a wiring board according to another embodiment.

Fig. 11 is a view showing a manufacturing step of a wiring board according to another embodiment.

Fig. 12 is a view showing a manufacturing step of a wiring board according to another embodiment.

[Formation of the Invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The wiring board of the embodiment described below is merely an example, and the present invention is not limited to the following embodiments. For example, in the following description, the wiring substrate having the core substrate will be described as an example, but a so-called coreless substrate having no core substrate may be used.

(embodiment)

Fig. 1 is a cross-sectional view showing a wiring board 100 of the embodiment. FIG. 2 is an enlarged plan view of the connection terminal 24A and the convex portion T included in the wiring board 100. Hereinafter, the configuration of the wiring board 100 will be described with reference to FIGS. 1 and 2 .

The wiring board 100 includes a core substrate 11, insulating layers 12 and 13, conductor layers 21 to 24, via conductors 31 and 32, and resist layers 41 and 42. Further, the core substrate 11 and the insulating layers 12 and 13 and the conductor layers 21 and 22 constitute a laminated body, and a semiconductor wafer is mounted on the surface (first main surface) side, and a mother board or the like is connected to the back surface (second main surface) side.

The core substrate 11 is made of a heat resistant resin sheet (for example, bismaleimide-three A resin plate made of a resin plate or a fiber-reinforced resin plate (for example, a glass fiber reinforced epoxy resin).

(Structure on the surface side)

The conductor layer 21 is formed on the surface of the core substrate 11. The conductor layer 21 includes a via land 21A that is in electrical contact with the via conductor 31, and a wiring 21B that is not in contact with the via conductor 31. The conductor layer 21 is formed of a metal having excellent conductivity such as copper.

The insulating layer 12 (first insulating layer) is formed by thermally hardening a thermosetting resin composition on the surfaces of the conductor layer 21 and the core substrate 11. In the insulating layer 12, a via hole (first via hole) 12A penetrating in the thickness direction is formed by laser or the like. The via hole 31 (first via conductor) is filled in the via hole 12A. The via conductor 31 electrically connects the conductor layer 21 and the conductor layer 23.

The conductor layer 23 is formed on the insulating layer 12. The conductor layer 23 includes a via end surface 23A that is in electrical contact with the via conductor 31, a wiring 23B that is not in contact with the via conductor 31, and a connection terminal 23C (first connection terminal). The conductor layer 23 is formed of a metal having excellent conductivity such as copper.

The connection terminal 23C is a terminal for connection to a semiconductor wafer mounted on the surface side of the wiring substrate 100. Further, the exposed portion of the connection terminal 23C may be coated with a metal plating layer. Metal plating layer It is composed of a single or plural layers (for example, a Ni layer/Au layer, a Ni layer/Pd layer/Au layer) selected from, for example, a metal layer selected from the group consisting of a Ni layer, a Sn layer, an Ag layer, a Pd layer, and an Au layer. Further, instead of the metal plating layer, an OSP (Organic Solderability Preservative) treatment may be performed. Further, the solder may be applied, or the solder may be applied to the metal plating layer after the metal plating layer is applied.

The resist layer 41 (first resist layer) is formed on the conductor layer 23 and the insulating layer 12. The resist layer 41 is formed of a photosensitive resist material. In the resist layer 41, an opening portion 41A is formed in which at least a part of the connection terminal 23C is exposed and the resist layer 41 itself forms the bottom surface 41S.

As shown in FIG. 1, the thickness T1 of the resist layer 41 of the bottom surface 41S is thinner than the thickness (height) T2 of the connection terminal 23C. Further, the resist layer 41 of the bottom surface 41S is filled between the connection terminals 23C in a state of being in close contact with the side surface S of the connection terminal 23C.

In addition, in FIG. 1, the NSMD shape in which a plurality of connection terminals 23C are disposed in one opening 41A is formed, and the number of connection terminals 23C exposed in one opening 41A may be any. For example, only one connection terminal 23C may be exposed in one opening 41A.

(constitution on the back side)

The conductor layer 22 is formed on the back surface of the core substrate 11. The conductor layer 22 includes a via end surface 22A that is in electrical contact with the via conductor 32, and a wiring 22B that is not in contact with the via conductor 32. The conductor layer 22 is formed of a metal having excellent conductivity such as copper.

The insulating layer 13 (second insulating layer) is formed by thermally curing the thermosetting resin composition on the back surface of the conductor layer 22 and the core substrate 11. In absolute The edge layer 13 is formed with a via hole (second via hole) 13A penetrating in the thickness direction by laser or the like. The via hole 32 (second via conductor) is filled in the via hole 13A. The via conductor 32 electrically connects the conductor layer 22 and the conductor layer 24.

The conductor layer 24 is formed on the insulating layer 13. The conductor layer 24 includes a connection terminal 24A (second connection terminal) that is in electrical contact with the via conductor 32, a connection terminal 24B that is not in contact with the via conductor 32, and a convex portion T that is formed on the connection terminal 24A. The conductor layer 24 is formed of a metal having excellent conductivity such as copper. Further, the conductor layer 24 may be provided with a wiring (not shown).

The connection terminals 24A and 24B are terminals for connection to a mother board or the like provided on the back side of the wiring board 100. Further, the exposed portions of the connection terminals 24A, 24B or the convex portion T may be coated with a metal plating layer. As the metal plating layer, a single or plural layers (for example, a Ni layer/Au layer, a Ni layer/Pd layer/Au) such as a metal layer selected from a Ni layer, a Sn layer, an Ag layer, a Pd layer, and an Au layer may be used. Layer). Further, instead of the metal plating layer, an OSP (Organic Solderability Preservative) treatment may be performed. Further, the solder may be applied, or the solder may be applied to the metal plating layer after the metal plating layer is applied.

As shown in FIG. 2, the outer diameter D1 of the convex portion T in plan view is larger than the outer diameter D2 of the via conductor 32 in plan view. Here, the outer diameter D1 of the convex portion T and the outer diameter D2 of the via conductor 32 mean the maximum value of the outer diameter. Further, in FIG. 2, the shape of the convex portion T in plan view is circular, but is not limited to this shape. For example, the shape of the convex portion T in the plan view may be set to be polygonal or elliptical. Further, in this case, the projection area in which the convex portion T is projected in the thickness direction of the insulating layer 13 is projected as long as the via conductor 32 is included. The projection area of the insulating layer 13 in the thickness direction may be sufficient.

The area of the convex portion T in the plan view may be wider than the S2 of the via conductor 32. By making the outer diameter D1 of the convex portion T in the plan view larger than the outer diameter D2 of the via conductor 32 in the plan view, it is difficult to cause resin residue on the connection terminal 24A.

The resist layer 42 (second resist layer) is formed on the conductor layer 24 and the insulating layer 13. In the resist layer 42, an opening portion 42A that penetrates the thickness direction and exposes a part of the convex portion T and the connection terminals 24A and 24B is formed. In other words, the opening 42A of the resist layer 42 has an SMD shape in which a part of the connection terminals 24A and 24B are exposed.

(Method of Manufacturing Wiring Substrate)

3 to 8 are views showing a manufacturing procedure of the wiring substrate 100 of the embodiment. Hereinafter, a method of manufacturing the wiring substrate 100 will be described with reference to FIGS. 1 and 3 to 8. It is to be noted that the same configurations as those described with reference to FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof will not be repeated.

A plate-shaped resin substrate (core substrate 11) to which copper foil is attached to the front and back surfaces is prepared. Next, electrolytic copper plating is performed in accordance with a conventional method, and a copper plating layer having a desired shape is formed on both surfaces of the core substrate 11. Thereafter, the copper foil and the copper plating layer on both surfaces of the core substrate 11 are etched into a desired shape, and the via end surface 21A and the wiring 21B constituting the conductor layer 21 are formed on the surface side, and the conductor layer 22 is formed on the back surface side. The vias are connected to the end face 22A and the wiring 22B (see FIG. 3).

Next, the surface of the conductor layer 21 and the conductor layer 22 is roughened by a copper surface roughening agent (for example, Mech-Etch Bond CZ: MEC Corporation). By roughening the surfaces of the conductor layers 21, 22, the conductor layers 21, 22 and The adhesion of the insulating layers 12, 13 formed on the conductor layers 21, 22, respectively, is improved.

Then, a thermosetting resin film is laminated on the front side and the back side of the core substrate 11 on which the conductor layers 21 and 22 are formed, and is hardened by vacuum heating under vacuum to form the insulating layers 12 and 13 respectively (refer to the figure). 4). Thereby, the surface and the back surface of the core substrate 11 are covered by the insulating layers 12 and 13, respectively. Next, the insulating layers 12 and 13 are irradiated with laser light of a predetermined intensity by, for example, a CO ₂ gas laser or a YAG laser, and via holes 12A and 13A are formed (see FIG. 5 ).

Thereafter, the insulating layers 12 and 13 including the via holes 12A and 13A are subjected to a roughening treatment. Further, when the insulating layers 12 and 13 are filled with a filler, the filler is removed and remains on the insulating layers 12 and 13, so that the water is appropriately washed. Next, the via holes 12A and 13A are subjected to desmear processing and outline etching, and the via holes 12A and 13A are cleaned. Further, an air blow treatment may be performed between the above washing and desmear treatment. Even in the case where the free filler is not completely removed by water washing, the residual of the filler can be more reliably suppressed by the air blowing treatment.

Next, seed layers M1 and M2 for electrolytic plating are formed on the insulating layers 12 and 13, respectively. The seed layers M1, M2 can be formed by a conventional method such as electroless copper plating, sputtering (PVD), vacuum evaporation, or the like. Then, dry films R1 and R2 composed of a photosensitive resin having an opening of a desired pattern are formed on the seed layers M1 and M2 on the insulating layers 12 and 13 (see FIG. 6).

Next, electrolysis is performed on the non-formed portions of the dry films R1 and R2. Copper plating is performed to form a metal layer (first metal layer) which becomes the via conductors 31 and 32, the conductor layer 23, and the conductor layer 24. Then, after the connection terminal 24A constituting the conductor layer 24 is formed, the convex portion T is formed on the connection terminal 24A by further performing electrolytic copper plating (see FIG. 7).

Next, after the dry films R1 and R2 are peeled off using a peeling liquid such as KOH, the seed layers M1 and M2 under the dry films R1 and R2 are removed by etching (see FIG. 8).

Next, the surface of the conductor layer 23 and the conductor layer 24 is formed by a copper surface roughening agent (for example, Mech-Etch Bond CZ: MEC Corporation). By roughening the surfaces of the conductor layers 23, 24, the adhesion between the conductor layers 23, 24 and the resist layers 41, 42 formed on the conductor layers 23, 24, respectively, is improved.

Next, after the resistive layers (photosensitive resins) are applied to the conductor layers 23 and 24 and the insulating layers 12 and 13, respectively, the resist layers 41 and 42 are formed, and exposure for forming the openings 41A and 42A, respectively, is performed. The openings 41A and 42A expose the connection terminals 23C, 24A, and 24B and the convex portion T.

Then, the wiring board 100 of the present embodiment is obtained by forming the opening 41A and the opening 42 once, and the opening 41A exposes the connection terminal 23C, and the resist layer 41 forms the bottom surface 41S. The opening 42 The resist layer 42 is penetrated in the thickness direction, and a part of the surface of the convex portion T and the connection terminal 24A or a part of the surface of the connection terminal 24B is exposed (see FIG. 1).

Further, when the resist layer 41 is developed, the wiring substrate 100 in the manufacturing process is short-time (the photosensitive resin sheet in the non-photosensitive portion) The time period in which the surface is slightly swelled is immersed in a sodium acid aqueous solution (concentration: 1% by weight), and then the photosensitive resin which is swollen with water is emulsified, and the swelled and emulsified photosensitive resin is removed from the wiring substrate 100 during the production process. Thereby, the opening portion 41A of the bottom surface 41S is formed by being filled between the connection terminals 23C and forming the resist layer 41.

As described above, in the wiring substrate 100 of the present embodiment, since the via conductor 32 in the via hole 13 is formed as a so-called filled via, the surface of the connection terminal 24A formed on the via conductor 32 is formed. It is easy to create pits. Therefore, a resin such as a resist material may remain in the pit. However, according to the method of manufacturing the wiring board 100 of the present embodiment, the conductive bumps T having an outer diameter larger than the outer diameter of the via conductor 32 are formed on the connection terminal 24A. Therefore, it is possible to suppress the formation of pits in the connection terminal 24A, and it is possible to suppress the resin residue such as the resist material from being generated in the pit.

Further, in the present embodiment, in the step of forming the connection terminal 23C and the connection terminal 24A, the via conductors 31 and 32 and the connection terminals 23C and 24A are formed by electrolytic plating, and the convex portion T is formed by forming the via conductor 31, 32 and electrolytic plating in the case of connecting the terminals 23C and 24A. Therefore, it is not necessary to add a separate step for forming the convex portion T, and the manufacturing steps can be simplified. Moreover, the manufacturing cost of the wiring board 100 can be reduced.

(Other embodiments)

9 to 12 are views for explaining a method of manufacturing the wiring substrate 100 of another embodiment. Here, an embodiment in which the convex portion T is formed by a method different from the above embodiment will be described. Hereinafter, the wiring substrate 100 of another embodiment will be described with reference to FIGS. 1 to 6 and 9 to 12. Manufacturing method. The same configurations as those described in the embodiments are denoted by the same reference numerals, and the description thereof will not be repeated.

First, the wiring substrate 100 is manufactured as described with reference to FIGS. 3 to 6, and a photosensitive resin having an opening having a desired pattern is formed on the seed layers M1 and M2 on the insulating layers 12 and 13. The dry films R1 and R2 are formed (see Fig. 6).

Then, electrolytic copper plating is performed on the non-formed portions of the dry films R1 and R2, and the via conductors 31 and 32 are formed in the via holes 12A and 13A, and the via end faces 23A, the wirings 23B and the connections constituting the conductor layer 23 are respectively formed. The terminal 23C and the connection terminals 24A and 24B constituting the conductor layer 24 (see FIG. 9). Further, since the via conductor 32 is a filling via, the pit 24R is likely to be generated at the connection terminal 24A formed on the via conductor 32.

Then, a dry film R3 is formed on the dry film R1, and a dry film R4 (third resist layer) having an opening portion AP (see FIG. 10) for forming the convex portion T is formed on the dry film R2.

By the electrolytic copper plating, a metal layer (second metal layer) which becomes the convex portion T is formed in the opening portion AP of the dry film R4 (see FIG. 11).

Next, after the dry films R1 to R4 are peeled off using a peeling liquid such as KOH, the seed layers M1 and M2 under the dry films R1 to R4 are removed by etching (see FIG. 12).

The surface of the conductor layer 23 and the conductor layer 24 is roughened by a copper surface roughening agent (for example, Mech-Etch Bond CZ: manufactured by MEC Corporation). By roughening the surfaces of the conductor layers 23, 24, the adhesion between the conductor layers 23, 24 and the resist layers 41, 42 formed on the conductor layers 23, 24, respectively, is improved.

Next, after the resistive layers 41 and 42 are formed on the conductor layers 23 and 24 and the insulating layers 12 and 13, respectively, the connection terminals 23C, 24A, 24B and the convex portion T are formed. Exposure of the exposed openings 41A, 42A. Then, the wiring board 100 of the present embodiment is obtained by forming the opening 41A and the opening 42 once, and the opening 41A exposes the connection terminal 23C, and the resist layer 41 forms the bottom surface 41S. The opening 42 The resist layer 42 is penetrated in the thickness direction, and a part of the surface of the convex portion T and the connection terminals 24A and 24B is exposed (see FIG. 1).

As described above, according to the method of manufacturing the wiring board 100 of the other embodiment, the connection terminal 24A is formed with the conductive convex portion T having an outer diameter larger than the outer diameter of the via conductor 32. Therefore, it is possible to suppress the formation of pits in the connection terminal 24A, and it is possible to suppress the resin residue such as the resist material from being generated in the pit.

Further, the step of forming the convex portion T is to form a dry film R4 (third resist layer) having the opening portion AP for forming the convex portion T on the connection terminal 24A, and electrolytic plating is performed on the dry film R4. After the metal layer which becomes the convex part T is formed in the opening part AP, the dry film R4 is removed. Therefore, the convex portion T can be surely formed on the connection terminal 24A. Moreover, the outer diameter or height of the convex portion T can be easily changed.

11‧‧‧ core substrate

12, 13‧‧‧ insulation

12A, 13A‧‧‧ access hole

21~24‧‧‧ conductor layer

21A, 22A, 23A‧‧‧ access end face

21B, 22B, 23B‧‧‧ wiring

23C, 24A, 24B‧‧‧ connection terminals

31, 32‧‧‧ Path conductor

41, 42‧‧‧Resist layer

41A, 42A‧‧‧ openings

41S‧‧‧ bottom

100‧‧‧Wiring substrate

S‧‧‧ side

T‧‧‧ convex

T1, T2‧‧‧ thickness

Claims (3)

A method of manufacturing a wiring board having a laminated body in which at least one conductor layer and a plurality of insulating layers are alternately laminated, wherein the first main surface of the laminated body and the second main surface opposite to the first main surface The main surface is formed by the surfaces of the first insulating layer and the second insulating layer constituting the plurality of insulating layers, and the method for manufacturing the wiring substrate is characterized in that the first insulating layer is formed to penetrate the first direction of the thickness direction. a via hole and a step of penetrating the second insulating layer in the thickness direction of the second via hole; forming a first via conductor filling the first via hole and a second via conductor filling the second via hole; a first connection terminal is formed on the first via conductor and the first insulating layer, a second connection terminal is formed on the second via conductor and the second insulating layer, and an outer diameter is formed on the second connection terminal. a step of forming a conductive convex portion larger than an outer diameter of the second via conductor; and forming a photosensitive first resist on the first insulating layer and the first connection terminal after the step of forming the convex portion Layer, and a step of forming a photosensitive second resist layer on the second insulating layer and the second connection terminal; and forming the first connection terminal and the convex portion on the first and second resist layers a step of exposing the exposed opening; and a step of forming the first opening and the second opening at a time by development of the first and second resist layers, wherein the first opening is the first connecting terminal The exposed opening portion, and the first resist layer forms a bottom surface The second opening portion penetrates the second resist layer in the thickness direction and exposes the convex portion. The method of manufacturing a wiring board according to claim 1, wherein in the step of forming the first and second connection terminals, the first and second via conductors and the first and second connections are formed by electrolytic plating. The first metal layer of the terminal is formed by the electrolytic plating when the first metal layer is formed. The method of manufacturing a wiring board according to claim 1, wherein the step of forming the convex portion has a step of forming a third resist layer having an opening portion for forming the convex portion on the second connection terminal; Plating, a step of forming a second metal layer that becomes the convex portion in the opening of the third resist layer, and a step of removing the third resist layer.