JP2020181925A - Wiring board and manufacturing method of wiring board - Google Patents

Abstract

To enhance power supply to a wiring board.SOLUTION: A wiring board 1 comprises: a core board 10; a first build-up layer 11 made up of first interlayer insulation layers 32 and first conductor layers 31 which are alternately laminated; and a second build-up layer 12 made up of second interlayer insulation layers 42 and second conductor layers 41 which are alternately laminated. In the conductor layers, among the first conductor layers 31 and the second conductor layers 41, which are located on the same rank from the core board 10, the area and the thickness of the conductor layers in the second build-up layer 12 are greater than the area and the thickness of the conductor layers in the first build-up layer 11.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

Patent Document 1 describes an upper build-up layer including a first conductor layer and an uppermost conductor layer including a pad for mounting an IC chip on the upper and lower surfaces of a core substrate, and a second conductor layer and a motherboard. A printed wiring board is disclosed in which a lower build-up layer including a bottom conductor layer including a pad for connecting the two is formed. The sum of the thickness of the first conductor layer and the thickness of the uppermost conductor layer is larger than the sum of the thickness of the second conductor layer and the thickness of the lowest conductor layer.

Japanese Unexamined Patent Publication No. 2014-45019

In the printed wiring board of Patent Document 1, the sum of the thicknesses of the conductor layers formed on the side closer to the IC chip than the center line of the printed wiring board is larger than the sum of the thicknesses of the conductor layers formed on the far side. .. It may be difficult to form the conductor layer on the side close to the IC chip at a fine pitch. In addition, the power supply may not be sufficient.

The wiring board of the present invention has a first surface and a second surface opposite to the first surface, and includes a core substrate including an insulating layer, a first surface side conductor layer, and a second surface side conductor layer. The first build-up layer provided on the first surface of the core substrate and the first interlayer insulating layer and the first conductor layer on the first interlayer insulating layer are alternately laminated, and the core substrate. It includes a second build-up layer provided on the second surface and in which a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated. Then, in the conductor layer located in the same order as the core substrate of the first conductor layer and the second conductor layer, the area of the conductor layer in the second build-up layer is within the first build-up layer. It is larger than the area of the conductor layer, and the thickness of the conductor layer in the second build-up layer is larger than the thickness of the conductor layer in the first build-up layer.

The method for manufacturing a wiring board of the present invention has a first surface and a second surface opposite to the first surface, and includes an insulating layer, a first surface side conductor layer, and a second surface side conductor layer. A first structure in which a core substrate is provided and a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer are alternately laminated on the first and second surfaces of the core substrate. It includes providing a second build-up layer in which a build-up layer and a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated. By providing the first build-up layer and the second build-up layer, the conductor layer on the second surface side is thicker than the conductor layer in the same order as the core substrate on the first surface side, and Includes forming to have a large area.

According to the embodiment of the present invention, it is considered that the power supply of the wiring board can be strengthened. In addition, it is possible to manufacture a wiring board having a high power supply capacity.

The cross-sectional view which shows an example of the wiring board of one Embodiment of this invention. The cross-sectional view which shows the other example of the wiring board of one Embodiment of this invention. The enlarged view which shows an example of the shape of the conductor layer surface on the via conductor in the wiring board of one Embodiment. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention.

A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1 having a first surface 1F and a second surface 1B opposite to the first surface 1F, which is an example of the wiring board of one embodiment. As shown in FIG. 1, the wiring board 1 includes a core substrate 10 having a first surface 10F and a second surface 10B opposite to the first surface 10F, and a first surface 10F on the first surface 10F of the core substrate 10. One build-up layer 11 and a second build-up layer 12 on the second surface 10B of the core substrate 10 are included. In the example of FIG. 1, the two build-up layers (first build-up layer 11 and second build-up layer 12) include the same number of conductor layers as each other. The first build-up layer 11 is formed by alternately laminating the first interlayer insulating layer 32 and the first conductor layer 31 on the first interlayer insulating layer 32. In the example of FIG. 1, the first build-up layer 11 includes three first conductor layers 31 and three first interlayer insulating layers 32. The second build-up layer 12 is formed by alternately laminating a second interlayer insulating layer 42 and a second conductor layer 41 on the second interlayer insulating layer 42. In the example of FIG. 1, the second build-up layer 12 includes three second conductor layers 41 and three second interlayer insulating layers 42. The number of conductor layers and interlayer insulating layers in the first and second build-up layers is not limited to three, and any number of conductors, for example, two or less, or four or more, is used. Layers and interlayer insulating layers may be provided.

The core substrate 10 is formed on both sides of the core insulating layer 5 and the core insulating layer 5, that is, on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively, the first surface side conductor layers 3 and the second. The surface side conductor layer 4 is included. Through-hole through holes 55 penetrating the core insulating layer 5 are formed in the core insulating layer 5, and by filling each through-hole through hole 55 with a conductor, the first surface side conductor layer 3 and the first surface side conductor layer 5 are formed. A through-hole conductor 50 that connects the two-sided conductor layer 4 is formed.

A desired conductor pattern is formed in each of the conductor layers (first surface side conductor layer 3, second surface side conductor layer 4, first conductor layer 31, and second conductor layer 41). In the example of FIG. 1, the first surface side conductor layer 3 and the second surface side conductor layer 4 are formed of three layers. The first conductor layer 31 and the second conductor layer 41 are formed of two layers. However, the number of layers forming each of the conductor layers is not limited to the example of FIG. 1, and for example, the first conductor layer 31 and the second conductor layer 41 may be formed of three layers. The first surface side conductor layer 3 and the second surface side conductor layer 4 may have, for example, a metal foil layer, an electroless plating film layer, and an electroplating film layer. The first conductor layer 31 and the second conductor layer 41 may have, for example, an electroless plating film layer and an electrolytic plating film layer. Each conductor layer can be formed, for example, with any metal such as copper, nickel, silver, palladium, alone or in combination.

The core insulating layer 5, the first interlayer insulating layer 32, and the second interlayer insulating layer 42 are formed by using an arbitrary insulating material. Examples of the insulating material include resin materials such as epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. Each insulating layer formed using these resin materials may contain a reinforcing material such as glass fiber or aramid fiber and / or an inorganic filler such as silica. When each build-up layer includes a plurality of interlayer insulating layers as in the example of FIG. 1, each interlayer insulating layer in each build-up layer may be formed by using the same resin material. Detachment between each interlayer insulation layer may be prevented. Further, for example, all the interlayer insulating layers, that is, the first interlayer insulating layer 32 in the first build-up layer 11 and the second interlayer insulating layer 42 in the second build-up layer 12 are made of the same insulating resin material. May be formed using. However, different resin materials may be used.

Each interlayer insulating layer includes first and second via conductors 51 and 52 that connect conductor layers formed on both sides of the first build-up layer 11 and the second build-up layer 12 to each other. Includes. The first interlayer insulating layer 32 includes a first via conductor 51, and the second interlayer insulating layer 42 includes a second via conductor 52. The first and second via conductors 51 and 52 are so-called filled vias formed by filling through holes penetrating each interlayer insulating layer with a conductor. The first and second via conductors 51 and 52 are integrally formed with the conductor layer on the upper side (opposite side of the core substrate) of each. Therefore, the first and second via conductors 51 and 52 and the first conductor layer 31 and the second conductor layer 41 are the same plating film (electroless plating film and electrolytic plating film) made of, for example, copper or nickel. Is formed by. The through-hole conductor 50 formed through the core insulating layer 5 is also formed by an electroless plating film and an electrolytic plating film made of copper, nickel, or the like.

The wiring board 1 of the example of FIG. 1 further has a first solder resist layer 6 formed on the first build-up layer 11 and a second solder resist layer formed on the second build-up layer 12. 7 is included. The first solder resist layer 6 covers the first conductor layer 31 of the uppermost layer, and the second solder resist layer 7 covers the second conductor layer 41 of the uppermost layer. The first and second solder resist layers 6 and 7 are formed by using, for example, an epoxy resin or a polyimide resin.

An electronic component (not shown) such as a semiconductor element can be mounted on the first surface 1F of the wiring board 1 (that is, the upper surface side of the wiring board 1). The outermost first conductor layer 31 of the first build-up layer 11 of the wiring board 1 includes a plurality of connection pads 31a for being electrically connected to the terminals of such electronic components. The solder resist layer 6 has an opening for exposing the connection pad 31a. On the other hand, an external electric circuit board such as a motherboard may be connected on the second surface 1B of the wiring board 1 (that is, the lower surface side of the wiring board 1). The outermost second conductor layer 41 of the second build-up layer 12 of the wiring board 1 includes a plurality of connection pads 41a for being electrically connected to the terminals of such an external board. The solder resist layer 7 has an opening for exposing the connection pad 41a.

In the wiring board 1, the area of the first conductor layer 31 in the first build-up layer 11 on the first surface 10F side of the core board 10 (here, the area of the conductor layer means the occupied area of the conductor in the conductor layer). The area of the second conductor layer 41 in the second build-up layer 12 on the second surface 10B side of the core substrate 10 is different (hereinafter, the material of each conductor layer is not limited to copper, but The ratio of the total area of the conductor pattern in each conductor layer to the area of the wiring substrate 1 is called the residual copper ratio). In the example shown in FIG. 1, in the conductor layers located in the same order from the core substrate 10, the residual copper ratio of the conductor layer on the second surface 10B side, that is, the residual copper ratio of the second conductor layer 41 is the first surface 10F. It is larger than the residual copper ratio of the conductor layer on the side, that is, the residual copper ratio of the first conductor layer 31. Here, the "conductor layers located in the same order from the core substrate 10" are ordered from the core substrate 10 to the outside of the first surface 10F side or the outside of the second surface 10B side in each build-up layer. It means conductor layers that have the same order when attached.

In the example shown in FIG. 1, in the first conductor layer 31 and the second conductor layer 41 located in the same order from the core substrate 10, the conductor thickness of the second conductor layer 41 is the conductor thickness of the first conductor layer 31. It is formed to be thicker than the other. For example, the conductor thickness of the second conductor layer 41 laminated on the second interlayer insulating layer 42, which is located closest to the core substrate 10 side of the second build-up layer 12, is the first build-up. It is thicker than the conductor thickness of the first conductor layer 31 laminated on the first interlayer insulating layer 32 which is located closest to the core substrate 10 side of the layers 11. Further, the conductor thickness of the outermost second conductor layer 41 of the second build-up layer 12 is thicker than the conductor thickness of the outermost first conductor layer 31 of the first build-up layer 11. Therefore, the current allowable amount on the second surface 1B side of the wiring board 1 can be increased. The voltage drop and heat generation of the power supply line on the second surface 1B side can be suppressed. Therefore, it is considered that the power supply can be strengthened on the second surface 1B of the wiring board 1.

The thickness of each of the first conductor layers 31 in the first build-up layer 11 may be equal or different. For example, the thickness of each of the first conductor layers 31 is 5 μm or more and 20 μm or less. Further, the thickness of each of the second conductor layers 41 in the second build-up layer 12 may be equal or different. For example, the thickness of each of the second conductor layers 41 is 15 μm or more and 30 μm or less. As described above, in the present embodiment, in the first conductor layer 31 and the second conductor layer 41 located in the same order from the core substrate 10, the thickness of the second conductor layer 41 is larger than the thickness of the first conductor layer 31. thick. In the example shown in FIG. 1, in the first conductor layer 31 and the second conductor layer 41 located in the same order from the core substrate 10, the thickness of the second conductor layer 41 is about the thickness of the first conductor layer 31. It is formed to be 1.25 times or more and about 2.0 times or less.

The thickness of each of the first surface side conductor layer 3 and the second surface side conductor layer 4 of the core substrate 10 is, for example, 5 μm or more and 30 μm or less. In the example of FIG. 1, the conductor thickness of the first surface side conductor layer 3 and the conductor thickness of the second surface side conductor layer 4 are substantially equal to each other. However, the conductor thicknesses of the first surface side conductor layer 3 and the second surface side conductor layer 4 may be formed to be different thicknesses. Also in this case, preferably, the sum of the areas of the conductor layers on the second surface 10B side of the core insulating layer 5 in the wiring substrate 1, that is, the sum of the areas of the second surface side conductor layer 4 and the area of the second conductor layer 41 ( The residual copper ratio on the second surface 10B side) is the sum of the areas of the conductor layers on the first surface 10F side of the core insulating layer 5, that is, the sum of the areas of the first surface side conductor layer 3 and the area of the first conductor layer 31. It is larger than (remaining copper ratio on the 1st surface 10F side). For example, the residual copper ratio on the second surface 10B side is about 1.1 to 1.3 times the residual copper ratio on the first surface 10F side. It is considered that the power supply strengthening on the second surface 10B side can be satisfactorily achieved.

In the example shown in FIG. 1, the first conductor layer 31 in the first build-up layer 11 and the second conductor layer 41 in the second build-up layer 12 are located in the same order from the core substrate 10. In the first conductor layer 31 and the second conductor layer 41, the conductor area of the second conductor layer 41 is larger than the conductor area of the first conductor layer 31, and the conductor thickness of the second conductor layer 41 is the first conductor layer 31. It is formed so as to be thicker than the conductor thickness of. However, the conductor area of all the second conductor layers 41 is larger than the conductor area of the corresponding first conductor layer 31, and the conductor thickness of all the second conductor layers 41 is that of the corresponding first conductor layer 31. It does not have to be thicker than each of the conductor thicknesses. The conductor area of at least one second conductor layer 41 is larger than the conductor area of the first conductor layer 31 located in the same order as the core substrate 10, and the conductor thickness thereof is the corresponding first conductor layer 31. It may be formed so as to be thicker than the conductor thickness. An example of such a wiring board is shown in FIG. In the wiring board 1a of the example of FIG. 2, among the second conductor layers 41 in the second build-up layer 12, they are laminated on the second interlayer insulating layer 42 located closest to the core substrate 10 side. The conductor area of the second conductor layer 411 is located in the same order as the core substrate 10, that is, the position closest to the core substrate 10 side among the first conductor layers 31 in the first build-up layer 11. It is formed larger than the conductor area of the first conductor layer 311 laminated on the first interlayer insulating layer 32. Further, the conductor thickness of the second conductor layer 411 is formed to be thicker than the conductor thickness of the first conductor layer 311.

In the examples shown in FIGS. 1 and 2, the thickness of each interlayer insulating layer in the first build-up layer 11 and the second build-up layer 12 is, for example, 15 μm or more and 100 μm or less. The first interlayer insulating layers 32 in the first build-up layer 11 may be formed to have the same thickness or may be formed to have different thicknesses. Similarly, each of the second interlayer insulating layers 42 in the second build-up layer 12 may be formed with the same thickness or may be formed with different thicknesses. For example, in the first interlayer insulating layer 32 and the second interlayer insulating layer 42 located in the same order from the core substrate 10, the thickness of the second interlayer insulating layer 42 is formed to be thicker than the thickness of the first interlayer insulating layer 32. May be done. The occurrence of warpage that may occur due to the difference in the residual copper ratio between the first surface 10F side and the second surface 10B side of the core substrate 10 may be suppressed. Here, the interlayer insulating layers located in the same order from the core substrate 10 are the interlayer insulating layers in each build-up layer from the core substrate 10 toward the outside on the first surface 10F side or the outside on the second surface 10B side. Means the interlayer insulating layers having the same order when ordered.

The first conductor layer 31 and the second conductor layer 41, which are located in the same order from the core substrate 10, are simultaneously formed by plating films (electroless plating film and electrolytic plating film). In order to form the second conductor layer 41 having a thicker conductor thickness than the first conductor layer 31, in the present embodiment, the first conductor layer 31 and the second conductor layer 41 are formed on the electroless plating film. When forming the electrolytic plating film, a voltage is applied so that the current density on the second surface 10B side of the core substrate 10 is higher than the current density on the first surface 10F side. As a result, the thickness of the electrolytic plating film on the second surface 10B side can be formed thicker than the thickness of the electrolytic plating film on the first surface 10F side. As described above, the first via conductor 51 is formed simultaneously and integrally with the first conductor layer 31, which is a conductor layer on the upper side (opposite side of the core substrate). Further, the second via conductor 52 is formed simultaneously and integrally with the second conductor layer 41, which is a conductor layer on the upper side (opposite side of the core substrate). The speed at which the through holes are filled with the electrolytic plating film and the speed at which the electrolytic plating film is laminated on the electroless plating film on the flat interlayer insulating layer can be controlled by the conditions of the electrolytic plating and the selection of the components of the plating solution. .. Therefore, the surface of each conductor layer facing the opposite side of the core substrate 10 can be curved convexly toward the opposite side of the core substrate 10. The convex portion of the embodiment in which the conductor layer includes such a convex portion is enlarged and shown in FIG. By increasing the current density in order to increase the film thickness of the electrolytic plating film, it is possible to increase the formation rate of the plating film in the through hole and on the electroless plating film on the flat interlayer insulating layer. Therefore, the amount of protrusion of the convex portion on the surface of the conductor layer can be larger. Since the purpose of FIG. 3 is to explain the convex portion of the conductor layer, the illustration of the via conductor on the convex portion of the conductor layer included in the wiring board 1 of FIG. 1 is omitted. There is.

In the example of FIG. 3, the conductor layer 600 is formed of the electroless plating film 601 and the electrolytic plating film 602. The electrolytic plating film 602 on the electroless plating film 601 fills the through hole 700a formed in the interlayer insulating layer 700 to form the electroless plating film 601 and the via conductor 800, and forms the core substrate of the interlayer insulating layer 700. It is formed on a surface facing the opposite side (upper side in FIG. 3). The electrolytic plating film 602 includes a convex portion that curves upwardly from the surface 600S of the conductor layer 600 (the surface of the portion of the conductor layer 600 on the interlayer insulating layer 700) on the via conductor 800. As described above, the height h of the convex portion from the surface 600s can be increased by increasing the thickness of the electrolytic plating film 602, that is, the thickness of the conductor layer 600. Therefore, if a conductor layer having a thick conductor thickness and a conductor layer having a thinner conductor thickness are formed at the same time, the height h becomes higher in the conductor layer having a thick conductor thickness to which a large current density is applied. That is, the thicker the conductor thickness D of the conductor layer 600 including the electrolytic plating film 602, the larger the height h of the convex portion of the conductor layer 600 from the surface 600S can be. Therefore, as shown in FIG. 1, the conductor thickness of the second conductor layer 41 on the second surface 10B side of the core substrate 10 is thicker than that of the first conductor layer 31 on the first surface 10F side. In the wiring board, the height h of the convex portion in the thicker second conductor layer 41 is equal to or larger than the height h of the convex portion in the thinner first conductor layer 31.

The convex portion as shown in FIG. 3 can be formed along the thickness direction Z of the wiring board 1. However, the cross-sectional shape of the convex portion is not limited to the shape shown in FIG. 3, and any shape may be used depending on the electroplating conditions when filling the through holes with plating, the shape or size of the through holes, and the like. It can be taken.

The height h of the convex portion is, for example, about 3 μm or less. For example, when the first conductor layer 31 of the wiring board 1 includes a convex portion, the height h (h1) of the convex portion of the first conductor layer 31 is about 1.5 μm or less, that is, the first conductor layer 31. It is about 1/10 or less of the conductor thickness D of. When the second conductor layer 41 includes a convex portion, the height h (h2) of the convex portion of the second conductor layer 41 is about 2.5 μm or less, that is, the conductor thickness D of the second conductor layer 41. It is about 1/10 or less. If the height h of the convex portion of the conductor layer is made higher than about 3 μm, a problem may occur in the lamination of the next interlayer insulating layer and the conductor layer on the formed conductor layer. There is a risk of thickness imbalance or distortion in the wiring board during manufacturing. In addition, there is a possibility that a problem may occur in the patterning accuracy of the conductor layer laminated on the conductor layer. It is considered that such a problem may be prominent on the side of the second surface 10B on which the second conductor layer 41 having a thicker conductor thickness D is formed. Preferably, the height h2 of the convex portion in the second conductor layer 41 having the thicker thickness D is larger than the height h1 of the convex portion in the first conductor layer 31 having the thinner thickness D, but is higher. The height h2 is about 1.7 times or less the height h1. However, it is convex on both the first conductor layer 31 on the first via conductor 51, or on both the first conductor layer 31 on the first via conductor 51 and the second conductor layer 41 on the second via conductor 52. No portion is formed, and the entire surface of the first conductor layer 31 facing the opposite side of the core substrate or the entire surface of the first conductor layer 31 and the second conductor layer 41 facing the opposite side of the core substrate is formed substantially flat. You may.

Next, using the wiring board 1 shown in FIG. 1 as an example, a method for manufacturing the wiring board of one embodiment will be described below with reference to FIGS. 4A to 4D.

As shown in FIG. 4A, a laminated plate having a core insulating layer 5 constituting the core substrate 10 and metal foils 3e provided on both sides of the core insulating layer 5 is prepared. For example, a double-sided copper-clad laminate having a metal foil 3e made of copper is prepared.

As shown in FIG. 4B, the through hole 55 is formed by irradiation with carbon dioxide gas laser light or the like, and includes, for example, a copper foil, a copper electroless plating film, and an electrolytic plating film by using a subtractive method. The first surface side conductor layer 3 and the second surface side conductor layer 4 having a desired conductor pattern are formed on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively. Further, the through-hole conductor 50 is formed by filling the through holes 55 with the electroless plating film and the electrolytic plating film.

As shown in FIG. 4C, the first interlayer insulating layer 32 and the second interlayer insulating layer 42 are formed. Further, the first conductor layer 31 is formed on the first interlayer insulating layer 32. Along with the formation of the first conductor layer 31, the second conductor layer 41 is formed on the second interlayer insulating layer 42. In the formation of the first conductor layer 31, the first via conductor 51 is formed in the first interlayer insulating layer 32. Further, in the formation of the second conductor layer 41, the second via conductor 52 is formed in the second interlayer insulating layer 42.

For the first and second interlayer insulating layers 32 and 42, for example, a prepreg containing a semi-cured epoxy resin and a reinforcing material such as glass fiber, or a film-shaped epoxy resin is laminated on both sides of the core substrate 10. It is formed by thermocompression bonding. When laminating the prepreg, a metal foil made of, for example, copper may be laminated on the prepreg and crimped together with the prepreg. After that, for example, by irradiating with carbon dioxide laser light, a through hole 32a for forming the first via conductor 51 is formed in the first interlayer insulating layer 32. Similarly, a through hole 42a for forming the second via conductor 52 is formed in the second interlayer insulating layer 42.

Then, for example, using a semi-additive method, a metal film obtained by electroless copper plating or the like and an electrolytic plating film formed on the metal film using this metal film as a seed layer are formed, and the first and first one having a desired conductor pattern. The second conductor layers 31, 41, and the first via conductor 51 and the second via conductor 52 are formed. In the wiring board 1 of the example of FIG. 1, the second conductor layer 41 has a thicker conductor thickness than the first conductor layer 31. Therefore, when the electrolytic plating film is formed so that the thickness of the electrolytic plating film on the second surface 10B side is thicker than the thickness of the electrolytic plating film on the first surface 10F side, the second surface 10B side of the core substrate 10 is formed. The voltage is applied so that the current density of the first surface is higher than the current density on the first surface 10F side. The thickness of the conductor layer of the second conductor layer 41 integrally formed with the second via conductor 52 is about 1. The thickness of the conductor layer of the first conductor layer 31 integrally formed with the first via conductor 51. It is about 25 times or more and about 2.0 times or less.

For example, by applying a general method for manufacturing a build-up wiring board using a semi-additive method, on the first conductor layer 31 and the second conductor layer 41 of FIG. 4C, the first interlayer insulating layer 32 and the first interlayer insulating layer 32 and the second conductor layer 41 are further applied. The first conductor layer 31, the second interlayer insulating layer 42, and the second conductor layer 41 are formed, and the first build-up layer 11 and the second build-up are formed on the first surface 10F and the second surface 10B of the core substrate 10. Layers 12 are formed respectively (FIG. 4D). A first via conductor 51 is formed on the laminated first interlayer insulating layer 32. Further, a second via conductor 52 is formed on the laminated second interlayer insulating layer 42.

In FIG. 4D, the first and second build-up layers 11 and 12, which are composed of three interlayer insulating layers and a conductor layer, respectively, are formed on the first surface 10F side and the second surface 10B side of the core substrate 10. However, the number of layers of the interlayer insulating layer and the conductor layer in the buildup layers 11 and 12 is not limited to this example, and the buildup includes a larger number of layers by repeating the above buildup process. Layers may be formed. However, regardless of the number of layers of the interlayer insulating layer and the conductor layer laminated on both sides of the core substrate 10, the formation of the conductor layer has a current density on the second surface 10B side of the core substrate 10 in the wiring board during manufacturing. It includes applying a voltage so as to be higher than the current density on the first surface 10F side. Therefore, in at least one set of conductor layers (first conductor layer 31 and second conductor layer 41) located in the same order as the core substrate 10, the second conductor layer 41 formed on the second surface 10B side of the core substrate 10 Is formed so as to be larger than the thickness of the first conductor layer 31 formed on the first surface 10F side. In FIG. 4D, when the first and second conductor layers are formed, a voltage is applied so that the current density on the second surface 10B side of the core substrate 10 is higher than the current density on the first surface 10F side. Therefore, in the conductor layer located in the same order as the core substrate 10 of the first conductor layer 31 and the second conductor layer 41, the thickness of the second conductor layer 41 formed on the second surface 10B side of the core substrate 10 Is formed to be larger than the thickness of the first conductor layer 31 formed on the first surface 10F side.

After that, the solder resist layer 6 is formed on the first build-up layer 11, and the solder resist layer 7 is formed on the second build-up layer 12. The solder resist layers 6 and 7 are formed by, for example, forming a resin layer containing a photosensitive epoxy resin, a polyimide resin, or the like, exposure using a mask having an appropriate pattern, and development.

The connection pads 31a and 41a exposed to the openings of the solder resist layers 6 and 7, respectively, may be subjected to electroless plating, solder leveler, spray coating or the like as necessary to obtain Au, Ni / Au, Ni / Pd / Au. A surface protective film (not shown) made of solder, heat-resistant preflux, or the like may be formed. By going through the above steps, the wiring board 1 of the example of FIG. 1 is completed.

The wiring board of the embodiment is not limited to the structure exemplified in each drawing and the structure, shape, and material exemplified in this specification. For example, the first and second via conductors 51, 52 and the like do not have to have a shape that reduces the diameter toward the core substrate 10. Further, the solder resist layers 6 and 7 may not be provided.

Further, the method for manufacturing the wiring board of the embodiment is not limited to the method described above with reference to each drawing. For example, the core substrate 10 may be formed by using a semi-additive method using a copper foil. Each conductor layer in the first and second build-up layers 11 and 12 may be formed by using a subtractive method. The conditions and order of the manufacturing method described above can be changed as appropriate. Depending on the structure of the wiring board actually manufactured, some steps may be omitted or another step may be added.

1 Wiring board 1a Wiring board 1F First side of wiring board 1B Second side of wiring board 5 Core insulating layer 10 Core board 10F First side of core board 10B Second side of core board 11 First build-up layer 12 Second Build-up layer 3 1st surface side conductor layer 4 2nd surface side conductor layer 31 1st conductor layer 32 1st interlayer insulating layer 41 2nd conductor layer 42 2nd interlayer insulating layer 50 Through hole conductor 51 1st via conductor 52 2 Via conductors 6, 7 Solder resist layer

Claims (8)

A core substrate having a first surface and a second surface opposite to the first surface, and including a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer.
A first build-up layer provided on the first surface of the core substrate and having a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer alternately laminated.
A second build-up layer provided on the second surface of the core substrate and having a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer alternately laminated.
It is a wiring board equipped with
In the conductor layer located in the same order as the core substrate among the first conductor layer and the second conductor layer, the area of the conductor layer in the second build-up layer is the conductor layer in the first build-up layer. The thickness of the conductor layer in the second build-up layer is larger than the thickness of the conductor layer in the first build-up layer. In the wiring board according to claim 1, the total area of the second surface side conductor layer and the second conductor layer is larger than the total area of the first surface side conductor layer and the first conductor layer. .. The wiring board according to claim 1, wherein the conductor layer in the second build-up layer is the conductor layer located in the same order as the core board of the first conductor layer and the second conductor layer. The thickness is 1.25 times or more and 2.0 times or less the thickness of the conductor layer in the first build-up layer. The wiring board according to claim 1, wherein a plurality of connection pads for connecting to terminals of electronic components are formed on the outermost first conductor layer of the first build-up layer. The wiring board according to claim 1.
A first via conductor that penetrates the first interlayer insulating layer and connects the conductor layers on both sides of the first interlayer insulating layer.
It has a second via conductor that penetrates the second interlayer insulating layer and connects the conductor layers on both sides of the second interlayer insulating layer.
The surface of the first conductor layer facing the opposite side of the core substrate is curved convexly from the surface of the first conductor layer toward the side opposite to the core substrate on the first via conductor.
The surface of the second conductor layer facing the opposite side of the core substrate is curved convexly from the surface of the second conductor layer toward the side opposite to the core substrate. In the wiring board according to claim 5, the height of the convex portion of the second conductor layer from the surface of the second conductor layer is the height of the convex portion of the first conductor layer. , Equal to or greater than the height of the first conductor layer from the surface. A core substrate having a first surface and a second surface opposite to the first surface and including a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer is provided.
A first build-up layer in which a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer are alternately laminated on the first surface and the second surface of the core substrate, and a first A second build-up layer in which a two-layer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated is provided.
It is a manufacturing method of a wiring board including
Providing the first build-up layer and the second build-up layer
The present invention includes forming the conductor layer on the second surface side so as to be thicker and have a larger area than the conductor layer of the same rank as the core substrate on the first surface side. In the method for manufacturing a wiring board according to claim 7, in providing the first build-up layer and the second build-up layer, the current density on the second surface side of the core substrate is on the first surface side. It includes performing electroplating by applying a voltage so as to be higher than the current density of.

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