JP2020181867A - Wiring board and manufacturing method of wiring board - Google Patents

Abstract

To suppress warpage of a wiring board.SOLUTION: A wiring board 1 comprises: a core board 10 including a core insulation layer 5, a first surface-side conductor layer 3a, and a second surface-side conductor layer 4a; a first build-up layer 11 in which first interlayer insulation layers 32 and first conductor layers 31 are alternately laminated; and a second build-up layer 12 in which second interlayer insulation layers 42 and second conductor layers 41 are alternately laminated. The number of the first conductor layers 31 is equal to that of the second conductor layers 41. The sum of the areas occupied by conductors in the first surface-side conductor layer 3a and the first conductor layers 31 is greater than the sum of the areas occupied by the conductors in the second surface-side conductor layer 4a and the second conductor layers 41. A center line in a thickness direction of the wiring board 1 is located in the first build-up layer 11 or the first surface-side conductor layer 3a.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

Patent Document 1 discloses a wiring board for mounting a semiconductor element or the like, which includes conductor layers adhered to the upper and lower surfaces of the core substrate and the insulating layers laminated on the upper and lower surfaces of the core substrate at different occupied area ratios. Has been done. The conductor layer is formed so that the conductor thickness of the conductor layer having a large occupied area ratio is thinner than the conductor thickness of the conductor layer having a small occupied area ratio as compared with the corresponding conductor layer on the opposite side of the core substrate. ing.

Japanese Unexamined Patent Publication No. 2016-139632

In the wiring board including the conductor layer of Patent Document 1, in the conductor layers on the upper and lower surfaces of the core substrate and the conductor layers on the upper surface side and the lower surface side centering on the core substrate, the conductor layers are arranged according to the occupied area ratio with respect to the insulating layer. Formed with different thicknesses. It may be difficult to match the resistance values of the signal lines on the upper and lower surfaces of the core substrate.

The wiring board of the present invention has a first surface and a second surface opposite to the first surface, and includes a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer. A first build-up layer provided on the first surface of the core substrate and alternately laminated with a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer, and the core substrate. A second build-up layer is provided on the second surface of the above, and the second interlayer insulating layer and the second conductor layer on the second interlayer insulating layer are alternately laminated. Then, the number of the first conductor layers in the first build-up layer is equal to the number of the second conductor layers in the second build-up layer, and the first surface side conductor layer and the first conductor layer are equal to each other. The total area occupied by the conductors is larger than the total area occupied by the conductors in the second surface side conductor layer and the second conductor layer, and the center line in the thickness direction of the wiring board is the first build-up. It is in the layer or in the conductor layer on the first surface side.

The method for manufacturing a wiring board of the present invention has a first surface and a second surface opposite to the first surface, and has a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer. A core substrate including the core substrate is provided, and a first build-up layer formed by alternately laminating a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer is provided on the first surface of the core substrate. A second build-up layer in which a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated is provided on the second surface of the core substrate. Includes. The provision of the first build-up layer and the provision of the second build-up layer form the same number of the first conductor layer and the second conductor layer, and the first surface side conductor. Making the total area occupied by the conductors in the layer and the first conductor layer larger than the total area occupied by the conductors in the second surface side conductor layer and the second conductor layer, and in the thickness direction of the wiring substrate. The thickness of the core insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer is adjusted so that the center line in the above is located in the first build-up layer or the first surface side conductor layer. It includes things.

According to the embodiment of the present invention, a conductor is provided in each conductor layer between the conductor layer provided on the first surface side of the core substrate and the conductor layer provided on the second surface side of the core substrate. It is considered that the warp of the wiring board can be suppressed even if the total area occupied is different. Moreover, such a highly reliable wiring board can be manufactured.

The cross-sectional view which shows an example of the wiring board of one Embodiment of this invention. The cross-sectional view which shows the other example of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention. The figure which shows an example of the manufacturing method of the wiring board of one Embodiment of this invention.

A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1 which is an example of a wiring board of one embodiment. As shown in FIG. 1, the wiring board 1 includes a core substrate 10 having a first surface 10F and a second surface 10B opposite to the first surface 10F, and a first surface on the first surface of the core substrate 10. It includes a build-up layer 11 and a second build-up layer 12 on the second surface of the core substrate 10. The two build-up layers (first build-up layer 11 and second build-up layer 12) include the same number of conductor layers as each other. The first build-up layer 11 is formed by alternately laminating the first interlayer insulating layer 32 and the first conductor layer 31 on the first interlayer insulating layer 32. In the example of FIG. 1, the first build-up layer 11 includes two first conductor layers 31 and two first interlayer insulating layers 32. The second build-up layer 12 is formed by alternately laminating a second interlayer insulating layer 42 and a second conductor layer 41 on the second interlayer insulating layer 42. In the example of FIG. 1, the second build-up layer 12 includes two second conductor layers 41 and two second interlayer insulating layers 42. The number of conductor layers and interlayer insulating layers in the first and second build-up layers is not limited to two, and any number, for example, one, or three or more conductor layers, is not limited to two. And an interlayer insulating layer may be provided. However, the number of the first conductor layer and the first interlayer insulating layer laminated in the first build-up layer is the same as the number of the second conductor layer and the second interlayer insulating layer laminated in the second build-up layer, respectively. Formed the same.

The core substrate 10 is formed on both sides of the core insulating layer 5 and the core insulating layer 5, that is, on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively, the first surface side conductor layers 3a and the second. The surface side conductor layer 4a is included. The core insulating layer 5 is formed with a through-hole conductor 50 that connects the first surface side conductor layer 3a and the second surface side conductor layer 4a.

Although each conductor layer (first surface side conductor layer 3a, second surface side conductor layer 4a, first conductor layer 31, and second conductor layer 41) is shown to have a single layer structure in FIG. It may have multiple layers, such as two or three. Each of these conductor layers may have, for example, a metal foil layer, an electroless plating film layer, and an electrolytic plating film layer. Each conductor layer can be formed, for example, with any metal such as copper, nickel, silver, palladium, alone or in combination.

The core insulating layer 5, the first interlayer insulating layer 32, and the second interlayer insulating layer 42 are formed by using an arbitrary insulating material. Examples of the insulating material include resin materials such as epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. Each insulating layer formed by using these resin materials may contain a reinforcing material such as glass fiber or aramid fiber and / or an inorganic filler such as silica. When each build-up layer includes a plurality of interlayer insulating layers as in the example of FIG. 1, each interlayer insulating layer in each build-up layer may be formed by using the same resin material. Detachment between each interlayer insulation layer may be prevented. Further, for example, all the interlayer insulating layers, that is, the first interlayer insulating layer 32 in the first build-up layer 11 and the second interlayer insulating layer 42 in the second build-up layer 12 are made of the same insulating resin material. May be formed using. However, different resin materials may be used.

Each interlayer insulating layer includes via conductors 51 and 52 that connect conductor layers formed on both sides of the interlayer insulating layer. The first interlayer insulating layer 32 includes a via conductor 51, and the second interlayer insulating layer 42 includes a via conductor 52. The via conductors 51 and 52 are so-called filled vias formed by filling through holes penetrating each interlayer insulating layer with a conductor. The via conductors 51 and 52 are integrally formed with the respective upper conductor layers. Therefore, the via conductors 51 and 52 are formed of, for example, an electroless plating film and an electrolytic plating film made of copper, nickel, or the like. The through-hole conductor 50 formed through the core insulating layer 5 is also formed by an electroless plating film and an electrolytic plating film made of copper, nickel, or the like.

The wiring board 1 of the example of FIG. 1 further has a first solder resist layer 6 formed on the first build-up layer 11 and a second solder resist layer formed on the second build-up layer 12. 7 is included. The first solder resist layer 6 covers the first conductor layer 31 of the uppermost layer, and the second solder resist layer 7 covers the second conductor layer 41 of the uppermost layer. The first and second solder resist layers 6 and 7 are formed by using, for example, an epoxy resin or a polyimide resin.

The outermost first conductor layer 31 of the first build-up layer 11 includes, for example, a connection pad 31a on which an electronic component or an external wiring board (not shown) is mounted. The solder resist layer 6 has an opening for exposing the connection pad 31a. The outermost second conductor layer 41 of the second build-up layer 12 includes a connection pad 41a. The connection pad 41a can be used, for example, for connecting to a motherboard or a package board of an electronic device in which the wiring board 1 is used. The solder resist layer 7 has an opening for exposing the connection pad 41a.

A desired conductor pattern is formed in each of the conductor layers (first surface side conductor layer 3a, second surface side conductor layer 4a, first conductor layer 31, and second conductor layer 41). In the wiring board 1, the sum of the areas occupied by the conductors in the conductor layer on the first surface 10F side of the core insulating layer 5 and the sum of the areas occupied by the conductors in the conductor layer on the second surface 10B side are different (hereinafter, the residual copper ratio). It is also called a difference. The material of each conductor layer is not limited to copper, but the ratio of the total area of the conductor pattern in each conductor layer to the area of the wiring board 1 is simply called the residual copper ratio. Ru). In the example of FIG. 1, the sum of the conductor areas occupied by the conductors in the conductor layer on the first surface 10F side, that is, the total area of the first surface side conductor layer 3a and the area of the first conductor layer 31 is the second surface 10B. It is larger than the sum of the conductor areas occupied by the conductors in the conductor layer on the side, that is, the sum of the areas of the second surface side conductor layer 4a and the area of the second conductor layer 41. For example, the ratio of the sum of the conductor areas on the second surface 10B side to the sum of the conductor areas on the first surface 10F side is larger than 1 and about 2 or less.

In such a wiring board, the build-up layer (second build-up layer 12) on the side where the residual copper ratio is small due to the difference in the coefficient of thermal expansion between the insulating layer made of a resin material and the conductor layer made of an arbitrary metal. ) Has a relatively large or small amount of heat shrinkage as compared with the build-up layer (first build-up layer 11) on the side having a large residual copper ratio. Therefore, during heat shrinkage, stress may be generated so that, for example, the second build-up layer 12 shrinks, that is, becomes an upwardly convex state, and the wiring board may warp. Deterioration of mountability may occur due to warpage.

Wiring to suppress warpage caused by the difference in residual copper ratio between both sides of the core substrate 10, that is, the first surface 10F side and the second surface 10B side from the core substrate 10, which may occur in the process of forming the build-up layer. In the substrate 1, the center line CC in the thickness direction of the wiring board 1 is adjusted so as to pass through the first build-up layer 11 or the first surface side conductor layer 3a. Therefore, the thickness of the first interlayer insulating layer 32 in the first build-up layer 11 is formed to be thicker than the thickness of the second interlayer insulating layer 42 in the second build-up layer 12. Preferably, the thickness of the first interlayer insulating layer 32 is such that the interlayer insulating layer formed under at least one conductor layer located in the same order as the core substrate in the first conductor layer 31 and the second conductor layer 41 is formed. Is formed thicker than the thickness of the second interlayer insulating layer 42. Here, the fact that the conductor layers are located in the same order from the core substrate 10 means that the conductor layers in each build-up layer are ordered from the core substrate 10 toward the outside on the first surface 10F side or the outside on the second surface 10B side. It means conductor layers that have the same order when attached. Further, the thickness of the core insulating layer 5 is formed to be thicker than the thickness of the second interlayer insulating layer 42. FIG. 1 shows an example in which the center line CC in the thickness direction of the wiring board 1 passes through the inside of the first surface side conductor layer 3a of the core board 10. As a result, in the wiring board 1, the difference in the amount of heat shrinkage that can occur due to the difference in the residual copper ratio between the first surface 10F side and the second surface 10B side of the core insulating layer 5 is the thickness of the core insulating layer 5 of the core substrate 10. It can be offset by the difference in the sum of the thicknesses of the insulating layers on both sides from the center of the direction, that is, the imbalance in the amount of resin on both sides. Therefore, it is considered that the occurrence of warpage caused by the difference in the residual copper ratio is suppressed.

The thickness of each of the first surface side conductor layer 3a, the second surface side conductor layer 4a, the first conductor layer 31 and the second conductor layer 41 is, for example, 5 μm or more and 20 μm or less. Preferably, the conductor thickness of the first surface side conductor layer 3a and the conductor thickness of the second surface side conductor layer 4a are substantially equal to each other. Further, preferably, among the first conductor layer 31 and the second conductor layer 41, the conductor thicknesses of the conductor layers located in the same order from the core substrate 10 are substantially the same. For example, the conductor thickness of the first conductor layer 31 laminated on the first interlayer insulating layer 32, which is located closest to the core substrate 10 side of the first build-up layer 11, is the second build-up. It is equal to the conductor thickness of the second conductor layer 41 laminated on the second interlayer insulating layer 42, which is located closest to the core substrate 10 side of the layers 12. Further, the conductor thickness of the outermost first conductor layer 31 of the first build-up layer 11 is equal to the conductor thickness of the outermost second conductor layer 41 of the second build-up layer 12. In the wiring board 1 of the present embodiment, in order to reduce warpage, the difference in conductor area between the first surface 10F side and the second surface 10B side of the core insulating layer 5 is offset by adjusting the thickness of the conductor layer. You don't have to. In the wiring board 1, there is no large difference in the sum of the thicknesses of the conductor layers between the first surface 10F side and the second surface 10B side of the core substrate 10. It is considered that the problem that it becomes difficult to match the resistance values of the signal lines formed by the pattern of the conductor layer on the first surface 10F side and the second surface 10B side of the core substrate 10 of the wiring board 1 is unlikely to occur.

FIG. 2 shows a wiring board 1a which is another example of the wiring board of one embodiment. In the example of FIG. 2, the wiring board 1a includes a first radiating element 21 and a second radiating element 22 constituting the antenna 2 on the second surface 10B side of the core insulating layer 5.

In the wiring board 1a, the second surface side conductor layer 4a includes the first radiating element 21. The outermost second conductor layer 411 of the second build-up layer 12 includes a second radiating element 22. The first radiating element 21 is composed of a conductor pattern formed on the second surface side conductor layer 4a. The second radiating element 22 is composed of a conductor pattern formed on the second conductor layer 411. A second interlayer insulating layer 42 is interposed between the first radiating element 21 and the second radiating element 22. The first radiating element 21 and the second radiating element 22 face each other via the second interlayer insulating layer 42 in order to form the antenna 2. The first radiating element 21 and the second radiating element 22 may form the antenna 2 by electromagnetically coupling with each other.

A signal to be transmitted from the antenna 2 or an external signal to be received by the antenna 2 is transmitted to the first radiating element 21. As described above, the first radiating element 21 may be a feeding element to which an electric signal should be supplied from the antenna 2 or to induce an electric signal based on an external radio wave.

The second radiating element 22 is insulated from a conductor other than the second radiating element 22. The second radiating element 22 cannot be energized from another conductor. The second radiating element 22 may be a non-feeding element that is not energized when the antenna 2 is used, as in the example of FIG.

In the example of FIG. 2, the first radiating element 21 which is a feeding element is included in the second surface side conductor layer 4a of the core substrate 10, and the signal to be transmitted by the antenna 2 is transmitted from the first build-up layer 11. It is transmitted to the first radiating element 21. Further, the signal received by the antenna 2 is transmitted from the first radiating element 21 to the first build-up layer 11. The first radiating element 21 is electrically connected to the first surface side conductor layer 3a of the core substrate 10 via the through-hole conductor 50. The first surface side conductor layer 3a and the first conductor layer 31 are electrically connected via the first via conductor 51. Therefore, for example, a high frequency signal can be transmitted bidirectionally between the first conductor layer 31 and the first radiating element 21 via the through-hole conductor 50 and the first via conductor 51.

A connection pad 31a is formed on the outermost first conductor layer 31 of the first build-up layer 11. For example, a signal generated by an electronic component (not shown) mounted on the connection pad 31a is transmitted in the first build-up layer 11 and in the first surface side conductor layer 3a via the connection pad 31a to be an antenna. Can be transmitted from 2. Further, the signal received by the antenna 2 can be transmitted, input to an electronic component (not shown) mounted on the connection pad 31a, and processed by this electronic component.

The wiring board 1a in the example of FIG. 2 includes a solder resist layer 71 formed on the second build-up layer 12. The solder resist layer 71 is formed by using, for example, an epoxy resin or a polyimide resin. The solder resist layer 71 covers the second radiating element 22.

As shown in FIG. 2, only the second interlayer insulating layer 42 is arranged between the first radiating element 21 and the second radiating element 22, and no conductor pattern is formed. Further, the first radiating element 21 is separated from other conductor patterns that can be formed on the second surface side conductor layer 4a. That is, in a plan view, a region without a conductor pattern is provided in the second surface side conductor layer 4a around the first radiating element 21. The second radiating element 22 is also separated from other conductor patterns that can be formed on the second conductor layer 411, and in a plan view, there is no conductor pattern around the second radiating element 22 of the second conductor layer 411. Is provided. The "planar view" means that the wiring board 1a is viewed from the outside with a line of sight parallel to the thickness direction of the wiring board 1a.

That is, in the wiring board 1a, the second surface side conductor layer 4a includes a region without a conductor pattern around the first radiating element 21. Further, the second conductor layer 411 includes a region without a conductor pattern around the second radiating element 22. Further, also in the second interlayer insulating layer 42 on the second surface side conductor layer 4a, the conductor pattern is not formed in the portion overlapping the periphery of the first and second radiating elements 21 and 22. Therefore, in the wiring board 1a, the difference in the sum of the conductor areas (difference in the residual copper ratio) between the first surface 10F side and the second surface 10B side of the core insulating layer 5 is larger than that in the case of the wiring board 1. It is thought that it has become. However, also in the wiring board 1a, similarly to the wiring board 1, the thickness of the first interlayer insulating layer 32 in the first build-up layer 11 is larger than the thickness of the second interlayer insulating layer 42 in the second build-up layer 12. Is also thickly formed. Further, the thickness of the core insulating layer 5 is formed to be thicker than the thickness of the second interlayer insulating layer 42. Therefore, the center line CC in the thickness direction of the wiring board 1 is adjusted so as to pass through the first build-up layer 11 or the first surface side conductor layer 3a. As a result, even in the wiring board 1a in which the antenna structure is included in one of the build-up layers, the residual copper on the first surface 10F side and the second surface 10B side of the core insulating layer 5 is the same as in the case of the wiring board 1. The difference in the amount of heat shrinkage that can occur due to the difference in rate is offset by the difference in the sum of the thicknesses of the insulating layers on both sides from the center of the core insulating layer 5 in the thickness direction of the core substrate 10, that is, the imbalance in the amount of resin on both sides. It is thought that. Therefore, it is considered that the occurrence of warpage is suppressed.

Next, using the wiring board 1 shown in FIG. 1 as an example, a method for manufacturing the wiring board of one embodiment will be described below with reference to FIGS. 3A to 3D.

As shown in FIG. 3A, a laminated plate having a core insulating layer 5 constituting the core substrate 10 and metal foils 3e provided on both sides of the core insulating layer 5 is prepared. For example, a double-sided copper-clad laminate having a metal foil 3e made of copper is prepared.

As shown in FIG. 3B, the through holes 10b are formed by irradiation with carbon dioxide gas laser light or the like, and a copper foil, a copper electroless plating film, and an electrolytic plating film are formed by using, for example, a semi-additive method using a copper foil. The first surface side conductor layer 3a and the second surface side conductor layer 4a, which include the above and have a desired conductor pattern, are formed on the first surface 10F side and the second surface 10B side of the core substrate 10, respectively. Further, the through-hole conductor 50 is formed by embedding the electroless plating film and the electrolytic plating film in the through hole 10b.

As shown in FIG. 3C, the first interlayer insulating layer 32 and the second interlayer insulating layer 42 are formed. Further, the first conductor layer 31 is formed on the first interlayer insulating layer 32. Along with the formation of the first conductor layer 31, the second conductor layer 41 is formed on the second interlayer insulating layer 42. In the formation of the first conductor layer 31, the first via conductor 51 is formed in the first interlayer insulating layer 32. Further, in the formation of the second conductor layer 41, the second via conductor 52 is formed in the second interlayer insulating layer 42.

For the first and second interlayer insulating layers 32 and 42, for example, a prepreg containing a semi-cured epoxy resin and a reinforcing material such as glass fiber, or a film-shaped epoxy resin is laminated on both sides of the core substrate 10. It is formed by thermocompression bonding. When laminating the prepreg, a metal foil made of, for example, copper may be laminated on the prepreg and crimped together with the prepreg. After that, for example, by irradiating carbon dioxide laser light, through holes 32a and 42a for forming the first and second via conductors 51 and 52 are formed in the first and second interlayer insulating layers 32 and 42, respectively. Laser.

Then, for example, the semi-additive method is used to form the first and second conductor layers 31 and 41 having a desired conductor pattern, and the first and second via conductors 51 and 52.

For example, by applying a general method for manufacturing a build-up wiring board using a semi-additive method, on the first conductor layer 31 and the second conductor layer 41 in FIG. 3C, the first interlayer insulating layer 32 and the first interlayer insulating layer 32 and the first are further formed. The first conductor layer 31, the second interlayer insulating layer 42, and the second conductor layer 41 are formed, and the first build-up layer 11 and the second build-up are formed on the first surface 10F and the second surface 10B of the core substrate 10. Layers 12 are formed respectively (FIG. 3D). Via conductors 51 and 52 are formed on the interlayer insulating layers 32 and 42. In FIG. 3D, the first and second built-up layers 11 and 12, which are composed of two interlayer insulating layers and a conductor layer, respectively, are formed on the first surface 10F side and the second surface 10B side of the core substrate.

After that, the solder resist layer 6 is formed on the first build-up layer 11, and the solder resist layer 7 is formed on the second build-up layer 12. The solder resist layers 6 and 7 are formed by, for example, forming a resin layer containing a photosensitive epoxy resin, a polyimide resin, or the like, exposure using a mask having an appropriate pattern, and development.

The connection pads 31a and 41a exposed to the openings of the solder resist layers 6 and 7 are subjected to electroless plating, solder leveler, spray coating or the like, if necessary, to form Au, Ni / Au, Ni / Pd / Au, or solder. , Or a surface protective film (not shown) made of heat-resistant preflux or the like may be formed. By going through the above steps, the wiring board 1 of the example of FIG. 1 is completed.

The wiring board of the embodiment is not limited to the structure exemplified in each drawing and the structure, shape, and material exemplified in this specification. For example, each via conductor such as the first via conductor 51 does not have to have a shape that reduces the diameter toward the core substrate 10. The second radiating element 22 may be exposed to the opening of the solder resist layer 7, and the solder resist layers 6 and 7 themselves may not be provided.

Further, the method for manufacturing the wiring board of the embodiment is not limited to the method described above with reference to each drawing. For example, the core substrate 10 may be formed by using a subtractive method. Each conductor layer in the first and second build-up layers 11 and 12 may be formed by using the full additive method. The conditions and order of the manufacturing method described above can be changed as appropriate. Depending on the structure of the wiring board actually manufactured, some steps may be omitted or another step may be added.

1 Wiring board 1a Wiring board 5 Core insulating layer 10 Core board 10F First side of core board 10B Second side of core board 11 First build-up layer 12 Second build-up layer 2 Antenna 3a First side conductor layer 4a First Two-sided conductor layer 21 First radiating element 22 Second radiating element 31 First conductor layer 32 First interlayer insulating layer 41 Second conductor layer 42 Second interlayer insulating layer 51 First via conductor 52 Second via conductors 6, 7 Solder resist layer

Claims (7)

A core substrate having a first surface and a second surface opposite to the first surface, and including a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer.
A first build-up layer provided on the first surface of the core substrate and having a first interlayer insulating layer and a first conductor layer on the first interlayer insulating layer alternately laminated.
A second build-up layer provided on the second surface of the core substrate and having a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer alternately laminated.
It is a wiring board equipped with
The number of the first conductor layers in the first build-up layer is equal to the number of the second conductor layers in the second build-up layer.
The total area occupied by the conductors in the first surface side conductor layer and the first conductor layer is larger than the total area occupied by the conductors in the second surface side conductor layer and the second conductor layer.
The center line in the thickness direction of the wiring board is in the first build-up layer or in the first surface side conductor layer. The wiring substrate according to claim 1, wherein the interlayer insulating layer formed under at least one conductor layer located in the same order as the core substrate in the first conductor layer and the second conductor layer. The thickness of the first interlayer insulating layer is thicker than the thickness of the second interlayer insulating layer. The wiring board according to claim 1, wherein the first interlayer insulating layer and the second interlayer insulating layer are formed of the same resin material. The wiring board according to claim 1, wherein the conductor thickness of the first surface side conductor layer and the second surface side conductor layer are the same, and the core substrate in the first conductor layer and the second conductor layer The conductor thicknesses of the conductor layers located in the same order are the same. The wiring board according to claim 1, further comprising a radiation element constituting an antenna on the second surface side conductor layer and / or the second conductor layer. The wiring board according to claim 1, further comprising a first solder resist layer covering the first conductor layer and a second solder resist layer covering the second conductor layer. A core substrate having a first surface and a second surface opposite to the first surface and including a core insulating layer, a first surface side conductor layer, and a second surface side conductor layer is provided.
A first build-up layer in which the first interlayer insulating layer and the first conductor layer on the first interlayer insulating layer are alternately laminated is provided on the first surface of the core substrate.
A second build-up layer in which a second interlayer insulating layer and a second conductor layer on the second interlayer insulating layer are alternately laminated is provided on the second surface of the core substrate.
It is a manufacturing method of a wiring board including
Providing the first build-up layer and the second build-up layer means forming the same number of the first conductor layer and the second conductor layer, and providing the first surface side conductor layer and the same number of conductor layers. Making the total area occupied by the conductors in the first conductor layer larger than the total area occupied by the conductors in the second surface side conductor layer and the second conductor layer, and the center in the thickness direction of the wiring substrate. Adjusting the thickness of the core insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer so that the wire is located in the first build-up layer or the first surface side conductor layer. Includes.

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