JP2016103596A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can suppress an adverse effect caused by magnetostriction in an MRAM.SOLUTION: In a semiconductor device 10 of the present embodiment, an MRAM 55 is arranged at a position on an F surface 30F of a substrate 30, which does not overlap an extended line of a diagonal line of an MPU 50. A first conductor layer 22 on an F surface 11F side of a core substrate 11 of the substrate 30 is thicker than a first conductor layer 22 on an S surface 11S side, and a total volume of the conductor layers on the F surface 11F side of the core substrate 11 of the substrate 30 is larger than a total volume of the conductor layers on the S surface 11S side.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device in which a semiconductor element and a semiconductor memory are mounted on a substrate, and a manufacturing method thereof.

  In recent years, MRAM (Magnetic Resistive Random Access Memory) has been developed as a nonvolatile semiconductor memory that replaces a volatile semiconductor memory such as a DRAM (see, for example, Patent Document 1).

JP 2004-023062 A (paragraph [0002], paragraph [0005], FIG. 5)

  However, it is conceivable that MRAM is adversely affected by magnetostriction, which was not a problem with DRAM.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of suppressing adverse effects due to magnetostriction in the MRAM and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to the invention of claim 1 includes a substrate, at least one semiconductor element mounted on the substrate, and a plurality of MRAMs mounted on the substrate and connected to the semiconductor elements. The plurality of MRAMs are arranged at positions in the peripheral region of the semiconductor element that do not overlap with the extension of the diagonal line in the planar shape of the semiconductor element.

The top view of the semiconductor device concerning a 1st embodiment of the present invention. 1 is a side sectional view of the semiconductor device taken along the line AA in FIG. Side view of interposer substrate Side sectional view showing manufacturing process of semiconductor device Side sectional view showing manufacturing process of semiconductor device Side sectional view showing manufacturing process of semiconductor device Side sectional view showing manufacturing process of semiconductor device Side sectional view showing manufacturing process of semiconductor device Side sectional view showing manufacturing process of semiconductor device Conceptual diagram of board warpage The top view of the semiconductor device concerning a modification The top view of the semiconductor device concerning a modification Side sectional view of a semiconductor device according to a modified example The top view of the semiconductor device concerning a modification

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The semiconductor device 10 according to the present embodiment is used as a motherboard for a server, a notebook computer, an in-vehicle device, a mobile phone, a smartphone, and the like, for example. Micro-processing unit) 50, MRAM 55, and other various electronic components 60 are mounted.

  As shown in FIG. 1, in the semiconductor device 10 of the present embodiment, one MPU 50 is disposed on the F surface 30 </ b> F that is the surface on the front side of the substrate 30. Four MRAMs 55 are arranged around the MPU 50. The MRAM 55 and the MPU 50 are electrically connected via a via conductor 23D and a first conductor layer 22 (see FIG. 2), which will be described later. Note that the planar shape of the MRAM 55 is smaller than the planar shape of the MPU 50.

  FIG. 2 shows an enlarged cross-sectional structure of the semiconductor device 10 cut at a portion where the MPU 50 and the MRAM 55 are arranged. As shown in the figure, the substrate 30 in the semiconductor device 10 has a structure having build-up layers 20 on both the front and back surfaces of the core substrate 11. The core substrate 11 is made of an insulating member. Conductor circuit layers 12 are respectively formed on an F surface 11 </ b> F that is a surface on the front side of the core substrate 11 and an S surface 11 </ b> S that is a surface on the back side of the core substrate 11. The core substrate 11 has a plurality of conductive through holes 14 formed therein. A plurality of through-hole conductive conductors 15 are formed in each conductive through-hole 14 to form a plurality of through-hole conductive conductors 15. The through-hole conductive conductors 15 form the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the S surface 11S. Is connected.

  Both the build-up layer 20 on the F surface 11F side of the core substrate 11 and the build-up layer 20 on the S surface 11S side, in order from the core substrate 11 side, the first insulating resin layer 21, the first conductor layer 22, the second An insulating resin layer 23 and a second conductor layer 24 are laminated, and a solder resist layer 25 is laminated on the second conductor layer 24.

  A plurality of via holes 21H and 23H are formed in the first insulating resin layer 21 and the second insulating resin layer 23, respectively. The via holes 21H and 23H are filled with plating to form a plurality of via conductors 21D and 23D. The conductor circuit layer 12 and the first conductor layer 22 are connected by the via conductor 21D of the first insulating resin layer 21, and the first conductor layer 22 and the first conductor layer 22 are connected by the via conductor 23D of the second insulating resin layer 23. The two conductor layers 24 are connected.

  The first conductor layer 22 on the F surface 11F side of the core substrate 11 is thicker than the first conductor layer 22 on the S surface 11S side. Thereby, the total volume of the conductor layer on the F surface 11F side of the core substrate 11 in the substrate 30 is larger than the total volume of the conductor layer on the S surface 11S side.

  A plurality of pad holes are formed in the solder resist layer 25, and a part of the second conductor layer 24 is located in the pad hole to form a pad 26. As shown in the figure, solder bumps 27 are respectively formed on a plurality of pads 26 on the F surface 30F side of the substrate 30, and the MPU 50 and the MRAM 55 are soldered to the solder bumps 27 group.

  The MPU 50 is directly mounted on the substrate 30, whereas the MRAM 55 is mounted on the substrate 30 via the interposer substrate 53 (hereinafter, a combination of the MRAM 55 and the interposer substrate 53 is referred to as “MRAM composite Body 56 "). As shown in FIG. 3, the interposer substrate 53 has substantially the same planar shape as the MRAM 55, and includes the build-up layers 53 </ b> B on the front and back surfaces of the core substrate 53 </ b> C, like the substrate 30. The core substrate 53C is thicker than the buildup layer 53B.

  The core substrate 53C of the interposer substrate 53 and the insulating resin layer of the buildup layer 53B are preferably as low in thermal expansion coefficient. For example, the thermal expansion coefficient of the core substrate 53C is 1 to 5 ppm / ° C., and the buildup layer 53B The thermal expansion coefficient of the insulating resin layer is 1 to 25 ppm / ° C. Further, the conductor layer of the buildup layer 53B is preferably as thin as possible.

  In addition, solder bumps 54 are formed on the pads 53P on the F surface 53F side of the interposer substrate 53. The solder bump 54 is smaller than the solder bump 27 formed on the substrate 30 and has a high melting point. An MRAM complex 56 is formed by soldering the MRAM 55 to the solder bumps 54 group.

  As shown in FIG. 1, one MRAM complex 56 is mounted in the vicinity of each central portion of the four sides of the MPU 50 in the F surface 30 </ b> F of the substrate 30. That is, the MRAM complex 56 is disposed at a position that does not overlap with the extension line of the diagonal line L of the MPU 50 on the F surface 30F of the substrate 30. Further, the mounting position of the MRAM composite 56 is a position that does not overlap with the diagonal line of the substrate 30. A region that is concentric with the MPU 50 and has a similar shape to the MPU 50 and includes four MRAM complexes 56 inside corresponds to the peripheral region S of the present invention.

  Next, a method for manufacturing the semiconductor device 10 of this embodiment will be described. First, the substrate 30 is manufactured as follows.

  (1) As shown in FIG. 4A, copper foil 11C is formed on both front and back surfaces of an insulating base material 11K made of epoxy resin or BT (bismaleimide triazine) resin and a reinforcing material such as glass cloth as a core substrate 11. Is prepared.

  (2) As shown in FIG. 4B, the core substrate 11 is irradiated with, for example, CO2 laser from the F surface 11F side to form a tapered hole 14A for forming the conductive through hole 14.

  (3) As shown in FIG. 4C, the taper hole 14A is drilled by irradiating the CO2 laser to the position directly behind the tapered hole 14A on the F surface 11F side of the S surface 11S of the core substrate 11 described above. The conductive through-hole 14 is formed from the tapered holes 14A and 14A.

  (4) An electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 11 </ b> C and the inner surface of the conductive through hole 14.

  (5) As shown in FIG. 4D, a predetermined pattern of plating resist 33 is formed on the electroless plating film on the copper foil 11C.

  (6) An electrolytic plating process is performed, and as shown in FIG. 5A, the electrolytic plating is filled in the conductive through holes 14 to form the through-hole conductive conductors 15 and the copper foil 11C on the copper foil 11C. An electrolytic plating film 34 is formed on a portion of the electrolytic plating film (not shown) exposed from the plating resist 33.

  (7) The plating resist 33 is peeled off, and the electroless plating film (not shown) and the copper foil 11C below the plating resist 33 are removed. As shown in FIG. The conductor circuit layer 12 is formed on the F surface 11F of the core substrate 11 and the conductor circuit layer 12 is formed on the S surface 11S of the core substrate 11 by the film 34, the electroless plating film, and the copper foil 11C. Then, the conductor circuit layer 12 on the F surface 11F and the conductor circuit layer 12 on the S surface 11S are connected by the through-hole conductive conductor 15.

  (8) As shown in FIG. 6A, a prepreg (a B-stage resin formed by impregnating a core material with a resin on the conductor circuit layer 12 on the F surface 11F of the core substrate 11) Sheet) and the copper foil 37 are laminated and then heated and pressed. At that time, the space between the conductor circuit layers 12 and 12 on the F surface 11F of the core substrate 11 is filled with the prepreg.

  (9) As shown in FIG. 6B, the prepreg as the first insulating resin layer 21 and the copper foil 37 are laminated on the conductor circuit layer 12 on the S surface 11S of the core substrate 11, and then heated and pressed. The At that time, the space between the conductor circuit layers 12 on the S surface 11S of the core substrate 11 is filled with the prepreg.

  A resin film that does not include a core material may be used as the first insulating resin layer 21 instead of the prepreg. In that case, a conductor circuit layer can be directly formed on the surface of the resin film by a semi-additive method without laminating a copper foil.

  (10) As shown in FIG. 7A, the first insulating resin layers 21 and 21 on both sides of the core substrate 11 formed by the prepreg described above are irradiated with CO2 laser to form a plurality of via holes 21H. Is done. The plurality of via holes 21 </ b> H are disposed on the conductor circuit layer 12.

  (11) An electroless plating process is performed, and electroless plating films (not shown) are formed on the first insulating resin layers 21 and 21 and in the via holes 21H and 21H.

  (12) As shown in FIG. 7B, a predetermined pattern of plating resist 40 is formed on the electroless plating film on the copper foil 37.

  (13) Electrolytic plating treatment is performed, and as shown in FIG. 7C, the plating is filled in the via holes 21H and 21H to form via conductors 21D and 21D, and further, the first insulating resin layer 21 and Electrolytic plating films 39 and 39 are formed on portions of the electroless plating film (not shown) 21 that are exposed from the plating resist 40.

  At this time, the current supplied to the electroless plating film on the F surface 11F side of the core substrate 11 immersed in the electrolytic copper plating solution is larger than the current supplied to the electroless plating film on the S surface 11S side. Yes. As a result, the electrolytic plating film 39 on the F surface 11F side becomes thicker than the electrolytic plating film 39 on the S surface 11S side.

  (14) The plating resist 40 is peeled off, and the electroless plating film (not shown) and the copper foil 37 below the plating resist 40 are removed. As shown in FIG. The first conductor layer 22 is formed on the first insulating resin layers 21 on the front and back of the core substrate 11 by the film 39, the electroless plating film, and the copper foil 37. And a part of each 1st conductor layer 22 of the front and back of the core board | substrate 11 and the conductor circuit layer 12 are connected by the via conductor 21D.

  (15) Through the same processing as the above (8) to (14), as shown in FIG. 8B, the second insulating resin layer 23 and the second insulating resin layer 23 are formed on the first conductor layers 22 on the front and back of the core substrate 11. The two conductor layers 24 are formed, and a part of each second conductor layer 24 and the first conductor layer 22 are connected by the via conductor 23D. In the present embodiment, in the electroplating process when forming the second conductor layer 24, the current applied to the electroless plating film on the F surface 11F side and the electroless plating film on the S surface 11S side are supplied. By making the current the same, the second conductor layer 24 on the F surface 11F side and the second conductor layer 24 on the S surface 11S side have the same thickness.

  (16) As shown in FIG. 8C, solder resist layers 25, 25 are laminated on the second conductor layers 24 on the front and back sides of the core substrate 11.

  (17) As shown in FIG. 9A, tapered pad holes are formed at predetermined locations on the front and back solder resist layers 25, 25 of the core substrate 11, and the second conductor layers on the front and back of the core substrate 11 are formed. A portion exposed from the pad hole in 24 becomes the pad 26.

  (18) On the pad 26, a nickel layer, a palladium layer, and a gold layer are laminated in this order to form the metal film 41 shown in FIG. 9B. Thus, the substrate 30 is completed. The metal film formed on the pad 26 may be a Ni / Au film, a Sn film, or an OSP (Organic Solderability Preservative) film.

Next, the MPU 50 and the MRAM 55 are mounted on the substrate 30 as follows.
(1) An MPU 50 and an MRAM complex 56 are prepared. The MRAM complex 56 is manufactured in advance by soldering the MRAM 55 to the F surface 53F of the interposer substrate 53 manufactured by the same method as the substrate 30.

  (2) Solder bumps 27 are formed on the pads 26 of the substrate 30.

  (3) The MPU 50 and the MRAM composite 56 are disposed on the solder bump 27 group of the substrate 30.

  (4) The substrate 30 is heated in a furnace (hereinafter referred to as “reflow” as appropriate), and then cooled. Thus, the semiconductor device 10 is completed.

  By the way, when the reflow and cooling of the substrate 30 are performed, the peripheral region S of the MPU 50 in the substrate 30 may be warped in a hill shape that rises around the MPU 50 as shown in the conceptual diagram of FIG.

  This warpage of the substrate 30 is considered to occur as follows. That is, the conductor included in the substrate 30 is thermally expanded by heating the substrate 30 and is contracted by cooling the substrate 30. At this time, since the contraction of the conductor on the F surface 30F side of the substrate 30 is inhibited by the MPU 50 mounted on the F surface 30F, the contraction amount of the conductor on the S surface 30S side is larger than the contraction amount of the conductor on the F surface 30F side. growing. Due to the difference in contraction amount of the conductor, it is considered that the peripheral region S of the MPU 50 in the substrate 30 has a hill shape protruding toward the F surface 30F side.

  Further, in the substrate 30 after reflow and cooling, as shown in FIG. 10, the lateral regions of the respective sides of the MPU 50 become comparatively gentle, whereas the extension line of the diagonal line L of the MPU 50 is relatively large. It is thought.

  Here, if the MRAM 55 is disposed on the extension line of the diagonal line L of the MPU 50, the MRAM 55 is deformed by the warp of the substrate 30 and a magnetic distortion is generated in the MRAM 55, and the MRAM 55 is adversely affected by the magnetic distortion. Conceivable. On the other hand, in the semiconductor device 10 of the present embodiment, the MRAM 55 is disposed in a position that does not overlap with the extension line of the diagonal line L of the MPU 50 in the peripheral region S of the MPU 50, so that the MRAM 55 is affected by the warp of the substrate 30. Can be suppressed, and adverse effects due to magnetostriction in the MRAM 55 can be suppressed.

  In the present embodiment, as described above, the total volume of the conductor layer on the F surface 30F side of the substrate 30 is larger than the total volume of the conductor layer on the S surface 30S side. The amount of contraction of the conductor can be brought close to the amount of contraction of the conductor on the S surface 30S side, and the substrate 30 can be mitigated from warping in a hill shape. Also by this, it can suppress that MRAM55 receives the influence of the curvature of the board | substrate 30, and the bad influence by the magnetic distortion in MRAM55 can be suppressed. Further, since the total volume of the conductor layer on the F plane 30F side and the total volume of the conductor layer on the S plane 30S side are adjusted by the thickness of the first conductor layer 22, the circuit pattern need not be changed. .

  Furthermore, since the MRAM 55 is mounted on the substrate 30 via the interposer substrate 53, it is possible to further suppress the MRAM 55 from being affected by the warp of the substrate 30. Further, since the interposer substrate 53 has the core substrate 53C that is thicker than the buildup layer 53B, the deformation of the MRAM 55 can be further suppressed. Note that the lower the thermal expansion coefficients of the core substrate 53C of the interposer substrate 53 and the insulating resin layer of the buildup layer 53B, the higher the rigidity of the interposer substrate 53 and the MRAM 55 is prevented from being affected by the warp of the substrate 30. be able to. Further, the thinner the conductor layer of the buildup layer 53B of the interposer substrate 53, the more the expansion and contraction of the interposer substrate 53 can be prevented, and the rigidity of the interposer substrate 53 becomes higher, and the MRAM 55 is affected by the warp of the substrate 30. This can be suppressed.

  Further, as one method for making the MRAM 55 less susceptible to the warp of the substrate 30, it is conceivable to perform reflow separately such as soldering the MRAM complex 56 after soldering the MPU 50. In the semiconductor device 10 of the embodiment, as described above, the MRAM 55 is arranged at a position that is not easily affected by the warp of the substrate 30, so that the soldering of the MPU 50 and the soldering of the MRAM complex 56 are performed by one reflow. Can do. Thereby, the number of steps can be reduced as compared with the case of reflowing separately. In addition, when reflowing separately, it is necessary to use different soldering points for the MPU 50 mounting solder and the MRAM composite 56 mounting solder. Can also reduce costs.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various other than the following can be made without departing from the scope of the invention. It can be changed and implemented.

  (1) In the above embodiment, the MPU 50 and the MRAM complex 56 are soldered by one reflow. However, after the MPU 50 is mounted and reflowed, the MRAM complex 56 is mounted and reflowed. There may be. In this case, since the MRAM 55 can be mounted in accordance with the warp of the substrate 30 after the MPU 50 is soldered, it is possible to further suppress the MRAM 55 from being affected by the warp of the substrate 30. In this case, the melting point of the solder for mounting the MPU 50 is higher than the melting point of the solder for mounting the MRAM composite 56.

  (2) In the above embodiment, in order to make the total volume of the conductor layer on the F surface 30F side of the substrate 30 different from the total volume of the conductor layer on the S surface 30S side, the F surface 30F side and the S surface 30S side are different. Although the thickness of the conductor layer was varied, the thickness of the conductor layer was made equal, and the remaining copper ratio (that is, the area of the circuit pattern (corresponding to the “conductor occupation area” of the present invention) / total area) was varied. The structure to be able to be used may be sufficient. Moreover, the structure which makes both the thickness of a conductor layer and the remaining copper ratios different may be sufficient.

  (3) In the above embodiment, the portion of the core substrate 11 where the total volume of the conductor layer on the F surface 11F side is larger than the total volume of the conductor layer on the S surface 11S side is the entire substrate 30. Only the peripheral region S of the MPU 50 in the substrate 30 may be used. In this case, for example, in the peripheral region S of the MPU 50 in the substrate 30, the remaining copper ratio on the F surface 30F side may be made larger than the remaining copper ratio on the S surface 30S side.

  (4) In the above embodiment, the conductor layer having a different thickness on the F surface 30F side and the S surface 30S side of the substrate 30 is the first conductor layer 22, but may be the second conductor layer 24. In addition, the thickness may be different between both the first conductor layer 22 and the second conductor layer 24. Furthermore, the thickness of the conductor circuit layer 12 may be varied.

  (5) In the above embodiment, the interposer substrate 53 has the core substrate 53C, but the interposer substrate 53 may have a coreless structure.

  (6) In the above-described embodiment, the MRAM 55 is mounted on the substrate 30 via the interposer substrate 53. However, the MRAM 55 may be directly mounted without using the interposer substrate 53.

  (7) In the above embodiment, the interposer substrate 53 and the MRAM 55 are pre-soldered before being mounted on the substrate 30, but the interposer substrate 53 and the substrate 30 are soldered simultaneously with the interposer substrate 53. A configuration may be employed in which the MRAM 55 is soldered.

  (8) In the above embodiment, the planar shape of the interposer substrate 53 is substantially the same as the planar shape of the MRAM 55, but it may be larger than the planar shape of the MRAM 55.

  (9) In the above embodiment, the MRAM 55 is disposed at a position that does not overlap the diagonal line of the substrate 30, but may be disposed on the diagonal line of the substrate 30 as shown in FIG. 11.

  (10) In the above embodiment, the MPU 50 is disposed at a position shifted from the center of the substrate 30, but may be disposed at the center of the substrate 30 as shown in FIG. 12.

  (11) In the above embodiment, the MPU 50 and the MRAM 55 are disposed on the same surface of the substrate 30. For example, the MPU 50 is disposed on the F surface 30F, and the MRAM 55 is disposed on the S surface 30S. Also good. At this time, as shown in FIG. 13, the MRAM 55 may be arranged at a position facing the MPU 50 across the substrate 30.

  (12) The planar shape of the MPU 50 and the MRAM 55 may be a square.

  (13) Although the number of MRAMs 55 connected to the MPU 50 is four in the above embodiment, the number may be other numbers (for example, eight as shown in FIG. 14).

  (14) In the above embodiment, the “semiconductor element” of the present invention is the MPU 50. However, for example, a CPU or a power semiconductor element may be used.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Core board | substrate 21 1st insulating resin layer 22 1st conductor layer 23 2nd insulating resin layer 24 2nd conductor layer 27 Solder bump 30 Board | substrate 53 Interposer board 53B Buildup layer 53C Core board | substrate 54 Solder bump 50 MPU (semiconductor) element)
55 MRAM

Claims (19)

A substrate,
A plurality of MRAMs mounted on the substrate;
At least one semiconductor element mounted on the substrate and connected to the MRAM,
The plurality of MRAMs are arranged at positions that do not overlap with an extension of a diagonal line in a planar shape of the semiconductor element in a peripheral region of the semiconductor element. The semiconductor device according to claim 1,
All of the semiconductor element and the plurality of MRAMs are disposed on one surface of the substrate. The semiconductor device according to claim 1 or 2,
The substrate comprises a core substrate and respective build-up layers laminated on the front and back of the core substrate,
The total volume of the conductor layer formed in the one build-up layer on which the semiconductor element is mounted is larger than the total volume of the conductor layer formed in the other build-up layer. The semiconductor device according to claim 1 or 2,
The substrate comprises a core substrate and respective build-up layers laminated on the front and back of the core substrate,
In the peripheral region of the semiconductor element, the total volume of the conductor layer formed on the one build-up layer on which the semiconductor element is mounted is equal to the conductor layer formed on the other build-up layer. Greater than total volume. The semiconductor device according to claim 3 or 4, wherein
The conductor layer formed on the one-side buildup layer is thicker than the conductor layer formed on the other-side buildup layer. A semiconductor device according to any one of claims 3 to 5,
The conductor occupation area of the conductor layer formed in the one side buildup layer is larger than the conductor occupation area of the conductor layer formed in the other side buildup layer. A semiconductor device according to any one of claims 3 to 5,
In the peripheral region of the semiconductor element, the conductor occupation area of the conductor layer formed in the one side buildup layer is larger than the conductor occupation area of the conductor layer formed in the other side buildup layer. A semiconductor device according to any one of claims 1 to 7,
The MRAM is mounted on the substrate via an interposer substrate. The semiconductor device according to claim 8,
The interposer substrate includes a core substrate and a build-up layer that is laminated on each of the front and back surfaces of the core substrate and has a thickness smaller than that of the core substrate. The semiconductor device according to claim 9,
The thermal expansion coefficient of the core substrate of the interposer substrate is 1 to 5 ppm / ° C.
The interlayer insulating layer formed in the buildup layer of the interposer substrate has a thermal expansion coefficient of 1 to 25 ppm / ° C. A semiconductor device according to any one of claims 1 to 10,
The plurality of MRAMs are arranged at positions that do not overlap diagonal lines in the planar shape of the substrate. A semiconductor device according to any one of claims 1 to 11,
The melting point of solder that solder-connects the semiconductor element and the substrate is higher than the melting point of solder that solder-connects the MRAM and the substrate. A method for manufacturing a semiconductor device, comprising: a substrate; a plurality of MRAMs mounted on the substrate; and at least one semiconductor element mounted on the substrate and connected to the MRAM,
The plurality of MRAMs are arranged at positions that do not overlap with an extension of a diagonal line in a planar shape of the semiconductor element in a peripheral region of the semiconductor element. A method of manufacturing a semiconductor device according to claim 13,
Forming a core substrate having through-hole conductors;
Forming build-up layers on the front and back of the core substrate,
The total volume of the conductor layer formed in the one build-up layer on which the semiconductor element is mounted is made larger than the total volume of the conductor layer formed in the other build-up layer. 15. A method of manufacturing a semiconductor device according to claim 14,
Laminating an electroless plating layer on an insulating layer formed on each of the one side buildup layer and the other side buildup layer;
The core substrate is immersed in a plating solution, and the current applied to the electroless plating layer of the one side buildup layer is set larger than the current supplied to the electroless plating layer of the other side buildup layer. Then, an electroplating layer is laminated on each electroless plating layer. A method of manufacturing a semiconductor device according to claim 14 or 15,
The conductor occupation area of the conductor layer formed in the one side buildup layer is made larger than the conductor occupation area of the conductor layer formed in the other side buildup layer. A method of manufacturing a semiconductor device according to any one of claims 13 to 16,
The MRAM is mounted on the substrate via an interposer substrate. A method of manufacturing a semiconductor device according to claim 17,
The interposer substrate is manufactured by laminating a buildup layer including an interlayer insulating layer having a thermal expansion coefficient of 1 to 25 ppm / ° C. on both sides of the core substrate having a thermal expansion coefficient of 1 to 5 ppm / ° C. A method of manufacturing a semiconductor device according to any one of claims 13 to 18,
After the semiconductor element is solder mounted on the substrate, the MRAM is solder mounted on the substrate.

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