JP7073602B2 - Printed circuit board - Google Patents

Description

The present invention relates to a printed circuit board (PRINTED CIRCUIT BOARD).

In the process of manufacturing a PCB, warpage may occur due to the PCB undergoing a heat treatment step. As electronic products become smaller and thinner, PCBs are becoming thinner, and as the thinning progresses, the defect rate due to warpage becomes a problem. There are various causes of warpage, such as a difference in the coefficient of thermal expansion (CTE) and a difference in the elastic modulus between the resin insulating material and the metal circuit. In order to control warpage, techniques for adjusting insulating materials such as development of low swelling resin and adjustment of inorganic filler content have been developed. On the other hand, in addition to the technique of adjusting the insulating material in order to reduce the warp, a technique of adding a warp prevention structure to the printed circuit board and adjusting the design of the circuit has also been developed.

Korean Publication No. 2016-0080433 Gazette

According to one aspect of the present invention, an insulating material having one surface and another surface facing each other, a circuit layer formed on the one surface and the other surface of the insulating material, and a metal layer formed on the circuit layer. , The electric conductivity of the metal layer is smaller than the electric conductivity of the circuit layer, and the thickness of the metal layer located on one side of the insulating material is the other side of the insulating material. Provided is a printed circuit board that is larger than the thickness of the metal layer located in.

According to one aspect of the present invention, an insulating material having one surface and another surface facing each other, one or more first insulating layers laminated on the one surface of the insulating material, and the other surface of the insulating material. One or more second insulating layers laminated on top, a first circuit layer formed on at least one of the one or more first insulating layers, and one or more second insulating layers. A second circuit layer formed on at least one of the insulating layers, a first metal layer formed on the first circuit layer, and a second metal formed on the second circuit layer. The electric conductivity of the first metal layer including the layer is smaller than the electric conductivity of the first circuit layer, and the electric conductivity of the second metal layer is the electric conductivity of the second circuit layer. A printed circuit board is provided in which the thickness of the first metal layer is smaller than that of the second metal layer and the thickness of the first metal layer is larger than the thickness of the second metal layer.

According to one aspect of the present invention, an insulating material, a circuit layer formed on the insulating material, and a metal layer formed on the circuit layer and having an electric conductivity smaller than that of the circuit layer. Provided is a printed circuit board including an insulating layer laminated on the insulating material, a via hole penetrating the insulating layer and the metal layer, and the circuit layer is exposed from the bottom surface of the via hole.

It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows the manufacturing method of the printed circuit board which concerns on embodiment of this invention. It is a figure which shows various circuit layers by a circuit formation method. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. It is a partially enlarged view of FIG. 24. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. FIG. 26 is a partially enlarged view. It is sectional drawing of the printed circuit board which concerns on embodiment of this invention. FIG. 28 is a partially enlarged view.

The terms used in this application are used solely to illustrate specific embodiments and are not intended to limit the invention. A singular expression contains multiple expressions unless explicitly expressed in a sentence.

In the present application, when a component is referred to as "contains" a component, this does not exclude other components unless otherwise stated, but may further include other components. means.

Also, throughout the specification, "above" means to be above or below the target portion, not necessarily above it with respect to the direction of gravity.

Further, "bonding" does not mean only the case where each component is in direct physical contact with each other in the contact relationship between the components, and other components are interposed between the components. , Used as a comprehensive concept up to the case where each component is in contact with other components.

The first, second, and the like terms are used to explain various components, and the above components are not limited by the above terms. The above terms are used only for the purpose of distinguishing one component from the other.

The sizes and thicknesses of the configurations shown in the drawings are arbitrary for convenience of explanation, and the present invention is not necessarily limited thereto.

In explaining the embodiment of the printed circuit board according to the present invention in detail with reference to the attached drawings and explaining with reference to the attached drawings, the same or corresponding components are designated by the same drawing reference numerals. Duplicate explanation is omitted.

In addition, each embodiment of the present invention described below must be understood not necessarily as a concept showing only one embodiment but as a concept including examples subordinate to each embodiment.

1 to 9 show cross-sectional views of printed circuit boards according to various embodiments.

Referring to FIG. 1, the printed circuit board according to the embodiment of the present invention includes an insulating material 110, a circuit layer 120, and a metal layer 130, and the electric conductivity of the metal layer 130 is the same as that of the circuit layer 120. The thickness of the metal layer 131, which is smaller than the electric conductivity and is located on the one side of the insulating material 110, can be larger than the thickness of the metal layer 132 located on the other side of the insulating material 110.

The insulating material 110 is a material composed of an insulating substance such as a resin, and has a thin plate shape. Both sides facing each other except the side surface of the insulating material 110 are referred to as one side and the other side. That is, the insulating material 110 can be provided with one side and the other side.

As the resin of the insulating material 110, various materials such as a thermosetting resin and a thermoplastic resin can be used, and specifically, an epoxy resin, a polyimide or the like can be used. Here, the epoxy resin includes, for example, naphthalene-based epoxy resin, bisphenol A-type epoxy resin, bisphenol F-type epoxy resin, novolak-based epoxy resin, cresol novolak-based epoxy resin, rubber-modified epoxy resin, and ring-type aliphatic epoxy. There are, but are not limited to, resins, silicon-based epoxy resins, nitrogen-based epoxy resins, phosphorus-based epoxy resins, and the like.

The insulating material 110 may be a prepreg (PPG) or a build-up film (build up film). In the case of a prepreg, the resin may contain a fiber reinforcing material such as glass cloth. In the case of a build-up film, the resin may be filled with an inorganic filler such as silica. As this build-up film, ABF (Ajinomoto Build-up Film) or the like can be used.

The insulating material 110 may be a core located in the middle of the printed circuit board, or may be each layer laminated on the core.

The circuit layer 120 is a conductor formed on one surface and the other surface of the insulating material 110 and patterned for transmitting an electric signal. The circuit layer 120 may be understood as a set of a plurality of circuit patterns, and each circuit pattern of the circuit layer 120 is formed with a predetermined width and thickness, and has a length and a direction according to the design of the circuit design. Etc. can be determined.

The circuit layer 120 can be formed of a metal, and in consideration of electrical conduction characteristics, copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), and gold (Au). ), Metals such as platinum (Pt) or alloys thereof.

The circuit layer 120 can include a seed layer S1. The seed layer S1 can be made of the same metal as the circuit layer 120. The existence of the seed layer S1 can be determined by a method for forming the circuit layer 120, and particularly when the circuit layer 120 is formed by a method such as SAP or MSAP, the circuit layer 120 may include the seed layer S1. can.

In FIG. 1, it may be understood that the circuit layer 120 is formed by the SAP method, and here the seed layer S1 is directly formed on one surface and the other surface of the insulating material 110. Unlike this, when the circuit layer 120 is formed by the MSAP method, the seed layer S4 can be located slightly separated from one side and the other side of the insulating material 110 (see (c) in FIG. 21). ). Here, the separation distance between the seed layer S4 and one surface (or the other surface) of the insulating material 110 matches the thickness of the thin metal foil (copper foil) M of the raw material used in MSAP.

Although the invention has been described with reference to FIG. 1, the circuit layer 120 does not necessarily have to be formed by the SAP method, and it does not exclude other methods including MSAP. For example, when the circuit layer 120 is formed by a subtractive method or a tenting method as shown in FIG. 21 (b), the circuit layer 120 may not include a seed layer. Is different from the circuit layer 120 formed by the SAP method of FIG. 21 (a).

The circuit layer 120 can be divided into a first circuit layer 121 formed on one surface of the insulating material 110 and a second circuit layer 122 formed on the other surface of the insulating material 110.

In the circuit layer 120, even if the first circuit layer 121 formed on one surface of the insulating material 110 and the second circuit layer 122 formed on the other surface of the insulating material 110 have substantially the same thickness. Often, for example, the thickness of the first circuit layer 121 and the second circuit layer 122 may be 15 μm.

The metal layer 130 is a layer formed on the circuit layer 120 and made of metal. The metal of the metal layer 130 may be an alloy material, specifically, a Fe—Ni (nickel steel) alloy such as invar, or a copper alloy such as brass of a Cu—Zn alloy. You may.

The metal layer 130 may be formed so as to be in contact with the circuit layer 120, or may be formed so as to match the width of the circuit layer 120. In this case, only the metal layer 130 may be observed in the plan view, and the circuit layer 120 may not be observed. However, the structure is not limited to this shape, and the structure in which the metal layer 130 and the circuit layer 120 do not come into contact with each other will be described later.

The electrical conductivity of the metal layer 130 is smaller than the electrical conductivity of the circuit layer 120. Therefore, the electrical signal can be substantially transmitted to the circuit layer 120.

The thickness of the metal layer 130 can be made thinner than the thickness of the circuit layer 120. The thickness of the metal layer 130 does not exceed two-thirds of the thickness of the coupled circuit layer 120.

Since the electric conductivity of the metal layer 130 is smaller than that of the circuit layer 120, the metal layer 130 is formed thinner than the circuit layer 120, so that effective signal transmission can be achieved. Here, the circuit layer 120 can have a thickness of 15 μm, and the metal layer 130 can have a thickness of 2 to 5 μm.

The metal layer 130 includes a first metal layer 131 formed on the first circuit layer 121 and a second metal layer 132 formed on the second circuit layer 122. That is, the first metal layer 131 is formed on one surface side of the insulating material 110, and the second metal layer 132 is formed on the other surface side of the insulating material 110.

The thickness of the metal layer 131 located on one side of the insulating material 110 can be larger than the thickness of the metal layer 132 located on the other side of the insulating material 110. That is, the thickness of the first metal layer 131 can be formed larger than the thickness of the second metal layer 132.

When the printed circuit board is heat-treated in the manufacturing process, the printed circuit board may be warped. The metal layer 130 can control the warp of the printed circuit board, and in particular, by making the thicknesses of the metal layers 130 formed on both sides of the insulating material 110 different from each other, in the printed circuit board. Warpage can be effectively controlled.

For example, when the printed circuit board warps downward (when viewed from the side), the metal layer 130 on the lower surface side of the insulating material 110 can be formed relatively thick to reduce the warp. On the other hand, when the printed circuit board warps upward convexly (crying), the metal layer 130 on the upper surface side of the insulating material 110 can be formed relatively thick to reduce the warp.

The coefficient of thermal expansion of the metal layer 130 can be smaller than the coefficient of thermal expansion of the circuit layer 120, in which case the rigidity of the metal layer 130 can be greater than the rigidity of the circuit layer 120. Alternatively, the coefficient of thermal expansion of the metal layer 130 can be greater than the coefficient of thermal expansion of the circuit layer 120, in which case the rigidity of the metal layer 130 can be less than the rigidity of the circuit layer 120.

Here, the rigidity means the deformation rate with respect to an external force, and can be simply seen as the deformation rate when an axial force (normal stress) is applied. This rigidity varies depending on the elastic modulus (modulus of elasticity) or Young's modulus (Young's modulus), and it can be understood that the larger the elastic modulus or Young's modulus is, the higher the rigidity is.

Assuming that the coefficient of thermal expansion of the metal layer 130 is smaller than the coefficient of thermal expansion of the circuit layer 120 and the rigidity of the metal layer 130 is larger than the rigidity of the circuit layer 120, the circuit layer 120 is formed of copper and the metal layer 130 is formed of Invar. An example is given. Further, assuming that the coefficient of thermal expansion of the metal layer 130 is larger than the coefficient of thermal expansion of the circuit layer 120 and the rigidity of the metal layer 130 is smaller than the rigidity of the circuit layer 120, the circuit layer 120 is formed of copper and the metal layer 130 is formed of brass. An example is given.

In either case, the coefficient of thermal expansion of the metal layer 130 is smaller than the coefficient of thermal expansion of the resin of the insulating material 110, and the rigidity of the metal layer 130 is larger than the rigidity of the resin of the insulating material 110. The warp of the printed circuit board can be controlled by adjusting the difference in thickness between the metal layers 131 and 132, that is, the difference in thickness between the first metal layer 131 and the second metal layer 132.

On the other hand, the difference in thickness between the first metal layer 131 and the second metal layer 132 is the difference in wiring density on both sides of the insulating material 110, that is, the difference between the first circuit layer 121 and the second circuit layer 122. It can be determined by the difference in wiring density. The wiring density of the circuit layer 120 is determined from the volume of the circuit layer 120. That is, the thickness of the metal layer 130 can be set in consideration of the volume of the circuit layer 120. Here, the volume of the circuit layer 120 means the total volume of the plurality of circuit patterns constituting the circuit layer 120.

For example, when the volume of the first circuit layer 121 located on one side of the insulating material 110 is smaller than the volume of the second circuit layer 122 located on the other side of the insulating material 110, it is located on the one side of the insulating material 110. The thickness of the first metal layer 131 can be larger than the thickness of the second metal layer 132 located on the other side of the insulating material 110.

Specifically, when the volume of the circuit layer 120 located on the upper surface of the insulating material 110 is small and the volume of the circuit layer 120 located on the lower surface of the insulating material 110 is large, the thermal expansion coefficient is relative to the upper surface of the insulating material 110. Since the upper surface of the insulating material 110 is relatively small in terms of rigidity, an upward convex warp may occur during heat treatment of the printed circuit board, and the metal layer 130 located on the upper surface of the insulating material 110 may occur. By making the thickness of the metal layer 130 larger than the thickness of the metal layer 130 located on the lower surface of the insulating material 110, it is possible to control the warp of the printed circuit board by balancing the thermal expansion rate and the rigidity of the upper and lower surfaces of the insulating material 110. can.

On the other hand, when the volume of the circuit layer 120 located on the upper surface of the insulating material 110 is large and the volume of the circuit layer 120 located on the lower surface of the insulating material 110 is small, the thermal expansion coefficient is relative to the lower surface of the insulating material 110. Since the lower surface of the insulating material 110 is relatively small in terms of rigidity, a convex warp may occur downward during heat treatment of the printed circuit board, and the metal layer 130 located on the lower surface of the insulating material 110 may occur. By making the thickness of the metal layer 130 larger than the thickness of the metal layer 130 located on the upper surface of the insulating material 110, it is possible to control the warp of the printed circuit board by balancing the thermal expansion rate and the rigidity of the upper and lower surfaces of the insulating material 110. can.

That is, since the metal layer 130 has a smaller electric conductivity and thickness than the circuit layer 120, it does not substantially participate in the transmission of electric signals by the circuit layer 120, and the metal layer 131 on both sides of the insulating material 110. , 132 can function to control the warp of the printed circuit board by the difference in thickness.

Referring to FIG. 2, the printed circuit board according to the embodiment of the present invention can include a through via 140.

The penetrating via 140 includes a first circuit layer 121 formed through the inside of the insulating material 110 and formed on one surface of the insulating material 110, and a second circuit layer 122 formed on the other surface of the insulating material 110. To connect.

The penetrating via 140 can be formed by forming a conductive layer inside the penetrating via hole 141 penetrating the inside of the insulating material 110. Here, the conductive layer may include a plating layer, a conductive paste, a conductive ink, and the like.

On the other hand, the penetrating via 140 and the circuit layer 120 can include the seed layer S1, and the seed layer S1 can be formed on the inner wall of the penetrating via hole 141 and one surface and the other surface of the insulating material 110. In this case, the conductive layer of the penetrating via 140 can include a seed layer S1 formed by electroless plating and an electrolytic plating layer formed by electrolytic plating.

Referring to FIG. 3, the printed circuit board according to the embodiment of the present invention can include a through via 140 and an alloy layer 150.

The penetrating via 140 is formed by penetrating the inside of the insulating material 110, and is formed on one surface of the insulating material 110 and the first circuit layer 121 and the second circuit layer 122 formed on the other surface of the insulating material 110. To connect with.

The penetrating via 140 can be formed by forming a conductive layer inside the penetrating via hole 141 penetrating the inside of the insulating material 110.

The alloy layer 150 can be formed between the insulating material 110 and the penetrating via 140, and between the insulating material 110 and the circuit layer 120. The alloy layer 150 can be made of the same metal as the metal layer 130.

As shown in FIG. 3, the alloy layer 150 can include a seed layer S2. The seed layer S2 can be made of the same metal as the alloy layer 150. The seed layer S2 can be formed on the inner wall of the through via hole 141 and one surface and the other surface of the insulating material 110. In this case, the conductive layer can be a plating layer, particularly a plating layer formed by electrolytic plating. Further, in this case, the width of the penetrating via 140 is narrower than the width of the penetrating via hole 141.

Referring to FIG. 4, in the alloy layer 150 described with reference to FIG. 3, the thickness of the first alloy layer 151 located on one surface of the insulating material 110 is the thickness of the second alloy layer located on the other surface of the insulating material 110. It can be larger than the thickness of 152. The thickness of the inner wall of the through via hole 141, that is, the third alloy layer 153 formed between the insulating material 110 and the through via 140 is the same as or the thickness of the first alloy layer 151 and / or the second alloy layer 152. It may be different, but in order to secure the width of the penetrating via 140, it must be not too thick and can be thinner than the thickness of the second alloy layer 152.

Referring to FIG. 5, the printed circuit board according to the embodiment of the present invention can include a solder resist layer 170.

The solder resist layer 170 is laminated on the metal layer 130 and can be formed of a photosensitive insulating material. An opening O is formed in the solder resist layer 170, and the circuit layer 120 can be exposed from the opening O. The exposed area of the circuit layer 120 becomes a wire bonding pad or solder ball pad for connecting electronic components. In order to expose the circuit layer 120 from the opening O of the solder resist layer 170, the metal layer 130 may not be formed in the region of the opening O. Since the electrical conductivity of the metal layer 130 is smaller than the electrical conductivity of the circuit layer 120, it is advantageous from the aspect of electrical signal transmission that the padded region is part of the circuit layer 120 rather than the metal layer 130. be.

Referring to FIG. 6, the printed circuit board according to the embodiment of the present invention may further include the surface treatment layer 171 in the printed circuit board described with reference to FIG.

The surface treatment layer 171 is formed on the region of the circuit layer 120 exposed from the opening O of the solder resist layer 170, and can prevent the circuit layer 120 from being oxidized. The surface treatment layer 171 can be made of metal. The surface treatment layer 171 of the metal material can be formed by electroless plating. Further, the surface treatment layer 171 may be composed of a plurality of layers. For example, the surface treatment layer 171 can be formed of gold. Further, the surface treatment layer 171'can be formed of a plurality of layers of a nickel layer and a gold layer. In this case, by forming the circuit layer (copper layer) -nickel layer-gold layer in this order, the nickel layer can be prevented from diffusing between the copper layer and the gold layer. On the other hand, the surface treatment layer 171 can also be formed of a non-metal such as OSP.

Referring to FIG. 7, the printed circuit board according to the embodiment of the present invention can include the build-up layer 160. The build-up layer 160 can include insulating layers 161 and 162, build-up circuit layers 163 and 164, vias 165, and build-up metal layers 167 and 168. In FIG. 7, one build-up layer 160 is formed on each side, and the printed circuit board is shown as four layers (based on the number of circuit layers). A plurality of printed circuit boards can be formed, and the printed circuit board can have various circuit layers such as 4 layers, 6 layers, 8 layers, and the like.

The insulating layers 161 and 162 are laminated on the metal layer 130, the first insulating layer 161 is laminated on the first metal layer 131, and the second insulating layer 162 is laminated on the second metal layer 132, respectively.

The insulating layers 161 and 162 are composed of an insulating substance such as a resin, and various materials such as a thermosetting resin and a thermoplastic resin can be used as the resin of the insulating layers 161 and 162. Epoxy resin, polyimide or the like can be used.

The insulating layers 161, 162 may be a prepreg (PPG) or a build-up film (build up film). In the case of a prepreg, the resin may contain a fiber reinforcing material such as glass cloth. In the case of a build-up film, the resin may be filled with an inorganic filler such as silica. As this build-up film, ABF (Ajinomoto Build-up Film) or the like can be used.

The insulating layers 161 and 162 can be formed of the same substance as the insulating material 110, and can also be formed of different substances from each other. For example, the insulating material 110 is a prepreg, and the insulating layers 161 and 162 can be formed of a build-up film.

The build-up circuit layers 163 and 164 are conductors formed on the insulating layers 161, 162 and patterned to transmit electrical signals. Although the build-up circuit layers 163 and 164 are substantially the same as the circuit layer 120 described above in terms of function, the terms build-up circuit layers 163 and 164 have been introduced because they need to be separated for the sake of explanation.

The build-up circuit layers 163 and 164 can be understood as a set of a plurality of circuit patterns. It can be understood that the circuit layer 120 and the build-up circuit layers 163 and 164 have functionally the same configuration, and the above description of the circuit layer 120 can also be applied to the build-up circuit layers 163 and 164. However, the formed positions are different from each other. The circuit layer 120 is a set of circuit patterns formed on the insulating material 110 which is a core, and the build-up circuit layers 163 and 164 are formed on the insulating layers 161 and 162 laminated on the insulating material 110. It is a set of circuit patterns. The thickness of the build-up circuit layers 163 and 164 can be substantially the same as the thickness of the circuit layer 120.

The build-up circuit layers 163 and 164 can be made of metal, but in consideration of electrical conduction characteristics, copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), It can be formed of a metal such as gold (Au), platinum (Pt) or an alloy thereof.

The build-up circuit layers 163 and 164 can include a seed layer S3. The seed layer S3 can be made of the same metal as the build-up circuit layers 163 and 164. The existence of the seed layer S3 is determined by the formation method of the build-up circuit layers 163 and 164, and particularly when the build-up circuit layers 163 and 164 are formed by the construction method of SAP, MSAP, etc., the build-up circuit layers 163 and 164 Can include a seed layer S3.

Although the invention is described with reference to FIG. 7, the build-up circuit layers 163 and 164 do not necessarily have to be formed by the SAP method, nor do they exclude other methods including MSAP.

The build-up circuit layers 163 and 164 can be divided into a first build-up circuit layer 163 formed on one side of the insulating material 110 and a second build-up circuit layer 164 formed on the other side of the insulating material 110. ..

The first build-up circuit layer 163 and the second build-up circuit layer 164 can have substantially the same thickness, for example, the thickness of the first build-up circuit layer 163 and the second build-up circuit layer 164. The sword can be 15 μm.

The via 165 is a conductor that penetrates the insulating layers 161 and 162 to connect the build-up circuit layers 163 and 164 and the circuit layer 120, and transmits an electric signal between circuit patterns in different layers. The via 165 can be made of the same metal as the build-up circuit layers 163, 164 and circuit layer 120.

The metal layer 130 is not formed in the formation region of the via 165 so that the via 165 and the circuit layer 120 are in direct contact with each other. Since the electrical conductivity of the metal layer 130 is smaller than the electrical conductivity of the circuit layer 120, direct contact between the via 165 and the circuit layer 120 is advantageous for transmission of electrical signals.

The via 165 can be formed by forming a conductive layer inside the via hole 166 formed in the insulating layers 161 and 162. Here, the conductive layer can be a plating layer or the like.

The build-up circuit layers 163 and 164 and the vias 165 can include a seed layer S3, which is formed on the inner surface (inner wall and bottom) of the via holes 166 and on the insulating layers 161, 162. be able to. In this case, the conductive layer is a plating layer formed by electrolytic plating, and the via 165 includes a seed layer S3 formed by electroless plating and a plating layer formed by electrolytic plating.

The build-up metal layers 167 and 168 are formed on the build-up circuit layers 163 and 164 and can be formed of the same metal as the metal layer 130. Since the build-up metal layers 167 and 168 have substantially the same functions as the metal layer 130, the above description of the metal layer 130 can be similarly applied to the build-up metal layers 167 and 168.

The thickness of the build-up metal layer 167, 168 located on the one side of the insulating material 110 can be larger than the thickness of the build-up metal layer 167, 168 located on the other side of the insulating material 110. ..

The build-up metal layer formed on the first build-up circuit layer 163 is called the first build-up metal layer 167, and the build-up metal layer formed on the second build-up circuit layer 164 is called the second build-up metal layer. It is called 168, and the thickness of the first build-up metal layer 167 can be larger than the thickness of the second build-up metal layer 168. This makes it possible to control the warp of the printed circuit board.

The thickness of the build-up metal layers 167 and 168 can be determined by the wiring densities of the circuit layers 120 and / or the build-up circuit layers 163 and 164. For example, if the wiring density of the first circuit layer 121 and / or the first build-up circuit layer 163 is smaller than the wiring density of the second circuit layer 122 and / or the second build-up circuit layer 164, the first build-up metal The thickness of the layer 167 can be greater than the thickness of the second build-up metal layer 168.

Referring to FIG. 7, the printed circuit board according to the embodiment of the present invention may further include a solder resist layer 170.

The solder resist layer 170 is laminated on the build-up metal layer 167 and 168 and can be formed of a photosensitive insulating material. An opening O is formed in the solder resist layer 170, and the build-up circuit layers 163 and 164 can be exposed from the opening O. The exposed area of the build-up circuit layers 163 and 164 becomes a pad. Since the build-up circuit layers 163 and 164 are exposed from the opening O of the solder resist layer 170, the build-up metal layers 167 and 168 may not be formed in the region of the opening O. Since the electrical conductivity of the build-up metal layers 167 and 168 is smaller than the electrical conductivity of the build-up circuit layers 163 and 164, the padded area is not the build-up metal layers 167 and 168, but the build-up circuit layer 163, Being part of 164 is advantageous from the aspect of electrical signal transmission.

Referring to FIG. 8, the printed circuit board according to the embodiment of the present invention may further include a surface treatment layer 171 as compared with the printed circuit board described with reference to FIG. 7.

The surface treatment layer 171 is formed on the region of the build-up circuit layers 163 and 164 exposed from the opening O of the solder resist layer 170, and can prevent the build-up circuit layers 163 and 164 from being oxidized. The surface treatment layer 171 can be made of metal. The surface treatment layer 171 of the metal material can be formed by electroless plating. Further, the surface treatment layer 171 can be composed of a plurality of layers. For example, the surface treatment layer 171 can be formed of gold. Further, the surface treatment layer 171'can be formed of a plurality of layers of a nickel layer and a gold layer. In this case, "build-up circuit layer (copper layer) -nickel layer-gold layer" can be formed in this order. The nickel layer can prevent diffusion between the copper layer and the gold layer. On the other hand, the surface treatment layer 171 can be formed of a non-metal such as OSP.

Referring to FIG. 9, the metal layer 130 and the circuit layer 120 can be separated from each other in the thickness direction as compared with the printed circuit board described with reference to FIG. That is, the metal layer 130 can be formed at a distance from the circuit layer 120. The solder resist layer 170 can be further formed in the space formed by separating the metal layer 130 and the circuit layer 120. That is, the metal layer 130 can be located in the middle of the solder resist layer 170.

The metal layer 130 can extend to a region where the circuit layer 120 is not formed. In this case, the formation region (cross-sectional area) of the metal layer 130 is larger than the formation region (cross-sectional area) of the circuit layer 120. However, even in this case, the metal layer 130 is not formed in the opening O of the solder resist layer 170. The metal layer 130 may be a metal sheet in which a hole is formed corresponding to the region of the opening O. That is, the metal layer 130 is not patterned according to the pattern of the circuit pattern of the circuit layer 120. Further, in this case, all the electric signals are transmitted to the circuit layer 120 and not to the metal layer 130.

In relation to the thickness of the metal layer 130, the thickness of the first metal layer 131 located on one side of the insulating material 110 is larger than the thickness of the second metal layer 132 located on the other side of the insulating material 110. This allows the warpage of the printed circuit board to be controlled. In addition to this, the contents described with reference to FIG. 6 and the like can be applied to this embodiment.

Hereinafter, a method for manufacturing a printed circuit board according to an embodiment of the present invention will be described.

10 to 20 are views showing a method of manufacturing a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 10, a penetrating via hole 141 is formed in the insulating material 110, and a seed layer S1 is formed on the inner wall of the penetrating via hole 141 and one surface and the other surface of the insulating material 110. The through via hole 141 can be formed by using a drill bit or the like, and the seed layer S1 can be formed by electroless plating. The penetrating via 140 can include an electrolytic plating layer electrolytically plated on the seed layer S1.

Referring to FIG. 11, the circuit layer 120 is formed by using the plating resist R1. Here, the first circuit layer 121, the electrolytic plating layer of the penetrating via 140, and the second circuit layer 122 can be formed in the same plating process.

The height (thickness) of the first circuit layer 121 and the second circuit layer 122 is lower (thinner) than the height (thickness) of the plating resist R1. This is because the metal layer 130 is formed by using the same plating resist R1.

That is, referring to FIG. 12, the metal layer 130 is formed on the circuit layer 120. The metal layer 130 can be formed by electrolytic plating using the plating resist R1.

Referring to FIG. 13, the plating resist R1 is peeled off, and an unnecessary portion of the seed layer S1 is removed. The removal of unnecessary portions of the seed layer S1 can be performed by etching. Here, the "unnecessary portion" means a portion that is not a region of the circuit layer 120, and is for preventing an unnecessary short circuit.

Referring to FIGS. 14 to 17, the buildup layer 160 is formed.

First, referring to FIGS. 14 and 15, the insulating layers 161 and 162 are laminated on the metal layer 130 to form the via hole 166. The via hole 166 can be formed by a method of removing a part of the metal layer 130. In this case, the via hole 166 is formed stepwise. That is, the via holes A in the regions of the insulating layers 161 and 162 are first removed so as to expose the metal layer 130 (FIG. 14), and then the via holes B in the region of the metal layer 130 are removed (FIG. 15). This is due to the difference in material between the insulating layers 161, 162 and the metal layer 130.

The via hole A in the region of the insulating layers 161 and 162 can be formed by a laser drill, and the via hole B in the region of the metal layer 130 can be formed by etching. The metal layer 130 and the circuit layer 120 are set to react with different etching solutions, and the circuit layer 120 can serve as a stopper in the etching of the metal layer 130. Further, when the metal layer 130 is etched, the insulating layers 161 and 162 can serve as an etching resist.

That is, the cross-sectional shape of the via hole 166 becomes narrower as the width of the via hole A in the regions of the insulating layers 161 and 162 becomes narrower toward the insulating material 110, because the laser beam amount becomes smaller toward the inward side. On the other hand, the width of the via hole B in the region of the metal layer 130 also becomes narrower toward the insulating material 110 side, which corresponds to the case where the etching is isotropic etching. In particular, in this case, the inner wall of the via hole B in the region of the metal layer 130 can form a curved surface.

On the other hand, at the point where the via hole A in the region of the insulating layers 161 and 162 and the via hole B in the region of the metal layer 130 are bonded, the width of the via hole A in the region of the insulating layers 161 and 162 is the via hole in the region of the metal layer 130. It can be narrower than the width of B. Further, the width of the bottom of the via hole B in the region of the metal layer 130 is substantially the same as the width of the bottom of the via hole A in the regions of the insulating layers 161 and 162.

However, the etching conditions can be adjusted so that the width of the via hole B in the region of the metal layer 130 becomes constant.

Referring to FIG. 16, the seed layer S3 is formed inside the via hole 166 and on the insulating layers 161 and 162, and the plating resist R2 is laminated and then patterned.

Referring to FIG. 17, the build-up circuit layers 163 and 164 and the build-up metal layers 167 and 168 are sequentially plated and formed. The plating resist R2 is peeled off.

Referring to FIGS. 18 and 19, a solder resist layer 170 is formed on the build-up metal layer 167 and 168, and an opening O is formed in the solder resist layer 170. The opening O is also formed by removing a part of the build-up metal layer 167 and 168, and can be divided into two parts in the same manner as the via hole 166 described above. That is, the opening O can include the opening C in the region of the solder resist layer 170 and the opening D in the region of the build-up metal layer 167 and 168.

The cross-sectional shape of the opening O becomes narrower as the width of the opening C in the region of the solder resist layer 170 goes toward the insulating material 110, which means that the exposure amount (or the light amount of the laser drill) is inward in the photolithography process. This is because it gets smaller as it goes. On the other hand, the width of the opening D in the region of the build-up metal layer 167 and 168 also becomes narrower toward the insulating material 110 side, which corresponds to the case where the etching is isotropic etching. In particular, in this case, the inner wall of the opening D in the region of the build-up metal layer 167 and 168 can form a curved surface.

On the other hand, at the point where the opening C in the region of the solder resist layer 170 and the opening D in the region of the build-up metal layer 167 and 168 are bonded, the width of the opening C in the region of the solder resist layer 170 is built-up. It can be narrower than the width of the opening D in the region of the metal layer 167 and 168. Further, the width of the bottom of the opening D in the region of the build-up metal layer 167 and 168 is substantially the same as the width of the bottom of the opening C in the region of the solder resist layer 170.

However, the etching conditions can be adjusted so that the width of the opening D in the region of the build-up metal layer 167 and 168 becomes constant.

Referring to FIG. 20, the surface treatment layer 171 is formed on the build-up circuit layers 163 and 164 exposed from the opening O. The surface treatment layer 171 can be plated with metal and formed of one or more layers.

FIG. 22 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention. The above-mentioned contents can be similarly applied to the following.

Referring to FIG. 22, the printed circuit board according to the embodiment of the present invention includes an insulating material 110, one or more first insulating layers 161 and one or more second insulating layers 162, and a first circuit layer 221. , A second circuit layer 222, a first metal layer 231 and a second metal layer 232 can be included.

The insulating material 110 includes one side facing each other and the other side. Circuits 321 and 322 can be formed on one surface and the other surface of the insulating material 110. The circuits 321 and 322 formed on one surface and the other surface of the insulating material 110 can be electrically connected by a penetrating via 141 penetrating the insulating material 110.

One or more first insulating layers 161 can be laminated on one surface of the insulating material 110. For example, if there are two first insulating layers 161 as shown in FIG. 22, the two layers are thick on one surface of the insulating material 110 (to the lower side of the insulating material 110 with reference to FIG. 22). It can be stacked sequentially in the direction.

Further, one or more second insulating layers 162 can be laminated on the other surface of the insulating material 110. For example, if there are two second insulating layers 162, as shown in FIG. 22, the two layers are thick on the other surface of the insulating material 110 (to the upper side of the insulating material 110 with reference to FIG. 22). It can be stacked sequentially in the direction.

Even when each of the first insulating layer 161 and the second insulating layer 162 is composed of three, four, etc., they are sequentially laminated on both sides of the insulating material 110 in the thickness direction by the above-mentioned method. Can be

On the other hand, when the first insulating layer 161 and the second insulating layer 162 are each one, one insulating layer is laminated on both sides of the insulating material 110, and the first insulating layer 161 and the first insulating layer 162 are laminated. 2 The insulating layer 162 is an insulating layer located on the outermost layer.

The first circuit layer 221 is formed on at least one of the one or more first insulating layers 161 described above. When the first insulating layer 161 is one, the first circuit layer 221 is formed on the first insulating layer 161. When the first insulating layer 161 is two or more, those are formed. It is formed on at least one of them. Of course, another circuit 321 can be formed on the other first insulating layer 161 on which the first circuit layer 221 is not formed, and can be electrically connected to the first circuit layer 221.

As shown in FIG. 22, the first circuit layer 221 can be formed on the first insulating layer 161 located on the outermost layer of the one or more first insulating layers 161.

The second circuit layer 222 is formed on at least one of the one or more second insulating layers 162 described above. When there is one second insulating layer 162, the second circuit layer 222 is formed on the second insulating layer 162, and when there are two or more second insulating layers 162, those are formed. It is formed on at least one of them. Of course, another circuit 322 is also formed on the other second insulating layer 162 on which the second circuit layer 222 is not formed, and can be electrically connected to the second circuit layer 222.

As shown in FIG. 22, the second circuit layer 222 can be formed on the second insulating layer 162 located on the outermost layer of the one or more second insulating layers 162.

The first metal layer 231 is formed on the first circuit layer 221, and the electric conductivity of the first metal layer 231 is smaller than the electric conductivity of the first circuit layer 221.

The second metal layer 232 is formed on the second circuit layer 222, and the electric conductivity of the second metal layer 232 is smaller than the electric conductivity of the second circuit layer 222.

The first circuit layer 221 and the second circuit layer 222 can have the same thickness as each other. Further, the thickness of the first metal layer 231 can be thinner than the thickness of the first circuit layer 221 and the thickness of the second metal layer 232 can be thinner than the thickness of the second circuit layer 222. The thickness of the first metal layer 231 does not exceed 2/3 of the thickness of the first circuit layer 221. Further, the thickness of the second metal layer 232 does not exceed 2/3 of the thickness of the second circuit layer 222. On the other hand, the thickness of the first metal layer 231 can be larger than the thickness of the second metal layer 232. By adjusting the thickness in this way, it is possible to control the warp of the printed circuit board.

The first circuit layer 221 and the second circuit layer 222 can be layers containing copper as a main component, and the first metal layer 231 and the second metal layer 232 are Fe-Ni such as invar. It can be made of a copper alloy material such as a (nickel steel) alloy or a Cu—Zn alloy brass.

The printed circuit board according to the embodiment of the present invention can further include a solder resist layer 170 laminated on the first insulating layer 161 and the second insulating layer 162 located on the outermost layer, respectively.

The first metal layer 231 and the second metal layer 232 are formed in the opening region so that the opening O is formed in the solder resist layer 170 and the first circuit layer 221 and the second circuit layer 222 are exposed from the opening O. Does not have to be formed. Such a structural feature is that the etched region is formed by etching the first metal layer 231 after forming the first metal layer 231 on the first circuit layer 221. Part) can be. Similarly, by forming the second metal layer 232 on the second circuit layer 222 and then etching the second metal layer 232, the etched region can be (a part of) the opening O.

FIG. 23 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 23, in the printed circuit board described with reference to FIG. 22, the first metal layer 231 and the first circuit layer 221 are separated from each other in the thickness direction, and the first metal layer 231 and the first circuit layer are separated from each other. A space is formed between the 221 and the solder resist layer 170.

Similarly, the second metal layer 232 and the second circuit layer 222 are separated from each other in the thickness direction, a space is formed between the second metal layer 232 and the second circuit layer 222, and a solder is formed in the space. The resist layer 170 is formed.

Here, the formation region of the first metal layer 231 can be larger than the formation region of the first circuit layer 221. The formation region of the second metal layer 232 is larger than the formation region of the second circuit layer 222. Can be done.

The first metal layer 231 can also be formed on the region where the first circuit layer 221 is not formed, and can be formed over the entire region excluding the opening O of the solder resist layer 170. The second metal layer 232 can also be formed on the region where the second circuit layer 222 is not formed, and can be formed over the entire region excluding the opening O of the solder resist layer 170. The first metal layer 231 and the second metal layer 232 may be metal sheets.

24 is a cross-sectional view of the printed circuit board according to the embodiment of the present invention, FIG. 25 is a partially enlarged view of FIG. 24, and FIG. 26 is a cross-sectional view of the printed circuit board according to the embodiment of the present invention. 27 is a partially enlarged view of FIG. 26, FIG. 28 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention, and FIG. 29 is a partially enlarged view of FIG. 28.

Referring to FIG. 24, the printed circuit board according to the embodiment of the present invention includes an insulating material 110, circuit layers 121 and 122, metal layers 131 and 132, and insulating layers 161 and 162, and includes an insulating layer 161. , 162 and the via holes 166 are formed in the metal layers 131 and 132, and the circuit layers 121 and 122 can be exposed from the bottom surface of the via holes 166.

The insulating material 110 is a plate-shaped material composed of an insulating substance such as a resin, and is as described above.

The circuit layers 121 and 122 are conductors patterned for transmitting electrical signals and are formed on the insulating material 110. The circuit layers 121 and 122 can be formed on both sides of the insulating material 110.

The metal layers 131 and 132 are conductors formed on the circuit layers 121 and 122 and having an electric conductivity smaller than that of the circuit layers 121 and 122.

The insulating layers 161 and 162 are plate-shaped materials composed of an insulating material such as a resin, and can be formed of the same or different material as the insulating material 110.

The via hole 166 is a hole that penetrates the insulating layers 161 and 162 and the metal layers 131 and 132, and the circuit layers 121 and 122 can be exposed from the bottom surface of the via hole 166. Further, when the conductive layer is formed in the via hole 166 and the via 165 is formed, the metal layers 131 and 132 and the side surface of the via 165 can come into contact with each other. In this case, the bottom surface of the via 165 can be in direct contact with the circuit layers 121, 122.

The via hole 166 can include a first hole E and a second hole F. The first hole E is located outside the second hole F, and the width of the first hole E and the width of the second hole F become narrower toward the inside.

FIG. 25 shows various forms of the via hole 166 including the first hole E and the second hole F.

As shown in FIGS. 25 (a) and 25 (b), the width of the first hole E can be narrower than the width of the second hole F on the surface where the first hole E and the second hole (F) meet. Further, as shown in (b), the side surface of the second hole F can be curved. It can be said that this is a result of the formation of the second hole F by isotropic etching of the metal layers 131 and 132. Here, the innermost width of the first hole E and the innermost width of the second hole F can be substantially the same.

On the other hand, by adjusting the thicknesses of the metal layers 131 and 132, the etching method, the conditions, etc., as shown in (c), the first hole E is formed on the surface where the first hole E and the second hole F are in contact with each other. The width and the width of the second hole F can be formed to be the same.

Referring to FIG. 26, a via 165 is formed in the via hole 166, and the via 165 can include a seed layer. Further, build-up circuit layers 163 and 164 connected to vias 165 can be formed on the insulating layers 161 and 162, and build-up metal layers 167 and 168 are formed on the build-up circuit layers 163 and 164. be able to.

The side surface of the via 165 in the via hole 166 can be in contact with the metal layers 131, 132, and if the via 165 includes a seed layer, the metal layers 131, 132 can be in contact with the seed layer.

27 shows a state in which the seed layer, via 165, build-up circuit layer 163, 164, and build-up metal layer 167, 168 are formed by (a), (b), and (c) of FIG. 25. There is.

Referring to FIG. 28, a solder resist layer 170 is formed on the insulating layers 161 and 162, an opening O is formed in the solder resist layer 170, and the openings O are the first opening G and the second opening H. Can be included. The first opening G is located outside the second opening H, and the width of the first opening G and the width of the second opening H become narrower toward the inside.

FIG. 29 shows various forms of the opening O including the first opening G and the second opening H.

As shown in FIGS. 29A and 29B, the width of the first opening G can be narrower than the width of the second opening H on the surface where the first opening G and the second opening H are in contact with each other. Further, as shown in (b), the side surface of the second opening H can be curved. It can be said that this is a result of the formation of the second opening H by isotropic etching of the build-up metal layers 167 and 168. Here, the innermost width of the first opening G and the innermost width of the second opening H can be substantially the same.

On the other hand, by adjusting the thickness of the build-up metal layer 167 and 168, the etching method, the conditions, and the like, as shown in FIG. 29 (c), on the surface where the first opening G and the second opening H are in contact with each other. , The width of the first opening G and the width of the second opening H can be formed to be the same.

On the other hand, as shown in FIGS. 28 and 29, the surface treatment layer 171 can be formed on the build-up circuit layers 163 and 164 exposed from the opening O.

Although the embodiments of the present invention have been described above, if the person has ordinary knowledge in the technical field, the addition of components can be performed within the range not deviating from the idea of the present invention described in the claims. The present invention can be variously modified and changed by modification, deletion, addition, etc., and it can be said that this is also included in the scope of the present invention.

110 Insulation 120 Circuit layer 121, 221 First circuit layer 122, 222 Second circuit layer 130 Metal layer 131, 231 First metal layer 132, 232 Second metal layer 140 Penetrating via 141 Penetrating via hole 150 Alloy layer 151 First alloy Layer 152 2nd alloy layer 153 3rd alloy layer 160 Build-up layer 161 1st insulation layer 162 2nd insulation layer 163 1st build-up circuit layer 164 2nd build-up circuit layer 165 Via 166 Via hole 167 1st build-up metal layer 168 Second build-up metal layer 170 Solder resist layer O Opening 171 Surface treatment layer S1, S2, S3, S4 Seed layer R1, R2 Plated resist

Claims (22)

An insulating material having one side and the other side facing each other,
A circuit layer formed on one surface and the other surface of the insulating material,
Including a metal layer formed on the circuit layer,
The electrical conductivity of the metal layer is smaller than the electrical conductivity of the circuit layer.
A printed circuit board in which the thickness of the metal layer located on the one side of the insulating material is thicker than the thickness of the metal layer located on the other side of the insulating material. The printed circuit board according to claim 1, wherein the thickness of the metal layer is thinner than the thickness of the circuit layer. The coefficient of thermal expansion of the metal layer is smaller than the coefficient of thermal expansion of the circuit layer.
The printed circuit board according to claim 1 or 2, wherein the rigidity of the metal layer is larger than the rigidity of the circuit layer. The coefficient of thermal expansion of the metal layer is larger than the coefficient of thermal expansion of the circuit layer.
The printed circuit board according to claim 1 or 2, wherein the rigidity of the metal layer is smaller than the rigidity of the circuit layer. The printed circuit board according to claim 1 or 2, wherein the volume of the circuit layer located on the one side of the insulating material is smaller than the volume of the circuit layer located on the other side of the insulating material. Formed through the inside of the insulating material,
The invention according to any one of claims 1 to 5, further comprising a penetrating via for connecting the circuit layer formed on one surface of the insulating material and the circuit layer formed on the other surface of the insulating material. The printed circuit board described. Further comprising an alloy layer formed between the insulating material and the penetrating via and between the insulating material and the circuit layer.
The printed circuit board according to claim 6, wherein the metal layer and the alloy layer are made of the same substance. The printed circuit board according to claim 7, wherein the thickness of the alloy layer located on the one side of the insulating material is thicker than the thickness of the alloy layer located on the other side of the insulating material. The penetrating via is formed in the penetrating via hole penetrating the insulating material.
The alloy layer includes a seed layer and includes a seed layer.
The printed circuit board according to claim 7 or 8, wherein the seed layer is formed on the inner wall of the through via hole and on one surface and the other surface of the insulating material. An insulating material having one side and the other side facing each other,
One or more first insulating layers laminated on the one surface of the insulating material,
With one or more second insulating layers laminated on the other surface of the insulating material,
A first circuit layer formed on at least one of the one or more first insulating layers, and a first circuit layer.
A second circuit layer formed on at least one of the one or more second insulating layers, and
The first metal layer formed on the first circuit layer and
A second metal layer formed on the second circuit layer, and the like.
The electric conductivity of the first metal layer is smaller than the electric conductivity of the first circuit layer.
The electric conductivity of the second metal layer is smaller than the electric conductivity of the second circuit layer.
The thickness of the first metal layer is thicker than the thickness of the second metal layer.
Printed circuit board. The first circuit layer and the first metal layer are formed on the first insulating layer located on the outermost layer.
The printed circuit board according to claim 10, wherein the second circuit layer and the second metal layer are formed on a second insulating layer located on the outermost layer. Further including a solder resist layer laminated on the first insulating layer and the second insulating layer located on the outermost layer, respectively.
An opening is formed in the solder resist layer, and an opening is formed.
The first circuit layer and the second circuit layer are exposed from the opening so that the first circuit layer and the second circuit layer are exposed.
The printed circuit board according to claim 11, wherein the first metal layer and the second metal layer are not formed in the region of the opening. The first metal layer and the first circuit layer are separated from each other in the thickness direction.
The printed circuit board according to claim 12, wherein the solder resist layer is further formed between the first metal layer and the first circuit layer. The printed circuit board according to claim 13, wherein the formation region of the first metal layer is larger than the formation region of the first circuit layer. Insulating material and
The circuit layer formed on the insulating material and
A metal layer containing invar , formed on the circuit layer, and having an electric conductivity smaller than that of the circuit layer.
The insulating layer laminated on the insulating material and
Includes the insulating layer and via holes penetrating the metal layer.
The circuit layer is exposed from the bottom surface of the via hole.
Printed circuit board. Further including vias formed in the via hole,
The printed circuit board according to claim 15, wherein the side surface of the via is in contact with the metal layer. The via hole includes a first hole and a second hole, and includes the first hole and the second hole.
The first hole penetrates the insulating layer and
The second hole penetrates the metal layer and
The printed circuit board according to claim 15, wherein each of the width of the first hole and the width of the second hole becomes narrower toward the insulating material side. On the surface where the first hole and the second hole are in contact with each other
The printed circuit board according to claim 17, wherein the width of the first hole is narrower than the width of the second hole. The printed circuit board according to claim 17, wherein the side surface of the second hole is a curved surface. The printed circuit board according to any one of claims 15 to 19, wherein the thickness of the metal layer does not exceed 2/3 of the thickness of the circuit layer. The coefficient of thermal expansion of the metal layer is smaller than the coefficient of thermal expansion of the circuit layer.
The printed circuit board according to any one of claims 15 to 19, wherein the rigidity of the metal layer is larger than the rigidity of the circuit layer. The coefficient of thermal expansion of the metal layer is larger than the coefficient of thermal expansion of the circuit layer.
The printed circuit board according to any one of claims 15 to 19, wherein the rigidity of the metal layer is smaller than the rigidity of the circuit layer.

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