JP7188836B2 - printed circuit board - Google Patents

Description

The present invention relates to printed circuit boards.

In recent years, there has been a rapid increase in interest in 5G communication using high-frequency bands of 20 GHz or higher, and technical research is being conducted to use new materials for PCBs in order to respond to this. Use of insulating materials with low dielectric constant (Dk) and low dielectric loss (Df), reduction of circuit surface roughness, improvement of connection between vias, etc., in order to minimize loss during signal transmission in high frequency bands technology development is required.

Korean Patent Publication No. 10-2011-0002112

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed circuit board with improved connections between vias.

According to one aspect of the present invention, a first insulating layer having a metal pad formed on one surface thereof; a plated via formed through the first insulating layer to be connected to one surface of the metal pad; a second insulating layer laminated on one surface of one insulating layer; and a paste via formed through the second insulating layer so as to be connected to the other surface of the metal pad; A printed circuit board is provided in which the other surface of the insulating layer is located within the first insulating layer.

According to another aspect of the present invention, a first insulating layer, a plated via formed through the first insulating layer, a second insulating layer laminated on the first insulating layer, and the plated via a paste via formed through the second insulating layer so as to be in contact therewith, wherein a contact interface between the plated via and the paste via is located within the first insulating layer. .

1 is a diagram showing a printed circuit board according to an embodiment of the invention; FIG. FIG. 2 illustrates a plurality of unit layers of a printed circuit board according to an embodiment of the invention; FIG. 2 illustrates vias in a printed circuit board according to an embodiment of the present invention; It is a figure which shows the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention. It is a figure for demonstrating the manufacturing method of the printed circuit board based on the Example of this invention.

Exemplary embodiments of printed circuit boards in accordance with the present invention will now be described in detail with reference to the accompanying drawings, wherein like or corresponding components are identified by like reference numerals, Duplicate explanation is omitted.

In addition, terms such as "first" and "second" used below are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are the first, second, etc. is not limited by the term

In addition, in the contact relationship between each component, the term “coupled” does not mean only the case where each component is in direct physical contact. It is used as a concept that includes the case where each component is in contact with another configuration.

FIG. 1 is a diagram showing a printed circuit board according to an embodiment of the present invention, FIG. 2 is a diagram showing a plurality of unit layers of the printed circuit board according to an embodiment of the present invention, and FIG. FIG. 2 illustrates vias in a printed circuit board according to an embodiment of the invention;

A printed circuit board according to embodiments of the present invention will be described from two aspects. The first aspect describes the structure within one unit layer, and the second aspect describes the via structure connecting different adjacent unit layers. Specifically, the former will be described with reference to FIGS. 1 and 2, and the latter will be described with reference to FIG.

1 and 2, a printed circuit board according to an embodiment of the present invention includes a first insulating layer 100, a plated via 130, a second insulating layer 200, and a paste via 230. As shown in FIG.

The printed circuit board may be formed of a plurality of unit layers, each of which includes a first insulating layer 100, a plated via 130, a second insulating layer 200, and a paste via 230. .

The first insulating layer 100 and the second insulating layer 200 are materials composed of an insulating material such as resin. The second insulation layer 200 is stacked on one surface of the first insulation layer 100 . When the printed circuit board is formed of a plurality of unit layers, each unit layer includes the first insulating layer 100 and the second insulating layer 200, so that the finally manufactured printed circuit board has the first insulating layer. It has a structure in which the 100 and the second insulating layer 200 are alternately and repeatedly laminated.

Various materials such as thermosetting resins and thermoplastic resins can be used as the resin of the insulating layers 100 and 200 .

The insulating layers 100, 200 can be made of materials with low dielectric constant and dielectric loss. In particular, the insulating layers 100 and 200 are made of a material with low dielectric constant (Dk) and dielectric loss tangent (Df), such as LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), PPE (Polyphenylene Ether), COP (Cyclo Olefin Polymer). , PFA (Perfluoroalkoxy), and PI (Polyimide). These materials are suitable for reducing signal loss in substrates that transmit high frequency signals.

However, the insulating layers 100 and 200 are not limited to the above materials, and can be made of other materials such as epoxy resin or polyimide. Examples of epoxy resins include naphthalene-based epoxy resins, bisphenol A-type epoxy resins, bisphenol F-type epoxy resins, novolak-based epoxy resins, cresol novolak-based epoxy resins, rubber-modified epoxy resins, and cycloaliphatic epoxy resins. Resins, silicon-based epoxy resins, nitrogen-based epoxy resins, phosphorus-based epoxy resins, and the like can be used, but are not limited to these.

The insulating layers 100 and 200 may contain a fiber reinforcing material such as glass cloth or an inorganic filler such as silica in the resin. Examples of the former include prepreg (PPG), and examples of the latter include build-up films such as ABF (Ajinomoto Build-up Film).

A first circuit 111 and a metal pad 110 are formed on one surface of the first insulating layer 100 .

The first circuit 111 and the metal pad 110 may be embedded in one surface of the first insulating layer 100 . In this case, the first circuit 111 and the metal pad 110 are the surface of the second insulating layer 200 that contacts one surface of the first insulating layer 100 (the other surface of the second insulating layer 200, which is the second insulating layer 200 in this specification). The side of the layer 200 that is not in contact with the first insulating layer 100 is called "one side", and the opposite side is called the "other side"), and the first circuits 111 and the metal pads 110 are formed on the first insulating layer. 100 and the second insulating layer 200 and embedded in one surface of the first insulating layer 100 .

The first circuit 111 is a conductor patterned to carry electrical signals. Metal pad 110 is a conductor that connects to first circuit 111 . The first circuit 111 and the metal pad 110 are made of copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum ( It can be made of a metal such as Pt) or an alloy thereof.

Each side of the first circuit 111 and the metal pad 110 may be inclined. In particular, each side surface of the first circuit 111 and the metal pad 110 may have a downward sloping surface, and the cross-sectional area of the first circuit 111 and the metal pad 110 increases downward (toward the second insulating layer 200). The further you go, the bigger it can get. In particular, the cross-sectional area of the metal pad 110 increases from one surface to the other surface. The slanted sides may be the result of forming the first circuit 111 and the metal pad 110 by a subtractive method such as tenting.

A second circuit 112 is formed on the other surface of the first insulating layer 100 .

The second circuit 112, like the first circuit 111, is a conductor patterned to carry electrical signals. The second circuit 112 is made of copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or the like, in consideration of electrical conduction characteristics. It can be made of metals or alloys thereof.

The second circuit 112 may have a finer pitch than the first circuit 111 . That is, the wiring density of the second circuits 112 is higher than the wiring density of the first circuits 111, the width of the second circuits 112 is smaller than the width of the first circuits 111, and the interval between the second circuits 112 is the same as that of the first circuits 111. It may be smaller than the interval between one circuit 111 .

The sides of the second circuit 112 may have no slope or a slope that is more vertical than the first circuit 111 . This may be the result of the first circuit 111 and the second circuit 112 being formed by different methods, for example, the first circuit 111 is formed by a subtractive method and the second circuit 112 is formed by an additive method ( additive), semi-additive method, modified semi-additive method, and the like.

The second circuit 112 may include a seed layer S underneath. The seed layer S can be formed by electroless plating, and in this case the second circuit 112 can be formed by electrolytic plating. The seed layer S may have a thickness of 2 μm or less.

A ground layer 113 may be formed on the other surface of the first insulating layer 100 . The second circuit 112 may be a patterned conductor, while the ground layer 113 may be a metal layer formed wider than the second circuit 112 .

When the printed circuit board is formed of a plurality of unit layers, the second circuit 112 or the ground layer 113 may be selectively formed on the other surface of the first insulating layer 100 of each unit layer. In the printed circuit board finally manufactured by laminating together, the circuit layers (the first circuit 111 and the second circuit 112) and the ground layer 113 can be alternately formed in a specific order. For example, in FIG. 1, the ground plane 113 is designed to be formed every three circuit layers.

However, the structure is not limited to this, and the second circuit 112 and the ground layer 113 may be formed together on the other surface of the first insulating layer 100 .

A plating via 130 is formed in the first insulating layer 100 .

Since the plated via 130 is formed in the first opening 120 penetrating the first insulating layer 100 , the plated via 130 may be formed to pass through the first insulating layer 100 . The plated via 130 is made of a metal such as copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), or an alloy thereof. It can be formed by plating in 120 .

The plating via 130 is connected to the metal pad 110 and contacts one surface of the metal pad 110 . The plated via 130 electrically connects the metal pad 110 and the second circuit 112 (or ground layer 113). At this time, since the metal pad 110 is connected to the first circuit 111 , the first circuit 111 and the second circuit 112 (or the ground layer 113 ) are electrically connected by the plated via 130 .

A surface of the plating via 130 that does not contact the metal pad 110 is exposed to the other surface of the first insulating layer 100 . However, the surface of the plated via 130 that is not in contact with the metal pad 110 is more depressed than the other surface of the first insulating layer 100 . That is, the surface of the plated via 130 on the other side of the first insulating layer 100 is located inside the first insulating layer 100 . Therefore, if one surface of the first insulating layer 100 is set as the bottom surface and the other surface of the first insulating layer 100 is set as the top surface, the top surface of the plated via 130 is positioned below the top surface of the first insulating layer 100 . Here, a space formed by the surface of the plated via 130 being recessed below the top surface of the first insulating layer 100 may be referred to as a recess space 140 . A thickness of the recess space 140 may be 3 μm or less.

A cross-sectional area of the plating via 130 may increase from one surface to the other surface of the first insulating layer 100 . That is, the cross-sectional area of the plated via 130 increases from the first circuit 111 to the second circuit 112 (or ground layer 113). Meanwhile, in one unit layer among the plurality of unit layers, the cross-sectional area of the plating via 130 may increase outward from the metal pad 110 . This may be the result of the first opening 120 being formed by laser machining, such as a _CO2 laser.

The plating via 130 may include a seed layer S underneath. The seed layer S can be formed by electroless plating, and in this case, the plated vias 130 can be formed by electrolytic plating. The seed layer S may have a thickness of 2 μm or less. The seed layer S of the second circuit 112 and the seed layer S of the plated via 130 may be connected to each other without an interface therebetween.

A paste via 230 is formed in the second insulating layer 200 . Paste vias 230 are vias formed with a conductive filler, and may be, for example, vias filled with a metal paste.

The metal of the metal paste forming paste via 230 may be different from the metal forming plated via 130 . The melting point of the metal of the paste via 230 may be lower than the melting point of the plating of the plated via 130 . The plated via 130 may be formed of a metal containing copper, and the paste via 230 may be formed of a metal containing bismuth-coated copper, tin, or silver.

The paste via 230 may be formed in the second opening 220 penetrating the second insulation layer 200 so as to penetrate the second insulation layer 200 . Paste via 230 is connected to metal pad 110 and contacts the other surface of metal pad 110 .

The cross-sectional area of the paste via 230 increases from the other surface of the metal pad 110 to the one surface of the second insulation layer 200 . The cross-sectional area of the plated via 130 and the cross-sectional area of the paste via 230 may increase or decrease symmetrically with respect to the metal pad 110 . That is, in one unit layer among the plurality of unit layers, the cross-sectional area of the plated via 130 and the cross-sectional area of the paste via 230 may increase outward from the metal pad 110 . This may be a result of the opposing working surfaces of the first opening 120 and the second opening 220 .

The paste via 230 may be exposed from one side of the second insulation layer 200 . In this case, the paste via 230 may protrude from one surface of the second insulation layer 200 . That is, if one surface of the second insulation layer 200 is referred to as a bottom surface, the other surface of the second insulation layer 200 is in contact with one surface of the first insulation layer 100, and the bottom surface of the paste via 230 is exposed from the bottom surface of the second insulation layer 200. and may protrude from the lower surface of the second insulating layer 200 .

On the other hand, the cross-sectional area of the paste via 230 may decrease from one surface of the second insulating layer 200 toward the outside. As a result, the cross-sectional area of the paste via 230 may increase from the other surface of the metal pad 110 to the one surface of the second insulating layer 200 and then decrease.

FIG. 3 shows a connection between a plated via 130 formed in one unit layer and a paste via 230 formed in another adjacent unit layer when forming a printed circuit board with a plurality of unit layers. FIG. 4 is a diagram showing relationships;

When forming a printed circuit board with a plurality of unit layers, the first insulating layer 100 of one unit layer is in contact with the second insulating layer 200 of another adjacent unit layer. At this time, the plated via 130 in one unit layer contacts the paste via 230 in another adjacent unit layer.

That is, the second insulation layer 200 is stacked on the first insulation layer 100, and the plated via 130 penetrating the first insulation layer 100 and the paste via 230 penetrating the second insulation layer 200 are in contact with each other. At this time, the contact interface between the plated via 130 and the paste via 230 is located within the first insulating layer 100 . As shown in FIG. 3, when the interface between the first insulating layer 100 and the second insulating layer 200 is A, the contact interface between the plated via 130 and the paste via 230 is the first insulating layer B compared to A. Located on the layer 100 side. Here, the space corresponding to B is the recess space 140 .

Specifically, the surface of the plated via 130 is recessed from the interface A, and when the first insulating layer 100 and the second insulating layer 200 are stacked, the paste via 230 is located in the region where the plated via 130 is recessed. As a result, the paste via 230 protrudes from the interface A by the distance B. FIG. Here, the side surfaces of the end portions of the paste vias 230 are in contact with the first insulating layer 100 .

Since the recess space 140 partially accommodates the paste via 230, unnecessary flow of the paste via 230 can be prevented. In addition, the recess space 140 is advantageous in matching the plated via 130 and the paste via 230, thus eliminating the need for additional via pads and reducing signal loss caused by the via pads.

In addition, the first circuit 111 and the metal pad 110 are formed on one surface of the first insulating layer 100 , the plating via 130 is formed on one surface of the metal pad 110 , and the second insulating layer 200 is formed on the other surface of the first insulating layer 100 . Laminated. Here, the side surfaces of the metal pad 110 may include inclined surfaces, and the cross-sectional area of the metal pad 110 may increase from one surface to the other surface of the metal pad 110 . A side surface of the first circuit 111 may also include the same inclined surface. The cross-sectional area of the second circuit 112 may also increase from one side to the other.

A second circuit 112 is formed on the other surface of the first insulating layer 100 . The sides of the second circuit 112 may include no sloped surfaces or nearly vertical sloped surfaces. A seed layer S may be provided below the second circuit 112 , and the seed layer S may be connected to the seed layer S provided below the plating via 130 .

A ground layer 113 may be formed on the other surface of the first insulating layer 100 .

The first insulating layer 100 and the second insulating layer 200 are made of LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), PPE (Polyphenylene Ether), COP (Cyclo Olefin Polymer), PFA (Perfluoroalkoxy), PI (polyethylene). It can be formed with at least one of them.

On the other hand, the cross-sectional areas of the first opening 120 penetrating the first insulating layer 100 and the second opening 220 penetrating the second insulating layer 200 may be reduced in the opposite directions from the interface A. FIG. In this case, the cross-sectional area of the plated via 130 decreases from one surface to the other surface, that is, the cross-sectional area of the plated via 130 increases from the bottom surface to the interface A. In addition, the cross-sectional area of the paste via 230 increases from the upper surface toward the interface between the first insulating layer 100 and the second insulating layer 200, and extends from the interface between the first insulating layer 100 and the second insulating layer 200 to the interface A. It gets smaller as you go. This is because a part of the paste via 230 is inserted inside the first opening 120 , so that the inclination of the side surface of the paste via 230 within the first opening 120 is the same as that of the side surface of the plated via 130 . Same as tilt.

FIG. 4 shows a printed circuit board according to an embodiment of the invention.

The printed circuit board shown in FIG. 4 can be a rigid flexible board. This printed circuit board can be used as a replacement for the coaxial cable.

The hard-soft substrate is divided into a rigid part and a flexible part, and the flexible insulating layer 310 formed over the rigid part and the flexible part is made of bendable material such as LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), PI (polyimide), or the like. In the rigid portion, rigid insulating layers 320 are laminated on both sides of the flexible insulating layer. A resin with low flexibility can be used for the rigid insulating layer 320 .

The rigid portion can include structures described with reference to FIGS. 1-3. A description of this is omitted because it is the same as the content described above.

5 to 18 are diagrams illustrating a method of manufacturing a printed circuit board according to an embodiment of the invention.

As shown in FIG. 5, a raw material in which a metal foil M is laminated on an insulating material is prepared. Here, the insulating material corresponds to the second insulating layer 200 described above, and the metal foil M serves as the base of the first circuit 111 and the metal pads 110 .

The insulating material is formed of materials such as LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), PPE (Polyphenylene Ether), COP (Cyclo Olefin Polymer), PFA (Perfluoroalkoxy), PI (Polyimide), etc., which have a small dielectric constant and dielectric loss tangent. It is possible and preferably the dissipation factor is less than 0.002 (at 10 GHz). Also, the insulating material can have a thickness of 25 to 100 μm. The metal foil M may be copper and may have a thickness of 10-20 μm. However, it is not limited to this.

In FIG. 6, a photosensitive resist R1 is deposited and patterned. The patterning of the photosensitive resist R1 can be formed by a photolithography process including exposure and development. The photosensitive resist R1 becomes an etching resist. That is, the patterned photosensitive resist R1 remains in the regions where the first circuits 111 and the metal pads 110 are formed.

As shown in FIG. 7, the patterned photosensitive resist R1 serves as an etching resist, and the metal foil M is etched. The first circuit 111 and the metal pad 110 may be formed by such a tenting method, but is not limited thereto. When the first circuit 111 and the metal pad 110 are formed by the tenting method, the sides of the first circuit 111 and the metal pad 110 are inclined, and the cross-sectional areas of the first circuit 111 and the metal pad 110 are insulated. It gets bigger as it goes to the material side. That is, the vertical cross section of the first circuit 111 and the metal pad 110 is trapezoidal. However, from FIG. 8 onwards, the inclined side surfaces of the first circuit 111 and the metal pad 110 are omitted.

In FIG. 8, the first insulating layer 100 is laminated on the insulating material, and one surface of the first insulating layer 100 contacts the insulating material. Lamination of the first insulating layer 100 can be realized by lamination by V-press. The first insulating layer 100 may have a thickness of 25-100 μm. The first insulating layer 100 can be made of the same or different material as the insulating material (the second insulating layer 200). However, the dissipation factor of the first insulating layer 100 can also be less than 0.002 (at 10 GHz).

Through the process of FIG. 8, a unit layer is formed by combining the first insulating layer 100 and the second insulating layer 200, and between the first insulating layer 100 and the second insulating layer 200, the first circuit 111 and the metal pad are formed. 110 is located, the first circuit 111 and the metal pad 110 are embedded in the first insulating layer 100 .

As shown in FIG. 9, a first opening 120 is formed in the first insulating layer 100 . The first opening 120 can be formed by laser processing such as CO ₂ laser or UV laser, or by mechanical processing such as sand blasting. A first opening 120 is formed on the metal pad 110 such that one surface of the metal pad 110 is exposed through the first opening 120 . The cross-sectional area of the first opening 120 may decrease toward the metal pad 110, and the width of the first opening 120 opposite the metal pad 110 may be 40-100 μm.

As shown in FIG. 10, a plating via 130 is formed within the first opening 120 . The plated via 130 can be filled by electroplating after the seed layer S is formed by electroless plating. At this time, the seed layer S formed by electroless plating may be formed to extend not only to the inner sidewalls and bottom surface of the first opening 120 but also to the other surface of the first insulating layer 100 . The seed layer S may have a thickness of 2 μm or less.

As shown in FIG. 11, a photosensitive resist R2 is layered on the seed layer S, and the photosensitive resist R2 is patterned. The photosensitive resist R2 is removed corresponding to the forming region of the second circuit 112. Next, as shown in FIG.

As shown in FIG. 12, the second circuit 112 is formed, and the second circuit 112 can be formed by electroplating. Thus, the second circuit 112 can be formed by a semi-additive method, but is not limited to this.

As shown in FIG. 13, the photosensitive resist R2 is removed.

In FIG. 14, the unnecessary seed layer S is removed. That is, the seed layer S other than the seed layer S positioned under the second circuit 112 is removed. Here, when removing the seed layer S, a part of one surface of the plated via 130 made of the same metal as the seed layer S is removed. That is, a recess space 140 is formed in the plating via 130 . Accordingly, one surface of the plated via 130 is recessed below the other surface of the first insulating layer 100 .

As shown in FIG. 15, the second opening 220 is formed after attaching the protective film 210 to one surface of the second insulating layer 200 . Protective film 210 may be a PET film. The protective film 210 can prevent burrs from being generated when the second opening 220 is processed. The second opening 220 can be formed by laser processing such as CO ₂ laser or UV laser, or by mechanical processing such as sand blasting. The width of the second opening 220 on one surface of the second insulating layer 200 may be 40 to 100 μm.

As shown in FIG. 16, the second opening 220 is filled with a metal paste. The metal paste may be a paste mixed with a thermosetting resin containing a metal filler made of tin-based, silver-based, or bismuth (Bi)-coated copper. The metal paste can be squeezed by a vacuum press or an air press.

In FIG. 17, protective film 210 is removed and paste via 230 is completed. A portion of the metal paste may be removed when removing the protective film 210 . However, even in this case, the metal paste protrudes from one surface of the second insulating layer 200 . Through this process, a unit layer of a printed circuit board can be formed.

In FIG. 18, a unit layer having a ground layer 113 instead of the second circuit 112 is manufactured.

That is, similarly, a unit layer in which the second insulating layer 200 and the first insulating layer 100 are stacked is prepared, the first opening 120 is processed, the seed layer S is formed, and the ground layer 113 is formed together with the plated via 130 by plating. be able to. Thereafter, a unit layer having the ground layer 113 formed thereon can be manufactured through processes of attaching the protective film 210, processing the second opening 220, forming the paste via 230, and removing the protective film 210. FIG.

The unit layer formed with the second circuit 112 described with reference to FIGS. 5 to 7 and the unit layer formed with the ground layer 113 described with reference to FIG. A circuit board can be manufactured (see FIG. 2).

An embodiment of the present invention has been described above. , deletions, additions, etc., can be modified and changed in various ways, and these are also included in the scope of rights of the present invention.

100 first insulating layer 110 metal pad 111 first circuit 112 second circuit 113 ground layer 120 first opening 130 plated via 140 recess space 200 second insulating layer 210 protective film 220 second opening 230 paste via

Claims (20)

a first insulating layer having a metal pad formed on one surface;
a plated via formed through the first insulating layer to connect to one surface of the metal pad;
a second insulating layer laminated on one surface of the first insulating layer;
a paste via formed through the second insulating layer so as to be connected to the other surface of the metal pad;
The outermost surface of the plated via on the other surface side of the first insulating layer is located between one surface and the other surface of the first insulating layer, and a printed circuit board surrounding it is in contact with the first insulating layer. . 2. The printed circuit board of claim 1, wherein the side surfaces of the metal pads are slanted. 3. The printed circuit board of claim 2, wherein the cross-sectional area of the metal pad increases from one surface to the other surface of the metal pad. further comprising a first circuit formed on one surface of the first insulating layer;
The printed circuit board according to any one of claims 1 to 3, wherein the side surface of the first circuit is slanted. 5. The printed circuit board according to claim 1, further comprising a second circuit formed on the other surface of said first insulating layer. 6. The printed circuit board of claim 5, wherein the plated via and the second circuit include a seed layer underneath. 7. The printed circuit board of claim 1, further comprising a ground layer formed on the other surface of the first insulating layer. The printed circuit board according to any one of claims 1 to 7, wherein the paste via protrudes from one surface of the second insulating layer. The printed circuit board according to any one of claims 1 to 8, wherein each cross-sectional area of the plated via and the paste via increases outward from the metal pad. The first insulating layer and the second insulating layer are LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), PPE (Polyphenylene Ether), COP (Cyclo Olefin Polymer), PFA (Perfluoroalkoxy), and PI (Polyimide). 10. The printed circuit board according to any one of claims 1 to 9, formed of at least one. a first insulating layer;
a plated via formed through the first insulating layer;
a second insulating layer laminated on the other surface of the first insulating layer;
a paste via formed through the second insulating layer so as to contact the plated via;
A printed circuit board in which a contact interface between the plated via and the paste via is located in the first insulating layer, and a side surface of an end portion of the paste via is in contact with the first insulating layer. 12. The printed circuit board of claim 11, wherein a side surface of an end of the paste via is in contact with the first insulating layer. further comprising a metal pad formed on one surface of the first insulating layer;
the plating via is formed on one surface of the metal pad;
13. The printed circuit board of claim 11, wherein the second insulating layer is laminated on the other surface of the first insulating layer. 14. The printed circuit board of claim 13, wherein the cross-sectional area of the metal pad increases from one surface to the other surface of the metal pad. further comprising a first circuit formed on one surface of the first insulating layer;
15. The printed circuit board of claim 13 or 14, wherein the side surface of the first circuit is slanted. 16. The printed circuit board of any one of claims 13 to 15, further comprising a second circuit formed on the other surface of the first insulating layer. 17. The printed circuit board of claim 16, wherein the plated via and the second circuit include a seed layer underneath. 18. The printed circuit board of any one of claims 13 to 17, further comprising a ground layer formed on the other surface of the first insulating layer. the cross-sectional area of the plated via increases from the bottom surface toward the contact interface,
The cross-sectional area of the paste via increases from the upper surface toward the interface between the first insulating layer and the second insulating layer, and extends from the interface between the first insulating layer and the second insulating layer to the contact interface. 19. A printed circuit board according to any one of claims 11 to 18, wherein the printed circuit board is as small as . The first insulating layer and the second insulating layer are LCP (Liquid Crystal Polymer), PTFE (Polytetrafluoroethylene), PPE (Polyphenylene Ether), COP (Cyclo Olefin Polymer), PFA (Perfluoroalkoxy), and PI (Polyimide). 20. A printed circuit board as claimed in any one of claims 11 to 19 formed of at least one.

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