CN112312650A

CN112312650A - Fine interlayer circuit structure and its manufacturing method

Info

Publication number: CN112312650A
Application number: CN201910710497.9A
Authority: CN
Inventors: 李家铭
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-08-02
Filing date: 2019-08-02
Publication date: 2021-02-02

Abstract

The application provides a fine interlayer circuit structure, which comprises a substrate circuit board, an insulating layer, a second circuit layer and a conductive paste layer, wherein the substrate circuit board is provided with a first circuit layer, the first circuit layer is positioned at the topmost layer of the substrate circuit board, the insulating layer covers the first circuit layer, the insulating layer is provided with a plurality of windows, one part of the first circuit layer is exposed from the windows, the second circuit layer is formed on the top surface of the insulating layer, and the conductive paste layer is filled in the windows, so that the first circuit layer and the second circuit layer are electrically connected through the conductive paste layer; wherein, no copper plating layer is formed on the wall of the opening.

Description

Fine interlayer circuit structure and its manufacturing method

Technical Field

The present invention relates to a circuit board structure, and more particularly, to a structure having a fine interlayer circuit and a method for fabricating the same.

Background

As the circuit design of 3C devices is refined, the requirements for the fineness of the carrier board lines thereof are also increased. The existing circuit carrier plate relates to a structure electrically linked between layers, an insulating layer between two layers of circuits is drilled, a copper plating layer is filled in a via hole by electroplating in the subsequent process, and the surface circuit layer after electroplating is brushed and ground in the subsequent process.

Disclosure of Invention

Accordingly, the present disclosure is directed to a circuit structure and a method for fabricating the same that facilitates high inter-layer circuit fineness and yield.

In order to achieve the above and other objects, the present application provides a fine interlayer circuit structure, which includes a substrate circuit board, an insulating layer, a second circuit layer and a conductive paste layer, wherein the substrate circuit board has a first circuit layer, the first circuit layer is located at the topmost layer of the substrate circuit board, the insulating layer covers the first circuit layer, the insulating layer has a plurality of windows, a portion of the first circuit layer is exposed from the windows, the second circuit layer is formed on the top surface of the insulating layer, and the conductive paste layer is filled in the windows, so that the first circuit layer and the second circuit layer are electrically connected through the conductive paste layer; wherein, no copper plating layer is formed on the wall of the opening.

In order to achieve the above and other objects, the present application also provides a method for fabricating a fine interlayer wiring structure, comprising:

providing a substrate circuit board, wherein the substrate circuit board is provided with a first circuit layer, and the first circuit layer is positioned at the topmost layer of the substrate circuit board;

laminating an insulating layer with copper foil on the top surface of the first circuit layer;

forming a plurality of windowing areas on the copper foil, and forming a plurality of windowing areas on the insulating layer, wherein the windowing areas correspond to the windowing areas respectively, so that a part of the first circuit layer is exposed from the windowing areas; and

filling conductive paste in the windows to form a conductive paste layer, so that the first circuit layer and the copper foil are electrically connected through the conductive paste layer; after the insulating layer is formed into the windows, the hole walls of the windows are not plated with copper.

The application utilizes the conductive paste to replace a copper plating layer which is commonly used in a via hole of a conventional circuit structure, so that the circuits between layers can form electric connection under the condition that the thickness of the top surface circuit layer is not influenced, therefore, the copper plating hole and the surface brushing process in the existing process can be omitted, the thickness of the top surface circuit layer is thinner, the circuit fineness can be improved, the thickness is uniform, the yield can be obviously improved, and the possibility of mass production is realized.

Further details regarding other functions and embodiments of the present application are described below with reference to the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic cross-sectional view of one embodiment of a fine interlayer circuit structure according to the present invention;

FIG. 2 is a schematic cross-sectional view of another embodiment of a fine interlayer circuit structure according to the present application;

fig. 3 to 7 are schematic views illustrating a process of fabricating a fine interlayer circuit structure according to an embodiment of the present invention.

Description of the symbols

10 substrate circuit board 11 base material

12 first line layer 20 insulating layer

21-window 30 second circuit layer

30A copper foil 31 fenestration area

40 conductive paste layer 50 plating layer

Detailed Description

Referring to fig. 1, an embodiment of a fine interlayer circuit structure of the present invention is shown, which comprises a substrate circuit board 10, an insulating layer 20, a second circuit layer 30, a conductive paste layer 40 and a plating layer 50.

In the present embodiment, the substrate circuit board 10 is a single-layer board structure, and has a base material 11 and a first circuit layer 12 located at the topmost layer, where the first circuit layer 12 is, for example, a copper layer. In other possible embodiments, the substrate wiring board may also be a multilayer board with multiple wiring layers.

The insulating layer 20 covers the first circuit layer 12, and the insulating layer 20 has a plurality of windows 21, a portion of the first circuit layer 12 is exposed from the windows 21, and no copper plating layer is formed on the walls of the windows 21, i.e., the windows 21 are not processed by chemical plating or electroplating. The insulating layer 20 is, for example, BT resin (bismalemide Triazine), FR-4 epoxy resin, polyimide, or other substrate material, dielectric material or solder resist material commonly used in circuit boards, and in the process, the insulating layer 20 may have photo-imageable (photo-imageable) properties.

The second circuit layer 30 is formed on the top surface of the insulating layer 20, and the second circuit layer 30 is a copper layer, preferably having a thickness of less than 5 μm, so that a fine circuit can be formed.

The conductive paste layer 40 is filled in the windows 21, so that the first and

second circuit layers

12 and 30 are electrically connected via the conductive paste layer 40, and the electrical conductivity thereof is preferably lower than 1.0 × 10^-4Ω · cm, the conductive paste layer 40 is formed using, for example, a conductive silver paste or a conductive copper paste.

In a possible embodiment, the second circuit layer 30 may be used for surface mounted devices (surface mounted devices), in which case the second circuit layer 30 may also have the plating layer 50 formed on the top surface thereof, the plating layer 50 may be, for example, a nickel/gold plating layer commonly referred to as "soft gold", and the plating layer 50 is not a copper layer. In other possible embodiments as shown in fig. 2, the second circuit layer 30 may also be an inner layer circuit of other multi-layer circuit boards, and the surface mount component does not need to be mounted on the second circuit layer 30, in which case the plating layer may be omitted.

The process of the foregoing embodiment is explained below with reference to fig. 3 to 7.

As shown in fig. 3, first, a substrate circuit board 10 is provided, in this embodiment, the substrate circuit board 10 is exemplarily shown as a single-layer board structure having a base material 11 and a first circuit layer 12, such as a copper layer, located at the topmost layer, and the first circuit layer 12 can be made of the copper layer by performing a conventional patterning process according to a desired circuit design.

As shown in FIG. 4, the insulating layer 20 with the copper foil 30A is pre-disposed on the top surface layer-top surface of the first circuit layer 12 by using a vacuum press, the thickness of the copper foil 30A is less than 5 μm, the insulating layer 20 is a photo-imageable resin, and the insulating layer 20 is not cured by irradiation with light during lamination.

As shown in fig. 5, a plurality of open windows 31 are formed in the copper foil 30A, and the specific method may be to attach a thin photoresist layer on the copper foil 30A, expose and develop the photoresist layer, etch the copper not covered by the photoresist layer, and finally remove the photoresist layer, so as to expose the local insulating layer 20 from the open windows 31. The insulating layer 20 after the window 21 is formed and a necessary post-curing process may be performed.

As shown in fig. 6, the insulating layer 20 is etched to remove the exposed portions of the windows 31, so as to form a plurality of windows 21 in the insulating layer 20, which correspond to the windows 31, respectively, and further expose a portion of the first circuit layer 12 from the windows 21.

As shown in fig. 7, a conductive paste, such as a conductive silver paste or a conductive copper paste, is filled in the windows 21 by a dispenser to form a conductive paste layer 40, so that the first circuit layer 12 is electrically connected to the copper foil 30A; before the conductive paste is filled, the hole walls of the windows 21 are not subjected to copper plating, including chemical copper plating and electrolytic copper plating, so that the thickness of the copper foil 30A is not increased by the copper plating. In other possible embodiments, after the conductive paste layer 40 is formed, a metal layer may be additionally formed on the top surface of the conductive paste layer 40, for example, a copper layer formed by electroplating, but the copper layer is not in contact with the wall of the opening 21. In a possible embodiment, the top surface of the conductive paste layer 40 is flush with the top surface of the copper foil 30A.

Finally, the copper foil 30A is patterned into a second wiring layer 30, and an electroless plating layer 50 such as an electroplating nickel/gold layer is formed on the second wiring layer as necessary, to have the structure shown in FIG. 1. In a possible embodiment, the second circuit layer 30 and the conductive paste layer 40 can be covered with a solder mask (not shown) before the formation of the plating layer 50, without forming the plating layer 50.

In the foregoing process, the opening 21 is filled with the conductive paste before the copper foil 30A is patterned, but in other possible embodiments, the copper foil 30A may be patterned into the second circuit layer before the opening 21 is filled with the conductive paste.

In the above process, the formation of the window 31 and the formation of the window 21 are performed in two steps, however, in other possible embodiments, the copper foil 30A and the insulating layer 20 may be simultaneously fired through by a laser engraving machine, and the window 31 and the window 21 may be simultaneously formed in one processing station.

In summary, the present application replaces the commonly used copper plating layer in the via hole of the conventional circuit structure with the conductive paste, so that the circuit between layers can be electrically connected without affecting the thickness of the top circuit layer, and thus, the copper plating hole and the surface brushing process in the existing process can be omitted, the thickness of the top circuit layer is thinner, the fineness of the circuit can be improved, the thickness is uniform, the yield can be significantly improved, and the possibility of mass production is provided.

The above-described embodiments and/or implementations are only illustrative of the preferred embodiments and/or implementations for implementing the technology of the present application, and are not intended to limit the implementations of the technology of the present application in any way, and those skilled in the art can make many changes or modifications to the equivalent embodiments without departing from the scope of the technology disclosed in the present application, but should still be considered as the technology or implementations substantially the same as the present application.

Claims

1. A fine interlayer wiring structure comprising:

the substrate circuit board is provided with a first circuit layer, and the first circuit layer is positioned at the topmost layer of the substrate circuit board;

an insulating layer covering the first circuit layer, the insulating layer having a plurality of windows, a portion of the first circuit layer being exposed from the windows;

a second circuit layer formed on the top surface of the insulating layer; and

a conductive paste layer filled in the windows to electrically connect the first and second circuit layers;

wherein, no copper plating layer is formed on the walls of the windows.

2. The fine interlayer wiring structure according to claim 1, wherein the thickness of the second wiring layer is less than 5 μm.

3. The fine interlayer wiring structure of claim 1, wherein the conductive paste layer has a conductivity of less than 1.0 x 10^-4Ω·cm。

4. The fine interlayer wiring structure as claimed in claim 1, wherein a non-copper plating layer is further formed on the top surface of the second wiring layer.

5. A method for manufacturing a fine interlayer wiring structure, comprising:

an insulating layer with copper foil on the top surface is combined with the top surface of the first circuit layer;

filling conductive paste in the windows to form a conductive paste layer, so that the first circuit layer and the copper foil are electrically connected through the conductive paste layer;

and after the insulating layer forms the windows, the hole walls of the windows are not subjected to copper plating treatment.

6. The method of claim 5, wherein the copper foil is patterned into a second circuit layer before the windows are filled with the conductive paste layer.

7. The method of claim 5, wherein the copper foil is patterned into a second circuit layer after the windows are filled with the conductive paste layer.

8. The method of manufacturing a fine interlayer wiring structure according to claim 5, wherein the copper foil and the second wiring layer have a thickness of less than 5 μm.

9. The method for producing a fine interlayer wiring structure according to claim 5, wherein the conductive paste layer has a conductivity of less than 1.0 x 10^-4Ω·cm。

10. The method for manufacturing a fine interlayer wiring structure according to claim 5, wherein a non-copper plating layer is further formed on the top surface of the second wiring layer.