KR100468195B1 - A manufacturing process of multi-layer printed circuit board - Google Patents

Abstract

The present invention shows a method for manufacturing a multilayer printed circuit board capable of via-on-via and at the same time facilitates high-density mounting by embedding a resistor inside the printed circuit board. That is, it has at least one internal via penetrating the electrical insulation layer, and the internal via forms bump-on vias to minimize the generation of heat and to achieve ultra-high density, miniaturization, and light weight, and at the same time internal or external circuit There is at least one resistor (resistance) inside the substrate and the resistor (resistance) is lower than vias formed through the circuit wiring or the insulating layer of the circuit board. Internal via formation has an advantage of minimizing heat generated by filling conductive paste or electrical insulator in the via hole by forming the bumps.

Description

A manufacturing process of multi-layer printed circuit board

The present invention realizes via-on-via due to bumps during the process of forming a multilayer by a method of manufacturing a multilayered printed circuit board by stacking a plurality of printed circuit boards, and at the same time, passive resistance such as resistance inside the multilayer circuit board. The present invention relates to a method for manufacturing a multilayer printed circuit board which enables high density mounting of a substrate by embedding electronic components.

BACKGROUND OF THE INVENTION In the current manufacturing method of a multilayer printed circuit board, various methods for implementing via-on-via by bump formation using various manufacturing processes have been developed due to the demand for high-density mounting, miniaturization, and weight reduction of the inside and outside of the substrate. In addition, as part of efforts to achieve ultra-high density, miniaturization, and ultra-light weight at this point, the manufacturing method of directly embedding passive electronic components such as resistors and kephasity has been developed in the multilayer printed circuit board. Coming. However, current technology is limited to simply manufacturing methods of multilayer printed circuit boards by via-on-via or to multilayer printed circuit boards by embedding passive electronic components. Since the technology of each other is not implemented at the same time, ultra-high density, ultra-miniaturization, ultra-lightweight, etc. are facing limitations. At present, some inventors have proposed a method of simultaneously implementing a multi-layer printed circuit board by via-on-via and internal mounting of passive electronic components. However, since the manufacturing method is complicated and in the via-on-via forming method, the inside of the via hole is mainly filled by the conductive paste, the smaller the size of the via hole, the smaller the size of the via hole may cause voids to occur in the hole.

Accordingly, in order to solve the above-mentioned problems, a multilayered resin multilayer substrate having an inner via via structure electrically connecting arbitrary layers and a printed circuit board using interlayer connection through fine bumps have been devised. On the other hand, as the conductor pattern gradually becomes finer, the via filling method of filling the via hole with copper plating has been attracting attention as an excellent method in terms of process and connection reliability.

Current via filling techniques include a method of electrically conducting via holes and then filling the inside of the via holes using an insulating resin or a conductive paste. However, when using this method, voids are generated inside the via hole, the surface is dented, and the thermal expansion coefficient difference between the metal and the insulating resin adversely affects the connection reliability and lowers the electrical conductivity. There is a problem. Therefore, the via hole filling method for filling the inside of the via hole with metal copper in the process of becoming increasingly finer wiring enables via-on-via (or stack-via) to further increase the density of printed circuit wiring. Since it is also stable in terms of connection reliability, its application is further expanded. As the filling method of the via hole, a method of filling the via hole through electroplating has been widely applied. However, even when the via hole is filled through the electroplating technology, there is a problem that voids are generated in the via hole even when the via hole is not filled or the filling is made. In addition, in order to remove such voids, the operation must be performed at a low current density of 1.5 A / dm ² or less. In this case, it takes a lot of plating time, which makes it difficult to apply the production site. In addition, it is difficult to easily apply due to the high working conditions and high incidence of defects.

Therefore, in order to solve the above-mentioned problems and at the same time to realize ultra-high density, ultra-light weight, miniaturization, and simplification of electronic component assembly, a multilayer printed circuit board through stable via-on-via is realized, and at the same time, the registration of the resistor inside the substrate is performed. There is an urgent need for technology that can be embedded.

Therefore, in order to solve the above-mentioned problems, the interlayer connection is formed without affecting the height ratio (aspect ratio = height / diameter) to the diameter of the internal via to improve connection reliability and at the same time register the resistor inside the printed circuit board. It is an object of the present invention to provide a method for producing a multilayer printed circuit board which can be formed to be extremely high in density, light in weight, and small in size.

1 is a cross-sectional view showing a substrate for a multilayer printed circuit board used in manufacturing a multilayer printed circuit board according to an embodiment of the present invention in the order of the manufacturing process.

2 is a cross-sectional view showing a sequence diagram of a manufacturing process of a substrate for a multilayer printed circuit board used to manufacture a multilayer printed circuit board according to another embodiment of the present invention.

3 is a cross-sectional view of a multilayer printed circuit board according to an exemplary embodiment of the present invention.

4 is a cross-sectional view of a multilayer printed circuit board according to an exemplary embodiment of the present invention.

The object of the present invention is to bond copper foil to one side or both sides of the resin film according to the purpose, to form bumps through copper plating and etching for interlayer connection by via-on-via, and simultaneously through electroless nickel plating It is achieved by a method for manufacturing a multilayer printed circuit board in which a resistor is embedded in the printed circuit board.

Hereinafter, the present invention will be described in more detail with reference to the following examples, but the scope of the present invention is not limited thereto.

Example 1

Hereinafter, various preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Manufacturing Process Diagram I for Multilayer Printed Circuit Boards (FIG. 1)

1 is a cross-sectional view showing a substrate for a multilayer printed circuit board used in manufacturing a multilayer printed circuit board according to an embodiment of the present invention in the order of a manufacturing process.

First, as shown in FIG. 1 (a), the copper foil 2 having a thickness of about 5 to 40 µm is adhered to both sides of the epoxy resin or the polyimide resin 1 of various thicknesses (adhesive on the epoxy resin or the polyimide resin). Copper foil is not limited to both sides but may be glued to only one side depending on the application.)

Next, as shown in (b), the dry film 3 is bonded with a vacuum laminator or a roll laminator on the copper foil bonded to the resin film. Then, as shown in (c), the circuit pattern is exposed on the dry film 3 and developed.

Next, as shown in (d), the copper foil 2 is etched using the dry film 3 as a mask to form a predetermined circuit pattern. Then, the dry film on the copper foil is peeled off as shown in (e), and the copper circuit pattern 2 is exposed.

Next, as shown in (f), the electrode is electrodeposited to have a thickness of about 0.1 μm to 5.0 μm using the electroless nickel plating 4 over the entire circuit board. Next, as shown in 5 of (g), the electrode is electrodeposited to have a thickness of about 10 μm to 50 μm using the electrolytic copper plating 5 on the nickel surface 4.

Next, as shown in (6) of (h), the dry film 6 is bonded with a vacuum laminator or a roll laminator on the copper foil formed by the electroplating 5. As shown in 6 of (i), the development is performed after exposing the remaining parts except for the part where the circuit is to be formed and the part where the interlayer connection by bump is to be made.

Next, as shown in (j), the copper plating layer 5 is etched using the dry film 6 as a mask to form a circuit.

Next, as shown in (k), the electroless nickel plating layer 4 is etched and removed except for the portion where the bump is to be formed and the portion where the resistor is to be formed. Then, the dry film on the copper foil is peeled off as shown in (l), and the copper circuit pattern 5 is exposed.

Next, as shown in (m), the dry film 7 is bonded to the entire surface of the printed circuit board by a vacuum laminator or a roll laminator. Next, as shown in (n), bumps are formed to expose the portions to be made between the layers, and then develop.

Next, as shown in (o), electrodeposition is performed using electrolytic gold plating, electroless gold plating, electrolytic tin, electroless tin, electrolytic tin / lead alloy plating, etc. using the metal resistor 8 as an etching resistor. Gold plating can be used as an etching resistor if its thickness is about 0.1 to 2 µm, about 0.5 to 4.0 µm for electroless tin, and about 5.0 to 18.0 µm for electrolytic tin and tin / lead alloys. (Etching resistors used in (8) of (o) can be other metals as well as those mentioned above.)

Next, the dry film is peeled off as shown in (p) and the bumps are formed by etching the copper surface except for a portion in which bumps are formed as shown in (5) (q) to form an interlayer connection.

As shown in (r), the metal resistors are peeled off to form circuit wiring and bumps.

The epoxy resin (9) is coated as shown in the following (s) and brushed to ensure the interlayer connection reliability so that the upper layer of the bump appears.

Next, as shown in (t), electroless copper plating is performed after electroless copper plating on the entire surface of the substrate as in (10) to form a multilayer circuit board. The thickness of the electroplating is about 5 ~ 40㎛ depending on the application.

The following process is repeated by repeating the steps (b) to (t) of FIG. 1 according to the number of layers of the multilayer circuit board.

3 is a cross-sectional view of a multilayer printed circuit board completed by the process of FIG. 1 or 2 above.

Manufacturing Process Diagram II for Multilayer Printed Circuit Board (FIG. 2)

2 is a cross-sectional view showing a substrate for a multilayer printed circuit board used in manufacturing a multilayer printed circuit board according to an embodiment of the present invention in the order of a manufacturing process.

First, (a) to (m) of FIG. 2 use the same manufacturing process as those of (a) to (m) of FIG. 1.

Next, as shown in (7) of (n), bumps are formed to expose the portions to be made between the layers, and then develop.

Next, as shown in (5) of (o), bumps are formed to form bumps by etching the copper surface except for the portion where the interlayer connection is to be made.

Next, as shown in (p), the dry film is peeled off to form circuit wiring and bumps.

As shown in the following (q), the epoxy resin 9 is coated and brushed so that the upper layer of the bumps appears to secure the interlayer connection reliability.

Next, as shown in (r), in order to form a multilayer circuit board, electroless copper plating is performed as in (10) to impart electrical conductivity to the entire surface of the substrate, followed by electroplating. The thickness of the electroplating is about 5 ~ 40㎛ depending on the application.

In the following process, if the multilayer circuit board is manufactured by repeating (b) to (r) of FIG. 1 according to the number of layers of the multilayer circuit board, the interlayer connection by via-on-via is made inside the multilayer printed circuit board and at the same time, the register Can be implemented at the same time.

4 is a cross-sectional view of another multilayer printed circuit board completed by the process of FIG. 1 or 2 above.

As described above, according to the present invention, a built-in resistor of a multilayer printed circuit board capable of high reliability, ultra high density, ultra light weight, and miniaturization can be provided.

Claims (6)

Bonding copper foil to one or both sides of the resin film; Etching the copper foil on the formed copper plating resin film to form a circuit pattern; Removing a dry film after forming the circuit pattern; Forming an electroless nickel plating on the circuit pattern; Electroplating the electroless nickel layer; Etching the remaining portions, except for portions to form bumps, internal circuits, and resistors; Forming a dry film for bump formation for via-on-via; And A method of manufacturing a multilayer printed circuit board comprising forming a resistor by forming a bump using a dry film as an etching register and simultaneously exposing an electroless nickel plating layer on a circuit pattern. delete 2. The multilayer printing according to claim 1, wherein the etching register uses a metal resistor selected from the group consisting of electrolytic gold plating, electroless gold plating, electrolytic tin, electroless tin, and electrolytic tin / lead alloy plating in addition to the dry film. Method of manufacturing a circuit board. The method of claim 1, further comprising coating an epoxy resin on the formed bumps and resistors and brushing the upper layers of the bumps to ensure interlayer connection reliability. 5. The method of claim 4, further comprising electroplating the electroless plating after electroless copper plating is applied to the entire surface of the substrate to form a via-on-via. Way. 6. The method of claim 5, wherein the step is repeated according to the number of layers of the multilayer circuit board.