JP2001156455A - Multilayer printed wiring board and manufacturing method for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board together with its manufacturing method wherein a current stably flows even when an operation frequency or electric-power quantity increases by suppressing fluctuation in tolerable current regardless of form, oxidized state, etc., of wiring comprising a conductor circuit. SOLUTION: A build-up wiring layer is provided wherein an upper-layer conductor circuit is electrically insulated from a lower-layer conductor circuit with an inter-layer resin insulating layer, while they are electrically connected through many via holes. Here, among the many via holes 10 and 20, at least a part of via holes is provided with a resistor 6. The resistor is provided in the via hole by selectively masking a part of many openings while the surface of inter-layer resin insulating layer comprising an opening which is not masked is electroless-plated or sputtered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board having a build-up wiring layer, and more particularly, to disposing a resistor in a part of an opening for forming a via hole in an interlayer resin insulating layer. Then, a multilayer printed wiring board with excellent electrical connectivity that can suppress variations in current input from a semiconductor element such as an IC chip to a conductor circuit and withstand increases in operating frequency, electric power, and the like is proposed.

[0002]

2. Description of the Related Art In recent years, as the frequency of a signal has been increased, it has been required that the material characteristics of a package substrate have a low dielectric constant and a low dielectric loss tangent. And the mainstream is shifting. Against this background, techniques relating to a printed wiring board using a resin substrate include, for example, Japanese Patent Publication No. 4-555.
There is one disclosed in Japanese Patent Application Publication No. 55-55. In this document, an interlayer resin insulating layer is formed using epoxy acrylate on a glass epoxy substrate on which an inner conductor circuit is formed, and then a via hole forming opening is provided using a photolithographic technique, and the surface is formed. There has been proposed a method of forming an outer conductor circuit and a via hole by performing a roughening process, providing a plating resist, and then performing a plating process.

[0003] However, the surface of the interlayer resin insulation layer made of a resin such as epoxy acrylate and the surface of the conductor circuit must be roughened in order to ensure adhesion to the conductor circuit. For this reason, when a high-frequency signal is propagated, there is a problem that the skin effect causes propagation only on the surface portion of the roughened conductor circuit, and noise is generated in the signal due to the unevenness of the surface. This problem was particularly remarkable when a resin substrate having a lower dielectric constant and a lower dielectric loss tangent than a ceramic substrate was used.

[0004] Further, the resin substrate has a lower heat radiation property than the conductor substrate and the ceramic substrate, and thus easily stores heat. As a result, the diffusion speed of copper ions constituting the conductor circuit increases, causing migration and causing interlayer insulation. Was destroyed. Therefore, in order to solve the above-described problems, a resin such as a resin is applied on one side of a substrate by spin coating or the like, and a metal (chromium, A technique of providing nickel, titanium, etc.) has been proposed in JP-A-7-45948 and JP-A-7-94865.

[0005]

However, it has been desired to reduce the size of the printed wiring board on which the IC is mounted, and to reduce the size of the entire device such as a mobile phone equipped with such a printed wiring board. In today's situation, the area for mounting electronic components such as resistors and capacitors other than IC chips is small, and it is increasingly difficult to mount those electronic components on a printed wiring board.

Therefore, in order to obtain a high-density printed wiring board having a wiring width of 50 μm or less, various heat treatments, annealing treatments, chemical treatments such as acid treatment, and the like are required, and wirings including conductor circuits are required. In this case, variations occur in the shape of the metal, the oxidation state of the metal, and the shape of the interlayer insulating layer. Since the current flowing through the wiring having such a variation also varies, and the allowable current fluctuates,
There is a limit to the amount of current flowing in the circuit. For this reason, when the operating frequency, the amount of electric power, and the like are increased, a problem such as a malfunction does occur.

[0007] The present invention has been made to solve the above-mentioned problems of the prior art, and its main objects are as follows.
It is an object of the present invention to provide a multilayer printed wiring board that operates normally even when the operating frequency and the amount of power increase, regardless of the state of the wiring, while suppressing the fluctuation of the allowable current. It is another object of the present invention to provide a multilayer printed wiring board in which a resistor is provided in at least a part of via holes in a build-up wiring layer. Yet another object of the present invention is to propose a method by which such a multilayer printed wiring board can be advantageously manufactured.

[0008]

Means for Solving the Problems The inventors of the present invention have conducted intensive studies for realizing the above-mentioned object, and as a result, among a number of via holes in a build-up wiring layer, at least a part of the via holes is provided with a resistor. By connecting the upper-layer conductor circuit and the lower-layer conductor circuit through the resistor, the fluctuation of the allowable current is eliminated, and even if the operating frequency and the electric energy are increased, it is found that the circuit operates normally. The present invention has been conceived of the invention having the following content as a gist configuration.

(1) That is, in the multilayer printed wiring board of the present invention, the upper conductive circuit and the lower conductive circuit are electrically insulated by the interlayer resin insulating layer, and the conductive circuits are separated from each other.
In a multilayer printed wiring board having a build-up wiring layer electrically connected to each other through a number of via holes formed in an interlayer resin insulating layer, at least a part of the plurality of via holes has a resistor. Is provided. The resistor is A
It is desirable to be formed from at least one metal selected from l, Fe, W, Mo, Sn, Ni, Co, Cr, Ti and a noble metal, and the thickness is desirably 15 μm or less.

(2) In the method for manufacturing a multilayer printed wiring board according to the present invention, the upper conductive circuit and the lower conductive circuit are electrically insulated by an interlayer resin insulating layer, and the conductive circuits are separated from each other by an interlayer resin insulating layer. In manufacturing a multilayer printed wiring board having a build-up wiring layer electrically connected to each other through a large number of via holes formed in an insulating layer, at least the following steps (1) to (3) during the manufacturing process, namely, the interlayer resin Forming a large number of openings from one surface of the insulating layer to the lower conductive layer; selectively masking some of the large number of openings, and electrolessly forming an interlayer resin insulating layer surface including the unmasked openings; Forming a thin-film resistor by plating or sputtering; releasing the masking; and masking the opening in which the thin-film resistor is formed. Forming a via hole including a thinned conductor layer by applying electroless copper plating or copper sputtering to the surface of the interlayer resin insulating layer including the masked opening, and plating resist on the thinned conductor layer. Forming a thick conductor layer by applying electrolytic copper plating to a portion where the plating resist is not formed. After peeling and removing the plating resist, an electroless copper plating layer or a copper sputter layer under the plating resist and a thin film A step of removing the resistor by etching to form an independent conductor circuit, a via hole, and a via hole in which the resistor is provided. In the above manufacturing method, the resistor is made of Al, Fe, W, Mo,
It is desirable to be formed from at least one metal selected from Sn, Ni, Co, Cr, Ti and a noble metal. Further, the thickness of the resistor is desirably 15 μm or less. Further, Cu, P
Other metals such as d may be laminated, and the total thickness including this metal layer is preferably around 20 μm.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a printed wiring board according to the present invention, a resistor is provided in at least a part of a via hole formed in an interlayer resin insulation layer of a build-up wiring layer, and an upper layer is formed via the resistor. The conductor circuit is connected to a lower conductor circuit. According to such a configuration, it is possible to obtain a printed wiring board in which an allowable current does not change and a current can flow stably irrespective of the wiring shape and the degree of oxidation.

Further, the resistor is made of Al, Fe, W, M
It is desirable to be formed from at least one metal selected from o, Sn, Ni, Co, Cr, Ti and a noble metal. The reason is that by using a transition metal, the adhesion between the resistor and the electrolytic copper plating film or the copper sputter layer and the adhesion between the resistor and the interlayer resin insulating layer can be improved.

The resistance-resistance temperature characteristics of the resistor embedded in the via hole include the thickness of the thin film, the diameter of the via hole,
The thickness is determined depending on the interlayer thickness, the type of the resistor, and the like, and the thickness is particularly preferably 15 μm or less, particularly preferably 10 μm or less. The reason for this is that if the thickness exceeds 15 μm, the role as a resistor is hardly exhibited, and it is difficult to form an interlayer resin insulating layer or a solder resist layer on the upper layer, and peeling may occur.

Further, another metal such as Cu or Pd can be laminated on the resistor, and the total thickness including the metal layer is preferably about 20 μm. like this
When a two-layer structure is adopted, Al, Fe, W, Mo, S
n, Ni, Co, Cr, Ti and C other than the noble metal layer
When an upper conductive circuit is formed of a metal having relatively good conductivity such as u or Ag, the upper conductive circuit needs to be completely removed by etching. The reason for this is that if it remains, it can conduct through the upper layer, making it difficult for electricity to flow to the lower conductor circuit, and because it only flows locally, it will not serve as a resistance function. is there.

Hereinafter, one method of manufacturing the multilayer printed wiring board of the present invention will be described. (1) First, a wiring board having an inner copper pattern formed on the surface of a resin substrate is manufactured. As the resin substrate, a resin substrate having inorganic fibers is desirable, and specifically, at least one or more selected from a glass cloth epoxy substrate, a glass cloth polyimide substrate, a glass cloth bismaleimide-triazine resin substrate, and a glass cloth fluororesin substrate Is good. The formation of the copper pattern on the resin substrate is performed by etching a copper-clad laminate having copper foil on both sides of the resin substrate.

(2) A resin insulating layer is formed on both sides of the wiring board manufactured in (1). This resin insulating layer functions as an interlayer resin insulating layer of the multilayer printed wiring board. This resin insulating layer can be coated with an uncured liquid (uncured resin),
It is formed by laminating a film-like resin by hot pressing.

(3) Next, the resin insulating layer is provided with a large number of openings for forming via holes for ensuring electrical connection with the conductor circuit on the substrate. The perforation of this opening is performed by laser light. At this time, a laser beam used includes a carbon dioxide gas laser, an ultraviolet laser, an excimer laser, a UV laser, and the like. When a hole is formed by the CO ₂ laser beam, desmear processing is performed. This desmearing treatment can be performed using an oxidizing agent composed of an aqueous solution such as chromic acid or permanganate, or may be treated with oxygen plasma, mixed plasma of CF ₄ and oxygen, corona discharge, or the like. .
The surface can also be modified by irradiating ultraviolet rays using a low-pressure mercury lamp. In particular, a mixed plasma of CF ₄ and oxygen can introduce a hydrophilic group such as a hydroxyl group or a carbonyl group on the resin surface, and can be used for CVD or PV afterwards.
This is advantageous because D processing is easy.

(4) A metal layer as a resistor is formed in some of the many openings provided in the step (3). At this time, openings other than the openings for disposing the resistors are previously covered with an etching resist or the like. The resistor is made of at least one metal selected from metals in Groups 4A to 1B and in the fourth to seventh periods, and is formed by plating, PVD or CVD. As a plating method, electroless plating is used, and as a PVD method,
Specific examples include vapor deposition methods such as sputtering and ion beam sputtering. As the CVD method, PE-CVD using an organic metal (MO) such as allylcyclopentadiphenylpalladium, dimethylgold acetylacetate, tin tetramethylacrylonitrile, or dicobalt octacarbonylacrylonitrile as a supply material
(Plasma Enhanced CVD).

(5) Next, the masking of the opening covered in (4) is released, and the opening in which the resistor layer is formed is covered with an etching resist.
A thin conductive layer is formed on the surface of the interlayer resin insulating layer including the masked opening by electroless copper plating or copper sputtering to provide a thin conductive layer. The thickness of the thin conductor layer is desirably 10 μm or less.
Further, when the conductor layer is formed by sputtering, a similar type of electroless plating layer may be formed on the sputtered layer. As the electroless plating, copper plating is optimal, and its thickness is desirably in the range of 0.1 to 2 μm. The reason for this is that etching can be removed without impairing the function of the electroplating performed later as a conductive layer.

(6) Next, a plating resist is formed on the thin conductor layer formed in (5). This plating resist is exposed by laminating a photosensitive dry film,
It is formed by developing.

(7) Next, using the conductor layer obtained in the step (5) as a plating lead, electroplating is applied to a portion where no plating resist is formed, and an electroplating film is provided to form a conductor circuit. At the same time as providing the conductor layer to be formed, the inside of the opening is filled with a plating film to form a via hole.

(8) After the plating resist is peeled off and removed, it is formed in the step (5) under the plating resist with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate. Dissolve and remove the thin conductor layer. As the method, there is a method of controlling an etching amount that can remove the conductor layer, or a method of using an etching solution that can remove only a specific conductor. The etching is performed by a normal etching method such as immersion or spraying. As a result, the thin conductor layer under the plating resist is completely removed, and a printed wiring board having a resistor disposed in some of the many via holes is obtained.

(9) Next, the above steps (2) to (8) are repeated to provide another via hole in which a resistor is buried just above the via hole and to form an upper layer further outside the conductor circuit. Provide a conductor circuit. The surface of the via hole is formed on a conductor pad functioning as a solder pad.

(10) Next, a solder resist composition is applied to the outer surface of the wiring substrate thus obtained, and the coating film is dried. Then, a photomask film having an opening is drawn on the coating film. An opening exposing a solder pad (including a conductive pad and a via hole) in the conductive layer is formed by mounting, exposing, and developing. here,
The opening diameter of the opening to be exposed can be larger than the diameter of the solder pad, and the solder pad may be completely exposed. Conversely, the opening diameter of the opening can be smaller than the diameter of the solder pad, and the periphery of the solder pad can be covered with a solder resist layer. In this case, the solder pads can be suppressed by the solder resist layer, and peeling of the solder pads can be prevented.

(11) Next, a "nickel-gold" metal layer is formed on the solder pad exposed from the opening. The nickel layer preferably has a thickness of 1 to 7 μm, and the gold layer has a thickness of 0.01 to 0.06 μm. The reason for this is that if the nickel layer is too thick, the resistance value will increase, and if it is too thin, it will easily peel off. On the other hand, if the gold layer is too thick, the cost increases, and if it is too thin, the effect of adhering to the solder body decreases.

(12) Further, a solder body is supplied onto the solder pad portion exposed from the opening to manufacture a six-layer multilayer printed wiring board. As a method of supplying the solder body, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening, thereby forming a solder pattern to form a solder carrier film. This is a method of applying a flux to a solder resist opening portion of a substrate, laminating a film so that a solder pattern is in contact with a pad, and heating and transferring the film.
On the other hand, the printing method is a method in which a printing mask (metal mask) having a through-hole provided in a portion corresponding to a pad is placed on a substrate, and a solder paste is printed and heat-treated.

In the above description, the semi-additive method is used as a method for forming a conductor circuit, but a full-additive method may be used. In the full additive method, a thin film resistor layer is formed by CVD or PVD processing in a part of the via hole forming openings formed in the resin insulating layer, and the remaining other of the via hole forming openings is formed. After forming a sputtered copper layer in the opening by CVD or PVD processing, laminating a photosensitive dry film or applying a liquid photosensitive resin, exposing and developing to provide a plating resist, electroless A thick conductor layer is formed by plating to form a conductor circuit.

Hereinafter, a detailed description will be given based on embodiments.

EXAMPLE 1 A bismaleimide-triazine (BT) resin substrate 1 having a conductive circuit 2 formed on the surface thereof (FIG. 1)
(A)), copper sulfate 8 g / l, nickel sulfate 0.
6 g, citric acid 15 g / l, sodium hypophosphite 29
g / l, boric acid 31 g / l, surfactant 0.1 g / l, immersed in an electroless plating solution having a pH of 9 and made of copper-nickel-phosphorus having a thickness of 3 μm on the surface of the conductor circuit 2. The roughened layer 3 was formed. Next, the substrate was washed with water.
A 0.3 μm tin layer was provided on the surface of the roughened layer 3 by immersing it in an electroless tin displacement plating bath composed of 1 mol / l tin borofluoride-1.0 mol / l thiourea solution at 50 ° C. for 1 hour. (See FIG. 1 (b), but the tin layer is not shown).

(2) Next, an interlayer resin insulating layer 4 is formed on the substrate 1 obtained in the above (1). On both sides of the substrate 1,
A 50 μm-thick thermosetting polyolefin resin sheet (Sumitomo 3M, trade name: 1592) is heated and pressed at a pressure of 9.8 × 10 ⁵ Pa while the temperature is raised to a temperature of 50 to 180 ° C., and laminated. (See FIG. 1 (c)).

(3) A large number of via hole forming openings are formed in the interlayer resin insulating layer 4 formed in (2). Using a carbon dioxide laser having a wavelength of 10.4 μm, the resin insulating layer 4 made of the polyolefin resin obtained in (2) above has a diameter of 80 mm.
An opening 5 for forming a via hole of μm was provided (see FIG. 1C). Further, the desmear and the surface of the resin were modified by plasma treatment with a mixed gas of CF ₄ and oxygen. By this modification, OH groups, carbonyl groups, CO 2
A hydrophilic group such as an OH group was confirmed. The oxygen plasma processing conditions are as follows: power 800 W, degree of vacuum 66.5 Pa, processing time 20 minutes.

(4) A Ni metal layer 6 as a resistor is formed in some of the many openings 5 provided in the step (3) by sputtering. The openings other than the openings for disposing the resistors are previously covered with a mask M1 made of an etching resist or the like, and sputtering using nickel as a target is performed at a pressure of 0.6 Pa, a temperature of 80 ° C.
The operation was performed under the conditions of electric power of 200 W and time of 5 minutes to form a nickel thin film on the surface of the (polyolefin-based) resin insulating layer 4. At this time, the thickness of the formed nickel sputter layer 6 was 0.1 μm. Further, a 0.1 μm-thick copper sputtered layer was formed on the nickel sputtered layer 6 under the same sputtering conditions. In addition, SV-4540 manufactured by Japan Vacuum Engineering Co., Ltd. was used as a sputtering apparatus.

(5) Next, the masking M1 of the opening covered in the above (4) is released, and the opening in which the resistor layer is formed is covered with a mask M2 made of an etching resist or the like. On the surface of the interlayer resin insulating layer including the opening where the opening is released, a copper sputtered layer 7 is formed by copper sputtering using the same apparatus as in the above (4), and a thin conductor layer is provided. At this time, the sputtering was performed at a pressure of 0.8 Pa, a temperature of 80 ° C., and a power of 200.
W was performed under the conditions of a sputtering time of 5 minutes, and the thickness of the formed copper sputtered layer 7 was 0.1 μm.

(6) Further, the mask M2 of the above (5) is released, and plating resists are provided on both surfaces of the substrate 1 on which the thin conductor layer made of the copper sputtered layer 7 is formed. A photosensitive dry film is stuck on the copper sputter layer 7, a photomask film is placed thereon, and exposed at 100 mJ / cm ² ,
It was developed with 0.8% sodium carbonate to provide a plating resist 8 having a thickness of 15 μm (see FIG. 2A).

(7) Next, under the following conditions, the plating resist
Electrolytic copper plating is applied to the part where no strike is formed.
At the same time that the electrolytic copper plating film 9 is provided,
The via hole 10 was formed by filling with the plating film 9. [Electrolytic plating aqueous solution] Copper sulfate pentahydrate: 60 g / l Leveling agent (HL, manufactured by Atotech): 40 ml / l Sulfuric acid: 190 g / l Brightener (UV, manufactured by Atotech): 0.5 ml / l Chloride ion: 40 ppm [Electroplating conditions] Bubbling: 3.0 L / min Current density: 0.5 A / dm²  Set current value: 0.18A Plating time: 130 minutes

(8) Next, after the plating resist 8 is peeled off and removed, the electroless plating film 7 under the plating resist is dissolved with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate. Remove it,
A thickness of about 2 consisting of the electroless plating film 7 and the electrolytic copper plating film 9
The upper conductive circuit 11 having a thickness of 0 μm and L / S = 25 μm / 25 μm was formed. At this time, a nickel sputtered layer 6 as a resistor is formed in some of the via holes 10.
The surface of these via holes 10 was flat, and the level of the surface of the upper-layer conductive circuit 11 was the same as that of the surface of the via hole 10. By such an etching process, the Ni sputtered layer 6 as a resistor is formed between the lower conductive circuit 2 and the upper conductive circuit 11. (See FIG. 2 (b)).

(9) The roughened layer 3 is formed on the substrate obtained in the above (8) in the same manner as in the above (1), and the above processes (4) to (8) are repeated to form the via holes 10 and In the outer layer of the conductor circuit 11, a via hole 20 in which a nickel sputtered layer 6 as a resistor was buried and a conductor circuit 21 were formed to manufacture a printed wiring board (FIG. 2C).
reference).

(10) On the other hand, 60 dissolved in DMDG
Of cresol nopolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) of 50% by weight, and sensitized oligomer (molecular weight 4000) obtained by acrylated 50% of the epoxy group.
80% by weight bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, Epicoat 1)
001) 14.121 parts by weight, imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals) 1.6 parts by weight, polyvalent acrylic monomer which is a photosensitive monomer (Nippon Kayaku, R6
04) 1.5 parts by weight, 30 parts by weight of a polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, DPE6A) and 0.36 parts by weight of a leveling agent made of an acrylate ester polymer (manufactured by Kyoeisha, Polyflow No. 75) were also mixed. Penzophenone (Kanto Chemical Co., Ltd.) 2 as a photoinitiator
0 parts by weight, EAB as photosensitization rate (Hodogaya Chemical)
0.2 parts by weight, and 10 parts by weight of DMDG (diethylene glycol dimethyl ether) were further added to adjust the viscosity to 2 parts.
A solder resist composition adjusted to 1.4 ± 0.3 Pa · S at 5 ° C. was obtained. The viscosity was measured with a B-type viscometer (Tokyo Keiki, DVL-B type) using a rotor No. 3 at 60 rpm and a rotor No. 3 at 46 rpm.

(11) The solder resist composition obtained in (10) was applied to both sides of the multilayer wiring board obtained in (9) in a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick soda lime glass substrate on which a circular pattern (mask pattern) of the solder resist opening is drawn by a chromium layer, The side on which the chromium layer was formed was brought into close contact with the solder resist layer, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development. Further, at 80 ° C., 1
Time, 1 hour at 100 ° C, 1 hour at 120 ° C, 150 ° C
And a heat treatment under the condition of 3 hours, the solder resist layer 22 (thickness 2
0 μm) (see FIG. 3A).

(12) Next, the substrate on which the solder resist layer 22 was formed was replaced with nickel chloride 30 g / 1, sodium hypophosphite 10 g / 1, sodium citrate 10 g / 1.
Immersed in an electroless nickel plating solution having a pH of 5 for 20 minutes to form a nickel plating layer 24 having a thickness of 5 μm on the opening.
Was formed. Further, the substrate was placed on an electroless gold plating solution composed of gold cyanide 2 g / 1, ammonium chloride 75 g / 1, sodium citrate 50 g / 1, and sodium hypophosphite 10 g / 1 at 93 ° C. for 23 hours. By dipping for 2 seconds, a gold plating layer 25 having a thickness of 0.03 μm was formed on the nickel plating layer 24.

(13) The solder resist layer 22
Solder paste was printed in the opening of the substrate and reflowed at 200 ° C. to form a solder bump (solder body) 26, thereby manufacturing a single-sided three-layer multilayer printed wiring board having the solder bump (FIG. 3B). reference).

(Example 2) In the step (4) of Example 1, instead of forming the Ni metal layer 6 by sputtering, it was formed by electroless nickel plating under the following conditions. In step 5), a single-sided, three-layer multilayer printed wiring board was formed in the same manner as in Example 1 except that the thin conductor layer was formed by electroless copper plating under the following conditions instead of being formed by sputtering. Was manufactured.

[Aqueous solution of electroless nickel plating] NiSO ₄ 0.1 mol / l PdCl ₂ 0.001 mol / l NaH ₂ PO ₂ 0.1 mol / l Na ₃ C ₆ H ₅ O ₇ 0.3 mol / l (NH ₄ ) SO ₄ 0.5 mol / l thiodiglycolic acid 10 mg / l pH = 10 [Electroless plating conditions] 20 minutes at a liquid temperature of 50 ° C

[Aqueous solution of electroless copper plating] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating Conditions] 30 minutes at 70 ° C liquid temperature

(Comparative Example) This is almost the same as Example 1, except that
A multilayer printed wiring board in which a nickel layer as a resistor was not formed in the via hole was obtained.

With respect to the printed wiring boards manufactured in Examples 1 and 2 and Comparative Example, in Examples 1 and 2, wiring defects and voids during circuit formation were confirmed, but a voltage was applied. There is no variation in the resistance and current value in the conductor circuit at the time, and the IC chip is mounted.
Even after confirming the operation, it worked normally. In the comparative example, the resistance in the conductor circuit when a voltage was applied,
There is variation in the current value.
In some cases, it did not work properly even after checking the operation.

[0046]

As described above, according to the present invention,
A resistor is buried in a part of the via hole forming opening in the build-up wiring layer, and the lower conductor circuit and the upper conductor circuit are electrically connected via the resistor. Provided is a multilayer printed wiring board capable of suppressing fluctuations in allowable current and stably supplying current even when the operating frequency or the amount of electric power increases, regardless of the shape or oxidation state of wiring including Can be.

[Brief description of the drawings]

FIGS. 1A to 1E are views showing a part of a manufacturing process of a multilayer printed wiring board according to a first embodiment of the present invention.

FIGS. 2 (a) to 2 (c) are views showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 3A and 3B are diagrams showing a part of the manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 substrate 2 copper foil 3 roughened layer 4 interlayer resin insulating layer 5 opening for via hole 6 nickel sputtered layer (resistor) 7 copper sputtered layer (thinned conductor layer 8 plating resist 9 electrolytic copper plated layer 10, 20 via hole 11, DESCRIPTION OF SYMBOLS 21 Conductor circuit 22 Solder resist layer 24 Nickel plating layer 25 Gold plating layer 26 Solder bump

Claims (4)

[Claims] An upper conductor circuit and a lower conductor circuit are electrically insulated by an interlayer resin insulation layer, and the conductor circuits are electrically connected to each other through a number of via holes formed in the interlayer resin insulation layer. A multilayer printed wiring board having a build-up wiring layer connected thereto, wherein a resistor is disposed in at least a part of the plurality of via holes. 2. The method according to claim 1, wherein the resistor is made of Al, Fe, W, Mo,
2. The multilayer printed wiring board according to claim 1, wherein the multilayer printed wiring board is formed of at least one metal selected from Sn, Ni, Co, Cr, Ti and a noble metal. 3. An upper conductive circuit and a lower conductive circuit are electrically insulated from each other by an interlayer resin insulating layer, and the conductive circuits are electrically connected to each other via a number of via holes formed in the interlayer resin insulating layer. In manufacturing a multilayer printed wiring board having a build-up wiring layer that is connected, during the manufacturing process, at least the following steps, i.e., a number of openings reaching the lower conductive layer from one surface of the interlayer resin insulating layer. Forming, selectively masking a part of the plurality of openings, and forming a thin film resistor by electroless plating or sputtering on the surface of the interlayer resin insulating layer including the unmasked openings; At the same time, the opening in which the thin-film resistor is formed is masked, and the interlayer tree including the masked opening is removed. Forming a via hole including a thinned conductor layer by applying electroless copper plating or copper sputtering to the surface of the resin insulating layer, providing a plating resist on the thinned conductor layer, and electrolytic copper plating on a portion where the plating resist is not formed Forming a thick conductor layer by peeling off the plating resist, removing the electroless copper plating layer or copper sputter layer and the thin film resistor under the plating resist by etching, and forming an independent conductor. Forming a circuit, a via hole, and a via hole in which a resistor is provided. A method for manufacturing a multilayer printed wiring board, comprising: 4. The resistor is made of Al, Fe, W, Mo, S
The method for manufacturing a multilayer printed wiring board according to claim 3, wherein the method is formed of at least one metal selected from n, Ni, Co, Cr, Ti and a noble metal.