JPH10190224A - Multilayer printed wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain adhesion between a via hole and a lower-layer conductor circuit and prevent cracking in an interlayer insulating layer during heat cycle, by forming the via hole from an electroless plating film and an electrolytic plating film, and forming a roughened layer on the surface of an area where the lower-conductor circuit is in contact with the via hole. SOLUTION: A via hole is formed of an electrolytic plating film 4 and an electroless plating film 3; the electroless plating film 3 is formed in an inner layer and the electrolytic plating film 4 is formed in an outer layer. The electrolytic plating film 4 is softer and more malleable than the electroless plating film 3. If a substrate warps during a heat cycle, therefore, the via hole is capable of following variation in the dimensions of a layer resin insulating layer 6. Further, since the inner portion of the via hole is formed of the harder electroless plating film 3 and the electroless plating film 3 is brought into tight contact with a lower-layer conductor circuit 2 through a roughening layer 5, the electroless plating film 3 does not strip from the lower-layer conductor circuit 2 during a heat cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a method of manufacturing the same, and more particularly, to a multilayer printed wiring board which suppresses cracks during a heat cycle without causing a decrease in peel strength, and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 4-55555. That is, an insulating material made of a photosensitive adhesive for electroless plating is applied on the core substrate, dried, exposed and developed to form an interlayer insulating material layer having a via hole opening. Next, after roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and then electroless plating is performed on a portion where no resist is formed, thereby forming a conductor including via holes. Form a circuit pattern. By repeating such a process a plurality of times, a multilayered build-up wiring board can be obtained.

[0003]

However, in such a multilayer printed wiring board, the conductor circuit is provided in a portion where no plating resist is formed, and the plating resist remains as it is in the inner layer. When an IC chip or the like is mounted, the substrate is warped due to the difference in the coefficient of thermal expansion between the IC chip and the resin insulating layer during a heat cycle, and there is no close contact between the plating resist and the conductor circuit. As a result, cracks occur in the interlayer insulating layer in contact with the boundary.

[0004] In order to solve such a problem, there is a method of removing a plating resist and thereafter providing a roughened layer on the surface of a conductor circuit. For example, JP-A-6-283860
According to the technology described in Japanese Patent Application Laid-Open Publication No. H11-163, a technology is disclosed in which a plating resist of an inner layer is removed, a roughened layer made of copper-nickel-phosphorus is provided on the surface of a conductor circuit made of an electroless plated film, and delamination is prevented. ing. However, cracks may be generated in the interlayer resin insulating layer in contact with the via holes, and a method for suppressing such cracks in the portions in contact with the via holes has been required.

[0005] Even when such cracks are suppressed, it is necessary to ensure the connection between the lower conductor circuit and the via hole. It is an object of the present invention to prevent cracks in an interlayer insulating layer that occur during a heat cycle while maintaining other characteristics, particularly adhesion between via holes and a lower conductor circuit.

[0006]

The gist of the present invention is as follows. In a multilayer printed wiring board in which an interlayer insulating layer is formed on a substrate provided with a lower layer conductor circuit, an upper layer conductor circuit is formed on the interlayer insulation layer, and the upper layer conductor circuit and the lower layer conductor circuit are connected by via holes. Wherein the via hole comprises an electroless plating film and an electrolytic plating film, and the lower conductive circuit has a roughened layer formed on a surface of a portion connected to the via hole. . The roughening layer is made of copper-nickel-phosphorus alloy plating. A lower conductor circuit is formed on a substrate, the surface of the lower conductor circuit is roughened, then an interlayer insulating layer is provided on the substrate, a hole for a via hole is formed in the interlayer insulating layer. After applying electroless plating on the insulating layer, providing a plating resist, applying electrolytic plating, removing the plating resist, and etching to form an upper conductor circuit and a via hole composed of an electroless plating film and an electrolytic plating film A method for manufacturing a multilayer printed wiring board. The roughened layer is formed by copper-nickel-phosphorus alloy plating.

The via holes are formed of an electrolytic plating film and an electroless plating film, an electroless plating film is formed on the inner layer side, and an electrolytic plating film is formed on the outer layer side (see FIGS. 18 and 19). (See enlarged view). The electrolytic plating film is softer and more malleable than the electroless plating film, so that even if the substrate warps during a heat cycle, the via hole can follow the dimensional change of the interlayer resin insulating layer, and the inner layer side of the via hole Is formed of a harder electroless plating film, and the electroless plating film adheres to the lower conductor circuit via the roughened layer, so that there is no separation from the lower conductor circuit during a heat cycle.

It is preferable that the metal layer into which the roughened layer enters is hard. This is because breakage in the metal layer hardly occurs when a force of peeling is applied. When the via hole is composed of only the electrolytic plating film, the electrolytic plating film itself is soft and easily peeled off by a heat cycle even when the via hole is in close contact with the lower conductor circuit via the roughened layer. Further, when the via hole is formed only of the electroless plating film, it cannot cope with a dimensional change of the interlayer resin insulating layer, and a crack occurs in the interlayer resin insulating layer on the via hole.

As described above, in the present invention, the via hole is formed by the electrolytic plating film and the electroless plating film, and the via hole is connected to the lower conductive circuit via the roughened layer. Cracking of the upper interlayer resin insulation layer and separation of the via hole from the lower conductive circuit can be prevented at the same time. In the present invention, a roughened layer may be provided on the surface of the via hole. It adheres firmly to the interlayer resin insulation layer, and the conductor circuit more easily follows the dimensional change of the interlayer resin insulation layer.

For this reason, an IC chip is mounted and the temperature is -55 ° C.
Even when a heat cycle test of up to 125 ° C. is performed, the occurrence of cracks in the interlayer resin insulating layer starting from the conductor circuit can be suppressed, and no peeling is observed.

In the present invention, the lower conductor circuit connected to the via hole is preferably composed of an electroless plating film and an electrolytic plating film. Further, an electroless plating film is provided on the inner layer side, and an electrolytic plating film is provided on the outer layer side. Since the inner layer side of the lower conductor circuit comes into close contact with the interlayer resin insulation layer, a harder electroless plating film is desirable to secure the peel strength, and the opposite side is connected to the via hole so that the electrolytic layer which is excellent in follow-up to dimensional change is connected. Plating film is desirable. When the interlayer resin insulating layer is roughened, it is preferable that the plating film which is hard to be roughened is harder. The reason for this is that when a peeling force is applied, destruction is less likely to occur at the plating film portion.

The roughened surface in the present invention may be formed not only at the portion connected to the via hole but also over the entire lower conductor circuit. This is because the adhesion to the interlayer insulating layer is excellent. The roughening layer in the present invention is an etching process,
It is desirable that the surface be a roughened surface of copper formed by polishing treatment, oxidation treatment, or oxidation-reduction treatment or a roughened surface formed by plating film. Particularly, the roughened layer is made of copper-nickel-
It is desirable that the alloy layer is made of phosphorus.

The composition of the alloy layer is 90 to 96 wt%, 1 to 5 wt%, 0.5 to 2 wt% in terms of copper, nickel and phosphorus, respectively.
Desirably, it is wt%. This is because these compositions have a needle-like structure at these composition ratios.

It should be noted that Cu-Ni-
The composition of P is shown in a ternary triangular diagram (FIG. 18). (C
u, Ni, P) = (100,0,0), (90,10,
0) and (90, 0, 10).

The oxidizing treatment is desirably a solution of an oxidizing agent comprising sodium chlorite, sodium hydroxide and sodium phosphate. Further, the oxidation-reduction treatment is performed by immersing the substrate in a solution of sodium hydroxide and sodium borohydride after the oxidation treatment.

The thickness of the roughened layer is preferably 1 to 5 μm. If the thickness is too large, the roughened layer itself is easily damaged and peeled off, and if the thickness is too small, the adhesiveness is reduced.

The thickness of the electroless plating film is 1 to 5 μm.
Is good. If it is too thick, the ability to follow the interlayer resin insulation layer will be reduced, and if it is too thin, the peel strength will decrease.If electrolytic plating is performed, the resistance will increase, and the thickness of the plating film will vary. It is because.

The thickness of the electrolytic plating film is 10 to
20 μm is preferred. If it is too thick, the peel strength will decrease,
This is because if it is too thin, the ability to follow the interlayer resin insulating layer is reduced.

In the present invention, it is desirable that a roughened layer is formed on at least the side surface. This is because cracks generated in the interlayer resin insulation layer due to the heat cycle are caused by poor adhesion between the side surfaces of the conductor circuit and the resin insulation layer.

In the present invention, it is desirable to use an adhesive for electroless plating as an interlayer resin insulating layer constituting the wiring board. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly subjected to the curing treatment include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 10 μm or less and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
It is desirable to use at least one selected from pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder. . This is because they can form more complex anchors.

Next, one method of manufacturing a printed wiring board according to the present invention will be described. (1) First, a wiring board having an inner layer copper pattern formed on the surface of a core board is manufactured. The copper pattern is formed on the core substrate by etching a copper-clad laminate, or by forming an adhesive layer for electroless plating on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate. The surface of the adhesive layer is roughened to a roughened surface, and the surface is subjected to electroless plating, or the entire surface is subjected to electroless plating, plating resist formation, electrolytic plating, plating resist removal, etching treatment, and electroplating. There is a method of forming a conductor circuit made of an electrolytic plating film.

Further, a roughened layer made of copper-nickel-phosphorus is formed on the lower conductive circuit surface of the wiring board. The roughened layer is formed by electroless plating. As the plating solution composition, the copper ion concentration, the nickel ion concentration, and the hypophosphite ion concentration were 2.2 × 10 ^{−2 to} 4.1 × 1 respectively.
0 ^-2 mol / l, 2.2 × 10 ^{-3 to} 4.1 × 10 ^-3 mo
1 / l, and preferably 0.20 to 0.25 mol / l. This is because the crystalline structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating bath in addition to the above compounds.

Other methods of forming the roughened layer include the above-described oxidation-reduction treatment and a method of forming a roughened surface by etching the copper surface along grain boundaries. Note that a through hole is formed in the core substrate, and the wiring layer on the front surface and the back surface can be electrically connected through the through hole. In addition, resin may be filled between the through-holes and the conductor circuits of the core substrate to ensure smoothness (FIGS. 1 to 1).
(Fig. 4).

(2) Next, an interlayer resin insulating layer is formed on the wiring board manufactured in the above (1). In particular, in the present invention, it is desirable to use the above-described adhesive for electroless plating as an interlayer resin insulating material (FIG. 5).

(3) After the formed adhesive layer for electroless plating is dried, openings for forming via holes are provided as necessary. In the case of a photosensitive resin, it is exposed and developed and then thermally cured. In the case of a thermosetting resin, it is thermally cured and then subjected to laser processing, so that an opening for forming a via hole is formed in the adhesive layer. Parts are provided (FIG. 6).

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent to roughen the surface of the adhesive layer (FIG. 7).
Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and it is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.
On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, a catalyst nucleus is applied to the wiring board whose surface of the adhesive layer is roughened. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Next, electroless plating is applied to the surface of the adhesive for electroless plating to form an electroless plating film on the entire roughened surface (FIG. 8). The thickness of the electroless plating film is 1 to 5 μm,
More preferably, it is 2-3 μm. Next, a plating resist is formed on the electroless plating film (FIG. 9). As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak or a phenol novolak type epoxy resin and an imidazole curing agent, but other commercially available products can also be used.

(7) Next, electrolytic plating is applied to the portion where the plating resist is not formed to form a conductor circuit and a via hole (FIG. 10). Here, it is desirable to use copper plating as the electroless plating.

(8) After removing the plating resist, the electroless plating film is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate to form an independent conductor circuit. (FIG. 11).

(9) Next, a roughened layer is formed on the surface of the conductor circuit (FIG. 12). Examples of the method of forming the roughened layer include an etching process, a polishing process, an oxidation-reduction process, and a plating process.
The oxidation-reduction treatment includes NaOH (10 g / l), NaClO
₂ (40 g / l) and Na ₃ PO ₄ (6 g / l) in an oxidation bath (blackening bath), NaOH (10 g / l), NaBH ₄ (5 g / l).
g / l) is used as a reducing bath. When forming a roughened layer of a copper-nickel-phosphorus alloy layer, it is deposited by electroless plating.

The electroless plating solution of this alloy includes copper sulfate 1 to 40 g / l and nickel sulfate 0.1 to 6.0 g / l.
l, citric acid 10-20 g / l, hypophosphite 10-1
00g / l, boric acid 10-40g / l, surfactant 0.
It is desirable to use a plating bath having a liquid composition of from 01 to 10 g / l.

(10) Next, an adhesive layer for electroless plating is formed on this substrate as an interlayer resin insulating layer (FIG. 1).
3). (11) Further, the steps (3) to (8) are repeated to provide a further upper layer conductor circuit (FIGS. 14 to 17).

(12) Next, the coating film of the solder resist composition is dried, and a photomask film having an opening formed thereon is placed on the coating film and exposed and developed to thereby form a conductive circuit. An opening exposing the pad portion is formed. Here, the opening diameter of the opening may be larger than the diameter of the pad, and the pad may be completely exposed.

(11) Next, a metal layer of "nickel-gold" is formed on the pad portion exposed from the opening.

(12) Next, a solder body is supplied onto the pad portion exposed from the opening. As a method of supplying the solder body, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening portion to form a solder pattern to form a solder carrier film. Is applied to a solder resist opening portion of a substrate, and then laminated such that a solder pattern is in contact with a pad, which is heated and transferred. On the other hand, the printing method is a method in which a metal mask having a through-hole provided at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heated.

[0038]

【Example】

(Example 1) (1) 0.6 mm thick glass epoxy resin or BT
A starting material was a copper-clad laminate in which 18 μm copper foil was laminated on both sides of a substrate 1 made of (bismaleimide triazine) resin. The copper foil of this copper-clad laminate was etched in a pattern according to a conventional method, drilled, and subjected to electroless plating to form a lower conductor circuit 2 and through holes on both surfaces of the substrate. Further, bisphenol F type epoxy resin was filled between the lower conductor circuits and in the through holes.

(2) The substrate on which the inner layer copper pattern is formed in the above (1) is washed with water and dried, and then the substrate is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid. To provide a Pd catalyst,
After activating this catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating was performed in an electroless plating bath having a pH of 9 to form a roughened layer 5 (uneven layer) of Cu-Ni-P alloy having a thickness of 2.5 µm on the entire surface of the copper conductor circuit.

(3) 70 parts by weight of a 25% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), polyether sulfone (PES) 30
Parts by weight, imidazole curing agent (Shikoku Chemicals, trade name: 2E
4MZ-CN) 4 parts by weight, caprolactone-modified tris (acryloxyethyl) isocyanurate (trade name: Aronix M325) manufactured by Toagosei Co., Ltd., a photosensitive monomer, benzophenone (Kanto Chemical) 5 as a photoinitiator
Parts by weight, 0.5 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer, and 35 parts by weight of an epoxy resin particle having an average particle size of 5.5 μm with respect to this mixture.
After mixing 5 parts by weight of 0.5 μm, they are mixed while adding NMP (normal methylpyrrolidone), adjusted to a viscosity of 12 Pa · s with a homodisper stirrer, and then kneaded with three rolls to form a photosensitive adhesive. An agent solution (interlayer resin insulating material) is obtained.

(4) The photosensitive adhesive solution obtained in the above (3) is applied to both surfaces of the substrate after the treatment in the above (2) using a roll coater, and left in a horizontal state for 20 minutes. From
Drying was performed at 60 ° C. for 30 minutes to form an adhesive layer 6 having a thickness of 60 μm. (5) A photomask film having via holes drawn thereon was placed on both surfaces of the substrate on which the adhesive layer 6 was formed in (4) above, and was exposed to ultraviolet light.

(6) The exposed substrate was spray-developed with a DMTG (triethylene glydimethyl ether) solution to form an opening serving as a 100 μmφ via hole in the adhesive layer. Furthermore, the substrate is super-high pressure mercury lamp
Exposure at 3000mJ / cm ² , 1 hour at 100 ℃, then 150 ℃
By performing the heat treatment for 5 hours, a 50 μm-thick adhesive layer having an opening (opening for forming a via hole) having excellent dimensional accuracy equivalent to a photomask film was formed. Note that the roughened layer is partially exposed in the opening serving as the via hole.

(7) The substrate on which the opening for forming a via hole is formed in (5) and (6) is immersed in chromic acid for 2 minutes.
The surface of the adhesive layer was roughened by dissolving and removing the epoxy resin particles present on the surface of the adhesive layer, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. (8) By applying a palladium catalyst (manufactured by Atotech) to the substrate that has been subjected to the surface roughening treatment (roughening depth: 5 μm) in the above (7), a catalyst is formed on the surface of the adhesive layer and the opening for the via hole. A nucleus was provided.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 3 having a thickness of 3 μm on the entire rough surface. Electroless plating solution EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l Electroless plating conditions 30 at a liquid temperature of 70 ° C. Minute

(10) A commercially available photosensitive dry film is stuck on the electroless copper plating film, and a mask is placed on the film.
Exposure at mJ / cm ² and development processing with 0.8% sodium carbonate provided a plating resist 7 having a thickness of 15 μm.

(11) Then, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 4 having a thickness of 15 μm. Electrolytic plating solution Copper sulfate 180 g / l Copper sulfate 80 g / l Additive (trade name: Capalaside G, manufactured by Adtech Japan)
L) 1 ml / l electroplating conditions Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(12) After stripping and removing the plating resist 7 with 5% KOH, etching is performed with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless plating film 3 is dissolved and removed to form an electroless copper plating film and an electrolytic copper plating. An 18 μm-thick conductor circuit (including a via hole) made of the film 4 was formed.

(13) The substrate on which the conductor circuit was formed was coated with copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g / l.
1, sodium hypophosphite 29 g / l, boric acid 31 g / l,
The surface was immersed in an electroless plating solution having a pH of 9 containing 0.1 g / l of a surfactant to form a roughened layer 5 made of copper-nickel-phosphorus having a thickness of 3 μm on the surface of the conductor circuit. The roughened layer 5 is
Analysis by PMA (X-ray fluorescence analyzer) revealed that Cu9
The composition ratio was 8 mol%, Ni 1.5 mol%, and P 0.5 mol%.

(14) By repeating the steps (4) to (12), a conductor circuit in a further upper layer was formed.

(15) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) in which 60% by weight of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was acrylated with 50% of epoxy groups, 15.0 g of 80% by weight bisphenol A epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, 1.6 imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN) 1.6
g, 3 g of a polyacrylic monomer which is a photosensitive monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), 1.5 g of a polyacrylic monomer (trade name: DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.) (Trade name: S-65), 0.71 g, and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer. In addition, the viscosity
A solder resist composition adjusted to 2.0 Pa · s at 25 ° C. was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL
-B type) in case of 60rpm, rotor No.4 and in case of 6rpm, rotor No.3.

(16) Solder resist composition on substrate
It was applied in a thickness of 20 μm. (17) Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the substrate was exposed to ultraviolet light of 1000 mJ / cm ² and developed by DMTG. In addition, 1 hour at 80 ° C, 1 hour at 100 ° C,
Heat treatment at 120 ° C for 1 hour, 150 ° C for 3 hours,
A solder resist layer (thickness: 20 μm) having a pad portion opened (opening diameter: 200 μm) was formed.

(18) Next, the substrate on which the solder resist layer was formed was treated with a nickel chloride 30 g / l, sodium hypophosphite 10 g / l, sodium citrate 10 g / l
It was immersed in an electroless nickel plating solution of H = 5 for 20 minutes to form a nickel plating layer 13 having a thickness of 5 μm at the opening. Further, the substrate was treated with potassium gold cyanide 2 g / l, ammonium chloride 75 g / l, sodium citrate 50 g / l,
The nickel plating layer 13 was immersed in an electroless gold plating solution containing 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds.
A gold plating layer having a thickness of 0.03 μm was formed thereon.

(19) Solder paste was printed on the opening of the solder resist layer and reflowed at 200 ° C. to form solder bumps, thereby producing a printed wiring board having solder bumps.

Example 2 Basically the same as Example 1, but roughening was performed by etching. An etching solution having a trade name of "Durabond" manufactured by Mec Co. was used.

(Comparative Example) (1), (2),
After the processes (3), (4), (5), (6), (7), and (8), a dry film photoresist was laminated, and a plating resist was formed by exposure and development. Then, after performing (9) of Example 1, the plating resist is peeled off in the same manner as in the process of (12), and the process of (13) is performed to roughen the entire surface of the conductor circuit. Example 1 After insulating layer, roughening, formation of plating resist, electroless copper plating, and peeling of plating resist, Example 1
(15), (16), (17), (18), (1
By the process of 9), a printed wiring board having solder bumps was manufactured.

An IC chip was mounted on each of the printed wiring boards manufactured in Examples and Comparative Examples, and a heat cycle test was performed at -55 ° C. for 15 minutes, at room temperature for 10 minutes, and at 125 ° C. for 15 minutes.
000 times and 2000 times. In Examples and Comparative Examples, the occurrence of cracks in the interlayer resin insulating layer on the via holes was confirmed with a scanning electron microscope. Similarly, the presence or absence of separation between the via hole and the lower conductor circuit was confirmed.

[0057]

[Table 1]

[0058]

As described above, according to the printed wiring board of the present invention, cracks generated in the interlayer resin insulating layer on the via holes during the heat cycle and peeling of the via holes from the lower conductive circuit are simultaneously suppressed. Thus, connection reliability can be improved.

[Brief description of the drawings]

FIG. 1

FIG. 17 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 18 is an enlarged structural view of a multilayer printed wiring board according to the present invention.

FIG. 19 is an enlarged structural view of a multilayer printed wiring board according to the present invention.

FIG. 20 is a triangular diagram showing the composition of a roughened layer of copper-nickel-phosphorus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Lower conductor circuit 3 Electroless copper plating film 4 Electrolytic copper plating film 5 Roughened layer 6 Interlayer resin insulation layer (adhesive layer for electroless plating) 7 Plating resist 20 Upper conductor circuit

Claims (4)

[Claims] An interlayer insulating layer is formed on a substrate provided with a lower conductive circuit, and an upper conductive circuit is formed on the interlayer insulating layer. The upper conductive circuit and the lower conductive circuit are connected by a via hole. In the multilayer printed wiring board, the via hole includes an electroless plating film and an electrolytic plating film, and the lower conductive circuit is characterized in that a roughened layer is formed on at least a surface connected to the via hole. Multi-layer printed wiring board. 2. The multilayer printed wiring board according to claim 1, wherein the roughening layer is made of copper-nickel-phosphorus alloy plating. 3. A lower conductor circuit is formed on a substrate, a roughening process is performed on at least a portion of the surface of the lower conductor circuit connected to the via hole, and then an interlayer insulating layer is provided on the substrate. Then, a hole for a via hole is formed in the interlayer insulating layer, and further, after performing electroless plating on the interlayer insulating layer, providing a plating resist, performing electrolytic plating, removing the plating resist, and etching. A method for manufacturing a multilayer printed wiring board, comprising forming an upper conductive circuit and a via hole comprising an electroless plating film and an electrolytic plating film. 4. The method according to claim 3, wherein the roughening layer is formed by copper-nickel-phosphorus alloy plating.