JP2000133940A - Multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board, where a conductor layer and an interlayer resin insulating layer are prevented from separating from each other, and the interlayer resin insulating layer is protected against cracking under conditions such as heat cycles, high temperature, high pressure, and high humidity. SOLUTION: A latticed conductor layer where a roughened layer 5 is formed on a part of its surface is formed on the board of a multilayer printed wiring board. Therefore, the conductor layer is brought into close contact with the interlayer resin insulating layer through the intermediary of the roughened layer 5. Furthermore, an electroplating film is formed on the outer layer of the latticed conductor layer, and a non-electroplating film is formed in the inner layer of the latticed conductor layer. Therefore, the roughened layer on the surface of the conductor layer gets into the interlayer resin insulating layer, and an electroplating film follows the interlayer resin insulating layer even if the interlayer resin insulating layer expands or shrinks attendant on surrounding conditions such as heat cycles, moisture absorption or dryness. Therefore, the conductor layer is prevented from separating from the interlayer insulating film, and the interlayer resin insulating layer is protected against cracking.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board, and more particularly to a multilayer printed wiring board which does not peel off from an interlayer resin insulating layer and can suppress cracks in the interlayer resin insulating layer.

[0002]

2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 4-55555. That is, an insulating material made of a photosensitive adhesive for electroless plating is applied on the core substrate, dried, exposed and developed to form an interlayer insulating material layer having a via hole opening. Next, after roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and then electroless plating is performed on a portion where no resist is formed, thereby forming a conductor including via holes. Form a circuit pattern. By repeating such a process a plurality of times, a multilayered build-up wiring board can be obtained.

[0003]

However, in such a multilayer printed wiring board, a conductor layer having a large area as a power supply layer or a ground layer is formed on the surface or inner layer of the core base material, and the conductor layer and the surface of the conductor layer have a large area. It has been a general design method to connect the solder pads through a wiring pattern and via holes.

However, when a conductor layer having a large area is formed in the inner layer, the residual solvent in the interlayer resin insulation layer volatilizes during heating and drying, and the conductor layer is pushed up to cause peeling. The applicants have previously proposed in Japanese Patent Application No. Hei 7-150457 that the power supply layer or the ground layer is formed of a grid-like conductor layer to prevent such separation.

However, even when the power supply layer or the ground layer is a grid-like conductor layer, the conductor layer has a larger area than the signal layer and has low adhesion to the interlayer resin insulation layer. In addition, there is a problem that peeling occurs between the conductor layer and the interlayer resin insulation layer under humid conditions, and cracks occur in the interlayer resin insulation layer due to a difference in thermal expansion coefficient between the conductor layer and the interlayer resin insulation layer. .

An object of the present invention is to prevent peeling of a conductive layer from an interlayer resin insulating layer and cracking of the interlayer resin insulating layer under such heat cycle conditions, high temperature, high pressure and high humidity conditions.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a multilayer printed wiring board having a grid-like conductor layer formed on a substrate and a conductor circuit formed on the conductor layer via an interlayer insulating layer. A multilayer printed wiring board, characterized in that a roughened layer is formed on at least a part of the surface of the lattice-shaped conductor layer, and the lattice-shaped conductor layer comprises an electroless plating film and an electrolytic plating film. It is.

The lattice-shaped conductor layer functions as a power supply layer or a ground layer, and a roughened layer is formed on at least a part of the surface of the conductor layer. Adheres closely to resin insulation layer. Therefore, the conductor layer does not peel off from the interlayer resin insulating layer even under heat cycle conditions, high temperature, high pressure, and high humidity conditions.

In particular, when a roughened layer is formed on the side surface of the lattice-shaped conductor layer, cracks generated at the boundary between the conductor layer and the interlayer resin insulation layer due to the difference in thermal expansion coefficient between the two can be suppressed. In addition, since the grid-like conductor layer acts as a power supply layer or a ground layer, a via hole is connected. However, in the present invention, the roughened layer on the grid-like conductor layer surface is formed. Excellent adhesion.

[0010] Further, the grid-like conductor layer is formed as follows. If the conductor layer is a planar conductor layer, the solvent remaining in the resin insulating layer on which the conductor layer is formed volatilizes during heating and drying, and the conductor layer is pushed up. This is because the planar conductor layer swells due to the stress of the plating film. In the case of the lattice shape, there is a portion where the conductor layer is not formed, and the residual solvent in the resin insulating layer can be removed from the portion where the conductor layer is not formed, and the stress of the plating film can be dispersed. There is no blister in the conductor layer.

In the present invention, it is necessary that the lattice-shaped conductor layer comprises an electroless plating film and an electrolytic plating film.
The electrolytic plating film is formed on the outer layer side, and the electroless plating film is formed on the inner layer side (FIG. 16).

The roughened layer on the surface of the conductive layer bites into the interlayer resin insulation layer and firmly adheres thereto, and the soft electrolytic plating film follows even if the interlayer resin insulation layer expands and contracts due to heat cycle, moisture absorption and drying. Therefore, peeling does not occur between the interlayer resin insulating layer and the conductor layer due to heat cycle, moisture absorption, and drying, and no crack occurs in the interlayer resin insulating layer.

In addition, a relatively hard electroless plating film is formed on the insulating layer side, and firmly adheres to the insulating layer. This adhesion is remarkable especially when a roughened surface as described later is formed on the resin insulating layer. The reason is that the hard plating film penetrates the roughened surface, so that even when a peeling force is applied, destruction hardly occurs on the metal side.

The thickness of the electroless plating film is 1 to 5 μm.
Is good. If it is too thick, the ability to follow the interlayer resin insulation layer will be reduced, and if it is too thin, the peel strength will decrease.If electrolytic plating is performed, the resistance will increase, and the thickness of the plating film will vary. It is because.

Further, the thickness of the electrolytic plating film is 10 to
20 μm is preferred. If it is too thick, the peel strength will decrease,
This is because if it is too thin, the ability to follow the interlayer resin insulating layer is reduced.

In the present invention, it is desirable that the lattice-shaped conductor layer has a circular conductor-free portion. This is because there is no corner portion due to the circular shape, and cracks generated from the corner portion as a starting point during a heat cycle can be suppressed.

As the lattice-shaped conductor layer 12 having a circular conductor-free portion, those shown in FIGS. 18A to 18C are preferable. In FIG. 18A, an elliptical conductor non-formed portion 150 is provided. In FIG. 18B, there is a rectangular non-conductor-formed portion 151 in which a radius is formed at each vertex. Also, in FIG. 18C, there is a perfectly circular conductor non-forming portion 152.

In the present invention, the roughened layer formed on the grid-like conductor layer surface is formed by a roughened surface of copper or a plating film formed by etching, polishing, oxidation, or oxidation-reduction. It is desirable that the surface is a roughened surface.

In particular, the roughened layer is preferably an alloy layer made of copper-nickel-phosphorus. This is because the via-hole is connected to the lattice-shaped conductor layer as described above, so that the roughened layer needs to be conductive.

The composition of the alloy layer is 90 to 96% by weight, 1 to 5% by weight, 0.5 to 2% by weight of copper, nickel and phosphorus, respectively.
Desirably, it is wt%. This is because these compositions have a needle-like structure at these composition ratios.

The oxidizing treatment is desirably a solution of an oxidizing agent comprising sodium chlorite, sodium hydroxide and sodium phosphate. Further, the oxidation-reduction treatment is performed by immersing the substrate in a solution of sodium hydroxide and sodium borohydride after the oxidation treatment.

Preferably, the roughened layer has a thickness of 1 to 5 μm. If the thickness is too large, the roughened layer itself is easily damaged and peeled off, and if the thickness is too small, the adhesiveness is reduced. In the present invention, it is desirable to use an adhesive for electroless plating as the interlayer resin insulating layer. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there.

By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface comprising an octopus pot-shaped anchor can be formed on the surface. In the adhesive for electroless plating, particularly as the heat-resistant resin particles subjected to the curing treatment, (a) a heat-resistant resin powder having an average particle diameter of 10 μm or less, and (b) a heat-resistant resin having an average particle diameter of 2 μm or less. Agglomerated particles obtained by aggregating the powder, (c) a mixture of a heat-resistant powder resin powder having an average particle diameter of 10 μm or less and a heat-resistant resin powder having an average particle diameter of 2 μm or less, (d) an average particle diameter of 2 to 10 μm It is desirable to use at least one selected from pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of the heat-resistant resin powder. This is because they can form more complex anchors.

Next, one method of manufacturing a printed wiring board according to the present invention will be described. (1) First, a wiring board having an inner layer copper pattern formed on the surface of a core board is manufactured.

The copper pattern is formed on the core substrate by etching the copper-clad laminate 1 or by applying an adhesive for electroless plating to a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate. After forming a layer, the surface of the adhesive layer is roughened to a roughened surface, and electroless plating is performed on the surface, or the entire surface is subjected to electroless plating, plating resist formation, electrolytic plating, plating resist removal, etching, and electrolytic treatment. There is a method of forming a conductor circuit composed of a plating film and an electroless plating film.

Further, a roughened layer 5 made of copper-nickel-phosphorus is formed on the lower conductor circuit surface of the wiring board. The roughened layer 5 is formed by electroless plating. As the plating solution composition, the copper ion concentration, the nickel ion concentration, and the hypophosphite ion concentration are 2.2 × 10−2 to 4. × 4, respectively.
1 × 10−2 mol / l, 2.2 × 10−3 to 4.1 ×
It is preferably 10-3 mol / l and 0.20 to 0.25 mol / l.

This is because the crystalline structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating bath in addition to the above compounds.

Other methods of forming the roughened layer 5 include the above-described oxidation-reduction treatment and a method of forming a roughened surface by etching the copper surface along grain boundaries. Note that a through hole is formed in the core substrate, and the wiring layer on the front surface and the back surface can be electrically connected through the through hole.

The resin may be filled between the through-holes and the conductor circuits of the core substrate to ensure smoothness (FIGS. 1 to 4). (2) Next, the interlayer resin insulating layer 6 is formed on the wiring board manufactured in the above (1). In particular, in the present invention, it is desirable to use the above-described adhesive for electroless plating as an interlayer resin insulating material (FIG. 5).

(3) After the formed adhesive layer for electroless plating is dried, openings for forming via holes are provided if necessary. In the case of a photosensitive resin, it is exposed and developed and then thermally cured. In the case of a thermosetting resin, it is thermally cured and then subjected to laser processing, so that an opening for forming a via hole is formed in the adhesive layer. Parts are provided (FIG. 6).

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent to roughen the surface of the adhesive layer (FIG. 7).
Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid, and it is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.

On the other hand, it is desirable to use chromic acid or permanganate (such as potassium permanganate) as the oxidizing agent. (5) Next, a catalyst nucleus is applied to the wiring board whose surface of the adhesive layer is roughened.

It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus. Generally, palladium chloride or a palladium colloid is used. In addition,
It is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Next, the surface of the adhesive for electroless plating is subjected to electroless plating to form an electroless plating film 3 on the entire roughened surface (FIG. 8). The thickness of the electroless plating film is 1-5μ
m, more preferably 2-3 μm.

Next, a plating resist 7 is formed on the electroless plating film 3 (FIG. 9). As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak or a phenol novolak type epoxy resin and an imidazole curing agent, but other commercially available products can also be used.

(7) Next, an electrolytic plating film 4 is formed in the portion where the plating resist is not formed, and a conductor circuit and a via hole are provided (FIG. 10). Here, it is desirable to use copper plating as the electroless plating.

(8) After the plating resist is removed, the electroless plating film is dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate to form an independent conductor circuit. I do. At this time, a grid-like conductor layer 11 (a ground layer or a power supply layer) formed in the inner layer is provided (FIG. 11).

(9) Next, the roughened layer 5 is formed on the surfaces of the grid-shaped conductor layer 11, the via hole, and the conductor pattern (FIG. 1).
2). As a method for forming the roughened layer 5, etching treatment,
There are polishing, oxidation-reduction, and plating. The oxidation-reduction treatment is performed by using NaOH (10 g / l), NaClO2 (4
0 g / l), Na3PO4 (6 g / l) in an oxidation bath (blackening bath), NaOH (10 g / l), NaBH4
(5 g / l) is used as a reducing bath.

When forming the roughened layer 5 of a copper-nickel-phosphorus alloy layer, it is deposited by electroless plating. As an electroless plating solution for this alloy, copper sulfate 1-4
0 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l
1, boric acid 10 to 40 g / l, surfactant 0.01 to 1
It is desirable to use a plating bath having a liquid composition of 0 g / l.

(10) Next, an adhesive layer for electroless plating is formed as an interlayer resin insulating layer 6 on this substrate (FIG. 1).
3). (11) Further, the steps (3) to (8) are repeated to provide a further upper conductive circuit, and a grid-like conductive layer functioning as a solder pad and a via hole are formed (FIGS. 14, 1).
5). At this time, a land 14 for forming a solder bump (may be constituted by a via hole like the land 140) can be provided on one surface.

(12) Then, if necessary, a roughening layer is provided on the surface of via holes, lattice-like conductor layers, lands, etc. (FIG. 16). The method of forming the roughened layer is the same as that described in (9).

(13) Next, a solder resist composition is applied to both surfaces of the printed wiring board after the treatment of the above (12). When applying a solder resist layer to both sides of the printed wiring board, the printed wiring board is sandwiched between a pair of application rolls of a roll coater in a state where the printed wiring board is vertically erected, and is conveyed from the lower side to the upper side and the substrate is It is desirable to apply the solder resist composition on both sides simultaneously. The reason for this is that the current basic specifications of printed wiring boards are both sides,
Curtain coat method (flow resin from top to bottom like a waterfall,
This is because the method of applying a substrate by passing it through a “curtain” of resin can only be applied on one side. By setting the viscosity of the solder resist composition to 1 to 10 Pa · s at 25 ° C., the composition does not flow even when the substrate is applied vertically and the transfer is good.

(14) Next, the coating film of the solder resist composition is dried at 60 to 80 ° C. for 5 to 60 minutes, and a photomask film having an opening formed thereon is placed on the coating film to expose and develop. By performing the processing, an opening that exposes the pad portion of the grid-like conductor layer is formed. The land is exposed on the opposite side. The coating film in which the openings are formed in this manner is further cured by a heat treatment at 80 ° C. to 150 ° C. for 1 to 10 hours. Thereby, the solder resist layer having the opening is in close contact with the roughened layer provided on the surface of the conductor circuit.

(15) Next, a metal layer of "nickel-gold" is formed on the solder pads and lands exposed from the openings. (16) Next, a solder body is supplied onto the solder pad exposed from the opening. (FIG. 17). As a method of supplying the solder body, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening portion to form a solder pattern to form a solder carrier film. Is applied to a solder resist opening portion of a substrate, and then laminated such that a solder pattern is in contact with a pad, which is heated and transferred. On the other hand, the printing method is a method in which a metal mask provided with a through hole at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heat-treated.

Hereinafter, description will be made based on embodiments.

[0046]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Example 1) (1) 0.6 mm thick glass epoxy resin or BT
A starting material was a copper-clad laminate in which 18 μm copper foil was laminated on both sides of a substrate 1 made of (bismaleimide triazine) resin. The copper foil of the copper-clad laminate was etched in a pattern according to a conventional method, drilled, and subjected to electroless plating to form an inner conductor circuit 2 and through holes on both surfaces of the substrate.

Further, bisphenol F type epoxy resin was filled between the lower layer conductor circuits and in the through holes. (2) The substrate on which the inner layer copper pattern is formed in the above (1) is washed with water and dried, and then the substrate is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid, After applying a Pd catalyst and activating this catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g /
l, citric acid 15 g / l, sodium hypophosphite 29 g /
1, boric acid 31 g / l, surfactant 0.1 g / l, pH = 9
Is plated in an electroless plating bath made of Cu-Ni-P alloy on the entire surface of the copper conductor circuit.
(Uneven layer) was formed.

(3) 70 parts by weight of 25% acrylate of cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), polyether sulfone (PES) 30
Parts by weight, imidazole curing agent (Shikoku Chemicals, trade name: 2E
4MZ-CN) 4 parts by weight, caprolactone-modified tris (acryloxyethyl) isocyanurate (trade name: Aronix M325) manufactured by Toagosei Co., Ltd., a photosensitive monomer, benzophenone (Kanto Chemical) 5 as a photoinitiator
Parts by weight, 0.5 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer, and 35 parts by weight of an epoxy resin particle having an average particle size of 5.5 μm with respect to this mixture.
After mixing 5 parts by weight of 0.5 μm, they are mixed while adding NMP (normal methylpyrrolidone), adjusted to a viscosity of 12 Pa · s with a homodisper stirrer, and then kneaded with three rolls to form a photosensitive adhesive. An agent solution (interlayer resin insulating material) is obtained.

(4) The photosensitive adhesive solution obtained in the above (3) is applied to both surfaces of the substrate after the treatment in the above (2) using a roll coater, and left in a horizontal state for 20 minutes. From
Drying was performed at 60 ° C. for 30 minutes to form an adhesive layer 6 having a thickness of 60 μm.

(5) A photomask film having via holes drawn thereon was placed on both sides of the substrate on which the adhesive layer 6 was formed in (4) above, and was exposed to ultraviolet rays. (6) The exposed substrate was spray-developed with a DMTG (triethylene glydimethyl ether) solution to form an opening serving as a 100 μmφ via hole in the adhesive layer. Further, the substrate is 3,000 mJ / cm2 using an ultra-high pressure mercury lamp.
Exposure at 100 ° C for 1 hour, and then heat treatment at 150 ° C for 5 hours, resulting in a 50μm thick adhesive with excellent dimensional accuracy equivalent to a photomask film and with openings (openings for forming via holes) An agent layer was formed. In addition,
The roughened layer is partially exposed in the opening serving as the via hole.

(7) The substrate on which the opening for forming a via hole is formed in (5) and (6) is immersed in chromic acid for 2 minutes.
The surface of the adhesive layer was roughened by dissolving and removing the epoxy resin particles present on the surface of the adhesive layer, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

(8) A palladium catalyst (manufactured by Atotech) is applied to the substrate that has been subjected to the surface roughening treatment (roughening depth: 5 μm) in the above (7), so that the adhesive layer and the opening for the via hole are formed. Catalyst nuclei were provided on the surface.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 3 having a thickness of 3 μm on the entire rough surface. Electroless plating solution EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l Electroless plating conditions 30 at a liquid temperature of 70 ° C. (10) A commercially available photosensitive dry film is stuck on the electroless copper plating film, a mask is placed, and 100 mJ / cm 2
And developed with 0.8% sodium carbonate to provide a plating resist 7 having a thickness of 15 μm.

(11) Next, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 4 having a thickness of 15 μm. Electrolytic plating solution Copper sulfate 180 g / l Copper sulfate 80 g / l Additive (trade name: Capalaside G, manufactured by Adtech Japan)
L) 1 ml / l Electroplating conditions Current density 1 A / dm2 Time 30 minutes Temperature Room temperature (12) After stripping off the plating resist 7 with 5% KOH, etching with a mixed solution of sulfuric acid and hydrogen peroxide, and electroless plating film 3 was dissolved and removed to form an 18 μm-thick inner conductor circuit (including via holes and an inner lattice-like ground layer 11) composed of the electroless copper plating film 3 and the electrolytic copper plating film 4.

(13) The substrate on which the conductor circuit was formed was coated with copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g / l.
1, sodium hypophosphite 29 g / l, boric acid 31 g / l,
The surface was immersed in an electroless plating solution having a pH of 9 containing 0.1 g / l of a surfactant to form a roughened layer 5 made of copper-nickel-phosphorus having a thickness of 3 μm on the surface of the conductor circuit.

The roughened layer 5 is formed by EPMA (X-ray fluorescence analyzer).
As a result of the analysis, 98 mol% of Cu, 1.5 mol of Ni
The composition ratio was 1% and P was 0.5 mol%. Further, the substrate is washed with water, and 0.1 mol / l tin borofluoride-
Immersion in an electroless tin displacement plating bath consisting of 1.0 mol / l thiourea solution at 50 ° C. for 1 hour, and a thickness of 0.3 μm on the surface of the roughened layer
m of the tin-substituted plating layer was formed.

(14) By repeating the steps (4) to (13), a grid-like power supply layer 12, via holes 10 and lands 14 are further formed on the upper layer, and the roughened layer 5 is provided on the surface thereof. . However, the tin-substituted plating layer was not formed on the roughened layer surface.

(15) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) in which 60% by weight of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was acrylated with 50% of epoxy groups, 15.0 g of 80% by weight bisphenol A epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, 1.6 imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN) 1.6
g, 3 g of a polyacrylic monomer which is a photosensitive monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), 1.5 g of a polyacrylic monomer (trade name: DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), and a dispersion defoamer (San Nopco) (Trade name: S-65), 0.71 g, and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer. In addition, the viscosity
A solder resist composition adjusted to 2.0 Pa · s at 25 ° C. was obtained.

The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with a rotor No. 4 and 6 rpm.
In the case of rotor No.3. (16) The solder resist composition was applied to the substrate at a thickness of 20 μm.

(17) Next, at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes.
After a drying treatment for 1 minute, the substrate was exposed to ultraviolet light of 1000 mJ / cm 2 and developed by DMTG. 1 hour at 80 ℃
Heat treatment was performed at 00 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours to open the upper surface, via holes and lands of the grid-like conductor layer (opening diameter: 200 μm). (Thickness: 20 μm).

(18) Next, the substrate on which the solder resist layer was formed was replaced with a nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g / l
It was immersed in an electroless nickel plating solution of H = 5 for 20 minutes to form a nickel plating layer having a thickness of 5 μm at the opening. Further, the substrate was placed on an electroless gold plating solution comprising 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds. By dipping, a gold plating layer having a thickness of 0.03 μm was formed on the nickel plating layer 13.

(19) Then, a solder paste was printed in the opening of the solder resist layer and reflowed at 200 ° C. to form a solder bump (solder body) 9 to manufacture a printed wiring board having the solder bump. .

(Example 2) Basically the same as Example 1, but the conductor circuit was roughened by etching. An etching solution having a trade name of "Durabond" manufactured by Mec Co. was used.

(Example 3) (1) Glass epoxy resin or BT having a thickness of 0.6 mm
A starting material was a copper-clad laminate in which 18 μm copper foil was laminated on both sides of a substrate made of (bismaleimide triazine) resin. The copper foil of the copper-clad laminate was etched in a pattern according to a conventional method to form inner layer copper patterns on both surfaces of the substrate.

(2) The substrate on which the inner layer copper pattern is formed in the above (1) is washed with water and dried, and then the substrate is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid. To provide a Pd catalyst,
After activating this catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating was performed in an electroless plating bath having a pH of 9 to form a roughened layer (uneven layer) of Cu-Ni-P alloy having a thickness of 2.5 µm on the entire surface of the copper conductor circuit.

Further, the substrate is washed with water and
ol / l tin borofluoride-1.0 mol / l thiourea solution, immersed in an electroless tin displacement plating bath at 50 ° C for 1 hour,
A tin-substituted plating layer having a thickness of 0.3 μm was formed on the surface of the roughened layer of the Ni—P alloy.

(3) 70% by weight of 25% acrylate of cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), polyether sulfone (PES) 30
Parts by weight, imidazole curing agent (Shikoku Chemicals, trade name: 2E
4MZ-CN) 4 parts by weight, caprolactone-modified tris (acryloxyethyl) isocyanurate (trade name: Aronix M325) manufactured by Toagosei Co., Ltd., a photosensitive monomer, benzophenone (Kanto Chemical) 5 as a photoinitiator
Parts by weight, 0.5 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer, and 35 parts by weight of an epoxy resin particle having an average particle size of 5.5 μm with respect to this mixture.
After mixing 5 parts by weight of 0.5 μm, they are mixed while adding NMP (normal methylpyrrolidone), adjusted to a viscosity of 12 Pa · s with a homodisper stirrer, and then kneaded with three rolls to form a photosensitive adhesive. An agent solution (interlayer resin insulating material) was obtained.

(4) The photosensitive adhesive solution is applied to both sides of the substrate by using a roll coater, and is applied in a horizontal state.
After drying for 30 minutes at 60 ° C,
A μm adhesive layer was formed.

(5) On both sides of the substrate on which the adhesive layer is formed,
A photomask film on which a via hole was drawn was placed and exposed to ultraviolet light. (6) The exposed substrate was spray-developed with a DMTG (triethylene glydimethyl ether) solution to form an opening serving as a 100 μmφ via hole in the adhesive layer. Further, the substrate is 3,000 mJ / cm2 using an ultra-high pressure mercury lamp.
Exposure and heat treatment at 100 ° C for 1 hour and then at 150 ° C for 5 hours, resulting in a 50μm thick adhesive with openings with excellent dimensional accuracy equivalent to a photomask film (via hole forming openings) An agent layer was formed. In addition,
The tin plating layer is partially exposed in the opening serving as the via hole.

(7) The substrate in which the opening for forming the via hole is formed is immersed in chromic acid for 2 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer, thereby roughening the surface of the adhesive layer. Then, it was immersed in a neutralizing solution (manufactured by Shipley) and washed with water.

(8) By applying a palladium catalyst (manufactured by Atotech) to the substrate subjected to the surface roughening treatment (roughening depth: 20 μm), catalyst nuclei are formed on the surface of the adhesive layer and the opening for the via hole. Granted.

(9) 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of an epoxy group of a 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, and added to methyl ethyl ketone. 15.0 g of dissolved 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), 1.6 g of imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN), polyvalent acrylic as a photosensitive monomer A mixed solution A was prepared by mixing 3 g of a monomer (manufactured by Nippon Kayaku, trade name: R604) and 1.5 g of a polyvalent acrylic monomer (manufactured by Kyoeisha Chemical, trade name: DPE6A).

On the other hand, 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were heated at 40 ° C. to 3 g of DMDG.
To prepare a mixed solution B.

The mixture A and the mixture B were mixed and stirred to obtain a liquid resist composition. (10) The liquid resist composition is applied on both sides of the substrate, which has been subjected to the catalyst nucleation treatment in (8) above, using a roll coater, and dried at 60 ° C. for 30 minutes to obtain a resist having a thickness of 30 μm. A layer was formed.

(11) A mask on which a pattern was drawn was laminated on the resist layer, and the resist layer was exposed to ultraviolet rays. (12) After the exposure in (11), the resist layer is
It was dissolved and developed with TG to form a plating resist on the substrate where the conductor circuit pattern was removed, and this was further exposed to 6000 mJ / cm 2 with an ultra-high pressure mercury lamp. Further, the plating resist is subjected to a heat treatment at 100 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain a permanent resist formed on the adhesive layer.

(13) On the substrate on which the permanent resist is formed,
A plating pretreatment (specifically, sulfuric acid treatment or the like and activation of the catalyst nucleus) is performed in advance, and then an electroless copper plating bath composed of 8.6 mM of copper sulfate, 0.15 M of triethanolamine, 0.02 M of formaldehyde, and a small amount of bipyridyl is used. Copper plating was performed, and electroless copper plating having a thickness of about 15 μm was deposited on the non-resist-formed portion to form a copper pattern, via holes, and a grid-like ground layer, thereby forming a conductor layer by an additive method.

(14) The steps (2) to (13) were further repeated to provide a via layer, a grid-like power supply layer, and a conductor layer composed of lands. Then, copper sulfate 8 g / l,
Nickel sulfate 0.6g / l, citric acid 15g / l, sodium hypophosphite 29g / l, boric acid 31g / l, surfactant
Plating is performed in an electroless plating bath composed of 0.1 g / l and pH = 9, and a 2.5 μm-thick roughened layer of Cu—Ni—P alloy is formed on all surfaces of via holes, lands, and a grid-like power supply layer. An uneven layer was formed.

(15) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of an epoxy group of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku) of 60% by weight dissolved in DMDG, 15.0 g of 80% by weight bisphenol A epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, 1.6 imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN) 1.6
g, 3 g of a polyacrylic monomer which is a photosensitive monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), 1.5 g of a polyacrylic monomer (trade name: DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), and a dispersion defoamer (San Nopco) (Trade name: S-65), 0.71 g, and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer. In addition, the viscosity
A solder resist composition adjusted to 2.0 Pa · s at 25 ° C. was obtained.

The viscosity was measured with a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm and rotor No. 4 and 6 rpm.
In the case of rotor No.3. (16) The substrate was sandwiched between a pair of application rolls of a roll coater in a vertically standing state, and the solder resist composition was applied to a thickness of 20 μm.

(17) Next, at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes.
After a drying treatment for 1 minute, the substrate was exposed to ultraviolet light of 1000 mJ / cm 2 and developed by DMTG. 1 hour at 80 ℃
Heat treatment under the conditions of 1 hour at 00 ° C, 1 hour at 120 ° C, and 3 hours at 150 ° C, and a part of the upper surface of the via hole, land, and grid-like power supply layer is opened (opening diameter: 200 µm). (Thickness: 20 μm).

(18) Next, the substrate on which the solder resist layer was formed was washed with a nickel chloride 30 g / l, sodium hypophosphite 10 g / l, sodium citrate 10 g / l
It was immersed in an electroless nickel plating solution of H = 5 for 20 minutes to form a nickel plating layer having a thickness of 5 μm at the opening. Further, the substrate was placed on an electroless gold plating solution comprising 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds. By dipping, a gold plating layer having a thickness of 0.03 μm was formed on the nickel plating layer.

(19) Solder paste was printed on the opening of the solder resist layer and reflowed at 200 ° C. to form solder bumps, thereby producing a printed wiring board having solder bumps.

(Embodiment 4) Similar to Embodiment 1, except that the grid pattern shown in FIG. 18C is provided as a ground layer on the core substrate, and the grid-like ground layer is not provided in (12). A signal layer was formed. Fig. 18 shows the ground layer.
As shown in (C), via-hole connection portions 16 are formed.

(Comparative Example) The same as in Example 1, except that the surface of the grid-like conductor layer 11 was not roughened. An IC chip is mounted on the printed wiring boards manufactured in Examples and Comparative Examples, and is mounted at −55 ° C. for 15 minutes, normal temperature for 10 minutes, and 125 ° C. for 15 minutes.
1000 heat cycle tests per minute, and 2000
Times.

Further, the humidity was 100%, the temperature was 121 ° C.,
200 at atmospheric pressure (PCT test: pressure cooker test)
Left for hours. With respect to Examples and Comparative Examples, the presence or absence of peeling and cracking of the interlayer resin insulating layer was confirmed by a microscope. Table 1 shows the results.

Cracks are less likely to occur in the conductor layer composed of the electroless plating film and the electrolytic plating film than in the conductor layer composed only of the electroless plating film.

[0087]

[Table 1]

[0088]

As described above, according to the printed wiring board of the present invention, the roughened layer is formed on the surface of the lattice-shaped conductor layer acting as the power supply layer and the ground layer, and the roughened layer is formed on the interlayer resin insulation layer. Cracks can be suppressed by forming the conductor layer into a two-layer structure of an electroless plating film and an electrolytic plating film without peeling.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to the present invention.

FIG. 2 is a manufacturing process diagram of a multilayer printed wiring board according to the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 6 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 7 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 8 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 9 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 10 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 11 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 12 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 13 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 14 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 15 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 16 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIG. 17 is a manufacturing process diagram of the multilayer printed wiring board according to the present invention.

FIGS. 18A to 18C are schematic diagrams showing a grid-like conductor layer having a circular conductor-free portion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Inner-layer conductor circuit 3 Electroless copper plating film 4 Electrolytic copper plating film 5 Roughening layer 6 Interlayer resin insulation layer (adhesive layer for electroless plating) 7 Plating resist 8 Solder resist 9, 90 Solder body (Solder bump) DESCRIPTION OF SYMBOLS 10 Solder pad 11 Inner-layer ground layer 12 Power supply layer 14 Land 140 Land (via hole) 150 Elliptical conductor non-forming part 151 Conductor non-forming part where apex is provided at the apex 152 True circular conductor non-forming part 16 via Hall connection

Claims (2)

[Claims] 1. A multilayer printed wiring board having a lattice-shaped conductor layer formed on a substrate and a conductor circuit formed on the conductor layer via an interlayer insulating layer, wherein the lattice-shaped conductor layer comprises: A multilayer printed wiring board, wherein a roughened layer is formed on at least a part of the surface, and the lattice-shaped conductor layer comprises an electroless plating film and an electrolytic plating film. 2. The multilayer printed circuit board according to claim 1, wherein the lattice-shaped conductor layer has a circular conductor-free portion.