JP2007227959A - Multilayer printed wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the crack of an interlayer insulating layer generated at the time of heat cycle, without causing reduction in peeling strength. <P>SOLUTION: In a multilayer printed wiring board in which the interlayer insulating layer is formed on a conductor circuit of a wiring substrate, the conductor circuit consists of an electroless plated film and an electrolytic plated film, and a coarse layer is provided in at least a part of the surface. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multilayer printed wiring board and a method for producing the same, and more particularly to a multilayer printed wiring board and a method for producing the same that suppress the generation of cracks during a heat cycle without causing a decrease in peel strength.

In recent years, so-called build-up multilayer wiring boards have attracted attention because of the demand for higher density of multilayer wiring boards. This build-up multilayer wiring board is manufactured, for example, by a method as disclosed in Patent Document 1. That is, an insulating material made of a photosensitive electroless plating adhesive is applied to the core substrate, and after drying and developing, an interlayer insulating material layer having openings for via holes is formed. After roughening the surface of this interlayer insulating material layer by treatment with an oxidizing agent, etc., a plating resist is provided on the roughened surface, and then electroless plating is applied to the non-resist forming portion to form via holes and conductor circuits. By forming and repeating such a process a plurality of times, a multilayer build-up wiring board can be obtained.
Japanese Patent Publication No. 4-55555

  However, in such a multilayer printed wiring board, the conductor circuit is provided in a portion where the plating resist is not formed, and the plating resist remains in the inner layer as it is. Therefore, when an IC chip or the like is mounted on such a wiring board, the board warps due to the difference in thermal expansion coefficient between the IC chip and the resin insulating layer during the heat cycle, and there is no adhesion between the plating resist and the conductor circuit. There is a problem that stress is concentrated on the portion, and a crack is generated in the interlayer insulating layer in contact with the boundary portion.

  The present invention has been made to solve the above-described problems of the prior art. The purpose is to prevent cracking of the interlayer insulating layer that occurs during the heat cycle without causing other properties, particularly, a decrease in peel strength.

As a result of diligent research toward the realization of the above object, the inventor has come up with an invention having the following contents.
(1) The multilayer printed wiring board of the present invention is a multilayer printed wiring board in which an interlayer insulating layer is formed on a conductor circuit of the wiring board, wherein the conductor circuit is composed of an electroless plating film and an electrolytic plating film, A roughening layer is provided on at least a part of the structure.
In this multilayer printed wiring board, the conductor circuit is preferably provided with a roughened layer on a part of the surface including at least the side surface, and the roughened layer may be made of an alloy plating of copper-nickel-phosphorus. preferable.

(2) The method for producing a multilayer printed wiring board according to the present invention is such that after electroless plating is performed on a substrate, a plating resist is provided, electrolytic plating is performed, and then the plating resist is removed, followed by etching treatment to perform electroless A conductive circuit comprising a plating film and an electrolytic plating film is provided, and a roughened layer is formed on at least a part of the surface of the conductive circuit, and then an interlayer insulating layer is provided.
The roughened layer is preferably formed by copper-nickel-phosphorus alloy plating.

  As described above, according to the present invention, it is possible to improve the connection reliability by preventing the occurrence of cracks during the heat cycle while preventing the peel strength from decreasing.

In the printed wiring board of the present invention, the conductor circuit is composed of an electrolytic plating film and an electroless plating film, the electroless plating film is formed on the inner layer side, and the electrolytic plating film is formed on the outer layer side (see FIG. 18, see enlarged view of FIG. 19). With such a configuration, the conductive circuit is softer and more malleable than the electroless plating film, so that the conductor circuit can follow the dimensional change of the interlayer resin insulation layer even if the substrate warps during the heat cycle. become.
Further, in the printed wiring board of the present invention, since the roughened layer is provided on the surface of the conductor circuit, the conductor circuit closely adheres to the interlayer resin insulation layer and follows the dimensional change of the interlayer resin insulation layer. It has become easier.

As a result, according to the printed wiring board of the present invention, even when an IC chip is mounted and a heat cycle test at −55 ° C. to 125 ° C. is performed, the generation of cracks in the interlayer resin insulation layer starting from the conductor circuit occurs. It can be suppressed and no peeling is observed.
In particular, providing a roughened layer on at least the side surface of the conductor circuit is advantageous in that cracks occurring in the interlayer resin insulating layer can be suppressed starting from the interface between the side surface of the conductor circuit and the interlayer resin in contact therewith.

  Furthermore, in the printed wiring board of the present invention, the inner layer side of the conductor is composed of an electroless plating film that is harder than the electrolytic plating film, so that the peel strength is not reduced. This is because the peel strength is on the side in contact with the interlayer insulation layer on the inner layer side of the conductor circuit (when the later-described electroless plating adhesive is used as the interlayer insulation, the portion in contact with the roughened surface). This is because the hardness increases as the hardness increases.

  Such a multilayer printed wiring board can be easily manufactured according to the manufacturing method of the present invention.

  Japanese Patent Laid-Open No. 6-283860 discloses a technique for preventing delamination by removing an inner layer plating resist and providing a roughened layer made of copper-nickel-phosphorus on the surface of a conductive circuit made of an electroless plating film. Is disclosed. However, the invention described in this publication has no recognition of cracks that occur when an IC chip is actually mounted and a heat cycle test is performed, and discloses a conductor circuit composed only of an electroless plating film. Stop. In addition, when an additional test was conducted with respect to the effect (see the comparative example of the present application), regarding the heat cycle test at −55 ° C. to 125 ° C., generation of cracks was not observed if it was about 1000 times. Development was observed. Therefore, the invention described in this publication is completely different from the present invention.

  In the present invention, the roughened layer on the surface of the conductor circuit is desirably a roughened surface of copper formed by etching treatment, polishing treatment, oxidation treatment or oxidation-reduction treatment, or a roughened surface formed by plating film. .

In particular, the roughened layer is preferably an alloy layer made of copper-nickel-phosphorus. This is because the alloy layer is a needle-like crystal layer and has excellent adhesion to the solder resist layer. Further, even if a solder body is formed on the alloy layer, there is no significant change in electric conductivity, and the solder body can be formed on the metal pad.
The composition of the alloy layer is preferably 90 to 96 wt%, 1 to 5 wt%, and 0.5 to 2 wt% in proportions of copper, nickel, and phosphorus, respectively. This is because the composition ratio has a needle-like structure.

  The composition of Cu—Ni—P that can form needle-like crystals is shown in FIG. 20 as a ternary triangular diagram. According to this figure, a range surrounded by (Cu, Ni, P) = (100, 0, 0), (90, 10, 0), (90, 0, 10) is preferable.

Moreover, when forming a roughening layer by oxidation treatment, it is desirable to use a solution of an oxidant composed of sodium chlorite, sodium hydroxide, and sodium phosphate.
When forming a roughened layer by oxidation-reduction treatment, it is desirable to immerse in a reducing agent solution comprising sodium hydroxide and sodium borohydride after the oxidation treatment.

  The roughened layer on the surface of the conductor circuit formed in this manner preferably has a thickness of 1 to 5 μm. This is because if the layer is too thick, the roughened layer itself is easily damaged and peeled off, and if it is too thin, the adhesiveness decreases.

In the present invention, it is desirable that the electroless plating film constituting the conductor circuit has a thickness of 0.1 to 5 μm, more preferably 0.5 to 3 μm. The reason for this is that if it is too thick, the followability with the interlayer resin insulation layer will be reduced. Conversely, if it is too thin, the peel strength will be reduced, or the resistance will increase when electrolytic plating is applied. This is because the thickness varies.

  In addition, it is desirable that the electrolytic plating film constituting the conductor circuit has a thickness of 5 to 30 μm, more preferably 10 to 20 μm. This is because if the thickness is too thick, the peel strength is lowered, and if it is too thin, the followability with the interlayer resin insulating layer is lowered.

  In the present invention, it is desirable that a roughened layer is formed on at least the side surface of the conductor circuit. The reason for this is that cracks that occur in the interlayer resin insulation layer due to heat cycles are caused by poor adhesion between the side surface of the conductor circuit and the resin insulation layer. This is because cracks occurring in the interlayer resin insulation layer starting from the interface with the insulation layer can be prevented.

  In the present invention, it is desirable to use an electroless plating adhesive as the interlayer resin insulating layer constituting the wiring board. This electroless plating adhesive is formed by dispersing a heat-resistant resin particle that is soluble in a cured acid or oxidant in an uncured heat-resistant resin that becomes insoluble in an acid or oxidant by the curing process. Things are optimal. This is because the heat-resistant resin particles are dissolved and removed by treatment with an acid and an oxidizing agent, and a roughened surface made of crucible-like anchors can be formed on the surface.

  In the above electroless plating adhesive, the heat-resistant resin particles particularly cured are (1) heat-resistant resin powder having an average particle size of 10 μm or less, and (2) heat-resistant resin having an average particle size of 2 μm or less. Aggregated particles obtained by agglomerating powder, (3) a mixture of heat-resistant powder resin powder having an average particle diameter of 2 to 10 μm and heat-resistant resin powder having an average particle diameter of 2 μm or less, and (4) an average particle diameter of 2 to 10 μm A pseudo-particle formed by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle size of 2 μm or less to the surface of the heat-resistant resin powder, and (5) having an average particle size of 0.1 to 0.8 μm It is desirable to use at least one selected from a heat-resistant resin powder and a mixture of a heat-resistant resin powder having an average particle size of more than 0.8 μm and an average particle size of less than 2 μm. This is because more complex anchors can be formed.

Next, one method for producing a printed wiring board according to the present invention will be described.
(1) First, a wiring substrate having an inner layer copper pattern formed on the surface of the core substrate is manufactured.
The copper pattern is formed on the core substrate by etching a copper-clad laminate, or an adhesive layer for electroless plating is formed on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate. There is a method in which the surface of the adhesive layer is roughened to obtain a roughened surface, which is subjected to electroless plating.

Further, if necessary, a roughened layer made of copper-nickel-phosphorus is formed on the copper pattern surface of the wiring board.
This roughening layer is formed by electroless plating. The electroless plating solution composition has a copper ion concentration, a nickel ion concentration, and a hypophosphite ion concentration of 2.2 × 10 ^{−2 to} 4.1 × 10 ⁻² mol / l and 2.2 × 10 ^{−3 to} 4.1 × 10 respectively. ^-3 mol / l, preferably 0.20 to 0.25 mol / l.
This is because the crystal structure of the coating deposited in this range becomes a needle-like structure, and thus the anchor effect is excellent. In addition to the above compounds, complexing agents and additives may be added to the electroless plating bath.
Other methods for forming the roughened layer include the oxidation (blackening) -reduction treatment described above and a method of forming a roughened surface by etching the copper surface along the grain boundary.

A through hole is formed in the core substrate, and the wiring layers on the front surface and the back surface can be electrically connected through the through hole.
Moreover, resin may be filled between the through hole and the conductor circuit of the core substrate to ensure smoothness (see FIGS. 1 to 4).

(2) Next, an interlayer resin insulating layer is formed on the wiring board produced in (1). In particular, in the present invention, it is desirable to use the above-described adhesive for electroless plating as an interlayer resin insulating material (see FIG. 5).

(3) After drying the electroless plating adhesive layer formed in (2), a via hole forming opening is provided as necessary.
At this time, in the case of a photosensitive resin, a via hole is formed in the adhesive layer by exposing and developing and then thermosetting, and in the case of a thermosetting resin, by thermosetting and then laser processing. An opening is provided (see FIG. 6).

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent, and the surface of the adhesive layer is roughened (see FIG. 7).
Here, examples of the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid. It is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded. On the other hand, as the oxidizing agent, it is desirable to use chromic acid or permanganate (such as potassium permanganate).

(5) Next, a catalyst nucleus is imparted to the wiring board whose surface of the adhesive layer is roughened.
For imparting the catalyst nucleus, it is desirable to use a noble metal ion or a noble metal colloid. Generally, palladium chloride or a palladium colloid is used. It is desirable to perform heat treatment to fix the catalyst core. Palladium is preferable as such a catalyst nucleus.

(6) Next, electroless plating is performed on the surface of the electroless plating adhesive to form an electroless plating film on the entire roughened surface (see FIG. 8). At this time, the thickness of the electroless plating film is 0.1 to 5 μm, and more preferably 0.5 to 3 μm.
Next, a plating resist is formed on the electroless plating film (see FIG. 9). As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolac or a phenol novolac type epoxy resin and an imidazole curing agent, but a commercially available product can also be used.

(7) Next, electrolytic plating is performed on the plating resist non-formation portion to form a conductor circuit and a via hole (see FIG. 10). At this time, the thickness of the electrolytic plating film is desirably 5 to 30 μm.
Here, it is desirable to use copper plating as the electroless plating.

(8) Further, after removing the plating resist, the electroless plating film under the plating resist is dissolved and removed with an etching solution such as a mixture of sulfuric acid and hydrogen peroxide, sodium persulfate, or ammonium persulfate, and an independent conductor circuit. (See FIG. 11).

(9) Next, a roughening layer is formed on the surface of the conductor circuit (see FIG. 12).
As a method for forming the roughened layer, there are an etching process, a polishing process, an oxidation-reduction process, and a plating process.
Among these treatments, the oxidation-reduction treatment comprises NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l) in an oxidation bath (blackening bath), NaOH (10 g / l), NaBH ₄ (5 g / l) is used as the reducing bath.
Moreover, the roughening layer which consists of a copper-nickel-phosphorus alloy layer is formed by precipitation by an electroless-plating process.
The electroless plating solution for this alloy includes copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l, boric acid 10 It is desirable to use a plating bath having a liquid composition of ˜40 g / l and a surfactant of 0.01 to 10 g / l.

(10) Next, an electroless plating adhesive layer is formed on this substrate as an interlayer resin insulation layer (see FIG. 13).
(11) Further, steps (3) to (8) are repeated to provide a further upper conductor circuit (see FIGS. 14 to 17). Here, a roughened layer may be formed on the surface of the conductor circuit in the same manner as in the above (9).

(12) Next, a solder resist composition was applied to the surface of the wiring board thus obtained, and after the coating film was dried, a photomask film having openings drawn thereon was placed on the coating film. By exposing and developing, an opening in which the pad portion of the conductor circuit is exposed is formed. Here, the opening diameter of the opening may be larger than the diameter of the pad, and the pad may be completely exposed. Conversely, the opening diameter of the opening can be made smaller than the diameter of the pad, and the periphery of the pad can be covered with a solder resist. In this case, the pad can be suppressed with a solder resist, and the peeling of the pad can be prevented.

(13) Next, a “nickel-gold” metal layer is formed on the pad portion exposed from the opening.

(14) Next, a solder body is supplied onto the pad portion exposed from the opening.
As a method for supplying the solder body, a solder transfer method or a printing method can be used. Here, the solder transfer method is to paste a solder foil on a prepreg, and to etch the solder foil by leaving only the portion corresponding to the opening portion, thereby forming a solder carrier film, and this solder carrier film. After the flux is applied to the solder resist opening of the substrate, the solder pattern is laminated so as to contact the pad, and this is transferred by heating. On the other hand, the printing method is a method in which a metal mask provided with a through hole at a position corresponding to a pad is placed on a substrate, a solder paste is printed, and heat treatment is performed.

Example 1
(1) A copper-clad laminate in which 18 μm copper foil 8 is laminated on both surfaces of a substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.6 mm was used as a starting material (see FIG. 1). ). The copper foil 8 of this copper clad laminate was etched, drilled and electrolessly plated in a pattern according to a conventional method, thereby forming inner layer copper patterns 4 and through holes 9 on both surfaces of the substrate (see FIG. 2).
Further, bisphenol F-type epoxy resin was filled between the conductor circuits 4 and in the through holes 9 (see FIG. 3).

(2) The substrate after the treatment of (1) is washed with water and dried, and then the substrate is subjected to acid degreasing and soft etching, and then treated with a catalyst solution composed of palladium chloride and an organic acid to obtain a Pd catalyst. After activating the catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 Plating was performed in an electroless plating bath composed of g / l, pH = 9, and a roughened layer 11 (uneven layer) having a thickness of 2.5 μm of a Cu—Ni—P alloy was formed on the surface of the copper conductor circuit 4. (See FIG. 4).

(3) 70 parts by weight of 25% acrylate of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), 30 parts by weight of polyethersulfone (PES), imidazole curing agent (Shikoku 4 parts by weight of Kasei Chemical Co., Ltd., trade name: 2E4MZ-CN), 10 parts by weight of caprolactone modified tris (acryloxyethyl) isocyanurate (trade name: Aronix M325, manufactured by Toagosei Co., Ltd.), a photosensitive monomer, benzophenone as a photoinitiator 5 parts by weight (manufactured by Kanto Chemical), 0.5 parts by weight of Michler's ketone (manufactured by Kanto Chemical) as a photosensitizer, and 35 parts by weight of an epoxy resin particle having an average particle size of 5.5 μm with respect to this mixture, After mixing 5 parts by weight of an average particle size of 0.5 μm, while adding NMP (normal methylpyrrolidone) Combined, adjusted to a viscosity 112Pa · s in a homodisper stirrer to obtain subsequently kneading the photosensitive adhesive solution 3-roll (interlayer resin insulating material).

(4) The photosensitive adhesive solution obtained in (3) above was applied to both surfaces of the substrate that had been treated in (2) above using a roll coater, left in a horizontal state for 20 minutes, and then 60 Drying was carried out at 30 ° C. for 30 minutes to form an adhesive layer 2 having a thickness of 60 μm (see FIG. 5).
(5) Photomask films on which via holes were drawn were placed on both sides of the substrate on which the adhesive layer 2 was formed in the above (4), and exposed by irradiating ultraviolet rays.

(6) The exposed substrate was spray-developed with a DMTG (triethylene glycol dimethyl ether) solution to form an opening serving as a via hole having a diameter of 100 μm in the adhesive layer. Furthermore, the substrate is exposed at 3000 mJ / cm ² with an ultra-high pressure mercury lamp and heat-treated at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours, so that the dimensional accuracy corresponding to a photomask film is excellent. An adhesive layer 2 having a thickness of 50 μm having an opening (via hole forming opening 6) formed as a group was formed (see FIG. 6). Note that the roughened layer 11 is partially exposed in the opening 6 serving as a via hole.

(7) The substrate on which the via hole forming opening 6 is formed in the above (5) and (6) is immersed in chromic acid for 2 minutes, and the epoxy resin particles existing on the surface of the adhesive layer are dissolved and removed. The surface of the layer was roughened, and then immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water (see FIG. 7).
(8) The surface of the adhesive layer 2 and the via hole opening 6 is formed by applying a palladium catalyst (manufactured by Atotech) to the substrate subjected to the roughening treatment (roughening depth 5 μm) in (7). Was provided with a catalyst nucleus.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 12 having a thickness of 3 μm over the entire rough surface (see FIG. 8).
[Electroless plating solution]
EDTA 150 g / l
Copper sulfate 20 g / l
HCHO 30 ml / l
NaOH 40g / l
α, α'-bipyridyl 80 mg / l
PEG 0.1 g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C

(10) A commercially available photosensitive dry film is pasted on the electroless copper plating film 12 formed in the above (9), a mask is placed, exposed at 100 mJ / cm ² , and developed with 0.8% sodium carbonate. The plating resist 3 having a thickness of 15 μm was provided (see FIG. 9).

(11) Next, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 13 having a thickness of 15 μm (see FIG. 10).
[Electrolytic plating solution]
Sulfuric acid 180g / l
Copper sulfate 80g / l
Additive (product name: Kaparaside GL, manufactured by Atotech Japan)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
30 minutes
Temperature room temperature

(12) After stripping and removing the plating resist 3 with 5% KOH, the electroless plating film 12 under the plating resist 3 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating film A conductor circuit (including a via hole) 5 having a thickness of 18 μm was formed (see FIG. 11).

(13) The substrate on which the conductor circuit 5 is formed is made of copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 A roughening layer 11 made of copper-nickel-phosphorus having a thickness of 3 μm was formed on the surface of the conductor circuit 5 by dipping in an electroless plating solution of pH = 9 consisting of g / l (see FIG. 12). At this time, when the formed roughened layer 11 was analyzed by EPMA (fluorescence X-ray analyzer), the composition ratio of Cu: 98 mol%, Ni: 1.5 mol%, P: 0.5 mol% was shown.

(14) By repeating the steps (4) to (12), a wiring board on which a further upper conductor circuit was formed was obtained (see FIGS. 13 to 17).

(15) On the other hand, 46.67 g of photosensitizing oligomer (molecular weight 4000) obtained by acrylating 50% of the epoxy group of 60% by weight of cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, into methyl ethyl ketone 15.0 g of 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), 1.6 g of imidazole curing agent (product name: 2E4MZ-CN), a photosensitive monomer Monovalent acrylic monomer (Nippon Kayaku, trade name: R604) 3 g, similarly polyacrylic monomer (Kyoeisha Chemical, trade name: DPE6A) 1.5 g, dispersion antifoam (San Nopco, trade name: S-) 65) 0.71 g was mixed, and 2 g of benzophenone (manufactured by Kanto Chemical) as a photoinitiator was added to this mixture, and Michler's ketone as a photosensitizer 0.2 g (manufactured by Kanto Kagaku) was added to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
The viscosity was measured with a B-type viscometer (Tokyo Keiki Co., Ltd., DVL-B type) with a rotor No. of 60 rpm. In the case of 4 or 6 rpm, the rotor No. 3 according.

(16) The solder resist composition was applied to the wiring board obtained in (14) with a thickness of 20 μm. Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask film was placed, exposed to 1000 mJ / cm ² of ultraviolet light, and DMTG developed. Further, a solder resist layer (thickness 20 μm) having a pad portion opened (opening diameter 200 μm) was heat-treated at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. Formed.

(17) Next, the substrate on which the solder resist layer is formed is placed in an electroless nickel plating solution having a pH of 5 consisting of 30 g / l nickel chloride, 10 g / l sodium hypophosphite, and 10 g / l sodium citrate for 20 minutes. Immersion was performed to form a nickel plating layer having a thickness of 5 μm in the opening. Further, the substrate was placed in an electroless gold plating solution composed of potassium gold cyanide 2 g / l, ammonium chloride 75 g / l, sodium citrate 50 g / l, and sodium hypophosphite 10 g / l at 93 ° C. for 23 seconds. A gold plating layer having a thickness of 0.03 μm was formed on the nickel plating layer by dipping.

(18) A solder bump was formed by printing a solder paste on the opening of the solder resist layer and reflowing at 200 ° C. to produce a printed wiring board having the solder bump.

(Example 2)
A printed wiring board having solder bumps was produced in the same manner as in Example 1 except that the surface of the conductor circuit was roughened by etching. At this time, an etching solution having a trade name of “Durabond” manufactured by MEC was used.

(Example 3)
A. Preparation of adhesive composition for electroless plating (1). 2. 35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, photosensitive monomer (Aronix M315, manufactured by Toagosei Co., Ltd.) 15 parts by weight, defoaming agent (manufactured by San Nopco, S-65) 0.5
Part by weight and 3.6 parts by weight of NMP were mixed with stirring.
(2). 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., polymer pole) with an average particle diameter of 1.0 μm, and 3.09 weights with an average particle diameter of 0.5 μm After mixing the parts, 30 parts by weight of NMP was further added and stirred and mixed with a bead mill.
(3). Imidazole curing agent (Shikoku Kasei, 2E4MZ-CN) 2 parts, Photoinitiator (Ciba Geigy, Irgacure I-907) 2 parts, Photosensitizer (Nippon Kayaku, DETX-S) 0.2 part And 1.5 parts by weight of NMP were mixed with stirring. These were mixed to prepare an electroless plating adhesive composition.

B. Preparation of lower interlayer resin insulation (1). 35 parts by weight of a resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, photosensitive resin (Aronix M315, manufactured by Toagosei Co., Ltd.) Parts, 0.5 parts by weight of an antifoaming agent (Sanopco, S-65) and 3.6 parts by weight of NMP were mixed with stirring.
(2). After mixing 12 parts by weight of polyethersulfone (PES) and 14.49 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei, polymer pole) having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, The mixture was stirred and mixed with a bead mill.
(3). Imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN) 2 parts, Photoinitiator (Ciba Geigy, Irgacure I-907) 2 parts, Photosensitizer (Nippon Kayaku, DETX-S) 0.2 parts And 1.5 parts by weight of NMP were mixed with stirring.
These were mixed to prepare a resin composition to be used as an insulating layer on the lower layer side constituting an interlayer resin insulating layer having a two-layer structure.

C. Preparation of resin filler (1). 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), SiO ₂ having an average particle diameter of 1.6 μm and a surface coated with a silane coupling agent Spherical particles (manufactured by Admatech, CRS 1101-CE, where the maximum particle size is not more than the inner layer copper pattern thickness (15 μm) described later) 170 parts by weight, leveling agent (San Nopco, Perenol S4) 1.5 The parts by weight were kneaded with three rolls, and the viscosity of the mixture was adjusted to 45,000 to 49,000 cps at 23 ± 1 ° C.
(2). 6.5 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN). These were mixed and the resin filler 10 was prepared.

D. Method for manufacturing printed wiring board
(1) A copper-clad laminate in which 18 μm copper foil 8 was laminated on both surfaces of a substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm was used as a starting material (see FIG. 21). First, after drilling the copper-clad laminate and forming a plating resist, electroless plating treatment is performed to form a through hole 9, and further, the copper foil 8 is etched into a pattern according to a conventional method, Inner layer copper patterns 4 were formed on both sides of the substrate 1.

(2) The substrate on which the inner layer copper pattern 4 and the through hole 9 are formed is washed with water, dried, and then used as an oxidation bath (blackening bath): NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l), a roughening layer 11 is formed on the surface of the inner layer copper pattern 4 and the through hole 9 by oxidation-reduction treatment using NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath. Provided (see FIG. 22).

(3) The resin filler 10 is applied to one side of the substrate using a roll coater to fill the space between the conductor circuits 4 or the through holes 9 and dry at 70 ° C. for 20 minutes. Similarly, the resin filler 10 was filled between the conductor circuits 4 or in the through holes 9 and dried by heating at 70 ° C. for 20 minutes (see FIG. 23).

(4) One side of the substrate after the processing of (3) above is applied to the surface of the inner layer copper pattern 4 or the land surface of the through hole 9 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyori Chemical). Polishing was performed so that the resin filler 10 did not remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
Next, the resin filler 10 was cured by heat treatment at 100 ° C. for 1 hour, 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours (see FIG. 24).

In this way, the surface layer portion of the resin filler 10 filled in the through holes 9 and the like and the roughened layer 11 on the upper surface of the inner layer conductor circuit 4 are removed to smooth both surfaces of the substrate, and the resin filler 10 and the inner layer conductor circuit 4 are smoothed. A wiring substrate was obtained in which the side surface of the through hole 9 was firmly adhered via the roughened layer 11 and the inner wall surface of the through hole 9 and the resin filler 10 were firmly adhered via the roughened layer 11. That is, by this step, the surface of the resin filler 10 and the surface of the inner layer copper pattern 4 are flush. Here, the filled cured resin had a Tg point of 155.6 ° C. and a linear thermal expansion coefficient of 44.5 × 10 ⁻⁶ / ° C.

(5) A roughened layer (concave / convex layer) 11 made of a Cu—Ni—P alloy having a thickness of 2.5 μm is formed on the land upper surfaces of the inner conductor circuit 4 and the through hole 9 exposed by the process of (4), Further, an Sn layer having a thickness of 0.3 μm was provided on the surface of the roughened layer 11 (see FIG. 25, but the Sn layer is not shown).
The formation method is as follows. That is, the substrate is acid degreased and soft etched, then treated with a catalyst solution composed of palladium chloride and an organic acid to give a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, nickel sulfate Plating is performed in an electroless plating bath comprising 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l, pH = 9, and copper A roughened layer 11 of Cu—Ni—P alloy was formed on the upper surface of the conductor circuit 4 and the upper surface of the land of the through hole 9. Next, a Cu—Sn substitution reaction was carried out under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.2, and the surface of the roughened layer 11 was Sn having a thickness of 0.3 μm. A layer was provided (the Sn layer is not shown).

(6) B interlayer resin insulation (viscosity 1.5 Pa · s) was applied to both sides of the substrate of (5) above with a roll coater, left in a horizontal state for 20 minutes, and then at 60 ° C. for 30 minutes. Drying (pre-baking) was performed to form the insulating layer 2a.
Further, an adhesive for electroless plating (viscosity 7 Pa · s) of A is applied onto the insulating layer 2a using a roll coater, left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes ( Pre-baking) was performed to form an adhesive layer 2b (see FIG. 26).

(7) A photomask film on which a black circle having a diameter of 85 μm is printed is adhered to both surfaces of the substrate on which the insulating layer 2a and the adhesive layer 2b are formed in the above (6), and is 500 mJ / cm ² by an ultrahigh pressure mercury lamp. Exposed. This is spray-developed with a DMTG solution, and further, the substrate is exposed at 3000 mJ / cm ² with an ultrahigh pressure mercury lamp, and subjected to a heat treatment (post-bake) at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours, An interlayer resin insulation layer (two-layer structure) 2 having a thickness of 35 μm and having an opening (via hole forming opening 6) having a diameter of 85 μm and excellent in dimensional accuracy corresponding to a photomask film was formed (see FIG. 27). Note that the tin plating layer was partially exposed in the opening serving as the via hole.

(8) The substrate with the openings formed is immersed in 800 g / l chromic acid at 70 ° C. for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer 2b of the interlayer resin insulation layer 2. The surface of the interlayer resin insulation layer 2 was roughened (depth: 3 μm), and then immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water (see FIG. 28).
Furthermore, a catalyst core was attached to the surface of the interlayer resin insulating layer 2 and the inner wall surface of the via hole opening 6 by applying a palladium catalyst (manufactured by Atotech) to the surface of the roughened substrate.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 12 having a thickness of 0.6 μm over the entire rough surface (see FIG. 29).
[Electroless plating solution]
EDTA 150g / l
Copper sulfate 20g / l
HCHO 30 ml / l
NaOH 40g / l
α, α'-bipyridyl 80 mg / l
PEG 0.1 g / l
[Electroless plating conditions]
30 minutes at a liquid temperature of 70 ° C

(10) A commercially available photosensitive dry film is pasted on the electroless copper plating film 12 formed in the above (9), a mask is placed, exposed at 100 mJ / cm ² and developed with 0.8% sodium carbonate. The plating resist 3 having a thickness of 15 μm was provided (see FIG. 30).

(11) Next, electrolytic copper plating was applied to the resist non-formed portion under the following conditions to form an electrolytic copper plating film 13 having a thickness of 15 μm (see FIG. 31).
[Electrolytic plating solution]
Sulfuric acid 180 g / l
Copper sulfate 80 g / l
Additive (manufactured by Atotech Japan, Kaparaside GL)
1 ml / l
[Electrolytic plating conditions]
Current density 1A / dm ²
30 minutes
Temperature room temperature

(12) After stripping and removing the plating resist 3 with 5% KOH, the electroless plating film 12 under the plating resist 3 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless copper plating film A conductor circuit (including via holes) 5 having a thickness of 18 μm composed of 12 and electrolytic copper plating film 13 was formed. Further, the surface of the adhesive layer for electroless plating between the conductor circuits located in the conductor circuit non-formed portion is etched by 1 to 2 μm at 70 ° C. for 3 minutes in 800 g / l chromic acid, and the surface is etched. The remaining palladium catalyst was removed (see FIG. 32).

(13) The substrate on which the conductor circuit 5 is formed is made of copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 A roughening layer 11 made of copper-nickel-phosphorus having a thickness of 3 μm was formed on the surface of the conductor circuit 5 by dipping in an electroless plating solution of pH = 9 consisting of g / l (see FIG. 33). At this time, when the formed roughened layer 11 was analyzed by EPMA (fluorescence X-ray analyzer), the composition ratio was Cu: 98 mol%, Ni: 1.5 mol%, and P: 0.5 mol%.
Furthermore, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.2, and the thickness of the roughened layer 11 was 0.3 μm. The Sn layer was provided (the Sn layer is not shown).

(14) By repeating the steps (6) to (13), a further upper conductor circuit was formed to obtain a multilayer printed wiring board. However, Sn substitution was not performed (see FIGS. 34 to 39).

(15) On the other hand, 46.67 g of photosensitizing oligomer (molecular weight 4000) obtained by acrylating 50% of the epoxy group of 60% by weight of cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, into methyl ethyl ketone 15.0 g of dissolved 80 wt% bisphenol A epoxy resin (manufactured by Yuka Shell, Epicoat 1001), 1.6 g of imidazole curing agent (manufactured by Shikoku Kasei, 2E4MZ-CN), polyvalent acrylic monomer as a photosensitive monomer (Nippon Kayaku Co., Ltd., R604) 3 g, 1.5 g polyvalent acrylic monomer (Kyoeisha Chemical Co., Ltd., DPE6A) and 0.71 g dispersion antifoam (Sannopco Co., S-65) were mixed, and this mixture was further mixed. 2 g of benzophenone (manufactured by Kanto Chemical) as a photoinitiator and 0.2 g of Michler ketone (manufactured by Kanto Chemical) as a photosensitizer To obtain a solder resist composition with an adjusted viscosity 2.0 Pa · s at 25 ° C..
The viscosity was measured with a B-type viscometer (Tokyo Keiki Co., Ltd., DVL-B type) with a rotor No. In the case of 4 or 6 rpm, the rotor No. 3 according.

(16) The solder resist composition was applied to both sides of the multilayer wiring board obtained in (14) with a thickness of 20 μm. Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask film having a thickness of 5 mm on which a circular pattern (mask pattern) was drawn was placed in close contact, and 1000 mJ / cm ^{2 was} placed. Were exposed to ultraviolet light and DMTG developed. Further, heat treatment was performed under conditions of 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours to open solder pad portions (including via holes and land portions thereof) ( A solder resist layer (thickness 20 μm) 14 having an opening diameter of 200 μm was formed.

(17) Next, the substrate on which the solder resist layer 14 is formed is applied to an electroless nickel plating solution having a pH of 5 and comprising 30 g / l of nickel chloride, 10 g / l of sodium hypophosphite, and 10 g / l of sodium citrate. The nickel plating layer 15 having a thickness of 5 μm was formed in the opening by dipping for 5 minutes. Further, the substrate was placed in an electroless gold plating solution composed of potassium gold cyanide 2 g / l, ammonium chloride 75 g / l, sodium citrate 50 g / l, and sodium hypophosphite 10 g / l at 93 ° C. for 23 seconds. The gold plating layer 16 having a thickness of 0.03 μm was formed on the nickel plating layer 15 by dipping.

(18) A solder bump (solder body) 17 was formed by printing a solder paste on the opening of the solder resist layer 14 and reflowing at 200 ° C., and a printed wiring board having the solder bump 17 was manufactured ( (See FIG. 40).

(Comparative example)
After the processing of (1), (2), (3), (4), (5), (6), (7), (8) of Example 1, a dry film photoresist is laminated, exposed and developed. The plating resist was formed by processing. Subsequently, after carrying out (9) of Example 1, the plating resist was peeled off in the same manner as in the process of (12), and the treatment of (13) of Example 1 was performed to roughen the entire surface of the conductor circuit. Further, the formation of the interlayer resin insulation layer, the roughening process, the formation of the plating resist, and the electroless copper plating process were similarly performed, and after the plating resist was peeled off, (15), (16), (17) of Example 1 A printed wiring board having solder bumps was manufactured by the processes of (18) and (19).

An IC chip was mounted on the printed wiring boards manufactured in Examples and Comparative Examples, and heat cycle tests were performed at -55 ° C for 15 minutes, at room temperature for 10 minutes, at 125 ° C for 15 minutes, 1000 times, and 2000 times.
In the evaluation of the test, the occurrence of cracks in the printed wiring board after the test was confirmed with a scanning electron microscope. The peel strength was also measured. The peel strength was in accordance with JIS-C-6481.

As a result, cracks were not observed in the comparative example and Examples 1 to 3 at about 1000 times, but were observed in the comparative example at 2000 times.
The peel strength was equal to or slightly higher than that in the case where the conductor circuit was formed only by the electroless plating film.
Thus, in the present invention, cracks occurring in the interlayer resin insulation layer can be prevented while ensuring a practical peel strength.

It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a manufacturing-process figure of the multilayer printed wiring board concerning invention. It is a structure enlarged view of the multilayer printed wiring board concerning invention. It is a structure enlarged view of the multilayer printed wiring board concerning invention. It is a triangular figure showing the composition of the roughening layer of copper-nickel-phosphorus. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention. It is a figure which shows each manufacturing process of the multilayer printed wiring board concerning invention.

Explanation of symbols

1 Substrate 2 Interlayer resin insulation layer (adhesive layer for electroless plating)
2a Insulating layer 2b Adhesive layer 3 Plating resist 4 Inner layer conductor circuit (Inner layer copper pattern)
5 Outer layer conductor circuit (outer layer copper pattern)
6 Opening for via hole 7 Via hole (BVH)
8 Copper foil 9 Through hole 10 Filling resin (resin filler)
DESCRIPTION OF SYMBOLS 11 Roughening layer 12 Electroless copper plating film 13 Electrolytic copper plating film 14 Solder resist layer 15 Nickel plating layer 16 Gold plating layer 17 Solder bump

Claims (2)

In a multilayer printed wiring board in which an interlayer insulating layer is formed covering a substrate provided with an inner layer conductor circuit, and an outer layer conductor circuit is formed on the interlayer insulating layer,
A roughened layer is formed on the surface of the interlayer insulating layer, and the outer conductor circuit is composed of an electroless plated film in close contact with the roughened layer and an electrolytic plated film formed on the electroless plated film. A multilayer printed wiring board characterized by being configured. An interlayer insulating layer is formed so as to cover the substrate on which the inner-layer conductor circuit is provided, a roughened layer is formed on the surface of the interlayer insulating layer, and then an electroless plating process is performed on the roughened layer. After forming a plating resist on the electroless plating film, further performing an electroplating process to form an electroplating film on the electroless plating film non-plating resist forming portion, and then removing the plating resist, A method for producing a multilayer printed wiring board, wherein an electroless plating film under a plating resist is dissolved and removed by etching treatment to provide an outer layer conductive circuit composed of an electroless plating film and an electrolytic plating film.

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