JP3152633B2 - Multilayer printed wiring board and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a method for manufacturing the same, and more particularly, to a multilayer printed wiring board with few short circuits between conductor circuits and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 4-55555. That is, on the core substrate, an insulating material made of a photosensitive electroless plating adhesive is applied, and dried and then exposed and developed to form an interlayer insulating material layer having a via hole opening, After roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and then electroless plating is performed on a non-resist forming portion to form a via hole and a conductor circuit. By forming and repeating such steps a plurality of times, a multilayered build-up multilayer wiring board can be obtained.

In such a build-up multilayer wiring board, the conductor circuit is provided in a portion where no plating resist is formed, and the plating resist remains as it is in the inner layer. Therefore, when an IC chip or the like is mounted on such a wiring board,
During the heat cycle, the substrate warps due to the difference in thermal expansion coefficient between the IC chip and the resin insulating layer. As a result, stress is concentrated on the boundary between the plating resist having poor adhesion and the conductor circuit, and there is a problem that cracks occur in the interlayer resin insulating layer in contact with the boundary.

As a means for suppressing such cracks, a roughening layer is formed on the surface of a conductor circuit after removing a plating resist (for example, a roughening layer made of a copper-nickel-phosphorus alloy by electroless plating). To improve the adhesion to the interlayer resin insulating layer formed on the conductor circuit. Here, as a method of forming a conductor circuit from which a plating resist has been removed, a method of forming a plating resist, performing electroless plating on a portion where the resist is not formed, and then removing the plating resist, and a thin film of electroless plating. There is a method in which a plating resist is formed on a substrate on which the entire surface is formed, electroless plating is performed on a portion where the resist is not formed, and then the plating resist and the electroless plating film under the plating resist are removed.

[0005]

However, in both of the above methods, a catalyst nucleus for depositing electroless plating is provided on a portion where no conductor circuit is formed (between conductor circuits). Tends to cause a decrease in insulation properties. Further, in the above method, the electroless plating film that cannot be completely removed becomes a residue, which also tends to cause a decrease in insulation.

Therefore, in this state, if an attempt is made to form a roughened layer by electroless plating in order to suppress the occurrence of the cracks, a catalyst nucleus or an electroless plated film is formed in a portion where conductor circuits are not formed (between conductor circuits). Remains, a roughened layer of a copper-nickel-phosphorus alloy or the like is formed also in that portion, and there is a problem that a short circuit occurs between the conductor circuits.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a main object of the present invention is to provide an insulation reliability between conductor circuits caused by forming at least a part of the conductor circuit with an electroless plating film. Of the conductor circuit and the resin insulation layer.
It is to propose an improved technique. Another object of the present invention is to propose a technique capable of forming a roughened layer by electroless plating only on the surface of a conductor circuit without depositing plating on portions where conductor circuits are not formed (between conductor circuits). .

[0008]

Means for Solving the Problems The inventors of the present invention have conducted intensive studies for realizing the above-mentioned object, and as a result, have conceived an invention having the following features as the main constitutions. (1) A roughened layer is formed on the surface of the resin
On the roughened layer, the conductor circuit at least partially made of an electroless plating is formed, even at least in the conductor circuit
In a multilayer printed wiring board in which a roughened layer is partially formed and an interlayer resin insulating layer is formed on the conductive circuit, the multilayer printed wiring board remains on a portion of the resin insulating layer surface where no conductive circuit is formed. The multilayer printed wiring board is characterized in that the amount of the catalyst nucleus for electroless plating is 0.01 to 1.0 μg / cm ² in terms of metal ions.

[0009]

[0010] In the multilayer printed wiring board according to the above (1) , the conductor circuit has a roughened layer on at least a part of its surface, preferably a copper-nickel-phosphorus alloy plating. Is preferred.

(2) The surface of the resin insulating layer formed on the substrate is roughened.
To form an electroless plating film on the surface of the roughened layer by applying a catalyst nucleus for electroless plating to the surface of the roughened layer , and then providing a plating resist, performing an electrolytic plating process, and then removing the plating resist. Then, by etching the electroless plating film under the plating resist to form a conductive circuit, a method of manufacturing a multilayer printed wiring board, wherein the conductive circuit formed on the surface of the resin insulating layer further includes an interlayer. When forming the resin insulation layer, the conductor circuit table
By forming a roughened layer on at least a part of the surface and further etching a portion of the surface of the resin insulating layer where no conductive circuit is formed, the amount of the electroless plating catalyst nuclei remaining on the portion is reduced by metal ions. 0.01 to 1.0 g / cm in conversion
² This is a method for manufacturing a multilayer printed wiring board.

[0012]

In the manufacturing method described in the above (2) , it is preferable that the etching treatment is performed using an acid or an oxidizing agent. Further, in the manufacturing method according to the above (2) , when further forming an interlayer resin insulating layer on the conductor circuit formed on the resin insulating layer surface, at least a part of the conductor circuit surface has a roughened layer, more desirably. Is preferably formed by copper-nickel-phosphorus alloy plating.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION The multilayer printed wiring board of the present invention and the method of manufacturing the same are characterized in that a conductive circuit on a resin insulating layer surface
The amount of electroless plating catalyst nuclei remaining in
By metallization, 0.01-1.
It is characterized in that it is properly controlled within the range of 0 g / cm ² .

Thus, according to the present invention, the electroless plating
The remaining amount of catalyst nuclei used to form
Controlled by electroless plating, which may remain in the roughened layer.
Since the residue of the deposited film is removed , a multilayer printed wiring board having excellent insulation reliability can be provided. Moreover,
According to the present invention, since the catalyst nuclei in the portions where the conductor circuits are not formed (between the conductor circuits) are effectively removed, even when electroless plating for roughening the surface of the conductor circuits is performed, plating is performed on those portions. Does not deposit, so short circuit between conductor circuits
Nothing to do.

In the present invention, the residual amount of the catalyst nucleus is more preferably adjusted to 0.01 to 1.0 μg / cm ² . The reason for this is that if an attempt is made to reduce the remaining amount of the catalyst nuclei, not only the resin insulating layer but also the conductor circuit may be dissolved. In addition, the residual amount of the catalyst core was measured as follows. . The substrate to which the catalyst nuclei have adhered is immersed in 6N hydrochloric acid and left as it is for 24 hours. . The concentration of metal ions (such as palladium) constituting the catalyst core in a hydrochloric acid solution is measured by an atomic absorption method. . From the concentration measured above, calculate the amount of catalyst nuclei attached to the conductive circuit non-formed portion of the substrate by the amount of metal ions,
The amount of metal ions is divided by the area of the catalyst nucleus providing surface exposed on the substrate to calculate the amount of metal ions per area of the catalyst nucleus providing surface exposed on the substrate from the amount of catalyst nuclei.

In the present invention, it is preferable that the etching treatment of the portion of the surface of the resin insulating layer where no conductor circuit is formed is performed with an acid or an oxidizing agent. Examples of the acid include hydrochloric acid, sulfuric acid, formic acid, and acetic acid, and examples of the oxidizing agent include chromic acid and permanganic acid. Especially, the concentration of chromic acid is 700 ~
900 g / l is good. Within this range, the surface of the resin insulating layer can be etched without excessively dissolving the conductor circuit. The treatment temperature is preferably 50 to 80 ° C., and the immersion time is preferably about 1 to 5 minutes.

The removal amount of the resin insulating layer by such etching treatment, that is, the depth of the depression is preferably 0.1 to 10 μm, preferably 1 to 6 μm, and more preferably 3 to 5 μm. The reason is that when the catalyst nuclei and the electroless plating film remaining on the surface of the resin insulating layer where the conductive circuit is not formed are dissolved and removed by etching, the remaining electroless plating film can be surely removed, and This is because unnecessary recesses do not reduce the smoothness of the interlayer resin insulating layer formed thereon. Also, if a portion of the surface of the resin insulation layer where no conductor circuit is formed (the surface of the resin insulation layer between the conductor circuits) is excessively etched, the resin insulation layer below the conductor circuit is melted and a so-called undercut occurs. This is not preferable because air bubbles are likely to remain in the portion and the adhesion strength of the conductor circuit is reduced. In this regard, if the depth of the depression is within the above range, such undercut can be reduced.

In the present invention, when an adhesive for electroless plating is used as the resin insulating layer, the wall surfaces of the dents of the resin insulating layer formed by the etching treatment are also roughened (FIG. 1 (i)). , FIG. 13). As a result, according to the present invention, the adhesion to the interlayer resin insulating layer further formed on the conductor circuit is improved, and the delamination that easily occurs under high temperature and high humidity conditions can be suppressed.

In the present invention, it is desirable that the conductor circuit is composed of an electrolytic plating film and an electroless plating film, the electroless plating film is formed on the inner layer side, and the electrolytic plating film is formed on the outer layer side. . The reason is that the electrolytic plating film is softer and more malleable than the electroless plating film. For this reason, the conductor circuit including the electrolytic plating film can follow the dimensional change of the interlayer resin insulating layer even if the substrate warps during the heat cycle. In addition, when the roughened layer is provided on the surface of the conductive circuit, the conductive circuit adheres firmly to the interlayer resin insulating layer, and the conductive circuit more easily follows the dimensional change of the interlayer resin insulating layer.

Therefore, when the IC chip is mounted, the
When a heat cycle test at 125 ° C. is performed, generation of cracks in the interlayer resin insulating layer starting from the conductor circuit can be suppressed, and no peeling is observed. Furthermore, according to the conductor circuit in which an electroless plating film harder than the electrolytic plating film is formed on the inner layer side, the peel strength does not decrease. This is because the peel strength increases as the hardness of the inner layer side surface of the conductor circuit increases.

Here, the thickness of the electroless plating film constituting the conductor circuit is preferably in the range of 0.1 to 5 μm, and more preferably 1 to 5 μm. The reason for this is that if the electroless plating film is too thick, the film in the portion where the conductor circuit is not formed cannot be removed by etching.If the film is too thin, on the other hand, the peel strength of the conductor circuit may be reduced, or when electroplating is performed. This is because the resistance value increases and the thickness of the plating film varies.

The thickness of the electrolytic plating film constituting the conductor circuit is preferably in the range of 10 to 40 μm, and more preferably 10 to 20 μm. The reason for this is that if the electrolytic plating film is too thick, the peel strength is reduced, and if it is too thin, the ability to follow the interlayer resin insulating layer is reduced.

It is preferable that a roughened layer is formed on at least a part of the surface of the conductor circuit. The reason for forming the roughened layer is to effectively prevent cracks in the interlayer resin insulating layer caused by poor adhesion between the conductor circuit and the interlayer resin insulating layer thereover in a heat cycle test.

This roughened layer is preferably an alloy plating layer made of copper-nickel-phosphorus. This is because such an alloy layer is a needle-like crystal layer and has excellent adhesion to the interlayer resin insulating layer.

The composition of the alloy layer is 90 to 96 wt%, 1 to 5 wt%, 0.5 to 2 wt% in terms of copper, nickel and phosphorus, respectively.
Desirably, it is wt%. This is because, at these composition ratios, a needle-like structure is shown.

Such a roughened layer preferably has a thickness of 1 to 10 μm, more preferably 1 to 5 μm. The reason is that if it is too thick, the roughened layer itself is easily damaged or peeled off, while if it is too thin, the adhesion to the interlayer resin insulating layer is reduced.

In the present invention, it is desirable to use an adhesive for electroless plating as the resin insulating layer constituting the wiring board. This adhesive for electroless plating is obtained by dispersing heat-resistant resin particles soluble in a cured acid or oxidizing agent in an uncured heat-resistant resin which becomes hardly soluble in an acid or an oxidizing agent by the curing treatment. Things are best.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly subjected to the curing treatment include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, an average particle diameter of 0.8 to 2.0.
It is desirable to use at least one selected from a mixture of a heat-resistant resin powder having a diameter of 0.1 μm and a heat-resistant resin powder having an average particle diameter of 0.1 to 0.8 μm. This is because they can form more complex anchors.

Next, one method of manufacturing the multilayer printed wiring board of the present invention will be described. (1) First, a wiring board having an inner copper pattern formed on the surface of a core board is manufactured. The copper pattern is formed on the core substrate by etching the copper clad laminate, or
An adhesive layer for electroless plating is formed on a substrate such as a glass epoxy substrate, a polyimide substrate, a ceramic substrate, or a metal substrate, and the surface of the adhesive layer is roughened to a roughened surface, which is then subjected to electroless plating. There is a way.

Further, if necessary, a roughened layer made of copper-nickel-phosphorus can be formed on the surface of the wiring board. This roughened layer is formed by electroless plating.
The electroless plating has a copper ion concentration, a nickel ion concentration, and a hypophosphite ion concentration of 2.2 × 10 ^-2 ~
4.1 × 10 ^-2 mol / l, 2.2 × 10 ^-3 to 4.1 × 10 ^-3 mol /
It is desirable to use a plating solution having a composition of 0.20 to 0.25 mol / l. The reason for this is that a film deposited in such a composition range has a needle-like crystal structure and is excellent in anchor effect. Note that a complexing agent or an additive may be added to the plating solution in addition to the compound.

Other methods of forming the roughened layer include an oxidation (blackening) -reduction treatment, a method of forming a roughened surface by etching a copper surface along a grain boundary, or a product manufactured by MEC Corporation. There is a method of performing a roughening treatment with an etching solution having a name of “MEC etch bond”. Note that a through hole is formed in the core substrate, and the wiring layer on the front surface and the back surface can be electrically connected through the through hole. Further, a resin may be filled between the through hole and the conductor circuit of the core substrate to ensure smoothness.

(2) On the wiring board prepared in the above (1),
An interlayer resin insulation layer is formed. In particular, in the present invention, it is desirable to use the above-described adhesive for electroless plating as an interlayer resin insulating material (see FIG. 1A).

(3) Next, the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent to roughen the surface of the adhesive layer (see FIG. 1 (b)). . Here, as the acid, phosphoric acid, hydrochloric acid, sulfuric acid,
Alternatively, there are organic acids such as formic acid and acetic acid, and it is particularly preferable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded. On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(4) Next, a catalyst nucleus for electroless plating is applied to the wiring board whose surface of the adhesive layer has been roughened. It is desirable to use a noble metal ion or a noble metal colloid for providing the catalyst nucleus, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(5) Next, electroless plating is applied to the surface of the adhesive layer, and an electroless plating film is formed on the entire roughened surface of the adhesive layer (see FIG. 1 (c)). At this time, the thickness of the electroless plating film is 1 to 5 μm.

(6) Next, a plating resist is formed on the electroless plating film (see FIG. 1D). As the plating resist composition, it is particularly desirable to use a composition comprising an acrylate of a cresol novolak or a phenol novolak type epoxy resin and an imidazole curing agent, but other commercially available products can also be used.

(7) Next, the plating resist non-formed portion is subjected to electrolytic plating to form a conductor circuit and a via hole (see FIG. 1 (e)). Here, it is desirable to use copper plating as the electrolytic plating.

(8) Further, after the plating resist is removed, the electroless plating film under the plating resist is replaced with a mixed solution of hydrogen peroxide and sulfuric acid, sodium persulfate, potassium persulfate,
It is dissolved and removed with an etching solution such as ammonium persulfate to form an independent conductor circuit (see FIG. 1 (f)).

(9) Next, the surface of the adhesive layer located at the portion where the conductor circuit is not formed is etched with chromic acid, and the surface of the adhesive layer at that portion is 0.1 to 10 μm, preferably 1 to 6 μm.
m, more preferably 3-5 μm, to form a depression (see FIG. 1 (g)).

(10) Then, a roughened layer is formed on the surface of the conductor circuit (see FIG. 1 (h)). As a method of forming the roughened layer,
There is a method of depositing a roughened layer of a copper-nickel-phosphorus alloy layer by electroless plating. For electroless plating of this alloy, copper sulfate 1-40 g / l, nickel sulfate 0.1-6.0 g
/ L, citric acid 10-20 g / l, hypophosphite 10-100 g
/ L, boric acid 10-40 g / l, surfactant 0.01-10 g / l
It is desirable to use a plating bath having a solution composition of

(10) Further, by repeating the above (2) to (8), an interlayer resin insulating layer and an upper conductive circuit are formed (see FIG. 1 (i)).

[0043]

【Example】

(Example 1) (1) 70 parts by weight of a 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), 30 parts by weight of polyether sulfone (PES), Imidazole curing agent (Shikoku Chemicals, trade name: 2E4MZ-CN) 4
Parts by weight, 10 parts by weight of caprolactone modified tris (acryloxyethyl) isocyanurate (trade name: Alonix M325) manufactured by Toagosei Co., Ltd., 5 parts by weight of benzophenone (Kanto Chemical) as a photoinitiator, 0.5 part by weight of Michler's ketone (manufactured by Kanto Chemical) as a sensitizer, 35 parts by weight of epoxy resin particles having an average particle size of 5.5 μm and 5 parts by weight of an epoxy resin particle having an average particle size of 0.5 μm were mixed with this mixture. Thereafter, mixing was performed while adding NMP (normal methylpyrrolidone), and the viscosity was adjusted to 12 Pa · s with a homodisper stirrer, followed by kneading with three rolls to obtain a photosensitive adhesive solution (interlayer resin insulating material). .

(2) The photosensitive adhesive solution obtained in the above (1) is
Apply to the substrate using a roll coater, leave it in a horizontal state for 20 minutes, dry it at 60 ° C for 30 minutes,
m of the adhesive layer 2 for electroless plating was formed (see FIG. 1A). (3) The substrate is immersed in chromic acid for 2 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer, roughen the surface of the adhesive layer 2, and then neutralize the substrate with a neutralizing solution (Shipley Co., Ltd.). ) And washed with water (see Fig. 1 (b)).

(4) A palladium catalyst (manufactured by Atotech) is applied to a substrate having a rough surface (roughening depth: 20 μm) formed on the adhesive layer 2 so that the adhesive layer 2 and the via hole opening are formed. Catalyst nuclei were provided on the surface (not shown).

(5) The substrate was immersed in an electroless copper plating bath having the following composition to form a 3 μm-thick electroless copper plating film 12 on the entire rough surface (see FIG. 1 (c)). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(6) Electroless copper plating film formed in (5)
A commercially available photosensitive dry film is affixed on top of 12, and a mask is placed on this dry film, exposed at 100 mJ / cm ² , developed with 0.8% sodium carbonate, and processed to a thickness of 15 mm.
A μm plating resist 3 was provided (see FIG. 1D).

(7) Next, in the portion where the plating resist is not formed,
Electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 13 having a thickness of 15 μm (see FIG. 1E). [Electroplating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (trade name: Capparaside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(8) After removing the plating resist 3 with 5% KOH, the electroless plating film under the plating resist 3 is removed.
12 was dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a conductor circuit 4 having a thickness of 18 μm comprising an electroless copper plating film 12 and an electrolytic copper plating film 13 (FIG. 1 (f)). reference).

(9) The substrate on which the conductive circuit 4 is formed is heated at 70 ° C. for 80 hours.
5 g of chromic acid at 0 g / l for 5 minutes to reduce the surface of the adhesive layer 2 for electroless plating located at the part where the conductor circuit is not formed to 3 μm.
The surface to which the catalyst nuclei were attached was removed to form a depression 18 (see FIG. 1 (g)).

(10) The substrate was made of copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l Was immersed in an electroless plating solution having a pH of 9 to form a roughened layer 11 made of copper-nickel-phosphorus having a thickness of 3 μm on the surface of the conductor circuit (see FIG. 1 (h)). (11) An adhesive layer 2 'for electroless plating and an upper conductive circuit 5 are further formed by repeating (1) to (8) (FIG. 1 (i)
reference).

Example 2 A. Preparation of adhesive composition for electroless plating. 35 parts by weight of a resin solution prepared by dissolving a 25% acrylated cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) in DMDG at a concentration of 80 wt%, 35 parts by weight, and 3.15 parts by weight of a photosensitive monomer (Alonix M315 manufactured by Toa Gosei) Parts, 0.5 parts by weight of antifoaming agent (manufactured by San Nopco, S-65), and 3.
6 parts by weight were mixed with stirring. . After mixing 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle diameter of 1.0 μm, and 3.09 parts by weight of an epoxy resin particle having an average particle diameter of 0.5 μm, Further, 30 parts by weight of NMP was added and mixed by stirring with a bead mill. . 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photoinitiator (Irgacure I-, manufactured by Ciba-Geigy)
907) 2 parts by weight, photosensitizer (DETX-S, manufactured by Nippon Kayaku) 0.2
Parts by weight and 1.5 parts by weight of NMP were mixed with stirring. These were mixed to prepare an adhesive composition for electroless plating.

B. Preparation of lower interlayer resin insulation agent 35 parts by weight of a resin solution prepared by dissolving a 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) at a concentration of 80 wt% in DMDG, and 4 parts by weight of a photosensitive monomer (Toa Gosei Co., Aronix M315) Parts, 0.5 parts by weight of antifoaming agent (manufactured by San Nopco, S-65), 3.6 parts of NMP
The parts by weight were mixed with stirring. . After mixing 12 parts by weight of polyether sulfone (PES) and 14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle diameter of 0.5 μm, 30 parts by weight of NMP was further added and stirred with a bead mill. Mixed. . 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photoinitiator (Irgacure I-, manufactured by Ciba-Geigy)
907) 2 parts by weight, photosensitizer (DETX-S, manufactured by Nippon Kayaku) 0.2
Parts by weight and 1.5 parts by weight of NMP were mixed with stirring. These were mixed to prepare a resin composition to be used as a lower insulating layer constituting a two-layer interlayer resin insulating layer.

C. Preparation of resin filler 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), Si coated with a silane coupling agent on the surface and having an average particle size of 1.6 μm
O ₂ spherical particles (manufactured by Admatech, CRS 1101-CE, where the maximum particle size is not more than the thickness (15 μm) of the inner layer copper pattern described later) 170 parts by weight, leveling agent (manufactured by San Nopco, Perenol S4) 1.5 The weight of the mixture is kneaded with three rolls and the viscosity of the mixture is 45,000 ~ at 23 ± 1 ° C.
Adjusted to 49,000cps. . Imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals) 6.5
Parts by weight. These were mixed to prepare a resin filler 10.

D. Manufacturing method of printed wiring board (1) 18 μm on both sides of substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
A copper-clad laminate on which m copper foils 8 were laminated was used as a starting material (see FIG. 2). First, the copper-clad laminate is drilled, subjected to an electroless plating treatment, and etched in a pattern to form an inner copper pattern 4 on both surfaces of the substrate 1.
And a through hole 9 were formed.

(2) The substrate on which the inner layer copper pattern 4 and the through hole 9 were formed was washed with water and dried, and then used as an oxidation bath (blackening bath) as NaOH (10 g / l) and NaClO ₂ (40 g / l).
l), Na ₃ PO ₄ (6 g / l), NaOH (10 g
/ L), a roughened layer 11 was provided on the surface of the inner layer copper pattern 4 and the through hole 9 by oxidation-reduction treatment using NaBH ₄ (6 g / l) (see FIG. 3).

(3) The resin filler 10 is applied to one surface of the substrate by using a roll coater to fill the space between the conductor circuits 4 or the inside of the through hole 9, and is dried at 70 ° C. for 20 minutes. In the same way, the resin filler 10 is filled between the conductor circuits 4 or in the through holes 9 at 70 ° C., 20 ° C.
It was dried by heating for minutes (see FIG. 4).

(4) One surface of the substrate after the treatment of the above (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku) to form the surface of the inner layer copper pattern 4 and the through holes 9. Polishing was performed so that the resin filler 10 did not remain on the land surface, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Next, a heat treatment was performed at 100 ° C. for 1 hour, at 120 ° C. for 3 hours, at 150 ° C. for 1 hour, and at 180 ° C. for 7 hours to cure the resin filler 10 (see FIG. 5).

In this manner, the surface layer portion of the resin filler 10 filled in the through holes 9 and the like and the roughened layer 11 on the upper surface of the inner conductor circuit 4 are removed to smooth both surfaces of the substrate.
A wiring board is firmly adhered to the side surface of the inner conductor circuit 4 via the roughened layer 11 and the inner wall surface of the through hole 9 is tightly adhered to the resin filler 10 via the roughened layer 11. Obtained. That is, by this step, the surface of the resin filler 10 and the surface of the inner layer copper pattern 4 become flush with each other. Here, the Tg point of the filled cured resin is 155.6 ° C., and the coefficient of linear thermal expansion is 44.5 × 10 ⁻⁶ /
° C.

(5) A thickness of 2.5 μm is formed on the upper surface of the land of the inner layer conductor circuit 4 and the through hole 9 exposed by the processing of (4).
A roughened layer (irregular layer) 11 made of a Cu—Ni—P alloy was formed, and a Sn layer having a thickness of 0.3 μm was provided on the surface of the roughened layer 11 (see FIG. 6; Is not shown). The formation method is as follows. That is, the substrate was acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g
Then, plating was performed in an electroless plating bath consisting of / l and pH = 9 to form a roughened layer 11 of a Cu-Ni-P alloy on the upper surface of the copper conductor circuit 4 and the upper surface of the land of the through hole 9. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50
C., a Cu-Sn substitution reaction was performed under the conditions of pH = 1.2,
Was provided with a 0.3 μm-thick Sn layer (the Sn layer is not shown).

(6) An interlayer resin insulating material of B (viscosity: 1.5 Pa · s) is applied to both surfaces of the substrate of (5) by a roll coater.
After being left in a horizontal state for 20 minutes, drying (prebaking) was performed at 60 ° C. for 30 minutes to form an insulating layer 2a. Further, an adhesive for electroless plating of A (viscosity 7 Pa) is placed on the insulating layer 2a.
S) was applied using a roll coater, left in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes to form an adhesive layer 2b (see FIG. 7).

(7) The insulating layer 2a and the adhesive layer in the above (6)
A photomask film on which a black circle of 85 μmφ was printed was brought into close contact with both surfaces of the substrate on which 2b was formed, and was exposed at 500 mJ / cm ² using an ultra-high pressure mercury lamp. This is spray-developed with a DMTG solution, and the substrate is further subjected to an ultra-high pressure mercury lamp for 30 minutes.
Exposure at 100 mJ / cm ² and heat treatment (post bake) at 100 ° C. for 1 hour and then at 150 ° C. for 3 hours
85μ with excellent dimensional accuracy equivalent to a photomask film
Thickness with mφ opening (via hole forming opening 6)
A 35 μm interlayer resin insulating layer (two-layer structure) 2 was formed (see FIG. 8). Note that the tin plating layer was partially exposed in the opening serving as the via hole.

(8) The substrate having the openings formed is treated with chromic acid.
By immersing for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer 2b of the interlayer resin insulating layer 2,
The surface of the interlayer resin insulation layer 2 was roughened (4 μm in depth), and then immersed in a neutralizing solution (manufactured by Shipley) and washed with water (see FIG. 9). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment, a catalyst nucleus was attached to the surface of the interlayer resin insulating layer 2 and the inner wall surface of the via hole opening 6.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 12 having a thickness of 0.7 μm on the entire rough surface (see FIG. 10). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(10) Electroless copper plating film formed in (9)
A commercially available photosensitive dry film was affixed onto the substrate 12, a mask was placed, exposed at 100 mJ / cm ² , developed with 0.8% sodium carbonate, and a plating resist 3 having a thickness of 15 μm was provided (FIG. 11). reference).

(11) Then, electrolytic copper plating was applied to the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 13 having a thickness of 20 μm (see FIG. 12). [Electroplating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (captoside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(12) After stripping and removing the plating resist 3 with 5% KOH, the electroless plating film under the plating resist 3
12 was dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a conductor circuit (including via holes) 5 having a thickness of 18 μm and comprising an electroless copper plating film 12 and an electrolytic copper plating film 13. Further, the surface of the adhesive layer for electroless plating between the conductor circuits located at the portion where the conductor circuits are not formed is immersed in 800 g / l chromic acid at 70 ° C. for 3 minutes, and the surface of the adhesive layer for electroless plating is etched by 1 to 2 μm. The remaining palladium catalyst was removed to form a depression 18 (see FIG. 13).

(13) The substrate on which the conductor circuit 5 is formed is made of copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l
1, sodium hypophosphite 29 g / l, boric acid 31 g / l,
A roughened layer 11 made of copper-nickel-phosphorus having a thickness of 3 μm was formed on the surface of the conductor circuit 5 by immersion in an electroless plating solution having a pH of 9 comprising 0.1 g / l of a surfactant (see FIG. 14). ). At this time, the formed roughened layer 11 is applied to EPMA (fluorescent X
Line analyzer), Cu: 98 mol%, Ni:
The composition ratio was 1.5 mol%, P: 0.5 mol%. further,
Tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature
A Cu-Sn substitution reaction was performed under the conditions of 50 ° C. and pH = 1.2 to provide a 0.3 μm thick Sn layer on the surface of the roughened layer 11 (the Sn layer is not shown).

(14) By repeating the above steps (6) to (13), a conductor circuit of a further upper layer was formed, and a multilayer printed wiring board was obtained. However, Sn substitution was not performed (FIGS. 15 to 20).
reference).

(15) On the other hand, 60% by weight dissolved in DMDG
Cresol novolak epoxy resin (Nippon Kayaku)
46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylizing 50% of the epoxy groups of epoxy resin, 15.0 g of an 80 wt% bisphenol A type epoxy resin (made by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing 1.6 g of an agent (2E4MZ-CN, manufactured by Shikoku Chemicals Co., Ltd.) and a polyvalent acrylic monomer (R604, manufactured by Nippon Kayaku
3 g), 1.5 g of polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A), and a dispersion defoaming agent (San Nopco,
S-65) of 0.71 g, and 2 g of benzophenone (Kanto Chemical) as a photoinitiator was added to the mixture.
0.2 of Michler's ketone (Kanto Chemical) as photosensitizer
g was added to obtain a solder resist composition whose viscosity was adjusted to 2.0 Pa · s at 25 ° C. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm and the rotor No.
In the case of 4, 6 rpm, the rotor No. 3 was used.

(16) On the multilayer wiring board obtained in the above (14),
After applying a Pd catalyst and activating this catalyst, copper sulfate 8 g
/ L, nickel sulfate 0.6g / l, citric acid 15g / l, sodium hypophosphite 29g / l, boric acid 31g / l, surfactant 0.1g / l, pH = 9 in an electroless plating bath
Cu-Ni-P alloy plating is applied, and a roughened layer 11
Was formed. The solder resist composition was applied to both sides of the multilayer wiring board in a thickness of 20 μm. Then 70
° C. for 20 minutes, after the drying process for 30 minutes was carried out at 70 ° C., a circle pattern (mask pattern) is brought into close contact with a photomask film having a thickness of 5mm drawn is placed, with ultraviolet 1000 mJ / cm ² Exposure and DMTG development processing. And even 80
1 hour at 100 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C, 150 ° C
Heat treatment under the conditions of 3 hours, to open the solder pad portion (including the via hole and its land portion) (opening diameter
A 200 μm) solder resist layer (thickness: 20 μm) 14 was formed.

(17) Next, the substrate on which the solder resist layer 14 has been formed is subjected to a pH of 30 g / l of nickel chloride, 10 g / l of sodium hypophosphite, and 10 g / l of sodium citrate.
= 5 for 20 minutes to form a nickel plating layer 15 having a thickness of 5 μm at the opening. Further, the substrate was placed on an electroless gold plating solution comprising 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds. By dipping, a gold plating layer 16 having a thickness of 0.03 μm was formed on the nickel plating layer 15.

(18) Then, a solder paste is printed in the opening of the solder resist layer 14 and reflowed at 200 ° C. to form a solder bump (solder body) 17. A printed wiring board having the solder bump 17 is formed. Manufactured (see FIG. 21).

Comparative Example A printed wiring board having solder bumps was manufactured in the same manner as in Example 2 except that the removal of the catalyst nucleus in step (12) of Example 2 was omitted.

With respect to the wiring boards of Examples 1 and 2 and Comparative Example manufactured as described above, the amount of the Pd catalyst remaining on the surface of the adhesive layer located at the portion where the conductive circuit was not formed was evaluated. In this evaluation, the same conditions as in Examples 1 and 2 were used to eliminate the need to calculate the area of the catalyst nucleus-applied surface exposed from the substrate, but a substrate not subjected to electroless plating and electrolytic plating was manufactured. Removing the catalyst core under the same conditions as in Examples 1 and 2,
This substrate was cut into a square of 5 cm and used as a test body.
The same applies to the comparative example except that the catalyst core was not removed. The surface area of this test piece is 5 × 5 × 2 = 50 cm ² because the catalyst nucleus-applying surface is present on the front and back surfaces. . The test body to which the catalyst nuclei were attached was immersed in 6N hydrochloric acid and left as it was for 24 hours. . The concentration of palladium ions constituting the catalyst core in a hydrochloric acid solution was measured by an atomic absorption method. The measuring device is [SA
S 7500A (manufactured by Seiko Electronic Industry Co., Ltd.)] was used. . From the concentrations measured above, the amount of catalyst nuclei attached to the test specimen was calculated in terms of palladium ion, and the amount of palladium ions per unit area of the catalyst nucleus-applied surface of the test specimen was calculated and evaluated.

As a result, the amounts of palladium ions in Examples 1 and 2 were 0.05 μg / cm ² and 0.1 μg / cm ² , respectively. On the other hand, in the comparative example, it was 8 μg / cm ² . Therefore, in Examples 1 and 2, no deposition of copper-nickel-phosphorous was observed in the portion of the substrate where no conductor circuit was formed, but in the comparative example, copper-nickel-phosphorous was not deposited in that portion.
Phosphorus precipitation was observed. When conduction between the conductor circuits was confirmed using a conduction checker, no short circuit was observed between the conductor circuits in Examples 1 and 2, but a short circuit was observed in the comparative example.

The PCT test (pressure cooker tes)
When t) was performed at 2 atmospheres, 100% humidity, 121 ° C. for 1000 hours, in the comparative example, peeling was observed between the conductor circuit and the adhesive layer for electroless plating formed thereon, In Examples 1 and 2, peeling was not observed. In Example 1, not only the bottom surface but also the wall surface of the depression 18 was roughened, and the adhesion between the resin insulating layer 2 and the adhesive layer 2 ′ for electroless plating formed on the conductor circuit was excellent. It is considered that the adhesion between the conductor circuit and the adhesive layer 2 'for electroless plating formed thereon is also excellent.

[0078]

As described above, according to the multilayer printed wiring board of the present invention, even if the roughened layer on the conductor circuit surface is formed by electroless plating, no short circuit between the conductor circuits occurs.
And it is possible to secure the insulation reliability between the conductor circuits
Both are interlayer resin insulation layers including resin insulation layers and conductor circuits
Excellent adhesion with

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to the present invention.

FIG. 2 is a view showing each manufacturing process of a multilayer printed wiring board in Example 2.

FIG. 3 is a view showing each manufacturing process of a multilayer printed wiring board in Example 2.

FIG. 4 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 5 is a view showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 6 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 7 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 8 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 9 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 10 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 11 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 12 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 13 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 14 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 15 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 16 is a diagram showing each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 17 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Example 2.

FIG. 18 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Embodiment 2.

FIG. 19 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Embodiment 2.

FIG. 20 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Embodiment 2.

FIG. 21 is a diagram illustrating each manufacturing process of the multilayer printed wiring board in Example 2.

[Explanation of symbols]

Reference Signs List 1 substrate 2 interlayer resin insulating layer (adhesive layer for electroless plating) 2 'interlayer resin insulating layer (adhesive layer for electroless plating) formed on conductive circuit 2a insulating layer 2b adhesive layer 3 plating resist 4 Inner layer conductor circuit (Inner layer copper pattern) 5 Outer layer conductor circuit (Outer layer copper pattern) 6 Via hole opening 7 Via hole (BVH) 8 Copper foil 9 Through hole 10 Filled resin (resin filler) 11 Roughened layer 12 Electroless copper Plating film 13 Electrolytic copper plating film 14 Solder resist layer 15 Nickel plating layer 16 Gold plating layer 17 Solder bump 18 Depression

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-186351 (JP, A) JP-A-6-283860 (JP, A) JP-A 5-304362 (JP, A) (58) Field (Int. Cl. ⁷ , DB name) H05K 3/00-3/46

Claims (6)

(57) [Claims] 1. A roughened layer is formed on a surface of a resin insulating layer of a substrate.
Is, that the roughened layer is formed a conductor circuit at least partially made of an electroless plating, further small that the conductor circuit
A roughened layer is formed at least in part,
In a multilayer printed wiring board in which an interlayer resin insulating layer is formed on a circuit, the amount of electroless plating catalyst nuclei remaining in a portion where a conductor circuit is not formed on the surface of the resin insulating layer is calculated in terms of metal ions.
A multilayer printed wiring board characterized by being 0.01 to 1.0 μg / cm ² . 2. The multilayer printed wiring board according to claim 1, wherein the roughening layer is a copper-nickel-phosphorus alloy plating layer. 3. A roughened layer is formed on a surface of a resin insulating layer formed on a substrate.
Is formed on the surface of the roughened layer, a catalyst nucleus for electroless plating is applied to form an electroless plating film, and then a plating resist is provided and electrolytic plating is performed, and then the plating resist is removed . Thereafter, by etching the electroless plating film under the plating resist to form a conductive circuit, a method of manufacturing a multilayer printed wiring board, further comprising: forming an interlayer resin insulating film on the conductive circuit formed on the surface of the resin insulating layer. In forming the layer, the surface of the conductor circuit
By forming a roughened layer on at least a part of the surface , and further performing an etching process on a portion of the surface of the resin insulating layer where a conductive circuit is not formed, the amount of the electroless plating catalyst nuclei remaining in the portion is calculated in terms of metal ions. 0.01 to 1.0 g / cm ²
A method for producing a multilayer printed wiring board. Wherein said etching process, a method for manufacturing a multilayer printed wiring board according to claim 3, characterized in that by using an acid or oxidizing agent. 5. The method according to claim 1, further comprising forming a roughened layer on at least a part of the surface of the conductor circuit when forming the interlayer resin insulation layer on the conductor circuit formed on the surface of the resin insulation layer. 5. The method for producing a multilayer printed wiring board according to 3 or 4 . Wherein said roughened layer is a copper - nickel - claim, characterized in that an alloy plating of phosphorus 3-5
The method for producing a multilayer printed wiring board according to any one of the above.