KR102436225B1 - Printed circuit board - Google Patents

Abstract

The present invention relates to a printed circuit board. The printed circuit board includes an insulating material having one surface and the other surface facing each other; a circuit layer formed on the one surface and the other surface of the insulating material; and a metal layer formed on the circuit layer, wherein the electrical conductivity of the metal layer is smaller than the electrical conductivity of the circuit layer, and the thickness of the metal layer located on the one side of the insulating material is on the other side of the insulating material. greater than the thickness of the metal layer on which it is located.

Description

Printed Circuit Board {PRINTED CIRCUIT BOARD}

The present invention relates to a printed circuit board.

In the PCB manufacturing process, warpage may occur while the PCB is subjected to a heat treatment process. As electronic products become smaller and thinner, PCBs are also becoming thinner, and as the thinning progresses, the defect rate due to warpage can become a problem. The causes of warpage are various, such as the difference in the coefficient of thermal expansion (CTE) between the resin insulating material and the metal circuit, and the difference in the elastic modulus. In order to control warpage, a technology for controlling the insulating material, such as the development of a low expansion resin and the control of the inorganic filler content, has been developed. On the other hand, in addition to the technology for controlling the insulation material to reduce the warpage, a technology for adding a warpage preventing structure to the printed circuit board or controlling the design of the circuit is being developed.

Korea Patent Publication No. 2016-0080433 (published on July 8, 2016)

According to an aspect of the present invention, an insulating material having one surface and the other surface facing each other; a circuit layer formed on the one surface and the other surface of the insulating material; and a metal layer formed on the circuit layer, wherein the electrical conductivity of the metal layer is smaller than the electrical conductivity of the circuit layer, and the thickness of the metal layer located on the one side of the insulating material is on the other side of the insulating material. A printed circuit board greater than the thickness of the metal layer is provided.

According to an aspect of the present invention, an insulating material having one surface and the other surface facing each other; at least one first insulating layer laminated on the one surface of the insulating material; at least one second insulating layer laminated on the other surface of the insulating material; a first circuit layer formed on at least one of the one or more first insulating layers; a second circuit layer formed on at least one of the one or more second insulating layers; a first metal layer formed on the first circuit layer; and a second metal layer formed on the second circuit layer, wherein the electrical conductivity of the first metal layer is smaller than the electrical conductivity of the first circuit layer, and the electrical conductivity of the second metal layer is that of the second circuit layer. The printed circuit board is smaller than the electrical conductivity and the thickness of the first metal layer is greater than the thickness of the second metal layer.

According to one aspect of the present invention, an insulating material; a circuit layer formed on the insulating material; a metal layer formed on the circuit layer and having an electrical conductivity smaller than that of the circuit layer; an insulating layer laminated on the insulating material; There is provided a printed circuit board including a via hole penetrating the insulating layer and the metal layer, the circuit layer being exposed through a bottom surface of the via hole.

1 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
2 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
3 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
4 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
5 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
6 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
7 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
8 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
9 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
10 to 20 are views showing a printed circuit board manufacturing method according to an embodiment of the present invention.
21 is a view showing various circuit layers according to a circuit forming method;
22 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
23 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
24 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
Fig. 25 is a partially enlarged view of Fig. 24;
26 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
Fig. 27 is a partially enlarged view of Fig. 26;
28 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.
Fig. 29 is a partially enlarged view of Fig. 28;

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated. In addition, throughout the specification, "on" means to be located above or below the target part, and does not necessarily mean to be located above the direction of gravity.

In addition, in the contact relationship between each component, the term "coupling" does not mean only when there is direct physical contact between each component, but another component is interposed between each component, so that the component is in the other component It should be used as a concept that encompasses even the cases in which each is in contact.

Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

Since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

An embodiment of a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals, and overlapping descriptions thereof are to be omitted.

In addition, each embodiment of the present invention described below is not necessarily a concept representing only one embodiment, and should be understood as a concept encompassing embodiments dependent on each embodiment.

1 to 9 are cross-sectional views of a printed circuit board according to various embodiments.

1, the printed circuit board according to an embodiment of the present invention includes an insulating material 110, a circuit layer 120 and a metal layer 130, and the electrical conductivity of the metal layer 130 is the circuit layer ( 120), and the thickness of the metal layer 131 positioned on the one side of the insulating material 110 may be greater than the thickness of the metal layer 132 positioned on the other side of the insulating material 110.

The insulating material 110 is a material composed of an insulating material such as resin, and has a thin plate shape. Except for the side surface of the insulating material 110 , both surfaces facing each other may be referred to as one surface and the other surface. That is, the insulating material 110 may have one surface and the other surface.

The resin of the insulating material 110 may be various materials such as a thermosetting resin or a thermoplastic resin, and specifically, may be an epoxy resin or polyimide. Here, the epoxy resin is, for example, a naphthalene type epoxy resin, a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a novolak type epoxy resin, a cresol novolak type epoxy resin, a rubber modified type epoxy resin, a cyclic alipha It may be a tick-based epoxy resin, a silicone-based epoxy resin, a nitrogen-based epoxy resin, a phosphorus-based epoxy resin, and the like, but is not limited thereto.

The insulating material 110 may be a prepreg (PPG) or a build-up film. In the case of the prepreg, a fiber reinforcement such as glass cloth may be included in the resin. In the case of the build-up film, an inorganic filler such as silica may be filled in the resin. As such a build-up film, Ajinomoto Build-up Film (ABF) or the like may be used.

The insulating material 110 may be a core positioned in the middle of the printed circuit board, or may be each layer laminated on the core.

The circuit layer 120 is a conductor that is formed on one surface and the other surface of the insulating material 110 and is patterned to transmit electrical signals. The circuit layer 120 may be understood as a set of a plurality of circuit patterns, and each circuit pattern of the circuit layer 120 is formed to have a predetermined width and thickness, and the length and direction are determined according to the circuit design design. .

The circuit layer 120 may be formed of a metal, and in consideration of electrical conductivity, copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum It may be made of a metal such as (Pt) or an alloy thereof.

The circuit layer 120 may include a seed layer S1 . The seed layer S1 may be formed of the same metal as the circuit layer 120 . The presence of the seed layer S1 may be determined according to the method of forming the circuit layer 120 . In particular, when the circuit layer 120 is formed by a method such as SAP or MSAP, the circuit layer 120 includes a seed layer ( S1) may be included.

In FIG. 1 , it can be understood that the circuit layer 120 is an example formed by the SAP method, wherein the seed layer S1 is directly formed on one surface and the other surface of the insulating material 110 . Alternatively, if the circuit layer 120 is formed by the MSAP method, the seed layer S4 may appear slightly spaced apart from one surface and the other surface of the insulating material 110 (refer to FIG. 21(c) ). Here, the separation distance between the seed layer S4 and the one surface (or the other surface) of the insulating material 110 will match the thickness of the thin metal foil (copper foil) M of the raw material used in the MSAP.

Although the invention has been described with reference to FIG. 1 , the circuit layer 120 does not necessarily have to be formed by the SAP method, nor does it exclude other methods including MSAP. For example, when the circuit layer 120 is formed by a subtractive or tenting method as shown in FIG. 21(b), the circuit layer 120 may not include a seed layer, which is the SAP method of FIG. 21(a). It is different from the circuit layer 120 formed by

The circuit layer 120 may be divided into a first circuit layer 121 formed on one surface of the insulating material 110 and a second circuit layer 122 formed on the other surface of the insulating material 110 .

In the circuit layer 120 , the first circuit layer 121 formed on one surface of the insulating material 110 and the second circuit layer 122 formed on the other surface of the insulating material 110 may have substantially the same thickness. For example, the thickness of the first circuit layer 121 and the second circuit layer 122 may be 15 μm.

The metal layer 130 is formed on the circuit layer 120 and is a layer made of metal. The metal of the metal layer 130 may be an alloy material, and specifically, a Fe-Ni (nickel steel) alloy such as invar, or a copper alloy such as brass, which is a Cu-Zn alloy.

The metal layer 130 may be formed to contact the circuit layer 120 , and may be formed to match the width of the circuit layer 120 . In this case, only the metal layer 130 may be observed and the circuit layer 120 may not be observed in the plan view. However, it is not limited to this shape, and a structure in which the metal layer 130 and the circuit layer 120 do not contact will be described later.

The electrical conductivity of the metal layer 130 is smaller than the electrical conductivity of the circuit layer 120 . Accordingly, the electrical signal may be substantially transmitted to the circuit layer 120 .

The thickness of the metal layer 130 may be smaller than the thickness of the circuit layer 120 . The thickness of the metal layer 130 does not exceed 2/3 of the thickness of the circuit layer 120 to which it is coupled.

Since the electrical conductivity of the metal layer 130 is smaller than the electrical conductivity of the circuit layer 120 , the metal layer 130 is formed to have a smaller thickness than the circuit layer 120 , thereby achieving effective signal transmission. Here, the circuit layer 120 may have a thickness of 15 μm, and the metal layer 130 may have a thickness of 2-5 μm.

The metal layer 130 includes a first metal layer 131 formed on the first circuit layer 121 and a second metal layer 132 formed on the second circuit layer 122 . That is, the first metal layer 131 is formed on one side of the insulating material 110 , and the second metal layer 132 is formed on the other side of the insulating material 110 .

The thickness of the metal layer 131 positioned on one side of the insulating material 110 may be greater than the thickness of the metal layer 132 positioned on the other side of the insulating material 110 . That is, the thickness of the first metal layer 131 may be greater than the thickness of the second metal layer 132 .

As the printed circuit board is heat treated in the manufacturing process, warpage may occur in the printed circuit board. The metal layer 130 can control warpage of the printed circuit board, and in particular, by making the thickness of the metal layer 130 formed on both sides of the insulating material 110 different from each other, the warpage of the printed circuit board can be effectively controlled. .

For example, if the printed circuit board is bent convexly downward (when viewed from the side) when there is no metal layer (smile), the metal layer 130 on the lower surface of the insulating material 110 is formed relatively thickly to reduce warpage and , Conversely, if the printed circuit board is bent convexly upward when there is no metal layer (crying), the metal layer 130 on the upper surface side of the insulating material 110 is formed to be relatively thick to reduce warpage.

The coefficient of thermal expansion of the metal layer 130 may be smaller than the coefficient of thermal expansion of the circuit layer 120 . In this case, the rigidity of the metal layer 130 may be greater than that of the circuit layer 120 . Alternatively, the coefficient of thermal expansion of the metal layer 130 may be greater than that of the circuit layer 120 , and in this case, the rigidity of the metal layer 130 may be less than that of the circuit layer 120 .

Here, rigidity means the strain with respect to an external force, and it can be simply regarded as the strain when an axial force (normal stress) is given. This stiffness depends on the modulus of elasticity or Young's modulus, and it can be understood that the greater the modulus or Young's modulus, the greater the stiffness.

The coefficient of thermal expansion of the metal layer 130 is smaller than the coefficient of thermal expansion of the circuit layer 120 , and the rigidity of the metal layer 130 is greater than that of the circuit layer 120 . There is an example in which this invar is formed. In addition, the thermal expansion coefficient of the metal layer 130 is greater than the thermal expansion coefficient of the circuit layer 120, and the rigidity of the metal layer 130 is smaller than the rigidity of the circuit layer 120, and the circuit layer 120 is made of copper, metal layer ( 130) is formed of brass.

In any case, the thermal expansion coefficient of the metal layer 130 is smaller than the thermal expansion coefficient of the resin of the insulating material 110 , and the rigidity of the metal layer 130 is greater than the rigidity of the resin of the insulating material 110 , so it is formed on both sides of the insulating material 110 . The warpage of the printed circuit board may be controlled by adjusting the thickness difference between the metal layers 131 and 132 , that is, the thickness difference between the first metal layer 131 and the second metal layer 132 .

On the other hand, the difference in the thickness of the first metal layer 131 and the second metal layer 132 is a wiring density difference between both surfaces of the insulating material 110 , that is, the first circuit layer 121 and the second circuit layer 122 . can be determined according to the difference in wiring density of The wiring density of the circuit layer 120 is determined by the volume of the circuit layer 120 . In other words, the thickness of the metal layer 130 may be set in consideration of the volume of the circuit layer 120 . Here, the volume of the circuit layer 120 means the total volume of the plurality of circuit patterns constituting the circuit layer 120 .

For example, when the volume of the first circuit layer 121 positioned on one side of the insulating material 110 is smaller than the volume of the second circuit layer 122 positioned on the other side of the insulating material 110, the insulating material ( The thickness of the first metal layer 131 positioned on one side of the 110 may be greater than the thickness of the second metal layer 132 positioned on the other side of the insulating material 110 .

Specifically, when the volume of the circuit layer 120 positioned on the upper surface of the insulating material 110 is small and the volume of the circuit layer 120 positioned on the lower surface of the insulating material 110 is large, the coefficient of thermal expansion is the upper surface of the insulating material 110 . This is relatively large and the rigidity of the upper surface of the insulating material 110 is relatively small, so during the heat treatment of the printed circuit board, bending may occur in a convex shape, and the metal layer 130 located on the upper surface of the insulating material 110 By making the thickness greater than the thickness of the metal layer 130 positioned on the lower surface of the insulating material 110 , the printed circuit board warpage can be controlled by balancing the coefficient of thermal expansion and rigidity of the upper and lower surfaces of the insulating material 110 .

Conversely, when the volume of the circuit layer 120 positioned on the upper surface of the insulating material 110 is large and the volume of the circuit layer 120 positioned on the lower surface of the insulating material 110 is small, the coefficient of thermal expansion is the lower surface of the insulating material 110 . Since the lower surface of the insulating material 110 is relatively large, and the rigidity is relatively small, bending may occur in a convex shape downward during heat treatment of the printed circuit board, and the metal layer 130 located on the lower surface of the insulating material 110 may be By making the thickness greater than the thickness of the metal layer 130 positioned on the upper surface of the insulating material 110 , the bending of the printed circuit board can be controlled by balancing the coefficient of thermal expansion and rigidity of the upper and lower surfaces of the insulating material 110 .

As a result, the metal layer 130 has small electrical conductivity and thickness compared to the circuit layer 120, and does not substantially participate in electrical signal transmission through the circuit layer 120, while the metal layer 131 on both sides of the insulating material 110, 132) Depending on the thickness difference, it can play a role in controlling the warpage of the printed circuit board.

Referring to FIG. 2 , the printed circuit board according to the embodiment of the present invention may include a through via 140 .

The through via 140 is formed through the inside of the insulating material 110 , and connects the first circuit layer 121 formed on one surface of the insulating material 110 and the second circuit layer 122 formed on the other surface of the insulating material 110 . .

The through-via 140 may be formed by forming a conductive layer inside the through-via hole 141 penetrating the inside of the insulating material 110 . Here, the conductive layer may include a plating layer, conductive paste, conductive ink, and the like.

Meanwhile, the through-via 140 and the circuit layer 120 may include a seed layer S1 , and the seed layer S1 may be formed on the inner wall of the through-via hole 141 and one and the other surfaces of the insulating material 110 . have. In this case, the conductive layer of the through-via 140 may include a seed layer S1 formed by electroless plating and an electrolytic plating layer formed by electroplating.

Referring to FIG. 3 , the printed circuit board according to the embodiment of the present invention may include a through-via 140 and an alloy layer 150 .

The through via 140 is formed through the inside of the insulating material 110 , and connects the first circuit layer 121 formed on one surface of the insulating material 110 and the second circuit layer 122 formed on the other surface of the insulating material 110 . .

The through-via 140 may be formed by forming a conductive layer inside the through-via hole 141 penetrating the inside of the insulating material 110 .

The alloy layer 150 may be formed between the insulating material 110 and the through-via 140 , and between the insulating material 110 and the circuit layer 120 . The alloy layer 150 may be formed of the same metal as the metal layer 130 .

As shown in FIG. 3 , the alloy layer 150 may include a seed layer S2 . The seed layer S2 may be formed of the same metal as the alloy layer 150 . The seed layer S2 may be formed on the inner wall of the through-via hole 141 and one and the other surfaces of the insulating material 110 . In this case, the conductive layer may be a plating layer, particularly a plating layer formed by electroplating. Also, in this case, the width of the through-via 140 is smaller than the width of the through-via hole 141 .

Referring to FIG. 4 , in the alloy layer 150 described with reference to FIG. 3 , the thickness of the first alloy layer 151 positioned on one surface of the insulating material 110 is the thickness of the first alloy layer 151 positioned on the other surface of the insulating material 110 . 2 It may be greater than the thickness of the alloy layer 152 . The thickness of the third alloy layer 153 formed between the inner wall of the through-via hole 141 , that is, the insulating material 110 and the through-via 140 , is determined by the first alloy layer 151 and/or the second alloy layer 152 . It may be the same as or different from the thickness of the through-via 140 , but should not be too large to secure the width of the through-via 140 , so it may be smaller than the thickness of the second alloy layer 152 .

Referring to FIG. 5 , the printed circuit board according to the embodiment of the present invention may include a solder resist layer 170 .

The solder resist layer 170 is stacked on the metal layer 130 and may be formed of a photosensitive insulating material. An opening O may be formed in the solder resist layer 170 , and the circuit layer 120 may be exposed through the opening O . The exposed region of the circuit layer 120 becomes a wire bonding pad or a solder ball pad for connecting electronic components. In order to expose the circuit layer 120 through the opening O of the solder resist layer 170 , the metal layer 130 may not be formed in the opening O region. Since the electrical conductivity of the metal layer 130 is smaller than that of the circuit layer 120 , it is advantageous in terms of electrical signal transmission that the pad region is a part of the circuit layer 120 rather than the metal layer 130 .

Referring to FIG. 6 , the printed circuit board according to the embodiment of the present invention may further include a surface treatment layer 171 in the printed circuit board described with reference to FIG. 5 .

The surface treatment layer 171 is formed on the region of the circuit layer 120 exposed through the opening O of the solder resist layer 170 to prevent oxidation of the circuit layer 120 . The surface treatment layer 171 may be formed of a metal. The surface treatment layer 171 made of a metal material may be formed of nothing. In addition, the surface treatment layer 171 may be composed of a plurality of layers. For example, the surface treatment layer 171 may be formed of gold. Also, the surface treatment layer 171 ′ may be formed of a plurality of layers of a nickel layer and a gold layer. In this case, the 'circuit layer (copper layer)-nickel layer-gold layer' is formed in the order, so that the nickel layer can prevent diffusion between the copper layer and the gold layer. Meanwhile, the surface treatment layer 171 may be formed of a non-metal such as OSP.

Referring to FIG. 7 , the printed circuit board according to the embodiment of the present invention may include a build-up layer 160 . The build-up layer 160 may include insulating layers 161 and 162 , build-up circuit layers 163 and 164 , vias 165 , and build-up metal layers 167 and 168 . In FIG. 7 , one buildup layer 160 is formed on each side of the printed circuit board as four layers (based on the number of circuit layers). The substrate is 4 layers, 6 layers, 8 layers... The number of circuit layers may vary.

The insulating layers 161 and 162 are stacked on the metal layer 130 , the first insulating layer 161 is on the first metal layer 131 and the second insulating layer 162 is on the second metal layer 132 . each is stacked.

The insulating layers 161 and 162 are made of an insulating material such as resin, and the resin of the insulating layers 161 and 162 may be various materials such as a thermosetting resin or a thermoplastic resin, and specifically, it may be an epoxy resin or polyimide, etc. .

The insulating layers 161 and 162 may be a prepreg (PPG) or a build-up film. In the case of the prepreg, a fiber reinforcement such as glass cloth may be included in the resin. In the case of the build-up film, an inorganic filler such as silica may be filled in the resin. As such a build-up film, Ajinomoto Build-up Film (ABF) or the like may be used.

The insulating layers 161 and 162 may be formed of the same material as the insulating material 110 or may be formed of different materials. For example, the insulating material 110 may be a prepreg, and the insulating layers 161 and 162 may be formed of a build-up film.

The build-up circuit layers 163 and 164 are conductors formed on the insulating layers 161 and 162 and patterned to transmit electrical signals. The build-up circuit layers 163 and 164 are substantially the same as the above-described circuit layer 120 in terms of function, but they need to be distinguished for explanation, so the terms build-up circuit layers 163 and 164 are introduced.

The build-up circuit layers 163 and 164 may be understood as a set of a plurality of circuit patterns. The circuit layer 120 and the build-up circuit layers 163 and 164 may be functionally understood to have the same configuration, so that the description of the circuit layer 120 is also applied to the build-up circuit layers 163 and 164 . However, the formed positions are different from each other. The circuit layer 120 is a set of circuit patterns formed on the insulating material 110 as a core, and the build-up circuit layers 163 and 164 are formed on the insulating layers 161 and 162 stacked on the insulating material 110 . It is a set of circuit patterns that become The build-up circuit layers 163 and 164 may have substantially the same thickness as the circuit layer 120 .

The build-up circuit layers 163 and 164 may be formed of metal, and in consideration of electrical conductivity, copper (Cu), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold ( Au), a metal such as platinum (Pt), or an alloy thereof may be formed.

The buildup circuit layers 163 and 164 may include a seed layer S3 . The seed layer S3 may be formed of the same metal as the build-up circuit layers 163 and 164 . The presence of the seed layer S3 may be determined according to a method of forming the build-up circuit layers 163 and 164 . In particular, when the build-up circuit layers 163 and 164 are formed by a method such as SAP or MSAP, build A seed layer S3 may be included in the up-circuit layers 163 and 164 .

Although the invention has been described with reference to FIG. 7 , the build-up circuit layers 163 and 164 are not necessarily formed by the SAP method, and other methods including MSAP are not excluded.

The build-up circuit layers 163 and 164 are a first build-up circuit layer 163 formed on one side of the insulating material 110 and a second build-up circuit layer 164 formed on the other side of the insulating material 110 . can be distinguished.

The first buildup circuit layer 163 and the second buildup circuit layer 164 may have substantially the same thickness, for example, the first buildup circuit layer 163 and the second buildup circuit layer ( 164) may have a thickness of 15 μm.

The via 165 is a conductor that penetrates the insulating layers 161 and 162 to connect the build-up circuit layers 163 and 164 and the circuit layer 120 , and transfers electrical signals between circuit patterns in different layers. The via 165 may be formed of the same metal as the build-up circuit layers 163 and 164 and the circuit layer 120 .

The metal layer 130 is not formed in the via 165 formation region so that the via 165 is in direct contact with the circuit layer 120 . Since the electrical conductivity of the metal layer 130 is smaller than that of the circuit layer 120 , direct contact between the via 165 and the circuit layer 120 is advantageous in electrical signal transmission.

The via 165 may be formed by forming a conductive layer inside the via hole 166 formed in the insulating layers 161 and 162 . Here, the conductive layer may be a plating layer or the like.

The build-up circuit layers 163 and 164 and the via 165 may include a seed layer S3 , and the seed layer S3 includes an inner surface (inner wall and bottom) of the via hole 166 and an insulating layer 161 . , 162) may be formed on. In this case, the conductive layer is a plating layer formed by electroplating, and the via 165 includes a seed layer S3 formed by electroless plating and a plating layer formed by electroplating.

The build-up metal layers 167 and 168 are formed on the build-up circuit layers 163 and 164 and may be made of the same metal as the metal layer 130 . Since the build-up metal layers 167 and 168 function substantially the same as the metal layer 130 , the above-described description of the metal layer 130 may be equally applied to the build-up metal layers 167 and 168 .

The thickness of the build-up metal layers 167 and 168 positioned on the one side of the insulating material 110 may be greater than the thickness of the build-up metal layers 167 and 168 positioned on the other side of the insulating material 110 . .

The build-up metal layer formed on the first build-up circuit layer 163 and the build-up metal layer formed on the first build-up metal layer 167 and the second build-up circuit layer 164 are formed on the second build-up metal layer 168 . ), and the thickness of the first buildup metal layer 167 may be greater than the thickness of the second buildup metal layer 168 . This allows the warpage of the printed circuit board to be controlled.

The thickness of the build-up metal layers 167 and 168 may be determined according to the wiring density of the circuit layer 120 and/or the build-up circuit layers 163 and 164 . For example, the wiring density of the first circuit layer 121 and/or the first buildup circuit layer 163 is higher than the wiring density of the second circuit layer 122 and/or the second buildup circuit layer 164 . When it is small, the thickness of the first build-up metal layer 167 may be greater than the thickness of the second build-up metal layer 168 .

Referring to FIG. 7 , the printed circuit board according to the embodiment of the present invention may further include a solder resist layer 170 .

The solder resist layer 170 is stacked on the build-up metal layers 167 and 168 and may be formed of a photosensitive insulating material. An opening O may be formed in the solder resist layer 170 , and the build-up circuit layers 163 and 164 may be exposed through the opening O. Exposed regions of the build-up circuit layers 163 and 164 become pads. In order to expose the build-up circuit layers 163 and 164 through the opening O of the solder resist layer 170 , the build-up metal layers 167 and 168 may not be formed in the opening O region. Since the electrical conductivity of the build-up metal layers 167 and 168 is smaller than the electrical conductivity of the build-up circuit layers 163 and 164, the pad area is the build-up circuit layer 163, not the build-up metal layers 167 and 168. 164) is advantageous in terms of electrical signal transmission.

Referring to FIG. 8 , the printed circuit board according to the embodiment of the present invention may further include a surface treatment layer 171 in the printed circuit board described with reference to FIG. 7 .

The surface treatment layer 171 is formed on the regions of the build-up circuit layers 163 and 164 exposed through the opening O of the solder resist layer 170 , and the build-up circuit layers 163 and 164 are oxidized. can prevent The surface treatment layer 171 may be formed of a metal. The surface treatment layer 171 made of a metal material may be formed by electroless plating. In addition, the surface treatment layer 171 may be composed of a plurality of layers. For example, the surface treatment layer 171 may be formed of gold. Also, the surface treatment layer 171 ′ may be formed of a plurality of layers of a nickel layer and a gold layer. In this case, the 'build-up circuit layer (copper layer)-nickel layer-gold layer' may be formed in the order. The nickel layer may prevent diffusion between the copper layer and the gold layer. Meanwhile, the surface treatment layer 171 may be formed of a non-metal such as OSP.

Referring to FIG. 9 , in the printed circuit board described with reference to FIG. 6 , the metal layer 130 and the circuit layer 120 may be spaced apart from each other in the thickness direction. That is, the metal layer 130 may be formed to be spaced apart from the circuit layer 120 . The solder resist layer 170 may be further formed in a space in which the metal layer 130 and the circuit layer 120 are spaced apart. In other words, the metal layer 130 may be positioned in the middle of the solder resist layer 170 .

The metal layer 130 may extend to a region where the circuit layer 120 is not formed. In this case, the metal layer 130 formation region (cross-sectional area) is larger than the circuit layer 120 formation region (cross-sectional area). However, even in this case, the metal layer 130 is not formed in the opening O of the solder resist layer 170 . The metal layer 130 may be a metal sheet in which a hole is formed corresponding to the area of the opening O. That is, the metal layer 130 is not patterned according to the pattern of the circuit pattern of the circuit layer 120 . Also, in this case, all electrical signals are transmitted to the circuit layer 120 and not to the metal layer 130 .

With respect to the thickness of the metal layer 130 , the thickness of the first metal layer 131 positioned on one side of the insulating material 110 may be greater than the thickness of the second metal layer 132 positioned on the other side of the insulating material 110 . Thereby, the warpage of the printed circuit board can be controlled. In addition, the matters described with reference to FIG. 6 may be applied to the present embodiment as well.

Hereinafter, a method of manufacturing a printed circuit board according to an embodiment of the present invention will be introduced.

10 to 20 are views showing a method of manufacturing a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 10 , a through-via hole 141 is formed in the insulating material 110 , and a seed layer S1 is formed on an inner wall of the through-via hole 141 and one and the other surfaces of the insulating material 110 . The through-via hole 141 may be formed using a drill bit or the like, and the seed layer S1 may be formed by electroless plating. The through-via 140 may include an electroplating layer electrolytically plated on the seed layer S1 .

Referring to FIG. 11 , the circuit layer 120 is formed using a plating resist R1 . Here, the first circuit layer 121 , the electrolytic plating layer of the through-via 140 , and the second circuit layer 122 may be formed in the same plating process.

The height (thickness) of the first circuit layer 121 and the second circuit layer 122 is smaller than the height (thickness) of the plating resist R1 . This is to form the metal layer 130 using the same plating resist R1.

That is, referring to FIG. 12 , the metal layer 130 is formed on the circuit layer 120 . The metal layer 130 may be formed by electroplating using a plating resist R1 .

Referring to FIG. 13 , the plating resist R1 is peeled off, and an unnecessary portion of the seed layer S1 is removed. The unnecessary removal of the seed layer S1 may be performed by etching. Here, the 'unnecessary part' means a place that is not a region of the circuit layer 120 and is to prevent unnecessary short circuit.

14 to 17 , a buildup layer 160 is formed.

14 and 15 , insulating layers 161 and 162 are stacked on the metal layer 130 , and a via hole 166 is formed. The via hole 166 may be formed in such a way that even a partial region of the metal layer 130 is removed. In this case, the via hole 166 is formed in stages. That is, the via hole A of the insulating layer 161 and 162 region is first removed to expose the metal layer 130 ( FIG. 14 ), and then the via hole B of the metal layer 130 region is removed ( FIG. 15 ). . This is due to a material difference between the insulating layers 161 and 162 and the metal layer 130 .

The via hole A in the insulating layer 161 and 162 region may be formed by laser drilling, and the via hole B in the metal layer 130 region may be formed by etching. By setting the metal layer 130 and the circuit layer 120 to react with different etching solutions, the circuit layer 120 may serve as a stopper in etching the metal layer 130 . Also, when the metal layer 130 is etched, the insulating layers 161 and 162 may serve as etching resists.

That is, when looking at the cross-sectional shape of the via hole 166 , the width of the via hole A of the insulating layer 161 and 162 region decreases toward the insulating material 110 , because the amount of laser light decreases toward the inside. Meanwhile, the width of the via hole B in the region of the metal layer 130 also decreases toward the insulating material 110 , which is the case when the etching is isotropic etching. In particular, in this case, the inner wall of the via hole B in the region of the metal layer 130 may form a curved surface.

On the other hand, at the point where the via hole (A) of the insulating layer (161, 162) region and the via hole (B) of the metal layer 130 region meet, the width of the via hole (A) of the insulating layer (161, 162) region is the metal layer 130. It may be smaller than the width of the via hole (B) of the region. In addition, the minimum width of the via hole B in the metal layer 130 region is substantially the same as the minimum width of the via hole A in the insulating layer 161 and 162 region.

However, the width of the via hole B in the region of the metal layer 130 may be made constant by adjusting the etching conditions.

Referring to FIG. 16 , a seed layer S3 is formed inside the via hole 166 and on the insulating layers 161 and 162 , and a plating resist R2 is laminated and then patterned.

Referring to FIG. 17 , the build-up circuit layers 163 and 164 and the build-up metal layers 167 and 168 are sequentially plated. The plating resist R2 is peeled off.

18 and 19 , a solder resist layer 170 is formed on the build-up metal layers 167 and 168 , and an opening O is formed in the solder resist layer 170 . The opening O is also formed to remove a portion of the build-up metal layers 167 and 168 , and may be divided into two parts like the above-described via hole 166 . That is, the opening O may include an opening C in the region of the solder resist layer 170 and an opening D in the region of the build-up metal layers 167 and 168 .

Looking at the cross-sectional shape of the opening O, the width of the opening C of the solder resist layer 170 region becomes smaller toward the insulating material 110 side. because it gets smaller. Meanwhile, the width of the opening D in the region of the buildup metal layers 167 and 168 also becomes smaller toward the insulating material 110 side, which is the case when the etching is isotropic etching. In particular, in this case, the inner wall of the opening D of the region of the build-up metal layers 167 and 168 may form a curved surface.

On the other hand, at the point where the opening C of the solder resist layer 170 and the opening D of the buildup metal layers 167 and 168 meet, the width of the opening C of the solder resist layer 170 is the build-up area. The width of the opening D of the metal layers 167 and 168 may be smaller than the width. In addition, the width of the lowest portion of the opening D of the regions of the buildup metal layers 167 and 168 is substantially the same as the width of the lowest portion of the opening C of the region of the solder resist layer 170 .

However, the width of the openings D in the regions of the buildup metal layers 167 and 168 may be uniform by adjusting the etching conditions.

Referring to FIG. 20 , a surface treatment layer 171 is formed on the buildup circuit layers 163 and 164 exposed by the opening O. As shown in FIG. The surface treatment layer 171 may be formed of one or more layers by plating metal.

22 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention. Hereinafter, the above-described contents may be equally applied.

Referring to FIG. 22 , the printed circuit board according to the embodiment of the present invention includes an insulating material 110 , one or more first insulating layers 161 , one or more second insulating layers 162 , and a first circuit layer 221 . , a second circuit layer 222 , a first metal layer 231 , and a second metal layer 232 .

The insulating material 110 has one surface and the other surface facing each other. Circuits 321 and 322 may be formed on one surface and the other surface of the insulating material 110 . The circuits 321 and 322 formed on one surface and the other surface of the insulating material 110 may be electrically connected through the through-via 141 penetrating the insulating material 110 .

One or more first insulating layers 161 may be stacked on one surface of the insulating material 110 . For example, if there are two first insulating layers 161 , as shown in FIG. 22 , two layers are formed on one surface of the insulating material 110 (to the lower side of the insulating material 110 based on FIG. 22 ). They may be sequentially stacked in the thickness direction.

In addition, one or more second insulating layers 162 may be stacked on the other surface of the insulating material 110 . For example, if there are two second insulating layers 162 , as shown in FIG. 22 , two layers are formed on the other surface of the insulating material 110 (toward the upper side of the insulating material 110 with reference to FIG. 22 ). They may be sequentially stacked in the thickness direction.

Each of the first insulating layer 161 and the second insulating layer 162 is three, four... Even when made of, etc., it may be sequentially laminated in the thickness direction on both surfaces of the insulating material 110 in the above-described manner.

On the other hand, if each of the first insulating layer 161 and the second insulating layer 162 is one, one insulating layer is laminated on both surfaces of the insulating material 110, and the first insulating layer 161 and the second insulating layer 162 is an insulating layer located at the outermost layer.

The first circuit layer 221 is formed on at least one of the one or more first insulating layers 161 described above. If there is one first insulating layer 161 , the first circuit layer 221 will be formed on the first insulating layer 161 , and when there are two or more first insulating layers 161 , at least one of them formed on either one. Of course, another circuit 321 may be formed on the other first insulating layer 161 on which the first circuit layer 221 is not formed and may be electrically connected to the first circuit layer 221 .

As shown in FIG. 22 , the first circuit layer 221 may be formed on the first insulating layer 161 positioned at the outermost layer among the one or more first insulating layers 161 .

The second circuit layer 222 is formed on at least one of the one or more second insulating layers 162 described above. If there is one second insulating layer 162 , the second circuit layer 222 will be formed on the second insulating layer 162 , and when there are two or more second insulating layers 162 , at least one of them formed on either one. Of course, another circuit 322 may be formed on another second insulating layer 162 on which the second circuit layer 222 is not formed and may be electrically connected to the second circuit layer 222 .

22 , the second circuit layer 222 may be formed on the second insulating layer 162 positioned at the outermost layer among the one or more second insulating layers 162 .

The first metal layer 231 is formed on the first circuit layer 221 , and the electrical conductivity of the first metal layer 231 is smaller than that of the first circuit layer 221 .

The second metal layer 232 is formed on the second circuit layer 222 , and the electrical conductivity of the second metal layer 232 is smaller than that of the second circuit layer 222 .

The first circuit layer 221 and the second circuit layer 222 may have the same thickness. Also, the thickness of the first metal layer 231 may be smaller than the thickness of the first circuit layer 221 , and the thickness of the second metal layer 232 may be smaller than the thickness of the second circuit layer 222 . The thickness of the first metal layer 231 does not exceed 2/3 of the thickness of the first circuit layer 221 . In addition, the thickness of the second metal layer 232 does not exceed 2/3 of the thickness of the second circuit layer 222 . Meanwhile, the thickness of the first metal layer 231 may be greater than the thickness of the second metal layer 232 . Due to this thickness control, the warpage of the printed circuit board can be controlled.

The first circuit layer 221 and the second circuit layer 222 may be layers containing copper as a main component, and the first metal layer 231 and the second metal layer 232 are Fe-Ni (nickel steel) such as invar. ) alloy, and may be made of a copper alloy material such as brass, which is a Cu-Zn alloy.

The printed circuit board according to an embodiment of the present invention may further include a solder resist layer 170 respectively laminated on the first insulating layer 161 and the second insulating layer 162 positioned on the outermost layer. .

An opening O is formed in the solder resist layer 170, and the first metal layer 231 and the second metal layer ( 232 may not be formed in the opening region. This structural feature is, in a methodological view, after the first metal layer 231 is formed on the first circuit layer 221 , the first metal layer 231 is etched, so that the etched area is an opening O (part of) can be Similarly, after the second metal layer 232 is formed on the second circuit layer 222 , the second metal layer 232 is etched, so that the etching region may become (part of) the opening O.

23 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 23 , in the printed circuit board described with reference to FIG. 22 , the first metal layer 231 and the first circuit layer 221 are spaced apart from each other in the thickness direction, and the first metal layer 231 and the first circuit layer A space is provided between the 221 , and a solder resist layer 170 is formed in the space.

Similarly, the second metal layer 232 and the second circuit layer 222 are spaced apart from each other in the thickness direction, so that a space is provided between the second metal layer 232 and the second circuit layer 222 , and the solder resist is in the space. Layer 170 is formed.

Here, the formation area of the first metal layer 231 may be larger than the formation area of the first circuit layer 221 . The formation area of the second metal layer 232 may be larger than the formation area of the second circuit layer 222 .

The first metal layer 231 may be formed on a region where the first circuit layer 221 is not formed, and may be formed over the entire region except for the opening O of the solder resist layer 170 . The second metal layer 232 may be formed on a region where the second circuit layer 222 is not formed, and may be formed over the entire region except for the opening O of the solder resist layer 170 . The first metal layer 231 and the second metal layer 232 may be metal sheets.

24 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention, FIG. 25 is a partial enlarged view of FIG. 24, FIG. 26 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention, and FIG. 27 is a partial enlarged view of FIG. 28 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention, and FIG. 29 is a partially enlarged view of FIG. 28 .

Referring to FIG. 24 , the printed circuit board according to the embodiment of the present invention includes an insulating material 110 , circuit layers 121 and 122 , metal layers 131 and 132 , and insulating layers 161 and 162 . A via hole 166 may be formed in the layers 161 and 162 and the metal layers 131 and 132 , and the circuit layers 121 and 122 may be exposed through the bottom surface of the via hole 166 .

The insulating material 110 is a plate-shaped material composed of an insulating material such as resin, as described above.

The circuit layers 121 and 122 are patterned conductors to transmit electrical signals, and are formed on the insulating material 110 . The circuit layers 121 and 122 may be formed on both surfaces of the insulating material 110 .

The metal layers 131 and 132 are formed on the circuit layers 121 and 122 and are conductors formed of a metal having electrical conductivity lower than the electrical conductivity of the circuit layers 121 and 122 .

The insulating layers 161 and 162 are a plate-shaped material composed of an insulating material such as resin, and may be formed of the same or a different material as the insulating material 110 .

The via hole 166 is a hole penetrating the insulating layers 161 and 162 and the metal layers 131 and 132 , and the circuit layers 121 and 122 may be exposed through the bottom surface of the via hole 166 . In addition, when a conductive layer is formed in the via hole 166 to form the via 165 , the metal layers 131 and 132 and side surfaces of the via 165 may contact each other. In this case, the bottom surface of the via 165 may directly contact the circuit layers 121 and 122 .

The via hole 166 may include a first hole (E) and a second hole (F). The first hole (E) is located outside the second hole (F), and each of the width of the first hole (E) and the width of the second hole (F) becomes smaller toward the inside.

In FIG. 25 , various types of via holes 166 including a first hole E and a second hole F are shown.

As shown in (a) and (b) of Figure 25, in the surface where the first hole (E) and the second hole (F) are in contact, the width of the first hole (E) is the second hole (F) may be smaller than the width of In addition, as shown in (b), the side surface of the second hole (F) may form a curved surface. This may be a result of forming the second hole F by isotropically etching the metal layers 131 and 132 . Here, the innermost width of the first hole (E) and the innermost width of the second hole (F) may be substantially the same.

On the other hand, by adjusting the thickness, etching method, conditions, etc. of the metal layers 131 and 132 , as shown in (c), in the surface where the first hole E and the second hole F are in contact, the first The width of the hole E and the width of the second hole F may be the same.

Referring to FIG. 26 , a via 165 is formed in the via hole 166 , and the via 165 may include a seed layer. In addition, buildup circuit layers 163 and 164 connected to vias 165 may be formed on the insulating layers 161 and 162 , and buildup metal layers 167 and 168 on the buildup circuit layers 163 and 164 . can be formed.

Sides of the via 165 in the via hole 166 may contact the metal layers 131 and 132 , and when the via 165 includes a seed layer, the metal layers 131 and 132 may contact the seed layer. have.

27 shows a state in which the seed layer, the via 165, the build-up circuit layers 163 and 164, and the build-up metal layers 167 and 168 are formed according to (a), (b) and (c) of FIGS. 25 . is shown.

Referring to FIG. 28 , a solder resist layer 170 is formed on the insulating layers 161 and 162 , an opening O is formed in the solder resist layer 170 , and the opening O is a first opening G ) and a second opening (H). The first opening G is located outside the second opening H, and the width of the first opening G and the width of the second opening H become smaller toward the inside.

In FIG. 29 , various forms of an opening O comprising a first opening G and a second opening are shown.

29A and 29B , in the surface where the first opening G and the second opening H are in contact with each other, the width of the first opening G is equal to the width of the second opening H ) may be smaller than the width of In addition, as shown in (b), the side surface of the second opening (H) may form a curved surface. This may be a result of forming the second opening H by the isotropic etching of the build-up metal layers 167 and 168 . Here, the innermost width of the first opening G and the innermost width of the second opening H may be substantially the same.

On the other hand, by adjusting the thickness, etching method, conditions, etc. of the build-up metal layers 167 and 168, as shown in (c), in the surface where the first opening (G) and the second opening (H) are in contact, The width of the first opening G and the width of the second opening H may be the same.

Meanwhile, as shown in FIGS. 28 and 29 , a surface treatment layer 171 may be formed on the buildup circuit layers 163 and 164 exposed through the opening O. As shown in FIG.

In the above, although the embodiments of the present invention have been described, those of ordinary skill in the art can add, change, delete or add components within the scope that does not depart from the spirit of the present invention described in the claims. The present invention may be variously modified and changed by such as, and this will also be included within the scope of the present invention.

110: insulation material
120: circuit layer
121, 221: first circuit layer
122, 222: second circuit layer
130: metal layer
131, 231: first metal layer
132, 232: second metal layer
140: through via
141: through-via hole
150: alloy layer
151: first alloy layer
152: second alloy layer
153: third alloy layer
160: build-up layer
161: first insulating layer
162: second insulating layer
163: first build-up circuit layer
164: second build-up circuit layer
165: via
166: via hole
167: first build-up metal layer
168: second build-up metal layer
170: solder resist layer
O: opening
171: surface treatment layer
S1, S2, S3, S4: seed layer
R1, R2: plating resist

Claims (22)

an insulating material having one surface and the other surface facing each other;
a circuit layer formed on the one surface and the other surface of the insulating material; and
a metal layer formed on the circuit layer;
The electrical conductivity of the metal layer is smaller than the electrical conductivity of the circuit layer,
The thickness of the metal layer located on the one side of the insulating material is greater than the thickness of the metal layer located on the other side of the insulating material.
According to claim 1,
The thickness of the metal layer is smaller than the thickness of the circuit layer printed circuit board.
According to claim 1,
The coefficient of thermal expansion of the metal layer is smaller than the coefficient of thermal expansion of the circuit layer,
A printed circuit board having a rigidity of the metal layer greater than a rigidity of the circuit layer.
According to claim 1,
The coefficient of thermal expansion of the metal layer is greater than the coefficient of thermal expansion of the circuit layer,
The rigidity of the metal layer is smaller than that of the circuit layer.
According to claim 1,
The volume of the circuit layer located on the one side of the insulating material is smaller than the volume of the circuit layer located on the other side of the insulating material.
According to claim 1,
It is formed through the inside of the insulating material,
The printed circuit board further comprising a through via connecting the circuit layer formed on the first surface of the insulating material and the circuit layer formed on the other surface of the insulating material.
7. The method of claim 6,
Further comprising an alloy layer formed between the insulating material and the through-via and between the insulating material and the circuit layer,
The printed circuit board is made of the same material as the metal layer and the alloy layer.
8. The method of claim 7,
The thickness of the alloy layer positioned on the one surface of the insulating material is greater than a thickness of the alloy layer positioned on the other surface of the insulating material.
8. The method of claim 7,
The through-via is formed in a through-via hole passing through the insulating material;
The alloy layer includes a seed layer,
The seed layer is formed on the inner wall of the through-via hole and on the one surface and the other surface of the insulating material.
an insulating material having one surface and the other surface facing each other;
at least one first insulating layer laminated on the one surface of the insulating material;
at least one second insulating layer laminated on the other surface of the insulating material;
a first circuit layer formed on at least one of the one or more first insulating layers;
a second circuit layer formed on at least one of the one or more second insulating layers;
a first metal layer formed on the first circuit layer; and
a second metal layer formed on the second circuit layer;
The electrical conductivity of the first metal layer is smaller than the electrical conductivity of the first circuit layer,
The electrical conductivity of the second metal layer is smaller than the electrical conductivity of the second circuit layer,
The thickness of the first metal layer is greater than the thickness of the second metal layer printed circuit board.
11. The method of claim 10,
The first circuit layer and the first metal layer are formed on a first insulating layer located in the outermost layer,
The second circuit layer and the second metal layer are formed on a second insulating layer located in an outermost layer.
12. The method of claim 11,
Further comprising a solder resist layer laminated on each of the first insulating layer and the second insulating layer located in the outermost layer,
An opening is formed in the solder resist layer,
so that the first circuit layer and the second circuit layer are exposed through the opening,
The first metal layer and the second metal layer are not formed in the opening region.
13. The method of claim 12,
The first metal layer and the first circuit layer are spaced apart from each other in a thickness direction,
The solder resist layer is a printed circuit board further formed between the first metal layer and the first circuit layer.
14. The method of claim 13,
The formation area of the first metal layer is larger than the formation area of the first circuit layer.
insulation material;
a circuit layer formed on the insulating material;
a metal layer formed on the circuit layer and having an electrical conductivity smaller than that of the circuit layer;
an insulating layer laminated on the insulating material;
a via hole passing through the insulating layer and the metal layer;
A printed circuit board in which the circuit layer is exposed through a bottom surface of the via hole.
16. The method of claim 15,
Further comprising a via formed in the via hole,
A side surface of the via is in contact with the metal layer.
16. The method of claim 15,
The via hole includes a first hole and a second hole,
The first hole passes through the insulating layer,
The second hole passes through the metal layer,
Each of the width of the first hole and the width of the second hole decreases toward the insulating material.
18. The method of claim 17,
On the surface where the first hole and the second hole are in contact,
A width of the first hole is smaller than a width of the second hole.
18. The method of claim 17,
A side surface of the second hole is a curved printed circuit board.
16. The method of claim 15,
The thickness of the metal layer is smaller than the thickness of the circuit layer printed circuit board.
16. The method of claim 15,
The coefficient of thermal expansion of the metal layer is smaller than the coefficient of thermal expansion of the circuit layer,
A printed circuit board having a rigidity of the metal layer greater than a rigidity of the circuit layer.
16. The method of claim 15,
The coefficient of thermal expansion of the metal layer is greater than the coefficient of thermal expansion of the circuit layer,
The rigidity of the metal layer is smaller than that of the circuit layer.

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