JP5452759B1 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

Info

Publication number
JP5452759B1
JP5452759B1 JP2013186118A JP2013186118A JP5452759B1 JP 5452759 B1 JP5452759 B1 JP 5452759B1 JP 2013186118 A JP2013186118 A JP 2013186118A JP 2013186118 A JP2013186118 A JP 2013186118A JP 5452759 B1 JP5452759 B1 JP 5452759B1
Authority
JP
Japan
Prior art keywords
opening
copper foil
substrate
carrier
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013186118A
Other languages
Japanese (ja)
Other versions
JP2015053423A (en
Inventor
主 松澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastern KK
Original Assignee
Eastern KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastern KK filed Critical Eastern KK
Priority to JP2013186118A priority Critical patent/JP5452759B1/en
Application granted granted Critical
Publication of JP5452759B1 publication Critical patent/JP5452759B1/en
Publication of JP2015053423A publication Critical patent/JP2015053423A/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

【課題】、微細配線に対応して効率よくかつ安価に基板に小径の孔開け加工が行える配線基板の製造方法を提供する。
【解決手段】コンフォーマルマスク4が形成された第1の基板3の両面に電解めっきを行って、開口部4aの開口径を狭めるように導体層5が厚付けされた当該導体層5をマスクとして開口部4aにレーザー光を照射して絶縁樹脂基材層1を除去し有底ビア6が形成される。
【選択図】図1
The present invention provides a method of manufacturing a wiring board that can efficiently and inexpensively drill a small-diameter hole corresponding to fine wiring.
Electrolytic plating is performed on both surfaces of a first substrate 3 on which a conformal mask 4 is formed, and the conductor layer 5 thickened so as to narrow the opening diameter of the opening 4a is masked. As a result, the opening 4a is irradiated with laser light to remove the insulating resin base material layer 1 and the bottomed via 6 is formed.
[Selection] Figure 1

Description

本発明は、例えば微細配線に対応して小径のビア孔を有する配線基板の製造方法に関する。   The present invention relates to a method of manufacturing a wiring board having a small diameter via hole corresponding to, for example, a fine wiring.

配線基板に配線パターンと接続するバイアホールその他の小径の孔を加工する方法として、機械加工のほかにレーザー加工が利用されている。高精度に小孔を加工するためには、プリント基板上に回路配線用のために形成されている銅箔等の導体膜を孔開けのためのレーザー加工用マスク(コンフォーマルマスク)として利用する方法が用いられる。   In addition to machining, laser machining is used as a method of machining via holes and other small-diameter holes connected to a wiring pattern on a wiring board. In order to process small holes with high accuracy, a conductor film such as copper foil formed on a printed circuit board for circuit wiring is used as a laser processing mask (conformal mask) for drilling holes. The method is used.

先ず、絶縁樹脂基板上に積層された導体膜(銅箔等)をエッチングして開口部を配置したコンフォーマルマスクを形成し、YAGレーザー、炭酸ガス(CO)レーザーなどのレーザー光を開口部に照射して孔開け加工(ビア孔形成)を行う。その後、ビア孔を含む導体膜に無電解銅めっき及び電解銅めっきを施して導体層を形成し、パターニング(エッチングレジスト形成⇒エッチング⇒エッチングレジスト剥離)することにより、必要な配線パターンが形成される(特許文献1参照)。 First, a conductive film (copper foil or the like) laminated on an insulating resin substrate is etched to form a conformal mask having openings, and laser light such as YAG laser or carbon dioxide (CO 2 ) laser is opened. Is irradiated to form a hole (via hole formation). After that, electroless copper plating and electrolytic copper plating are applied to the conductor film including the via hole to form a conductor layer, and a necessary wiring pattern is formed by patterning (etching resist formation⇒etching⇒etching resist peeling). (See Patent Document 1).

特開2008−198922号公報JP 2008-198922 A

配線基板の導体膜に設けた開口部にレーザーを照射して小径の穴を加工する場合、導体膜の開口径が小さいほど微小径の穴加工ができる。しかし、エッチングにより銅箔等の導体膜にコンフォーマルマスクを形成する場合、エッチング液によりサイドエッチングが発生し、エッチングレジストの開口径より大きな開口径でエッチングされてしまう。このため、例えば開口径φ40μm以下のビア孔を形成するためには、φ20μm以下のエッチングレジストパターンを焼き付ける必要があり、ガラス乾板のような特殊な治具が必要になる。   When a small-diameter hole is processed by irradiating a laser to the opening provided in the conductor film of the wiring board, the smaller the hole diameter of the conductor film, the smaller the hole can be processed. However, when a conformal mask is formed on a conductor film such as a copper foil by etching, side etching occurs due to the etching solution, and etching is performed with an opening diameter larger than the opening diameter of the etching resist. Therefore, for example, in order to form a via hole having an opening diameter of φ40 μm or less, it is necessary to bake an etching resist pattern of φ20 μm or less, and a special jig such as a glass dry plate is required.

本発明の目的は、上記従来技術の課題を解決し、微細配線に対応して効率よくかつ安価に基板に小径の孔開け加工が行える配線基板の製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a method of manufacturing a wiring board capable of drilling a small diameter in a board efficiently and inexpensively corresponding to fine wiring.

上記目的を達成するため、本発明に係る配線基板の製造方法は以下の構成を備える。
即ち、絶縁樹脂基材の両面に銅箔を密着させてキャリヤ付銅箔が積層された第1の基板を用意する工程と、前記第1の基板のうち一方の前記キャリヤ付銅箔をエッチングにより除去して開口部を有するコンフォーマルマスクを形成する工程と、前記コンフォーマルマスクが形成された前記第1の基板の両面に電解めっきを行って、前記キャリヤ付銅箔の開口部壁面を含んで導体層を厚付けする工程と、前記開口部の開口径を狭めるように前記導体層が厚付けされた当該導体層をマスクとして前記開口部にレーザー光を照射して前記絶縁樹脂基材層を除去して底部に他方のキャリヤ付銅箔の銅箔が露出した有底ビアを形成する工程と、を含むことを特徴とする。
In order to achieve the above object, a method for manufacturing a wiring board according to the present invention comprises the following arrangement.
That is, a step of preparing a first substrate in which a copper foil with a carrier is laminated on both surfaces of an insulating resin base material and a copper foil with a carrier is laminated, and etching the copper foil with a carrier of one of the first substrates by etching. Removing the step of forming a conformal mask having an opening, and performing electroplating on both surfaces of the first substrate on which the conformal mask is formed, including the wall surface of the opening of the copper foil with carrier. A step of thickening the conductive layer; and the insulating resin base layer is formed by irradiating the opening with a laser beam using the conductive layer thickened as the mask so as to narrow the opening diameter of the opening. And forming a bottomed via in which the copper foil of the other carrier-attached copper foil is exposed at the bottom.

上記配線基板の製造方法を用いれば、コンフォーマルマスクが形成された第1の基板の両面に電解めっきを行って、開口部の開口径を狭めるように導体層が厚付けされた当該導体層をマスクとして開口部にレーザー光を照射して絶縁樹脂基材層を除去し有底ビアが形成されるので、開口部の壁面に厚付けされる導体層の厚さを変えて開口部の開口径をコントロールすることにより、配線基板に所望の径のビア孔を孔開け加工することができる。
また、導体層にエッチングで微小径の開口部を形成するためにエッチングレジストの焼付に分解能が高いガラス乾板のような特殊な治具は不要であり、一般的な設備を使用して安価にコンフォーマルマスクを形成できるうえに、エネルギーレベルの高い炭酸ガスレーザーを使用することで、微細な孔径のビア孔を短時間で形成することができる。
If the above method for manufacturing a wiring board is used, the conductive layer is thickened so that the opening diameter of the opening is narrowed by performing electrolytic plating on both surfaces of the first substrate on which the conformal mask is formed. As the mask irradiates the opening with laser light, the insulating resin substrate layer is removed and a bottomed via is formed, so the opening diameter of the opening can be changed by changing the thickness of the conductor layer thickened on the wall of the opening By controlling this, a via hole having a desired diameter can be formed in the wiring board.
In addition, since a small-diameter opening is formed in the conductor layer by etching, a special jig such as a glass dry plate with high resolution is not required for baking of the etching resist, and it is inexpensively configured using general equipment. In addition to forming a formal mask, a via hole having a fine hole diameter can be formed in a short time by using a carbon dioxide laser having a high energy level.

また、多層配線基板の製造方法においては、絶縁樹脂基材の内層に内層導体パターンが各々形成された両面絶縁樹脂層に銅箔を密着させてキャリヤ付銅箔が各々積層された第1の基板を用意する工程と、前記第1の基板の両面に積層された前記キャリヤ付銅箔をエッチングにより各々除去して前記絶縁樹脂層が底部に露出した開口部を有するコンフォーマルマスクを形成する工程と、前記コンフォーマルマスクが形成された前記第1の基板の両面に電解めっきを行って、前記キャリヤ付銅箔の開口部壁面を含んで導体層を各々厚付けする工程と、を含むことを特徴とする。
上記配線基板の製造方法を用いれば、多層配線基板の微細配線パターンどうしを層間接続する導体が充填される微細なビア孔を効率よくしかも安価に形成することができる。
In the method for manufacturing a multilayer wiring board, the first substrate in which the copper foil with a carrier is laminated by bringing the copper foil into close contact with the double-sided insulating resin layer in which the inner layer conductor pattern is formed on the inner layer of the insulating resin base material And a step of forming a conformal mask having an opening in which the insulating resin layer is exposed at the bottom by respectively removing the copper foil with carrier laminated on both surfaces of the first substrate by etching. And performing electrolytic plating on both surfaces of the first substrate on which the conformal mask is formed, and thickening the conductor layers including the opening wall surfaces of the copper foil with carrier. And
By using the above method for manufacturing a wiring board, it is possible to efficiently and inexpensively form a fine via hole filled with a conductor that connects the fine wiring patterns of the multilayer wiring board to each other.

上記配線基板の製造においてレーザー光を照射するコンフォーマルマスクとなる導体層開口部の表面の開口径が最小開口径よりも10μm以上大きいことを特徴とする。
導体層開口部の表面の開口径を大きくすることにより、穴の加工径を決める最小開口径は小さいがレーザー光のエネルギーを最小開口部よりも広い面積で集光することができるので、レーザー光を効率よく穴あけ加工に使用することができる。
In the production of the wiring board, the opening diameter of the surface of the conductor layer opening serving as a conformal mask for irradiating laser light is 10 μm or more larger than the minimum opening diameter.
By increasing the opening diameter of the surface of the conductor layer opening, the minimum opening diameter that determines the processing diameter of the hole is small, but the energy of the laser beam can be collected in a larger area than the minimum opening, so the laser beam Can be efficiently used for drilling.

上述した配線基板の製造方法を用いれば、微細配線に対応して効率よくかつ安価に基板に小径の孔開け加工を行うことができる。   If the manufacturing method of a wiring board mentioned above is used, a small diameter drilling process can be performed to a board | substrate efficiently and cheaply corresponding to fine wiring.

配線基板の製造方法の加工工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the manufacturing method of a wiring board. 多層配線基板の製造方法の加工工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the manufacturing method of a multilayer wiring board. コンフォーマルマスクの開口部の断面写真図と電解銅めっきを厚付けした後の開口部の断面写真図である。It is the cross-sectional photograph figure of the opening part of a conformal mask, and the cross-sectional photograph figure of the opening part after thickening electrolytic copper plating.

以下、本発明の実施形態について図面を参照しながら具体的に説明する。
図1(A)〜(K)を参照して配線基板の製造方法についてその配線基板の構造と共に説明する。尚、以下の説明では、キャリヤ付銅箔は、例えば極薄銅箔(銅箔;厚さ2〜5μm)に剥離層を介してキャリヤ銅箔(厚さ18μm;キャリヤ箔)が積層されたもの(例えばF-HP;Heat-Resistant Peelable Copper Foil)が用いられるものとする。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
A method for manufacturing a wiring board will be described with reference to FIGS. 1A to 1K together with the structure of the wiring board. In the following description, the carrier-attached copper foil is, for example, an ultra-thin copper foil (copper foil; thickness 2 to 5 μm) laminated with a carrier copper foil (thickness 18 μm; carrier foil) via a release layer. (For example, F-HP; Heat-Resistant Peelable Copper Foil) is used.

図1(A)に示すように、絶縁樹脂基材1(例えばFR‐4)の両面にキャリヤ付銅箔2が貼ってある第1の基板3を用意する。第1の基板3において、キャリヤ付銅箔2は絶縁樹脂基材1に接着している銅箔2aに剥離層を介してキャリヤ箔といわれるキャリヤ銅箔2bが貼り合わせてある。キャリヤ銅箔2bは、剥離層から銅箔2aより容易に剥離することができる。   As shown in FIG. 1A, a first substrate 3 having a carrier-attached copper foil 2 pasted on both surfaces of an insulating resin base material 1 (for example, FR-4) is prepared. In the first substrate 3, the carrier-attached copper foil 2 is bonded to a copper foil 2 a bonded to the insulating resin base material 1 with a carrier copper foil 2 b called a carrier foil through a release layer. The carrier copper foil 2b can be more easily separated from the release layer than the copper foil 2a.

図1(B)において、第1の基板3のうち一方(例えば上面側)のキャリヤ付銅箔2をエッチングにより除去して開口部4aを有するコンフォーマルマスク4を形成する。第1の基板3のキャリヤ付銅箔2に、マスクパターンに相当するエッチングレジストを積層してエッチングを行うことでキャリヤ付銅箔2が部分的に除去され、絶縁樹脂基材1が底部に露出した開口部4aが形成される。
キャリヤ付銅箔2をエッチングして形成された開口部4aの断面は、エッチングのサイドエッチによりテーパーがついた状態に仕上がる。このテーパーの形状はキャリヤ付銅箔2の厚さを調整することにより変えることができる。
In FIG. 1B, one of the first substrates 3 (for example, the upper surface side) copper foil 2 with a carrier is removed by etching to form a conformal mask 4 having an opening 4a. Etching is performed by laminating an etching resist corresponding to a mask pattern on the copper foil 2 with a carrier on the first substrate 3, so that the copper foil 2 with a carrier is partially removed and the insulating resin substrate 1 is exposed at the bottom. Opened portion 4a is formed.
The cross section of the opening 4a formed by etching the carrier-attached copper foil 2 is finished in a tapered state by etching side etching. The shape of the taper can be changed by adjusting the thickness of the copper foil 2 with a carrier.

図1(C)において、コンフォーマルマスク4が形成された第1の基板3の両面に電解銅めっきを行って、キャリヤ付銅箔2の開口部4aの内壁面を含んで導体層5を厚付けする。このときの銅めっき厚の調整は、電流値の大きさもしくはめっき時間の長さによって行うことができる。電解液に流れる電流値を高くすると銅の析出速度が速くなるため銅めっきを厚く付けることができる。また、同じ電流値でめっき時間を長くしても同様に銅めっきを厚く付けることができる。一般的には生産効率を高めるため、電流値の大きさでめっき厚を調整している。   In FIG. 1C, electrolytic copper plating is performed on both surfaces of the first substrate 3 on which the conformal mask 4 is formed, and the conductor layer 5 including the inner wall surface of the opening 4a of the copper foil with carrier 2 is thickened. Attach. Adjustment of the copper plating thickness at this time can be performed according to the magnitude of the current value or the length of the plating time. When the value of the current flowing through the electrolyte is increased, the copper deposition rate is increased, so that the copper plating can be thickened. Further, even if the plating time is increased with the same current value, the copper plating can be similarly thickened. Generally, in order to increase production efficiency, the plating thickness is adjusted by the magnitude of the current value.

導体層5に電解めっきをすると、導体エッジ部はめっきの形状がめっき浴の添加剤の効果で丸みを帯びるという現象と開口部導体層断面のテーパー形状の影響でめっきの断面形状に顕著なR形状ができるので、導体層5は表面の開口径を開口部4aの最小開口径よりも大きくすることができる。   When the conductive layer 5 is electrolytically plated, the conductor edge portion is markedly rounded due to the phenomenon that the plating shape is rounded by the effect of the additive of the plating bath and the taper shape of the opening conductor layer cross section. Since the shape can be formed, the opening diameter of the surface of the conductor layer 5 can be made larger than the minimum opening diameter of the opening 4a.

実験によれば、図3において開口部4aの開口径φ60μmのキャリヤ銅箔2bの上に厚さ28μmの銅めっきをした場合、開口部4aの開口径はφ16μmとなった。
これは、厚さ24μmの銅めっきを行うと開口径4aは4μm(60μm−28×2μm)であるところ、表面銅厚が厚くなり、開口径が小さくなるほど開口部壁面への銅めっきの付回り悪くなったことが原因と考えられる。
According to the experiment, when copper plating with a thickness of 28 μm is formed on the carrier copper foil 2b having an opening diameter of φ60 μm in the opening 4a in FIG. 3, the opening diameter of the opening 4a is φ16 μm.
This is because, when copper plating with a thickness of 24 μm is performed, the opening diameter 4a is 4 μm (60 μm−28 × 2 μm). However, the surface copper thickness increases, and the smaller the opening diameter, the more the copper plating is applied to the wall surface of the opening. The cause is thought to be worse.

次に、図1(D)において、開口部4aの開口径を狭めるように導体層5が厚付けされた当該導体層5をマスクとして開口部4aにレーザー光を照射する。レーザー光は、エネルギーレベルが高い炭酸ガスレーザーが好適に用いられる。これにより、図1(E)に示すように開口部4aに露出する絶縁樹脂基材層1を部分的に除去して他方のキャリヤ付銅箔2の銅箔2aが底部に露出した有底ビア6を形成する。レーザー光は開口部4aの最小開口径が小さくても導体層表面の開口径が大きいため光をより多く受けることができ導体層5をマスクとして開口部4aに露出する絶縁樹脂基材1をエネルギー効率良く除去することができる。   Next, in FIG. 1D, the opening 4a is irradiated with laser light using the conductor layer 5 with the conductor layer 5 thickened so as to narrow the opening diameter of the opening 4a. As the laser beam, a carbon dioxide laser having a high energy level is preferably used. Thereby, as shown in FIG. 1E, the insulating resin base material layer 1 exposed in the opening 4a is partially removed, and the bottomed via in which the copper foil 2a of the other carrier-attached copper foil 2 is exposed at the bottom. 6 is formed. Even if the minimum opening diameter of the opening 4a is small, the laser light can receive more light because the opening diameter on the surface of the conductor layer is large, and the insulating resin base material 1 exposed to the opening 4a using the conductor layer 5 as a mask has energy. It can be removed efficiently.

次いで、図1(F)において有底ビアの底部に露出する銅箔2aを除去した後、第1の基板3の両面に積層するキャリヤ銅箔2bを各々剥離させて絶縁樹脂基材層1に銅箔2a(薄膜)のみが積層され、貫通したビア孔7を有する第2の基板8が形成される。   Next, after removing the copper foil 2a exposed at the bottom of the bottomed via in FIG. 1 (F), the carrier copper foil 2b laminated on both surfaces of the first substrate 3 is peeled off to form the insulating resin base material layer 1. Only the copper foil 2a (thin film) is laminated, and the second substrate 8 having the via hole 7 penetrating therethrough is formed.

次いで、図1(G)において、第2の基板8の両面にビアフィルめっきを施すと同時にビア孔7を導体層9の導体で埋め、銅箔2aに導体層9を厚付けする。ビアフィルめっきは、めっき成長を抑制する抑制剤及びめっき成長を促進する促進剤が添加された硫酸銅めっき浴めっきを用いて、ビア孔7内部に優先的に銅を析出させるめっき法である。   Next, in FIG. 1G, via fill plating is applied to both surfaces of the second substrate 8, and the via hole 7 is filled with the conductor of the conductor layer 9, and the conductor layer 9 is thickened on the copper foil 2a. Via fill plating is a plating method in which copper is preferentially deposited inside the via hole 7 by using a copper sulfate plating bath plating to which an inhibitor for suppressing plating growth and an accelerator for promoting plating growth are added.

最後に、図1(H)において、第2の基板8の両面に形成された導体層9にエッチングレジストを積層して露光現像してレジストパターンを形成した後エッチングにより導体層9を部分的に除去して導体パターン10を形成する。そして、エッチングレジストを剥離することにより、絶縁樹脂基材1の両面に導体パターン10が形成された配線基板11が得られる。   Finally, in FIG. 1 (H), an etching resist is laminated on the conductor layer 9 formed on both surfaces of the second substrate 8, exposed and developed to form a resist pattern, and then the conductor layer 9 is partially etched. The conductor pattern 10 is formed by removing. Then, by removing the etching resist, the wiring substrate 11 having the conductor pattern 10 formed on both surfaces of the insulating resin base material 1 is obtained.

また、上述した図1(G)における第2の基板8に対するビアフィルめっきに替えて、図1(I)に示すように銅箔2a上にパターンめっきを施してパターン化された導体層12を厚付けする。その後、図1(J)に示すように、パターン化された導体層12の間から露出する銅箔2aをソフトエッチングにより除去して第2の基板8の両面に導体パターン10を形成する。このようにして、絶縁樹脂基材1の両面に導体パターン10が形成された配線基板11を形成してもよい。   Further, in place of the above-described via fill plating for the second substrate 8 in FIG. 1G, the conductive layer 12 patterned by applying pattern plating on the copper foil 2a as shown in FIG. Attach. Thereafter, as shown in FIG. 1 (J), the copper foil 2a exposed between the patterned conductor layers 12 is removed by soft etching to form conductor patterns 10 on both surfaces of the second substrate 8. Thus, you may form the wiring board 11 in which the conductor pattern 10 was formed in both surfaces of the insulating resin base material 1. FIG.

上記配線基板の製造方法を用いれば、コンフォーマルマスク4が形成された第1の基板3の両面に電解銅めっきを行って、開口部4aの開口径を狭めるように導体層5が厚付けされた当該導体層5をマスクとして開口部4にレーザー光を照射して絶縁樹脂基材1を除去しビア孔7が形成されるので、開口部4の壁面に厚付けされる導体層5の厚さにより開口径をコントロールすることで、配線基板11に所望の径のビア孔7を孔開け加工することができる。
また、導体層にエッチングで微小径の開口部を形成するためにエッチングレジストの焼付に分解能が高いガラス乾板のような特殊な治具は不要であり、一般的な設備を使用して安価にコンフォーマルマスク4を形成できるうえに、エネルギーレベルの高い炭酸ガスレーザーをより多く集光して使用することで、効率よく微細な孔径のビア孔7を短時間で形成することができる。
If the above-described method for manufacturing a wiring board is used, electrolytic conductor plating is performed on both surfaces of the first substrate 3 on which the conformal mask 4 is formed, and the conductor layer 5 is thickened so as to narrow the opening diameter of the opening 4a. Further, the insulating resin base material 1 is removed by irradiating the opening 4 with laser light using the conductor layer 5 as a mask to form the via hole 7, so the thickness of the conductor layer 5 thickened on the wall surface of the opening 4 By controlling the opening diameter accordingly, the via hole 7 having a desired diameter can be formed in the wiring substrate 11.
In addition, since a small-diameter opening is formed in the conductor layer by etching, a special jig such as a glass dry plate with high resolution is not required for baking of the etching resist, and it is inexpensively configured using general equipment. In addition to the formation of the formal mask 4, the via holes 7 having a fine hole diameter can be efficiently formed in a short time by condensing more carbon dioxide lasers having a high energy level.

次に多層配線基板の製造方法について図2を参照して説明する。
図2(A)において、絶縁樹脂基材21の内層に内層導体パターン22が形成された第1の基板22の両面絶縁樹脂層21aに銅箔2aを密着させてキャリヤ付銅箔2が各々積層された第1の基板23を用意する。
Next, a method for manufacturing a multilayer wiring board will be described with reference to FIG.
In FIG. 2 (A), the copper foil 2a with a carrier is laminated | stacked by sticking the copper foil 2a to the double-sided insulating resin layer 21a of the 1st board | substrate 22 with which the inner layer conductor pattern 22 was formed in the inner layer of the insulating resin base material 21, respectively. The prepared first substrate 23 is prepared.

図2(B)において、第1の基板23の両面に積層されたキャリヤ付銅箔2をエッチングにより各々除去し、開口部24aを有するコンフォーマルマスク24を各々形成する。第1の基板22のキャリヤ付銅箔2に、マスクパターンに相当するエッチングレジストを積層してエッチングを行うことでキャリヤ付銅箔2が部分的に除去され、絶縁樹脂層21aが底部に露出した開口部24aが形成される。   In FIG. 2B, the carrier-attached copper foils 2 laminated on both surfaces of the first substrate 23 are respectively removed by etching to form conformal masks 24 each having an opening 24a. Etching is performed by laminating an etching resist corresponding to the mask pattern on the copper foil 2 with a carrier on the first substrate 22, so that the copper foil 2 with a carrier is partially removed and the insulating resin layer 21 a is exposed at the bottom. An opening 24a is formed.

図2(C)において、コンフォーマルマスク24が形成された第1の基板23の両面に電解銅めっきを行って、キャリヤ付銅箔2の開口部24aの内壁面を含んで導体層25を各々厚付けする。第1の基板23の表層は、キャリヤ付銅箔2のうちのキャリヤ銅箔2bであるので、銅めっきが厚付けされる。このときの銅めっき厚の調整は、電流値の大きさによって行われる。   In FIG. 2C, electrolytic copper plating is performed on both surfaces of the first substrate 23 on which the conformal mask 24 is formed, and the conductor layers 25 including the inner wall surfaces of the openings 24a of the carrier-attached copper foil 2 are formed. Thicken. Since the surface layer of the first substrate 23 is the carrier copper foil 2b of the carrier-attached copper foil 2, the copper plating is thickened. Adjustment of the copper plating thickness at this time is performed according to the magnitude of the current value.

図2(D)において、開口部24aの開口径を狭めるように導体層25が厚付けされた当該導体層25をマスクとして開口部24aにレーザー光を照射する。レーザー光は、エネルギーレベルが高い炭酸ガスレーザーが好適に用いられる。これにより、図2(E)に示すように開口部24aに露出する絶縁樹脂層21aを部分的に除去して内層導体パターン22が底部に露出した有底ビア26が第1の基板23の両面に形成される。   In FIG. 2D, the opening 24a is irradiated with laser light using the conductor layer 25 thickened so as to narrow the opening diameter of the opening 24a as a mask. As the laser beam, a carbon dioxide laser having a high energy level is preferably used. 2E, the insulating resin layer 21a exposed at the opening 24a is partially removed, and the bottomed via 26 where the inner layer conductor pattern 22 is exposed at the bottom is formed on both surfaces of the first substrate 23. Formed.

図2(F)において、第1の基板23の両面に積層するキャリヤ銅箔2bを各々剥離させることにより、両面絶縁樹脂層21aに銅箔2aのみが積層され、内層導体パターン22が露出した有底ビア26を両面に有する第2の基板27が形成される。   In FIG. 2 (F), the carrier copper foil 2b laminated on both surfaces of the first substrate 23 is peeled off, so that only the copper foil 2a is laminated on the double-sided insulating resin layer 21a and the inner layer conductor pattern 22 is exposed. A second substrate 27 having bottom vias 26 on both sides is formed.

次に、図2(G)において、第2の基板27の両面に積層された銅箔2aをソフトエッチングにより除去する。キャリヤ付銅箔2に形成されるコンフォーマルマスク24の開口径と電解銅めっき後(導体層25積層後)の開口径は前者が広く後者が狭い。電解銅めっき後の開口部24aの周囲の銅は、コンフォーマルマスク24のキャリヤ付銅箔2の端面に銅めっきが厚付けされたものなので、絶縁樹脂層21aに接着していない。そのため、キャリヤ銅箔2b及び導体層25(電解銅めっき)を剥がすと、銅箔2aがない絶縁樹脂層21aの露出部分ができる。この露出部分が後のめっき工程で段差になるのを防ぐためにソフトエッチングで除去する。エッチング液には、硫酸/過酸化水素、過硫酸ソーダ、過硫酸カリなどの水溶液が用いられる。   Next, in FIG. 2G, the copper foil 2a laminated on both surfaces of the second substrate 27 is removed by soft etching. The former is wide and the latter is narrow in the opening diameter of the conformal mask 24 formed on the copper foil 2 with a carrier and the opening diameter after electrolytic copper plating (after laminating the conductor layer 25). The copper around the opening 24a after the electrolytic copper plating is not bonded to the insulating resin layer 21a because the copper plating is thickened on the end face of the copper foil 2 with a carrier of the conformal mask 24. Therefore, when the carrier copper foil 2b and the conductor layer 25 (electrolytic copper plating) are peeled off, an exposed portion of the insulating resin layer 21a without the copper foil 2a is formed. In order to prevent this exposed portion from becoming a step in the subsequent plating step, it is removed by soft etching. As the etching solution, an aqueous solution of sulfuric acid / hydrogen peroxide, sodium persulfate, potassium persulfate or the like is used.

次いで、図2(H)において、ソフトエッチングされた第2の基板27の両面に無電解銅めっきを行って絶縁樹脂層21a及び有底ビア26の壁面を覆う導体膜28を形成する。   Next, in FIG. 2H, electroless copper plating is performed on both surfaces of the soft-etched second substrate 27 to form a conductive film 28 that covers the insulating resin layer 21a and the wall surface of the bottomed via 26.

次に、図2(I)において、導体膜28が形成された第2の基板27の両面にパネルめっきを施して導体膜28に導体層29を厚付けする。パネルめっきは、有底ビア26内のビア孔めっきと第2の基板27の両面に電解銅めっきを同時に行ってビア孔を導体層29で埋めるとともに基板両面に導体層29を厚付けする。   Next, in FIG. 2I, panel plating is performed on both surfaces of the second substrate 27 on which the conductor film 28 is formed, and the conductor layer 29 is thickened on the conductor film 28. In the panel plating, via hole plating in the bottomed via 26 and electrolytic copper plating are simultaneously performed on both surfaces of the second substrate 27 to fill the via holes with the conductor layer 29 and thicken the conductor layer 29 on both surfaces of the substrate.

次に図2(J)において、第2の基板27の両面に形成された導体層29にエッチングレジストを積層してパターン化した後、エッチングにより導体層29を部分的に除去して導体パターン30を形成する。そして、エッチングレジストを剥離することにより、第2の基板27の両面に導体パターン30が形成された多層配線基板31が得られる。   Next, in FIG. 2J, an etching resist is laminated on the conductor layer 29 formed on both surfaces of the second substrate 27 and patterned, and then the conductor layer 29 is partially removed by etching to form a conductor pattern 30. Form. Then, by removing the etching resist, a multilayer wiring substrate 31 in which the conductor pattern 30 is formed on both surfaces of the second substrate 27 is obtained.

また、図2(I)において第2の基板27の両面にパネルめっきに替えて図2(K)に示すようにパターンめっきを施して導体膜28上にパターン化された導体層32を厚付けしてもよい。次いで、図2(L)に示すように、パターン化された導体層32の間から露出する導体膜28をフラッシュエッチングにより部分的に除去して第2の基板27の両面に導体パターン30が形成された多層配線基板31を製造するようにしてもよい。フラッシュエッチングは、厚さ2〜5μm程度の銅層(導体膜28)をめっきレジストを用いることなく除去するものである。   Also, in FIG. 2 (I), both sides of the second substrate 27 are replaced with panel plating, and pattern plating is applied as shown in FIG. 2 (K) to thicken the conductor layer 32 patterned on the conductor film 28. May be. Next, as shown in FIG. 2 (L), the conductor film 28 exposed between the patterned conductor layers 32 is partially removed by flash etching to form a conductor pattern 30 on both surfaces of the second substrate 27. The multilayer wiring board 31 thus manufactured may be manufactured. In the flash etching, a copper layer (conductor film 28) having a thickness of about 2 to 5 μm is removed without using a plating resist.

尚、本実施形態では絶縁樹脂層の孔開け加工は炭酸ガスレーザーで行っているが、UV−YAGレーザー他のレーザーを使用しても同じ加工ができる。
また、本発明の孔開け方法により形成された孔の導通には導体層の導体で埋めるほかに穴壁に導体層の導体をめっきすることでも達成される。
In this embodiment, the hole forming process of the insulating resin layer is performed with a carbon dioxide gas laser, but the same process can be performed using a UV-YAG laser or another laser.
In addition, the conduction of the holes formed by the drilling method of the present invention can be achieved by plating the conductors of the conductor layer on the hole walls in addition to filling the conductors of the conductor layer.

上述した配線基板の製造方法を用いれば、多層配線基板31の微細配線パターンどうしを層間接続する導体層29,32が充填される微細な有底ビア26を効率よくしかも安価に形成することができる。   If the above-described method for manufacturing a wiring board is used, the fine bottomed via 26 filled with the conductor layers 29 and 32 for connecting the fine wiring patterns of the multilayer wiring board 31 to each other can be efficiently and inexpensively formed. .

1,21 絶縁樹脂基材 2 キャリヤ付銅箔 2a 銅箔 2b キャリヤ銅箔 3,23 第1の基板 4,24 コンフォーマルマスク 4a,24a 開口部 5,9,12,25,29,32 導体層 6,26 有底ビア 7 ビア孔 8,27 第2の基板 10,30 導体パターン 11 配線基板 21a 絶縁樹脂層 22 内層導体パターン 28 導体膜 31 多層配線基板   DESCRIPTION OF SYMBOLS 1,21 Insulation resin base material 2 Copper foil with carrier 2a Copper foil 2b Carrier copper foil 3,23 First substrate 4,24 Conformal mask 4a, 24a Opening 5, 9, 12, 25, 29, 32 Conductor layer 6, 26 Bottomed via 7 Via hole 8, 27 Second substrate 10, 30 Conductor pattern 11 Wiring substrate 21a Insulating resin layer 22 Inner layer conductor pattern 28 Conductor film 31 Multilayer wiring substrate

Claims (3)

絶縁樹脂基材の両面に銅箔を密着させてキャリヤ付銅箔が積層された第1の基板を用意する工程と、
前記第1の基板のうち一方の前記キャリヤ付銅箔をエッチングにより除去して開口部を有するコンフォーマルマスクを形成する工程と、
前記コンフォーマルマスクが形成された前記第1の基板の両面に電解めっきを行って、前記キャリヤ付銅箔の開口部壁面を含んで導体層を厚付けする工程と、
前記開口部の開口径を狭めるように前記導体層が厚付けされた当該導体層をマスクとして前記開口部にレーザー光を照射して前記絶縁樹脂基材層を除去して底部に他方のキャリヤ付銅箔の銅箔が露出した有底ビアを形成する工程と、
を含むことを特徴とする配線基板の製造方法。
Preparing a first substrate in which a copper foil with a carrier is laminated by adhering a copper foil to both surfaces of an insulating resin base;
Removing the copper foil with carrier of one of the first substrates by etching to form a conformal mask having an opening;
Performing electrolytic plating on both surfaces of the first substrate on which the conformal mask is formed, and thickening a conductor layer including an opening wall surface of the copper foil with carrier;
Using the conductor layer with the conductor layer thickened to narrow the opening diameter of the opening as a mask, the opening is irradiated with laser light to remove the insulating resin base material layer, and the other carrier is attached to the bottom. Forming a bottomed via in which the copper foil is exposed;
A method for manufacturing a wiring board, comprising:
絶縁樹脂基材の内層に内層導体パターンが各々形成された両面絶縁樹脂層に銅箔を密着させてキャリヤ付銅箔が各々積層された第1の基板を用意する工程と、
前記第1の基板の両面に積層された前記キャリヤ付銅箔をエッチングにより各々除去して前記絶縁樹脂層が底部に露出した開口部を有するコンフォーマルマスクを形成する工程と、
前記コンフォーマルマスクが形成された前記第1の基板の両面に電解めっきを行って、前記キャリヤ付銅箔の開口部壁面を含んで導体層を各々厚付けする工程と、
前記開口部の開口径を狭めるように前記導体層が厚付けされた当該導体層をマスクとして前記開口部にレーザー光を照射して前記絶縁樹脂層を除去して前記内層導体パターンが底部に露出した有底ビアを前記第1の基板の両面に形成する工程と、
を含むことを特徴とする配線基板の製造方法。
Preparing a first substrate in which the copper foil with carrier is laminated by bringing the copper foil into close contact with the double-sided insulating resin layer in which the inner layer conductor pattern is formed on the inner layer of the insulating resin base material;
Removing the copper foil with carrier laminated on both surfaces of the first substrate by etching to form a conformal mask having an opening in which the insulating resin layer is exposed at the bottom; and
Performing electroplating on both surfaces of the first substrate on which the conformal mask is formed, and thickening each of the conductor layers including the wall surface of the opening of the copper foil with carrier;
The opening layer is exposed to a laser beam using the conductor layer with the conductor layer thickened so as to reduce the opening diameter of the opening to remove the insulating resin layer, and the inner layer conductor pattern is exposed at the bottom. Forming bottomed vias on both sides of the first substrate;
A method for manufacturing a wiring board, comprising:
前記レーザー光を照射するコンフォーマルマスクとなる導体層の開口部の表面の開口径が最小開口径よりも10μm以上大きいことを特徴とする請求項1又は請求項2記載の配線基板の製造方法。   3. The method of manufacturing a wiring board according to claim 1, wherein the opening diameter of the surface of the opening portion of the conductor layer serving as a conformal mask for irradiating the laser light is 10 μm or more larger than the minimum opening diameter.
JP2013186118A 2013-09-09 2013-09-09 Wiring board manufacturing method Active JP5452759B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013186118A JP5452759B1 (en) 2013-09-09 2013-09-09 Wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013186118A JP5452759B1 (en) 2013-09-09 2013-09-09 Wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JP5452759B1 true JP5452759B1 (en) 2014-03-26
JP2015053423A JP2015053423A (en) 2015-03-19

Family

ID=50614541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013186118A Active JP5452759B1 (en) 2013-09-09 2013-09-09 Wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP5452759B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10321970A (en) * 1997-05-21 1998-12-04 Nippon Avionics Co Ltd Printed wiring board and manufacture thereof
JP2008218804A (en) * 2007-03-06 2008-09-18 Hitachi Aic Inc Wiring board
JP2008288434A (en) * 2007-05-18 2008-11-27 Nippon Mektron Ltd Method for manufacturing multilayer printed wiring board and wiring board thereof
JP2009125837A (en) * 2007-11-21 2009-06-11 Hitachi Aic Inc Machining method for printed circuit board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10321970A (en) * 1997-05-21 1998-12-04 Nippon Avionics Co Ltd Printed wiring board and manufacture thereof
JP2008218804A (en) * 2007-03-06 2008-09-18 Hitachi Aic Inc Wiring board
JP2008288434A (en) * 2007-05-18 2008-11-27 Nippon Mektron Ltd Method for manufacturing multilayer printed wiring board and wiring board thereof
JP2009125837A (en) * 2007-11-21 2009-06-11 Hitachi Aic Inc Machining method for printed circuit board

Also Published As

Publication number Publication date
JP2015053423A (en) 2015-03-19

Similar Documents

Publication Publication Date Title
TWI692284B (en) Printed wiring board and its manufacturing method
JP5360494B2 (en) Multilayer wiring substrate, method for manufacturing multilayer wiring substrate, and via fill method
JP3807312B2 (en) Printed circuit board and manufacturing method thereof
KR100701353B1 (en) Multi-layer printed circuit board and manufacturing method thereof
JP2008288434A (en) Method for manufacturing multilayer printed wiring board and wiring board thereof
TWI487451B (en) Manufacturing method of multilayer printed wiring board
US9131635B2 (en) Manufacturing method of substrate structure
KR100772432B1 (en) Method of manufacturing printed circuit board
JP2014216406A (en) Method of manufacturing core substrate of multilayer lamination wiring board, core substrate of multilayer lamination wiring board, and multilayer lamination wiring board
JP5452759B1 (en) Wiring board manufacturing method
JP4127213B2 (en) Double-sided wiring tape carrier for semiconductor device and manufacturing method thereof
JP2004193520A (en) Manufacturing method of printed circuit board
JP4153328B2 (en) Manufacturing method of multilayer printed wiring board
JP2009060151A (en) Production process of laminated wiring board
JP4045120B2 (en) Multilayer printed wiring board and manufacturing method thereof
JP2004319994A (en) Method for manufacturing printed wiring board
JP5495002B2 (en) Printed wiring board and manufacturing method thereof
JP2006339483A (en) Wiring board and manufacturing method thereof
JP6303364B2 (en) Method for forming through hole in core substrate
JP3984092B2 (en) Multilayer printed wiring board and manufacturing method thereof
JP2005101035A (en) Multilayer flexible wiring board, and manufacturing method thereof
JP2005294364A (en) Printed wiring board and via hole forming method using via filling plating
JP2002217536A (en) Pretreatment method for plating to non-through hole or through-hole in printed wiring board
JP2016054245A (en) Multilayer printed wiring board and method for manufacturing the same
KR20030080413A (en) The electroplating method of micro via hole for the use of multiple layers printed circuit board using step current density

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131203

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131227

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5452759

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250