JP2001308532A - Printed wiring board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the wiring efficiency of a built-up multilayer printed wiring board. SOLUTION: Imbedded bumps B1-B3 are formed by performing electrolytic plating inside blind via holes by using copper foil 2 formed on a single side copper-clad layered board 11 as a feeding layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a method for manufacturing a printed wiring board, and more particularly, to a printed wiring board suitable for application to a build-up multilayer printed wiring board.

[0002]

2. Description of the Related Art In a conventional build-up multilayer printed wiring board, a blind via hole is formed in a build-up layer, and a plating layer is formed on a side wall in the blind via hole to provide conduction with an inner layer circuit. Was.

FIG. 4 is a sectional view showing a configuration example of a conventional build-up multilayer printed wiring board. In FIG. 4, the double-sided copper-clad laminate 10a used as the inner layer board N1 includes:
Circuit patterns 11, 12 and inner through hole I
H is formed, and on the side wall of the inner through hole IH,
A copper plating layer 13 for connecting the upper and lower circuit patterns 11 and 12 is formed. Build-up layers T1 and T2 are formed on the front and back surfaces of the inner layer plate N1, respectively.

In the manufacturing process of the build-up layers T1 and T2, after the surface treatment of the copper foil of the double-sided copper-clad laminate 10a, resin layers 10b and 10c are formed on the front and back surfaces of the double-sided copper-clad laminate 10a. It is formed. Here, the resin layers 10b and 10c used for the build-up layers T1 and T2 are:
It can be formed by integrally laminating a prepreg, a resin sheet, an adhesive sheet in which a copper foil is coated with a resin, and the like, under heat and pressure, with the inner layer plate N1. Thereafter, a hole is formed from the surfaces of the resin layers 10b and 10c by using a laser to form a blind via hole BH. Then, the resin layers 10b, 10b are formed by electroless plating.
After forming an electroless plating layer on the entire surface of c, electrolytic copper plating is performed using the electroless plating layer as a power supply layer, and patterning of the copper plating layer is performed.

Thus, circuit patterns 15 and 18 are formed on the surfaces of the build-up layers T1 and T2, and copper plating layers 14 and 17 are formed on the side walls of the blind via holes BH. As a result, the build-up layer T
On the first side, the circuit patterns 12 and 15 can be connected, and on the buildup layer T2 side, the circuit patterns 11 and 18 can be connected.

[0006] Solder resists 16a and 16b are formed on the circuit patterns 15 and 18 of the build-up layers T1 and T2, and recesses of blind via holes BH are buried, and solder bumps are partially formed on the circuit patterns 15 and 18. 19 and 21 are formed, and the IC chip 20 is mounted on the build-up multilayer printed wiring board via the solder bump 19.

[0007]

However, in the conventional method of forming the copper plating layers 14 and 17 in the blind via hole BH, an electroless plating layer is formed under the electrolytic plating layer in order to form a power supply layer required for electrolytic plating. If it is necessary to form a plating layer and the diameter of the blind via hole BH is too small, it is difficult to stably form the electroless plating layer in the blind via hole BH.

For this reason, in order to stably form the copper plating layers 14 and 17 in the blind via hole BH, the diameter of the blind via hole BH needs to be somewhat large, which hinders a high density of circuit patterns. There was a problem.

Further, in the conventional method of forming an electrolytic plating layer using an electroless plating layer formed under the electrolytic plating layer as a power supply layer, copper plating layers 14 and 17 are formed on the side wall of the blind via hole BH. It was difficult to completely fill the inside of the blind via hole BH with the copper plating layers 14 and 17.

For this reason, the circuit patterns 15 and 18 cannot be formed on the surface 22 of the blind via hole BH, and the solder bump 21 cannot be directly stacked on the surface 22 of the blind via hole BH. Pattern 18 must be formed on the surface other than the surface 22 of the blind via hole BH. As a result, it is necessary to use an extra area corresponding to the area of the area where the solder bump 21 is formed, which hinders miniaturization of the build-up multilayer printed wiring board, and
Since the connection between the interlayer wirings is bypassed, there is a problem that the wiring efficiency is deteriorated.

Further, even when a number of build-up layers are stacked, the second layer blind via hole cannot be superimposed on the first layer blind via hole, which requires an extra area. There was also the problem of being done.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed wiring board and a method for manufacturing a printed wiring board that can improve wiring efficiency.

[0013]

According to the first aspect of the present invention, there is provided a single-sided copper-clad laminated substrate having a hole processed from a resin side to a copper foil surface, and the copper foil is provided with: And a filling portion in which the hole is filled by electrolytic plating serving as a power supply layer.

Thus, power can be supplied from the direction of the bottom of the hole formed in the resin via the copper foil originally formed on the single-sided copper-clad laminate. For this reason, it is possible to form the electrolytic plating layer in the blind via hole without forming the electroless plating layer, and even when the diameter of the blind via hole is reduced, the electrolytic plating layer can be stably formed in the blind via hole. Since it can be formed, the density of the build-up multilayer printed wiring board can be increased.

Further, by supplying the plating solution from the resin side and supplying power from the copper foil side, it is possible to supply and supply the plating solution from different directions. For this reason, it becomes possible to form the electrolytic plating layer only inside the blind via hole, and when forming the electrolytic plating layer in the blind via hole, the power supply layer becomes unnecessarily thick and the power supply layer pattern cannot be formed. Therefore, the inside of the blind via hole can be completely filled with the electrolytic plating layer.
As a result, the blind via holes can be stacked in many stages directly, and when connecting the upper and lower blind via holes, there is no need to displace the upper and lower blind via holes in the horizontal direction. Can be reduced in size.

According to a second aspect of the present invention, there is further provided a build-up layer in which via holes are filled by electrolytic plating using the filling portion as a power supply layer.

Accordingly, even when a number of build-up layers are stacked, the direction of the bottom of the blind via hole formed in the upper build-up layer can be reduced via the filling portion and the conductive pattern formed in the lower build-up layer. It is possible to supply power from Therefore, it is possible to form an electrolytic plating layer in the upper blind via hole without forming an electroless plating layer serving as a power supply layer on the surface of the upper build-up layer, and to reduce the diameter of the blind via hole. Also, since a uniform electrolytic plating layer can be formed in the blind via hole, the density of the build-up multilayer printed wiring board can be increased.

Further, since the blind via hole of the upper build-up layer can be formed directly on the blind via hole of the lower build-up layer, the area for forming the upper blind via hole can be reduced. And the size of the build-up multilayer printed wiring board can be reduced.

According to the third aspect of the present invention, the step of forming a hole from the resin side of the single-sided copper-clad laminate to the surface of the copper foil, and filling the hole by electrolytic plating using the copper foil as a power supply layer. And performing the following.

This makes it possible to fill the blind via hole with the electrolytic plating layer without forming an electroless plating layer serving as a power supply layer, thereby simplifying a manufacturing process when filling the blind via hole with the electrolytic plating layer. It is possible to do.

According to the fourth aspect of the present invention, the step of forming a hole from the resin layer side of the single-sided copper-clad laminate to the surface of the copper foil, and the electrolytic plating using the copper foil as a power supply layer, provide the resin layer. Filling the holes formed in, and flattening the filling surface of the holes, roughening the surface of the resin layer, forming a conductive pattern on the resin layer, A step of forming a build-up resin layer on the resin layer on which the conductive pattern is formed, a step of drilling the build-up resin layer up to the surface of the filling surface, and electrolytic plating using the copper foil as a power supply layer, Filling a hole formed in the build-up resin layer.

Thus, the build-up layer can be laminated while overlapping the blind via holes without using a complicated manufacturing method, and the adhesion of the conductive pattern formed in the build-up layer can be improved. This makes it possible to stably manufacture a build-up multilayer printed wiring board capable of high-density mounting.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A build-up multilayer printed wiring board according to an embodiment of the present invention will be described below with reference to the drawings. In the following examples, a description will be given of a build-up multilayer printed wiring board having a three-layer structure.
The build-up multilayer printed wiring board may have any number of layers.

FIG. 1 is a sectional view showing a configuration example of a build-up multilayer printed wiring board according to a first embodiment of the present invention. In FIG. 1, a copper foil 2 is formed on one side of a single-sided copper-clad laminated substrate I1, and a buried bump B1 is buried in a resin layer 1a of the single-sided copper-clad laminated substrate I1.
The conductive pattern L1 is formed on the surface of the resin layer 1a. Here, the embedded bump B1 is formed by supplying a plating solution into a blind via hole formed in the resin layer 1a using the copper foil 2 formed on the single-sided copper-clad laminate I1 as a power supply layer.

A build-up layer I2 is formed on the single-sided copper-clad laminated substrate I1, and a resin layer 1b of the build-up layer I2 is formed.
Is embedded with a buried bump B2, and a conductive pattern L2 is formed on the surface of the resin layer 1b.
Here, the buried bump B2 supplies power to the build-up layer I2 via the buried bump B1 and the conductive pattern L1, using the copper foil 2 as a power supply layer, and supplies a plating solution into a blind via hole formed in the resin layer 1b. It is formed by this.

A build-up layer I3 is formed on the build-up layer I2. A buried bump B3 is buried in the resin layer 1c of the build-up layer I3.
The conductive pattern L3 is formed on the surface of c. Here, the buried bump B3 uses the copper foil 2 as a power supply layer, passes through the buried bump B1 and the conductive pattern L1, and further includes the buried bump B2 and the conductive pattern L1.
Power is supplied to the build-up layer I3 via the second layer 2 and a plating solution is supplied into a blind via hole formed in the resin layer 1c.

A solder resist 3 is formed on the build-up layer I3, and a solder bump 4 is formed immediately above the buried bump B3 to form an IC chip 5.
Are mounted on the build-up layer I3 via the solder bumps 4.

In the single-sided copper-clad laminate I1, after the buried bump B3 is formed, the copper foil 2 is patterned to form a conductive pattern. Then, solder bumps 7 and solder resists 6 are formed on the patterned copper foil 2.

As a result, the buried bumps B1 to B3 can be formed by electrolytic plating without forming an electroless plating layer, and the buried bumps B1 to B3 can be formed even in a blind via hole having a small diameter of about 0.1 μm.
Since B3 can be formed stably, the density of the build-up multilayer printed wiring board can be increased.

Further, by embedding the inside of the blind via hole with the embedding bumps B1 to B3, the embedding bumps B1 to B3 are formed immediately above the embedding bumps B1 to B3, or the solder bumps 4 are formed immediately above the embedding bumps B1 to B3. Can be overlapped. Therefore, it is not necessary to separately provide exclusive conductive patterns L1 to L3 for connecting the buried bumps B1 to B3 or for connecting the buried bumps B3 and the solder bumps 4. The size can be reduced.

Further, by forming the buried bumps B1 to B3 in an overlapping manner, for example, a signal input to the solder bump 7 is transmitted to the solder bump 4 by the shortest path without detouring through the conductive patterns L1 to L3. It is possible to suppress the propagation delay caused by the passage of the conductive patterns L1 to L3.

The insulating material used for the resin layers 1a to 1c may be any of a thermosetting resin and a photoreactive resin. For example, a thermosetting epoxy resin or a photosensitive epoxy resin can be used. In addition, the resin layers 1a, 1
The formation of the blind via holes b and 1c may be performed by drilling using a drill, a laser, or the like, or drilling using photoetching.

FIG. 2 is a sectional view showing a manufacturing process of the build-up multilayer printed wiring board according to the first embodiment of the present invention.

In FIG. 2A, a blind via hole H1 is formed in the resin layer 1a by, for example, laser irradiation from the resin layer 1a side. Here, the single-sided copper-clad laminated substrate I1
Copper foil 2 is left as it is. In addition, the small diameter of the blind via hole H1 is not particularly limited, and is set to 0.1 mm.
It may be about 1 μm.

Next, in FIG. 2 (b), a chemical solution treatment such as permanganic acid is performed to remove the residue generated by laser processing or the like and to etch the surface of the copper foil 2 in the blind via hole H1. This exposes the complete copper surface 8. Then, the plating solution M1 is selectively supplied from the resin layer 1a side, and the plating solution M1 is
Electroplating using the copper foil 2 as a power supply layer is performed so as not to touch the back side of the substrate.

As a result, the electrolytic plating layer is sequentially deposited only in the blind via hole H1 from the bottom in the blind via hole H1 upward, and as shown in FIG. 2C, the bump B1 is embedded in the blind via hole H1.
Is formed.

In the above-described example, the case where the single-sided copper-clad laminate substrate I1 is used has been described. In this case, power is supplied from the copper foil 2 on the lower surface of the resin layer 1a, and the plating layer is formed sequentially from the bottom of the blind via hole H1, so that when the copper foil is previously formed on the upper surface of the resin layer 1a, Also, the copper foil on the upper surface of the resin layer 1a is not plated.

Next, in FIG. 2D, the resin layer 1 is formed by mechanically polishing the buried bump B1.
The raised portion of the embedded bump B1 is flattened with respect to a.

Next, in FIG. 2E, the surface of the resin layer 1a is roughened by performing a treatment with a chemical such as permanganic acid to form a rough surface 9 on the surface of the resin layer 1a.

Next, in FIG. 2F, an electroless plating layer is formed on the entire upper surface of the resin layer 1a by performing electroless plating. Then, a conductive layer is formed on the resin layer 1a by performing electrolytic plating using the electroless plating layer as a power supply layer, and the conductive layer is patterned to form a conductive pattern L1. Here, the resin layer 1a
By forming the rough surface 9 on the surface of the resin layer 1a
And the electroless plating layer can be improved in adhesion, and the conductive pattern L1 can be formed stably.

Next, in FIG. 2G, a resin layer 1b is formed on the resin layer 1a on which the conductive pattern L1 is formed. Here, the resin layer 1b can be formed by integrally laminating a prepreg or a resin sheet under heat and pressure with the single-sided copper-clad laminate substrate I1. And
Laser irradiation from the resin layer 1b side, etc.
Then, a blind via hole H2 is formed. Here, since the blind via hole H1 is completely buried with the buried bump B1, the blind via hole H2 can be formed not only on the conductive pattern L1 but also directly on the buried bump B1.

Next, by performing a treatment with a chemical such as permanganic acid, residues generated by laser processing or the like are removed, and the surfaces of the buried bumps B1 and the conductive patterns L1 in the blind via holes H2 are etched. Exposing the complete conductive surface. Then, the plating solution M2 is selectively supplied from the resin layer 2a side, and electrolytic plating using the copper foil 2 as a power supply layer is performed so that the plating solution M2 does not touch the back side of the copper foil 2.

As a result, power is supplied from the copper foil 2 into the blind via hole H2 via the buried bump B1 and the conductive pattern L1.
2 from the bottom up, blind via hole H2
Electrolytic plating layers are sequentially deposited only in the inside. As a result, FIG.
As shown in (h), a buried bump B2 is formed in the blind via hole H2.

In the same manner, a conductive pattern L2 is formed on the resin layer 1b. The copper foil 2 is used as a power supply layer to supply power to the blind via hole of the resin layer 1c via the embedded bump B1, the conductive pattern L1, the embedded bump B2, and the conductive pattern L2 sequentially.
The buried bump B3 can be formed.

Next, when the formation of the buried bumps B1 to B3 is completed and the role of the copper foil 2 as the power supply layer is completed, the copper foil 2 is patterned to form the copper foil 2 of the single-sided copper-clad laminated substrate I1. Is formed.

FIG. 3 is a sectional view showing a manufacturing process of a build-up multilayer printed wiring board according to a second embodiment of the present invention. In FIG. 3, the single-sided copper-clad laminates I1, I1
Are bonded together with the bonding foil I0 interposed therebetween. Then, a plating solution is supplied from both sides, and the single-sided copper-clad laminated substrates I1, I
Power is supplied to the 1 ′ copper foil. Thereby, the resin layers 1a, 1a
'Blind via holes H1, H2 respectively formed in
Embedded bumps can be simultaneously formed in 2 ′.

[0047]

As described above, according to the present invention,
Without using electroless plating, the blind via holes can be filled with an electrolytic plating layer, and a build-up multilayer printed wiring board having a high wiring density can be stably manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration example of a build-up multilayer printed wiring board according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the build-up multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a build-up multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a configuration example of a conventional build-up multilayer printed wiring board.

[Explanation of symbols]

 I1 I1 'Laminated substrate I2, I3 Build-up layer 1a, 1a', 1b, 1c Resin layer 2 Copper foil 3, 6 Solder resist 4, 7 Solder bump 5 IC chip 8 Copper surface 9 Rough surface B1-B3 Embedded bump L1- L3 Conductive pattern H1, H2, H1 'Opening I0 Laminating foil

Claims (4)

[Claims] 1. A single-sided copper-clad laminated substrate having a hole processed from a resin side to a copper foil surface, and a filling portion filled with the hole by electrolytic plating using the copper foil as a power supply layer. Printed wiring board. 2. The printed wiring board according to claim 1, further comprising a build-up layer in which via holes are filled by electrolytic plating using the filling portion as a power supply layer. 3. A method of forming a hole from the resin side of a single-sided copper-clad laminate to the surface of a copper foil, and filling the hole by electrolytic plating using the copper foil as a power supply layer. To manufacture printed wiring boards. 4. A step of forming a hole from the resin layer side of the single-sided copper-clad laminate to the surface of the copper foil, and a step of filling the hole formed in the resin layer by electrolytic plating using the copper foil as a power supply layer. A step of flattening the filling surface of the hole; a step of roughening the surface of the resin layer; a step of forming a conductive pattern on the resin layer; and a step of forming a conductive pattern on the resin layer on which the conductive pattern is formed. A step of forming a build-up resin layer; a step of drilling the build-up resin layer up to the surface of the filling surface; and a hole formed in the build-up resin layer by electrolytic plating using the copper foil as a power supply layer. And a step of performing filling of the printed wiring board.