JP5313202B2 - Build-up type multilayer printed wiring board and manufacturing method thereof - Google Patents

Abstract

In order to provide a method for inexpensively and stably producing build-up multilayer printed circuit boards having a stacked via structure allowing high-density mounting, a build-up multilayer printed circuit board is provided with: a flexible insulating base material (1); inner-layer circuit patterns (11A, 11B) formed on both sides of the insulating base material (1); and a double-sided core substrate (16). Said double-sided core substrate (16) comprises: an embedded via (6) that passes through the insulating base material (1) and is electrically connected to the inner circuit patterns (11A and 11B); and a cover plating layer (9) that covers the receiving land sections of the inner layer circuit patterns (11A, 11B) exposed by the embedded via (6), and the surface layer of which comprises gold, silver or nickel. The build-up multilayer printed circuit board is further provided with a build-up layer laminated on the double-sided core substrate (16). The build-up layer comprises an outer layer circuit pattern (23) on the surface layer, and a blind via (22A) that is electrically connected to the outer layer circuit pattern (23) and the inner-layer circuit pattern (11A). The blind via (22A) constitutes the embedded via (6) and a stack via structure.

Description

  The present invention relates to a build-up type multilayer printed wiring board having a stacked via structure and a manufacturing method thereof.

  In recent years, miniaturization and high functionality of electronic devices have been further advanced, and the demand for high-density mounting on printed wiring boards is increasing. In order to realize a printed wiring board capable of high-density mounting, a build-up type multilayer printed wiring board capable of providing a fine circuit wiring pattern is known (for example, see Patent Document 1).

  A build-up type multilayer printed wiring board generally has a double-sided printed wiring board having a through hole or a multilayer printed wiring board as a core substrate, and about one or two build-up layers on both sides or one side of the core substrate. It is provided. This build-up type multilayer printed wiring board is a bottomed type that electrically connects a circuit (inner layer circuit pattern) provided on a core substrate and a circuit (outer layer circuit pattern) provided on a build-up layer. Interlayer conduction part (blind via) is provided. This blind via is composed of a plated layer formed on the inner wall of a bottomed via hole (blind via hole) that penetrates the build-up layer and exposes the receiving land portion provided as a part of the inner circuit pattern on the bottom surface. This is an interlayer conductive path.

  However, as the blind via depth increases, the following problems arise. First, each of the members constituting the printed wiring board is thermally expanded, so that the blind via is easily broken. Furthermore, when a plating layer is formed on the inner wall of a bottomed via hole to obtain interlayer conduction, the plating solution tends to stay at the bottom of the via hole, so that a desired plating thickness cannot be obtained. For this reason, as the depth of the blind via increases, it becomes more difficult to ensure the reliability as the interlayer conductive path.

  As a countermeasure against the above problem, it is conceivable to form a plating layer sufficiently thick on the inner wall of the bottomed via hole. However, as the thickness of the plating layer formed on the inner wall of the bottomed via hole increases, the thickness of the conductor layer formed on the buildup layer inevitably increases accordingly. The outer layer circuit pattern is formed by wet etching the conductor layer on the build-up layer according to a desired pattern. For this reason, it becomes difficult to miniaturize the outer layer circuit pattern as the thickness of the conductor layer on the buildup layer increases. As a result, there is a problem that it becomes difficult to satisfy the demand for high-density mounting.

  By the way, among the build-up type multilayer printed wiring boards, in particular, a build-up type multilayer printed wiring board having a stack via structure is required from the viewpoint of increasing the density and improving the degree of design freedom. Here, the stack via structure is a structure that electrically connects the outer layer circuit pattern and the inner layer circuit pattern on the interlayer connection portion that electrically connects the inner layer circuit patterns formed on the front surface and the back surface of the core substrate. This is a structure in which the interlayer connection parts are stacked. Conventionally, a method described in Patent Document 2 is known as one of methods for manufacturing a build-up type multilayer printed wiring board having a stacked via structure.

  Next, in order to clarify the problems of the prior art, a conventional method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure will be described with reference to FIG. FIG. 4 is a process cross-sectional view illustrating a method for manufacturing a conventional build-up type multilayer printed wiring board.

(1) A flexible double-sided copper-clad laminate 104 having a copper foil 102 and a copper foil 103 (each 12 μm thick) on both sides of a flexible insulating base material 101 (25 μm thick) made of a polyimide film is prepared. . Then, as can be seen from FIG. 4A, through holes 105 (φ100 μm) penetrating through the double-sided copper-clad laminate 104 in the thickness direction are formed using laser processing or NC drills.

(2) Next, as can be seen from FIG. 4 (1), a conductive paste is filled into the through hole 105 by screen printing or the like, and then the filled conductive paste is cured to form the embedded via 106. Form.

(3) Next, as can be seen from FIG. 4 (1), a lid plating layer 107 made of a copper plating film is formed on the exposed via 105 and the surrounding copper foils 102, 103 by performing an electrolytic copper plating process. (Φ200 μm, 10 μm thickness) is formed. The lid plating layer 107 reduces the contact resistance between the embedded via 106 and the copper foils 102 and 103, ensures the reliability of interlayer connection by the embedded via 106, and at the time of laser processing the blind via hole later. Formed to protect 106. Note that the thickness of the lid plating layer 107 is determined in consideration of the resistance to the laser beam irradiated when forming the subsequent blind via hole. That is, the lid plating layer 107 needs to have a thickness that does not penetrate during laser processing.

(4) Next, as can be seen from FIG. 4 (1), the copper foils 102 and 103 are processed by the photofabrication technique, and the inner layer circuit pattern having the receiving land portion 108 (φ300 μm) having a larger diameter than the lid plating layer 107. Are formed on both surfaces of the flexible insulating base material 101. Here, the photofabrication method is a processing method for patterning a processing layer (copper foil or the like) into a predetermined pattern. The formation of a resist layer on the processing layer, exposure, development, It consists of a series of processes such as etching and stripping of the resist layer. In this step, it is necessary to cover the entire lid plating layer 107 with a resist layer so that the lid plating layer 107 is not damaged. For this reason, the diameter of the receiving land portion 108 must be larger than the diameter of the lid plating layer 107. This becomes a factor that prevents the inner layer circuit pattern from being densified.

(5) Next, in order to improve the adhesion with the adhesive used for laminating the build-up layer, the surface of the inner layer circuit pattern is roughened. This roughening treatment increases the absorption rate of carbon dioxide (CO ₂ ) laser light (wavelength: about 9.8 μm) on the copper surface, so that the lid plating layer 107 is less resistant to laser processing.

(6) Next, as can be seen from FIG. 4 (1), the polyimide film 109 (12 μm thickness) is adhered onto the inner layer circuit pattern via the adhesive layer 110 (25 μm thickness), and the coverlay 111 is formed. Form. Here, the thickness of the adhesive layer 110 is determined so that the adhesive layer 110 can completely fill the lid plating layer 107 and the inner layer circuit pattern. For this reason, the greater the thickness of the lid plating layer 107, the greater the thickness of the adhesive layer 110.

  Up to this step, the double-sided core substrate 112 shown in FIG. 4A is obtained.

(7) Next, a flexible single-sided copper-clad laminate 113 is prepared. As can be seen from FIG. 4B, an opening serving as a conformal mask is formed on the copper foil 113b of the single-sided copper-clad laminate 113 using a photofabrication technique. Here, the single-sided copper clad laminate 113 has a copper foil 113b (12 μm thickness) on one side of a polyimide film 113a (thickness 25 μm).

(8) Next, as can be seen from FIG. 4 (2), the single-sided copper-clad laminate 113 in which the copper foil 113 b has been processed in the previous step is laminated on both sides of the double-sided core substrate 112 via the adhesive layer 114. Glue.

(9) Next, as shown in FIG. 4B, laser processing is performed using a conformal mask formed on the copper foil 113b to form blind via holes (conduction holes) 115A and 115B.

  The laser processing in this step often uses a carbon dioxide laser in consideration of productivity. However, since the roughened copper surface is susceptible to thermal damage by a carbon dioxide laser, attention must be paid to laser processing conditions (such as pulse energy of laser light). There are two methods for preventing the cover plating layer 107 from penetrating, that is, a method for reducing the power of the laser beam and a method for increasing the thickness of the cover plating layer 107. The former method cannot be employed because the processing speed decreases and the productivity decreases. On the other hand, when the latter method is used, it is difficult to form a fine outer layer circuit pattern as will be described in detail later, so that the demand for high-density mounting of the printed wiring board cannot be satisfied.

(10) Next, as can be seen from FIG. 4 (3), an electrolytic copper plating film is formed on the copper foil 113 b and the inner walls of the blind via holes 115 A and 115 B by conducting a conductive treatment and subsequent electrolytic copper plating treatment. To do. The thickness of this electrolytic copper plating film needs to be about 25-30 micrometers in order to ensure interlayer conduction. By this step, blind vias 116A and 116B that function as interlayer conductive paths are formed. The blind via 116A is stacked on the embedded via 106 of the core substrate via the lid plating layer 107, and a stacked via structure is formed. On the other hand, the blind via 116B does not constitute a stacked via structure.

(11) Next, as shown in FIG. 4 (3), the electrolytic copper plating film formed in the previous step is processed using a photofabrication technique to form an outer layer circuit pattern 117. As can be seen from FIG. 4 (3), the build-up type multilayer printed wiring board 118 includes a component mounting portion 118a in which a build-up layer is laminated on the double-sided core substrate 112, and a flexible cable extending from the component mounting portion 118a. Part 118b. The flexible cable portion 118b is a part of the double-sided core substrate 112 that is not provided with a build-up layer.

  Through the above steps, a conventional build-up type multilayer printed wiring board 118 having a step via structure is manufactured.

JP 2004-200260 A JP 2000-151118 A

  As one of the problems of the prior art, as described above, in order to prevent the lid plating layer 107 from penetrating when forming the blind via holes 115A and 115B by laser processing while maintaining productivity, the lid plating layer 107 is used. It must be thickened. As the lid plating layer 107 becomes thicker, the thickness of the adhesive layer 110 that embeds the inner layer circuit pattern increases, so that the blind via holes 115A and 115B become deeper. The thickness of the electrolytic copper plating film formed on the blind via holes 115A and 115B and the copper foil 113b needs to be about 25 to 30 μm as described above in order to ensure the connection reliability of the blind vias 116A and 116B. . In this case, since the total thickness of the conductor layer (copper foil 113b and electrolytic copper plating film) on the build-up layer is 37 to 42 μm, a fine outer layer circuit pattern with a pitch of about 100 μm is formed with a high yield. Is extremely difficult in practice.

  As described above, the conventional build-up type multilayer printed wiring board having the step via structure has a problem that it cannot satisfy the demand for high-density mounting.

  The present invention has been made based on the above technical recognition, and provides a build-up type multilayer printed wiring board having a stack via structure capable of high-density mounting, and such a printed wiring board. It aims at providing the method of manufacturing cheaply and stably.

According to one aspect of the present invention, a flexible insulating base material, an inner layer circuit pattern provided on both surfaces of the insulating base material and having a receiving land portion, and penetrating the insulating base material and the receiving land portion. A buried via for electrically connecting the inner layer circuit patterns on the front and back surfaces of the insulating base material, the receiving land portion where the buried via is exposed, and a surface layer made of a metal constituting the inner layer circuit pattern. A core substrate having a lid plating layer made of a material resistant to an etchant;
A build-up layer laminated on the core substrate, the outer layer circuit pattern provided on the surface layer, the blind via hole penetrating the build-up layer in the thickness direction and exposing the lid plating layer on the bottom surface There is provided a build-up type multilayer printed wiring board comprising a build-up layer, which is a plating film formed on an inner wall and has a blind via electrically connecting the inner layer circuit pattern and the outer layer circuit pattern. .

According to another aspect of the present invention, there is provided a double-sided copper-clad laminate having a flexible insulating base material, and a first copper foil and a second copper foil provided on the front surface and the back surface, respectively. ,
Forming a through hole penetrating the double-sided copper-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a cover plating layer having at least a surface layer of silver, gold or nickel in a region where the embedded via is exposed and a region which is a receiving land portion of a blind via hole even if the embedded via is not exposed;
Forming a resist layer having a predetermined pattern on the first copper foil;
Etching the first copper foil using the resist layer and the lid plating layer as an etching resist to form an inner layer circuit pattern having a receiving land portion covered with the lid plating layer,
After peeling off the resist layer and subjecting the surface of the inner layer circuit pattern to a roughening treatment, an adhesive layer filling the inner layer circuit pattern and the lid plating layer is formed,
A build-up layer having a third copper foil on the surface layer is laminated on the adhesive layer,
By irradiating a predetermined position of the build-up layer with infrared laser light, penetrating the build-up layer in the thickness direction, the cover plating layer is exposed on the bottom, forming a blind via hole,
A blind for electrically connecting the conductive layer made of the third copper foil and the plating film and the inner layer circuit pattern by forming a plating film on the inner wall of the blind via hole and the third copper foil. A method of manufacturing a build-up type multilayer printed wiring board for forming a via is provided.

  Due to these features, the present invention has the following effects.

  The build-up type multilayer printed wiring board according to the present invention has a cover plating layer made of a material whose surface layer is resistant to a metal etchant constituting an inner layer circuit pattern at a receiving land portion of a blind via hole. Since this lid plating layer has high resistance to infrared lasers, the thickness of the lid plating layer can be greatly reduced. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the buildup layer can be shallowed. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and the outer circuit pattern can be miniaturized. Therefore, the build-up type multilayer printed wiring board having the stacked via structure according to the present invention can satisfy the demand for high-density mounting.

  Further, in the method for manufacturing a build-up type multilayer printed wiring board according to the present invention, a cover plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern is formed on the receiving land portion of the build-up via hole. Form. Since this lid plating layer has high resistance to infrared lasers, it can be formed significantly thinner. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the build-up layer can be formed shallow. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and a fine outer layer circuit pattern can be formed. Furthermore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same, so that productivity can be improved.

It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 1st Embodiment of this invention following FIG. 1A. However, (6) is a plan view corresponding to (5). It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 1st Embodiment of this invention following FIG. 1B. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 1st Embodiment of this invention following FIG. 1C. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 2nd Embodiment of this invention following FIG. 2A. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 2nd Embodiment of this invention following FIG. 2B. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 2nd Embodiment of this invention following FIG. 2C. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 3rd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board concerning the 3rd Embodiment of this invention following FIG. 3A. It is process sectional drawing which shows the manufacturing method of the buildup type multilayer printed wiring board which concerns on the 3rd Embodiment of this invention following FIG. 3B. It is process sectional drawing for demonstrating the manufacturing method of the buildup type multilayer printed wiring board which has a stack via structure by a prior art.

  Hereinafter, three embodiments according to the present invention will be described with reference to the drawings.

  In addition, in each figure, the component which has an equivalent function is attached | subjected the same code | symbol, and detailed description of the component of the same code | symbol is not repeated. The numerical values in the description of the embodiments are all exemplary values, and the present invention is not limited to these values. Further, the drawings are schematic and mainly show characteristic portions according to each embodiment, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones.

(First embodiment)
A method for manufacturing a build-up type multilayer printed wiring board having a stack via structure according to the first embodiment will be described with reference to FIGS. 1A to 1D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.

(1) Flexible double-sided copper clad laminate 4 having copper foil 2 and copper foil 3 (each 12 μm thick) on the front and back surfaces of flexible insulating base material 1 (thickness 25 μm) such as polyimide film, respectively. Prepare. Then, as shown in FIG. 1A (1), through holes 5 (φ100 μm) penetrating through the double-sided copper-clad laminate 4 in the thickness direction are formed by using laser processing or NC drills. When the through hole 5 is formed by laser processing, the conformal laser processing method using the copper foils 2 and 3 processed into a predetermined pattern as a metal mask, or the copper foils 2 and 3 and the insulation below them. A direct laser processing method in which the resin (flexible insulating base material 1) is directly processed with a laser beam can be selected. Here, in consideration of productivity, a direct laser processing method that does not require a copper foil etching step by a photofabrication method was selected.

(2) Next, as shown in FIG. 1A (2), the through-hole 5 is filled with the conductive paste 6A by screen printing or the like, and then the filled conductive paste 6A is cured. From the viewpoint of reduction in the number of steps and electrical characteristics, the conductive paste 6A preferably has a low volume resistivity and does not require a conductive treatment when a lid plating layer 9 described later is formed. Here, AE1244 (volume resistivity: 5 × 10 ⁻⁵ Ω · cm) manufactured by Tatsuta Electronics Co., Ltd. was used. In this step, as shown in FIG. 1A (2), the upper and lower portions of the through-hole 5 are filled until the conductive paste 6A overflows so that voids or the like do not occur in the through-hole 5 due to the lack of the conductive paste. It is preferable to do. In addition, since the conductive paste is filled in the through hole instead of the blind via hole, the printing machine used in this process does not need to be a vacuum type and has a differential pressure enough to adsorb the double-sided copper clad laminate 4. As long as it has a mechanism capable of generating

(3) Next, both sides of the double-sided copper clad laminate 4 in which the through-hole 5 shown in FIG. 1A (2) is filled with the conductive paste 6A are mechanically polished by a belt sander or roll buff, or chemical mechanically polished (CMP : Polishing by Chemical Mechanical Polishing). As a result, as shown in FIG. 1A (3), the excess conductive paste 6A protruding from the through hole 5 is scraped, and the buried via 6 is formed. The copper foil 2 and the copper foil 3 are also shaved by polishing in this step, and the copper foil 2 and the copper foil 3 become a copper foil 2a and a copper foil 3a having a thickness of about 5 μm, respectively.

  When polishing a flexible thin double-sided copper-clad laminate as in this step, the double-sided copper-clad laminate 4 is bonded to a hard substrate (several mm thick) via an adhesive sheet before polishing. ) Etc. and then polishing. By doing in this way, the polisher for hard substrates can be used. As another method of polishing the thin film, the double-sided copper-clad laminate 4 is adsorbed and held on a flat plate, the surface opposite to the adsorption surface is polished, and then the double-sided copper-clad laminate 4 is turned over and polished. This surface may be adsorbed on a flat plate, and the unpolished surface may be polished.

(4) Next, as can be seen from FIG. 1A (4), a plating resist layer 7 is formed on each of the copper foil 2a and the copper foil 3a. This plating resist layer 7 has an opening 8a in a region where the embedded via 6 is exposed, and further has an opening 8b in a region which becomes a receiving land portion of a blind via hole without the embedded via 6. The diameters of the openings 8a and 8b are preferably determined in consideration of the diameter of the blind via hole and the alignment accuracy when forming the blind via hole. Here, it is set to φ200 μm.

(5) Next, as shown in FIG. 1A (4), by performing electrolytic or electroless plating using the plating resist layer 7, the lid plating layer 9 is formed in the openings 8a and 8b of the plating resist layer 7. To do. More specifically, the lid plating layer 9 is formed as follows. First, electrolytic copper plating is performed to form a copper plating layer 9a having a thickness of 2 μm on the bottom surfaces of the openings 8a and 8b. Thereafter, electroless silver plating is performed to form a silver plating layer 9b having a thickness of 0.5 μm on the copper plating layer 9a. This series of plating processes is performed with the plating resist layer 7 left.

  The lid plating layer 9 is not limited to the above configuration. For example, a nickel plating layer by electroless nickel plating may be formed instead of the copper plating layer 9a. Moreover, you may comprise the lid plating layer 9 as one silver plating layer or a nickel plating layer using electrolysis or electroless plating.

  The plating layer constituting the surface layer of the lid plating layer 9 needs to have resistance to copper etchant (may be selective etching with respect to copper). As a plating layer that satisfies this condition, a gold plating layer by electroless gold plating or a nickel plating layer by electroless nickel plating may be formed instead of the silver plating layer 9b. In addition, instead of the silver plating layer 9b, a nickel plating layer and a gold plating layer may be sequentially formed on the copper plating layer 9a. Thus, the cover plating layer 9 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni). A plating layer made of nickel, copper, or the like can be configured singly or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the lid plating layer 9 composed of the copper plating layer 9a and the silver plating layer 9b is formed can be obtained. The configuration of the lid plating layer 9 is selected in consideration of productivity and cost.

(6) Next, after the plating resist layer 7 is peeled off, as shown in FIGS. 1B (5) and (6), an etching resist having a predetermined pattern for forming inner layer circuit patterns 11A and 11B described later. The layer 10 is formed on the copper foils 2a and 2b. Here, FIG. 1B (5) is a cross-sectional view taken along the line A-A 'of FIG. 1B (6). That is, FIG. 1B (6) is a view of the base material shown in FIG. 1B (5) as viewed from above. In order to form the etching resist layer 10, a dry film resist (about 10 μm thick) for forming a fine wiring may be used. Even in this case, since the thickness of the lid plating layer 9 is as thin as 2.5 μm as described above, the lid plating layer 9 can be filled.

  Since the lid plating layer 9 functions as an etching resist during circuit pattern etching, it is not necessary to provide an etching resist layer for protecting the lid plating layer 9 as shown in FIGS. 1B (5) and (6). . Therefore, the shape of the lid plating layer 9 can be used as it is as the shape of the receiving land portion of the blind via hole without using an exposure machine capable of highly accurate alignment. This improves productivity and contributes to the manufacture of an inexpensive printed wiring board.

(7) Next, as can be seen from FIG. 1B (7), the copper foil 2a and the copper foil 3a are etched using the etching resist layer 10 and the lid plating layer 9 as an etching resist, thereby providing flexible insulation. The inner layer circuit pattern 11A and the inner layer circuit pattern 11B are formed on the front surface and the back surface of the base material 1, respectively. Thereafter, the etching resist layer 10 is peeled off. The inner layer circuit patterns 11 </ b> A and 11 </ b> B have blind via hole receiving land portions covered with the cover plating layer 9.

  The etchant used in this step is one that etches the copper foils 2a and 3a but does not damage the lid plating layer 9 (silver plating layer 9b). For example, an etchant using cupric chloride or ferric chloride can be used as such an etchant.

  When the surface layer of the lid plating layer 9 is composed of a nickel plating layer, the etching in this step is performed as selective etching using, for example, an ammonia-based alkali etchant.

  Through the steps so far, the double-sided circuit substrate 12 shown in FIG. 1B (7) is obtained. Inner layer circuit patterns 11A and 11B having receiving land portions are formed on the double-sided circuit substrate 12, and the embedded via 6 electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B. The lid plating layer 9 also has a function of reducing the contact resistance between the embedded via 6 and the copper foils 2 and 3 and ensuring the reliability of the embedded via 6 as an interlayer connection path.

(8) Next, in order to improve adhesiveness with an adhesive (adhesive layer 14 described later) used for stacking the buildup layers, the surface of the inner layer circuit patterns 11A and 11B is subjected to a roughening treatment. Here, the roughening process was performed using the multi bond 150 of Nippon Macder Mid Co., Ltd. In addition, you may perform a roughening process using the neo-brown process NBD series etc. by Ebara Densan.

  As described above, the roughening treatment improves the adhesion between the copper foils 2a and 3a and the adhesive, but increases the absorption rate of carbon dioxide laser light in the copper foils 2a and 3a. However, in this embodiment, a silver plating layer 9b having copper etchant resistance is formed on the surface layer of the lid plating layer 9 covering the receiving land portion of the blind via hole. For this reason, the lid plating layer 9 is not roughened by the roughening treatment in this step, and the absorption rate of the carbon dioxide laser light in the receiving land portion does not increase. Actually, when the absorption rate of the carbon dioxide laser beam was measured before and after the roughening treatment, the absorption rate increased from about 20% to about 30% on the surfaces of the copper foils 2a and 3a, but on the surface of the silver plating layer 9b. There was no increase in absorption. In addition, since the thickness of the copper plating layer 9a and the copper foil 2a (3a) under the silver plating layer 9b is not reduced by the irradiation of the carbon dioxide laser beam, the resistance to thermal damage caused by laser processing is sufficiently ensured. Yes. Since the silver plating layer 9b hardly absorbs infrared laser light before this step (roughening treatment), the resistance of the lid plating layer 9 to the infrared laser light is maintained sufficiently high after the roughening treatment in this step. .

(9) Next, as shown in FIG. 1B (8), coverlays 15 are formed on the front and back surfaces of the double-sided circuit board 12 so as to cover the inner layer circuit patterns 11A and 11B. More specifically, after forming an adhesive layer 14 that fills the inner layer circuit pattern with the structures 11A and 11B and the lid plating layer 9, an insulating film 13 (12 μm thick) made of, for example, a polyimide film is formed on the adhesive layer 14. By forming the coverlay 15, the coverlay 15 is formed. The adhesive layer 14 is obtained by curing, for example, an acrylic or epoxy adhesive.

  The thickness of the adhesive layer 14 is determined so that the inner layer circuit pattern 11A (11B) and the lid plating layer 9 can be completely filled. The thickest portion of the inner layer circuit pattern 11A (11B) is a receiving land portion of the blind via hole. The thickness of the receiving land portion is 7.5 μm (copper foil 2a (3a): 5 μm, lid plating layer 9: 2.5 μm), which is smaller than the conventional one due to the thinning of the lid plating layer 9. Therefore, the thickness of the adhesive layer 14 can be set to a value (8 μm) that is significantly smaller than the conventional one.

  Through the steps so far, the double-sided core substrate 16 shown in FIG. 1B (8) is obtained.

(10) Next, as can be seen from FIG. 1C (9), a single-sided copper-clad laminate having a copper foil 17b (12 μm thick) on one side of a flexible insulating base material 17a (for example, a polyimide film having a thickness of 25 μm). 17 is prepared. And the conformal mask 18 (opening part) for forming a blind via hole is formed in the copper foil 17b of the single-sided copper clad laminated board 17 using the photofabrication method.

(11) Next, as shown in FIG. 1C (9), the single-sided copper-clad laminate 17 on which the conformal mask 18 is formed is bonded to the double-sided core via an adhesive layer 19 made of an adhesive for building up. The substrate 16 is laminated and adhered. The adhesive used here is a flow-out such as a low-flow type prepreg or a bonding sheet so that the adhesive does not flow out to the flexible cable portion (double-sided core substrate 16 not covered with the single-sided copper-clad laminate 17). Those with less are preferred. Even if the single-sided copper clad laminate 17 having the unprocessed copper foil 17b is bonded to the double-sided core substrate 16 through the adhesive layer 19, the copper foil 17b is processed to form the conformal mask 18. Good.

  Here, the diameter of the conformal mask 18 was set to 120 μm, which is a value 80 μm smaller than the diameter 200 μm of the receiving land portion (lid plating layer 9) of the blind via hole. Therefore, the conformal mask 18 may be formed by a technique that can obtain an alignment accuracy of ± 40 μm. As this alignment method, for example, there are the following two methods.

  The first method is a method in which the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16 after the conformal mask 18 is formed. In this method, target marks are formed in advance on the double-sided core substrate 16. Then, after aligning the single-sided copper-clad laminate 17 using this target mark, the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16.

  The second method is a method in which the conformal mask 18 is formed after the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16. In this method, first, target marks are formed in advance on the double-sided core substrate 16. Then, the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16 to form a resist layer on the copper foil 17b. Thereafter, the double-sided core substrate 16 and the photomask are aligned using the mark indicating the reference position provided on the photomask for exposure and the target mark of the double-sided core substrate 16. Then, the resist layer is exposed and developed to form a conformal mask 18 at a predetermined position on the copper foil 17b.

(12) Next, as shown in FIG. 1C (10), laser processing is performed using the conformal mask 18 formed in the previous step, and the blind via holes 20A and 20B with the cover plating layer 9 exposed on the bottom surface (for conduction) Hole). More specifically, the flexible insulating base material 17a, the adhesive layer 19, the insulating film 13, and the adhesive layer 14 in the conformal mask 18 are removed. In the laser processing method in this step, it is preferable to use a carbon dioxide laser having a high processing speed and excellent productivity, but more generally, an infrared laser can be used.

  Here, the details of the laser processing in this step will be described. As the carbon dioxide laser processing machine, ML605GTXIII-5100U2 manufactured by Mitsubishi Electric Corporation was used. The laser beam diameter was adjusted to 200 μm with a predetermined aperture or the like, the laser irradiation position was adjusted, and then 5 shots of laser pulses with a pulse width of 10 μSec and a pulse energy of 5 mJ were irradiated to form blind via holes 20A and 20B. Although the thickness of the lid plating layer 9 is as thin as 2.5 μm, the absorption of the carbon dioxide laser beam of the silver plating layer 9 b is small, so that the laser beam penetrates the lid plating layer 9 or the lid plating layer 9 extends from the embedded via 6. Laser processing can be performed without peeling.

(13) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 20A and 20B are formed.

(14) Next, as shown in FIG. 1D (11), by conducting a conductive treatment and subsequent electrolytic copper plating treatment, on the inner walls (side and bottom surfaces) of the blind via holes 20A and 20B and the copper foil 17b, An electrolytic copper plating film 21 is formed. The thickness of the electrolytic copper plating film 21 was about 15 to 20 μm in order to ensure interlayer conduction. As a result, the outer conductive film (copper foil 17b and electrolytic copper plating film 21) and the inner circuit patterns 11A and 11B are electrically connected to form blind vias 22A and 22B that function as interlayer conductive paths.

(15) Next, as shown in FIG. 1D (12), a conductive layer on the flexible insulating base material 17a (copper foil 17b and the electrolytic copper plating film 21 thereon) is formed in a predetermined manner by a photofabrication technique. The outer layer circuit pattern 23 is formed by processing into a pattern.

  After this, although not shown, if necessary, a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.

  Through the above steps, the build-up type multilayer printed wiring board 24 according to the first embodiment is obtained. The double-sided core substrate 16 of the build-up type multilayer printed wiring board 24 includes a flexible insulating base material 1 and inner layer circuit patterns 11A and 11B provided on both surfaces of the flexible insulating base material 1 and having receiving land portions, An embedded via 6 that penetrates the flexible insulating base material 1 and the receiving land portion and electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B is provided. Further, a cover plating layer 9 made of a material that covers the receiving land portion where the embedded via 6 is exposed and whose surface layer is resistant to the metal etchant constituting the inner layer circuit patterns 11A and 11B is provided.

  On the double-sided core substrate 16, a build-up layer having an outer layer circuit pattern 23 provided on the surface layer is laminated via an adhesive layer 19.

  The blind vias 22A and 22B are made of a plating film formed on the inner walls of the blind via holes 20A and 20B that penetrate the build-up layer in the thickness direction and the cover plating layer 9 is exposed on the bottom surface. The circuit patterns 11A and 11B and the outer layer circuit pattern 23 are electrically connected. Further, as shown in FIG. 1D (12), the blind via 22A is arranged so as to overlap the embedded via 6 with the lid plating layer 9 interposed therebetween. Thus, the build-up type multilayer printed wiring board 24 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 22A.

  As shown in FIG. 1D (12), the build-up type multilayer printed wiring board 24 includes a component mounting portion 24a in which a build-up layer is laminated on the double-sided core substrate 16, and a flexible cable extending from the component mounting portion 24a. Part 24b. The flexible cable portion 24b is a part of the double-sided core substrate 16 where the buildup layer is not provided. The flexible cable portion 24b is not an essential component and may not be provided.

  In the present embodiment, the build-up layers are provided on the front and back surfaces of the double-sided core substrate 16, but the build-up layers may be provided only on one side.

  As described above, in the present embodiment, the lid plating layer 9 is formed in the region that becomes the receiving land portion of the blind via holes 20A and 20B that penetrate the build-up layer. The surface layer of the lid plating layer 9 is composed of a plating layer (silver plating layer 9b or the like) resistant to a copper etchant. Thereby, since the lid plating layer 9 is not roughened when the copper films 2a and 3a are roughened, the laser on the surface of the receiving land portion (lid plating layer 9) is formed when the blind via holes 20A and 20B are formed by laser processing. There is almost no light absorption, and even when the lid plating layer 9 is thin, it is not damaged by the laser beam. Therefore, the lid plating layer 9 can be made much thinner than conventional.

  By thinning the lid plating layer 9, the adhesive layer 14 of the coverlay 15 can be thinned. Thereby, the blind via holes 20A and 20B can be formed shallowly. For example, it is about 10 μm smaller than the conventional one. Thereby, the electrodeposition easiness of the electrolytic copper plating film | membrane 21 with respect to the inner wall of blind via-hole 20A, 20B improves. Furthermore, the influence on the blind vias 22A and 22B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced. Of the members constituting the build-up type multilayer printed wiring board 24, the adhesive constituting the adhesive layer 14 has a particularly large coefficient of thermal expansion, so that the effect of making the adhesive layer 14 thinner is great. For this reason, it is possible to reduce the thickness of the electrolytic copper plating film 21 necessary for improving yield and ensuring connection reliability. As a result, according to the present embodiment, it is possible to form a fine outer layer circuit pattern 23, and it is possible to obtain a build-up type multilayer printed wiring board 24 having a stacked via structure that satisfies the requirements for high-density mounting. .

  Further, when the copper foils 2 a and 3 a are etched to form the inner layer circuit pattern 11, the lid plating layer 9 has copper etchant resistance, so that it is not necessary to provide a resist layer for protecting the lid plating layer 9. Thereby, according to this invention, the diameter of the receiving land part (copper foil 2a, 3a) coat | covered with the lid plating layer 9 can be made the same as the lid plating layer 9, and densification of an inner-layer circuit pattern can be carried out. Can be planned. In addition, since it is not necessary to use an exposure machine capable of highly accurate alignment, productivity can be improved and a printed wiring board can be manufactured at low cost.

  Further, the lid plating layer 9 is provided on the receiving land portion of the blind via hole 20B that does not constitute the stacked via structure. Therefore, the structure of the blind via hole 20B (via depth and the like) is substantially the same as the blind via hole 20A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to the present embodiment, a large processing margin can be ensured and productivity can be improved.

(Second Embodiment)
Next, a build-up type multilayer printed wiring board according to the second embodiment will be described. One of the differences between the second embodiment and the first embodiment is that the build-up type multilayer printed wiring board according to the second embodiment has an inner layer terminal on the flexible insulating base material in the flexible cable portion. The plating layer that protects the surface of the inner layer terminal is formed in the same plating step as the lid plating layer formed on the embedded via and the receiving land portion. Thereby, the number of processes can be reduced and productivity can be improved.

  A method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure according to the present embodiment will be described with reference to FIGS. 2A to 2D. 2A to 2D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.

  Since the process until obtaining the base material shown in FIG. 1A (3) of the first embodiment is the same as that of the first embodiment, the description thereof will be omitted and the subsequent processes will be described.

(1) As shown in FIG. 2A (1), electrolytic copper plating treatment is performed on both surfaces of the base material, and electrolytic copper plating films 31 and 32 (respectively on the copper foils 2a and 3a and the exposed embedded via 6) 2 μm thick).

(2) Next, as shown in FIG. 2A (2), an etching resist layer 33 having a predetermined pattern is formed on the electrolytic copper plating films 31 and 32 to form inner layer circuit patterns 34A and 34B described later. To form.

(3) Next, as shown in FIG. 2A (3), using the etching resist layer 33, the electrolytic copper plating films 31, 32 and the copper foils 2a, 3a are etched, thereby receiving blind via hole receiving land portions. Inner layer circuit patterns 34A and 34B are formed. Thereafter, the etching resist layer 33 is peeled off. In the etching in this step, for example, an etchant using cupric chloride or ferric chloride can be used.

(4) Next, as can be seen from FIG. 2B (4), a plating resist layer 35 is formed on both surfaces of the base material obtained in the previous step. The plating resist layer 35 has an opening 36b in the receiving land portion of the blind via hole, and further has an opening 36c in a region where the inner layer terminal is formed. 2B (4), the plating resist layer 35 may have an opening 36a in a region where the embedded via 6 is exposed. Whether or not the opening 36a is provided is arbitrary.

(5) Next, as shown in FIG. 2B (4), electrolytic copper exposed to the openings 36a, 36b, 36c of the plating resist layer 35 by performing electrolysis or electroless plating using the plating resist layer 35. A lid plating layer 37 (0.5 μm thickness) made of a silver plating layer is formed on the plating films 31 and 32. Thereafter, the plating resist layer 35 is peeled off. If there is a portion where the plating lead is not connected, electroless plating is performed. As can be seen from FIG. 2B (4), a silver plating layer (lid plating layer 37) serving as a terminal protective film is formed on a part of the inner layer circuit pattern serving as an inner layer terminal exposed to the opening 36c by the plating process in this step. Is formed, and the inner layer terminal 50 is completed.

  The plating layer constituting the surface layer of the lid plating layer 37 needs to have resistance to the copper etchant used in the subsequent roughening treatment. The silver plating layer satisfies this condition. Further, as the lid plating layer 37, a nickel plating layer by electroless nickel plating or a gold plating layer by electroless gold plating may be formed instead of the copper plating layer. In addition, as the lid plating layer 37, a nickel plating layer by electroless nickel plating and a gold plating layer by electroless gold plating may be sequentially formed. Thus, the lid plating layer 37 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni). The plating layer which consists of nickel etc. can be comprised individually or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the silver plating layer is formed can be obtained. The configuration of the lid plating layer 37 is selected in consideration of productivity, cost, and the connection method to the inner layer terminal.

  Through the steps so far, a double-sided circuit base material 38 shown in FIG. 2B (5) is obtained.

(6) Next, in order to improve the adhesiveness with the adhesive (adhesive layer 40 described later) used for stacking the buildup layers, the surface of the inner layer circuit patterns 34A and 34B is roughened. This roughening process can be performed in the same manner as the method described in the first embodiment.

  In the present embodiment, the lid plating layer 37 that covers the receiving land portion to be irradiated with laser light later is composed of a silver plating layer having copper etchant resistance. For this reason, the lid plating layer 37 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.

(7) Next, as shown in FIG. 2B (6), cover lays 41 are formed on the front and back surfaces of the double-sided circuit substrate 38 so as to cover the inner layer circuit patterns 34A and 34B in the component mounting portion. This cover lay 41 is formed by adhering an insulating film 39 (12 μm thick) made of, for example, a polyimide film to a double-sided circuit substrate 38 via an adhesive layer 40 made of, for example, an acrylic or epoxy adhesive. .

  The thickness of the adhesive layer 40 is determined so that the inner layer circuit pattern 34A (34B) and the lid plating layer 37 can be completely filled. Among the inner layer circuit pattern 34A (34B), the thickness of the thickest receiving land portion is 7.5 μm (copper foil 2a (3a): 5 μm, electrolytic copper plating film 31 (32): 2 μm, lid plating layer 37: 0. 5 μm). Therefore, the thickness of the adhesive layer 40 can be set to a value (8 μm) that is significantly smaller than the conventional one.

  Through the steps so far, a double-sided core substrate 42 shown in FIG. 2B (6) is obtained.

(8) Next, as can be seen from FIG. 2C (7), a single-sided copper-clad laminate having a copper foil 43b (12 μm thick) on one side of a flexible insulating base material 43a (for example, a polyimide film having a thickness of 25 μm). Prepare 43. In the same manner as in the first embodiment, a conformal mask 44 (opening) for forming blind via holes is formed in the copper foil 43b of the single-sided copper-clad laminate 43 using a photofabrication technique. .

(9) Next, as shown in FIG. 2C (7), in the same manner as in the first embodiment, the single-sided copper-clad laminate 43 on which the conformal mask 44 is formed is made of an adhesive for build-up. The adhesive layer 45 is laminated and adhered to the front and back surfaces of the double-sided core substrate 42.

(10) Next, as shown in FIG. 2C (8), the blind via holes 46A and 46B (conduction holes) are formed by performing laser processing using the conformal mask 44 in the same manner as in the first embodiment. To do.
(11) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 46A and 46B are formed.

(12) Next, as shown in FIG. 2D (9), by conducting a conductive treatment and a subsequent electrolytic copper plating treatment, the inner walls (side and bottom surfaces) of the blind via holes 46A and 46B and the lid plating layer 37 are formed. Then, an electrolytic copper plating film 47 is formed. The thickness of this electrolytic copper plating film 47 was about 15 to 20 μm in order to ensure interlayer conduction. Thereby, blind vias 48A and 48B functioning as interlayer conductive paths are formed.

(13) Next, as shown in FIG. 2D (10), the conductive layer (copper foil 43b and the electrolytic copper plating film 47 thereon) is processed into a predetermined pattern by a photofabrication technique. Then, the outer layer circuit pattern 49 is formed.

  After this, although not shown, if necessary, a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.

  Through the above steps, the build-up type multilayer printed wiring board 51 according to the second embodiment is obtained. As shown in FIG. 2D (10), the build-up type multilayer printed wiring board 51 according to the present embodiment has a stacked via structure including embedded vias 6 and blind vias 48A.

  Further, as shown in FIG. 2D (10), the build-up type multilayer printed wiring board 51 includes a component mounting part 51a in which a build-up layer is laminated on a double-sided core substrate 42, and a flexible film extending from the component mounting part 51a. Cable portion 51b. The flexible cable portion 51b is a part of the double-sided core substrate 42 that is not provided with a buildup layer. The flexible cable portion 51 b is provided with an inner layer terminal 50 exposed on the flexible insulating base material 1. A protective plating film made of the same material as the lid plating layer 37 is formed on the surface of the inner layer terminal 50. A plurality of inner layer terminals 50 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.

  In the present embodiment, the buildup layers are provided on the front and back surfaces of the double-sided core substrate 42, but the buildup layers may be provided only on one side.

  As described above, according to the present embodiment, the surface plating layer of the inner layer terminal 50 can be formed simultaneously with the formation of the lid plating layer 37. Thereby, it becomes possible to reduce the number of processes and improve productivity.

  Furthermore, according to the present embodiment, the following effects can be obtained.

  First, as in the first embodiment, by thinning the lid plating layer 37, the adhesive layer 40 of the coverlay 41 can be made much thinner than before. Thereby, the blind via holes 46A and 46B can be formed shallowly. For example, it is about 10 μm smaller than the conventional one. Thereby, the ease of electrodeposition of the electrolytic copper plating film 47 to the inner walls of the blind via holes 46A and 46B is improved. Furthermore, the influence on the blind vias 48A and 48B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced. For this reason, it is possible to reduce the thickness of the electrolytic copper plating film 47 necessary for improving yield and ensuring connection reliability. As a result, according to the present embodiment, it is possible to form a fine outer layer circuit pattern 49, and to obtain a build-up type multilayer printed wiring board 51 having a stack via structure that satisfies the requirements for high-density mounting. .

  Further, the lid plating layer 37 is provided on the receiving land portion of the blind via hole 46B that does not constitute the stacked via structure. For this reason, the structure of the blind via hole 48B (via depth and the like) is substantially the same as the blind via hole 48A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.

(Third embodiment)
Next, a build-up type multilayer printed wiring board according to the third embodiment will be described. One of the differences between the third embodiment and the second embodiment is that the coverlay is not provided inside the component mounting portion, and the boundary region between the component mounting portion of the printed wiring board and the flexible cable portion. It is to provide. As a result, there is no need to consider the flow of the adhesive filling the inner layer circuit pattern of the component mounting portion, so the options for the adhesive are expanded. Furthermore, since the thickness of the printed wiring board in the component mounting portion can be reduced, the outer layer circuit pattern can be further miniaturized.

  A method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure according to the present embodiment will be described with reference to FIGS. 3A to 3C are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.

  Since the process until obtaining the base material shown in FIG. 2A (3) of the second embodiment is the same as that of the second embodiment, the description thereof will be omitted, and the subsequent processes will be described.

(1) As shown in FIG. 3A (1), cover lays 63 are respectively formed on the front surface and the back surface of the base material in the boundary region between the region to be the component mounting portion 76a and the flexible cable portion 76b. The coverlay 63 is formed by adhering an insulating film 61 (12 μm thick) made of, for example, a polyimide film to a base material via an adhesive layer 62 (8 μm thick) made of, for example, an acrylic or epoxy adhesive. To do.

(2) Next, as can be seen from FIG. 3A (2), a plating resist layer 64 is formed in the regions to be the component mounting portions 76a on both sides of the base material obtained in the previous step. The plating resist layer 64 has an opening 65b in the receiving land portion of the blind via hole. In addition, as for the area | region in which an inner layer terminal is formed, the coverlay 63 becomes a plating resist layer so that FIG. 3A (2) may show. Further, as shown in FIG. 3A (2), the plating resist layer 64 may have an opening 65a in a region where the embedded via 6 is exposed. Whether or not the opening 65a is provided is arbitrary.

(3) Next, as shown in FIG. 3A (2), by performing electrolysis or electroless plating using the plating resist layer 64 and the coverlay 63, the openings 65a and 65b of the plating resist layer 64 are exposed. A lid plating layer 66 made of a silver plating layer (0.5 μm thick) is formed on the electrolytic copper plating films 31 and 32. Thereafter, the plating resist layer 64 is peeled off. If there is a portion where the plating lead is not connected, electroless plating is performed. As can be seen from FIG. 3A (2), a silver plating layer (lid plating layer 66) serving as a terminal protective film is also formed on the surface of the copper plating layer serving as the inner layer terminal by the plating treatment in this step, and the inner layer terminal 67 is formed. Is completed.

  The plating layer constituting the surface layer of the lid plating layer 66 needs to have resistance to the copper etchant used in the subsequent roughening treatment. The silver plating layer satisfies this condition. The lid plating layer 66 can adopt the same material and configuration as the lid plating layer 37 in the second embodiment.

  Through the steps so far, a double-sided core substrate 68 shown in FIG. 3A (3) is obtained.

(4) Next, in order to improve the adhesiveness with the adhesive (adhesive material layer 71 described later) used for stacking the buildup layers, the surface of the inner layer circuit patterns 34A and 34B is subjected to a roughening treatment. This roughening process can be performed in the same manner as the method described in the first embodiment.

  The lid plating layer 66, which is a portion to be irradiated with laser light later, is composed of a silver plating layer having copper etchant resistance, as in the first embodiment. For this reason, the lid plating layer 66 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.

(5) Next, the adhesive layer 71 filling the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion is formed. When the adhesive layer 71 is formed, the cover lay 63 functions like a dam that prevents the adhesive from flowing out from the component mounting region 76a to the flexible cable portion 76b. Therefore, in this step, an adhesive with a high flow-out can be used in addition to an adhesive with a low flow-out such as a low-flow type prepreg or a bonding sheet.

(6) Next, as shown in FIG. 3B (4), a single-sided copper-clad laminate having a copper foil 69b (12 μm thick) on one side of a flexible insulating base material 69a (for example, a polyimide film having a thickness of 25 μm). Prepare 69. In the same manner as in the first embodiment, a conformal mask 70 (opening) for forming blind via holes is formed in the copper foil 69b of the single-sided copper-clad laminate 69 using the photofabrication technique. .

(7) Next, as shown in FIG. 3B (4), the single-sided copper-clad laminate 69 with the conformal mask 70 formed on the double-sided core via an adhesive layer 71 made of an adhesive for build-up. The substrate 68 is laminated and adhered to the front and back surfaces.

(8) Next, as shown in FIG. 3B (5), in the same manner as in the first embodiment, laser processing is performed using the conformal mask 70 to form blind via holes 72A and 72B (conduction holes). To do.
(9) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 72A and 72B are formed.

(10) Next, as shown in FIG. 3C (6), by conducting a conductive treatment and a subsequent electrolytic copper plating treatment, the inner walls (side and bottom surfaces) of the blind via holes 72A and 72B and the lid plating layer 66 are formed. Then, an electrolytic copper plating film 73 is formed. The thickness of this electrolytic copper plating film 73 was about 15 to 20 μm in order to ensure interlayer conduction. Thereby, blind vias 74A and 74B functioning as interlayer conductive paths are formed.

(11) Next, as shown in FIG. 3C (7), the conductive layer (copper foil 69b and the electrolytic copper plating film 73 thereon) is processed into a predetermined pattern by a photofabrication technique. The outer layer circuit pattern 75 is formed.

  After this, although not shown, if necessary, a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.

  Through the above steps, a build-up type multilayer printed wiring board 76 according to the third embodiment is obtained. As shown in FIG. 3C (7), the build-up type multilayer printed wiring board 76 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 74A.

  As shown in FIG. 3C (7), the build-up type multilayer printed wiring board 76 includes a component mounting portion 76a in which a build-up layer is laminated on a double-sided core substrate 68, and a flexible cable extending from the component mounting portion 76a. Part 76b. The flexible cable portion 24b is a part of the double-sided core board 68 that is not provided with a buildup layer. The flexible cable portion 76 b is provided with an inner layer terminal 67 exposed on the flexible insulating base material 1. A plurality of inner layer terminals 67 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.

  Further, as shown in FIG. 3C (7), the cover lay 63 configured by sequentially laminating the adhesive layer 62 and the insulating film 61 is formed in the boundary region between the component mounting portion 76a and the flexible cable portion 76b. It is provided on the flexible insulating base material 1.

  The adhesive layer 71 fills the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion 76a. The thickness of the adhesive layer 71 needs to be equal to or greater than the thickness of the cover lay 63 and is preferably the same as the thickness of the cover lay 63.

  In the present embodiment, the buildup layers are provided on the front and back surfaces of the double-sided core substrate 68, but the buildup layers may be provided only on one side.

  As described above, in this embodiment, the coverlay 63 is provided in the boundary region between the component mounting portion 76a and the flexible cable portion 76b, and is not provided inside the component mounting portion 76a. For this reason, it is not necessary to consider the flow of the adhesive filling the inner layer circuit patterns 34A and 34B of the component mounting portion 76a to the flexible cable portion 76b. Therefore, the choice of the adhesive used for forming the adhesive layer 71 is eliminated. Spread. Furthermore, since the thickness of the printed wiring board in the component mounting portion 76a can be reduced, the blind via holes 72A and 72B can be further shallowed. As a result, according to the present embodiment, the outer layer circuit pattern 75 can be further finely formed.

  Further, similarly to the first and second embodiments, in the present embodiment, the lid plating layer 66 is provided on the receiving land portion for the blind via hole 72B that does not constitute the stacked via structure. Therefore, the structure of the blind via hole 72B (via depth, etc.) is substantially the same as the blind via hole 72A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.

  Further, as in the second embodiment, the surface plating layer of the inner layer terminal 67 can be formed simultaneously with the formation of the lid plating layer 66. Thereby, it becomes possible to reduce the number of processes and improve productivity.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the individual embodiments described above. . You may combine suitably the component covering different embodiment. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

1,101 Flexible insulating base material 2,2a, 3,3a, 102,103 Copper foil 4,104 Double-sided copper-clad laminate 5,105 Through hole 6A Conductive paste 6,106 Embedded via 7,35,64 Plating Resist layer 8a, 8b, 36a, 36b, 36c, 65a, 65b Opening 9, 37, 66, 107 Lid plating layer 9a Copper plating layer 9b Silver plating layer 10, 33 Etching resist layer 11A, 11B, 34A, 34B Inner layer circuit Pattern 12, 38 Double-sided circuit base material 13, 39, 61 Insulating film 14, 40, 62, 110 Adhesive layer 15, 41, 63, 111 Coverlay 16, 42, 68, 112 Double-sided core substrate 17, 43, 69, 113 Single-sided copper-clad laminate 17a, 43a, 69a, 113a Flexible insulating base material 17b, 43b, 69b, 113b Copper Foil 18, 44, 70 Conformal mask 19, 45, 71, 114 Adhesive layer 20A, 20B, 46A, 46B, 72A, 72B, 115A, 115B Blind via hole (conduction hole)
21, 31, 32, 47, 73 Electrolytic copper plating film 22A, 22B, 48A, 48B, 74A, 74B, 116A, 116B Blind via 23, 49, 75, 117 Outer circuit pattern 24, 51, 76, 118 Build-up type Multilayer printed wiring boards 24a, 51a, 76a, 118a Component mounting parts 24b, 51b, 76b, 118b Flexible cable parts 50, 67 Inner layer terminal 108 Receiving land part 109 Polyimide film

Claims (8)

A flexible insulating base material; inner layer circuit patterns provided on both sides of the insulating base material and having receiving land portions; and the front and back surfaces of the insulating base material passing through the insulating base material and the receiving land portions. Embedded vias that electrically connect the inner layer circuit pattern, and a material that covers the receiving land portion where the embedded via is exposed and whose surface layer is resistant to a metal etchant that constitutes the inner layer circuit pattern. A core substrate having a lid plating layer,
A build-up layer laminated on the core substrate, the outer layer circuit pattern provided on the surface layer, the blind via hole penetrating the build-up layer in the thickness direction and exposing the lid plating layer on the bottom surface A build-up layer, which is a plating film formed on an inner wall, and has a blind via that electrically connects the inner layer circuit pattern and the outer layer circuit pattern;
A build-up type multilayer printed wiring board characterized by comprising: The build-up type multilayer printed wiring board according to claim 1,
A cover lay configured as a laminate of a first adhesive layer and an insulating film sequentially, provided on the surface of the insulating base material in the boundary region between the component mounting portion and the flexible cable portion;
A second adhesive layer that fills the inner layer circuit pattern and the lid plating layer in the component mounting portion;
A build-up type multilayer printed wiring board characterized by comprising: The build-up type multilayer printed wiring board according to claim 1 or 2,
A lid plating layer made of a material that covers the receiving land portion not provided above the buried via and whose surface layer is resistant to a metal etchant constituting the inner layer circuit pattern; Build-up type multilayer printed wiring board. A build-up type multilayer printed wiring board according to any one of claims 1 to 3,
The build-up type multilayer printed wiring board, wherein the inner layer circuit pattern is made of copper, and at least a surface layer of the lid plating layer is made of silver, gold, or nickel. A build-up type multilayer printed wiring board according to any one of claims 1 to 4,
The build-up type further comprising an inner layer terminal that is disposed on the insulating base material in the flexible cable portion so as to be exposed, and has a plating layer formed of the same material as the lid plating layer on the surface. Multilayer printed wiring board. Preparing a double-sided copper-clad laminate having a flexible insulating base material, and a first copper foil and a second copper foil respectively provided on the front and back surfaces thereof;
Forming a through hole penetrating the double-sided copper-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a cover plating layer having at least a surface layer of silver, gold or nickel in a region where the embedded via is exposed and a region which is a receiving land portion of a blind via hole even if the embedded via is not exposed;
Forming a resist layer having a predetermined pattern on the first copper foil;
Etching the first copper foil using the resist layer and the lid plating layer as an etching resist to form an inner layer circuit pattern having a receiving land portion covered with the lid plating layer,
After peeling off the resist layer and subjecting the surface of the inner layer circuit pattern to a roughening treatment, an adhesive layer filling the inner layer circuit pattern and the lid plating layer is formed,
A build-up layer having a third copper foil on the surface layer is laminated on the adhesive layer,
By irradiating a predetermined position of the build-up layer with infrared laser light, penetrating the build-up layer in the thickness direction, the cover plating layer is exposed on the bottom, forming a blind via hole,
A blind for electrically connecting the conductive layer made of the third copper foil and the plating film and the inner layer circuit pattern by forming a plating film on the inner wall of the blind via hole and the third copper foil. Forming vias,
A manufacturing method of a build-up type multilayer printed wiring board characterized by the above. Preparing a double-sided copper-clad laminate having a flexible insulating base material and a first copper foil and a second copper foil on its front and back surfaces, respectively;
Forming a through hole penetrating the double-sided copper-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a copper plating film on the first copper foil and the exposed buried via;
Forming a resist layer having a predetermined pattern on the copper plating film;
By etching the copper plating film and the first copper foil using the resist layer as an etching resist, an inner layer circuit pattern having a receiving land portion of a blind via hole is formed,
Forming a lid plating layer having at least a surface layer made of silver, gold or nickel on a part of the inner layer circuit pattern to be the receiving land part and an inner layer terminal;
After performing a roughening process on the surface of the inner layer circuit pattern, an adhesive layer that fills the inner layer circuit pattern and the lid plating layer in a component mounting portion is formed,
A build-up layer having a third copper foil on the surface layer is laminated on the adhesive layer,
By irradiating a predetermined position of the build-up layer with infrared laser light, penetrating the build-up layer in the thickness direction, the cover plating layer is exposed on the bottom, forming a blind via hole,
A blind for electrically connecting the conductive layer made of the third copper foil and the plating film and the inner layer circuit pattern by forming a plating film on the inner wall of the blind via hole and the third copper foil. Forming vias,
A manufacturing method of a build-up type multilayer printed wiring board characterized by the above. Preparing a double-sided copper-clad laminate having a flexible insulating base material and a first copper foil and a second copper foil on its front and back surfaces, respectively;
Forming a through hole penetrating the double-sided copper-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a copper plating film on the first copper foil and the exposed buried via;
Forming a resist layer having a predetermined pattern on the copper plating film;
By etching the copper plating film and the first copper foil using the resist layer as an etching resist, an inner layer circuit pattern having a receiving land portion of a blind via hole is formed,
On the surface of the insulating base material in the boundary region between the component mounting portion and the flexible cable portion, a first adhesive layer and an insulating film are sequentially laminated to form a cover lay,
A cover plating layer having at least a surface layer made of silver, gold or nickel is formed on a part of the inner layer circuit pattern serving as an inner layer terminal of the receiving land portion and the flexible cable portion,
After roughening the surface of the inner layer circuit pattern, forming a second adhesive layer filling the inner layer circuit pattern and the lid plating layer in the component mounting portion,
A build-up layer having a third copper foil on the surface layer is laminated on the second adhesive layer,
By irradiating a predetermined position of the build-up layer with infrared laser light, penetrating the build-up layer in the thickness direction, the cover plating layer is exposed on the bottom, forming a blind via hole,
A blind for electrically connecting the conductive layer made of the third copper foil and the plating film and the inner layer circuit pattern by forming a plating film on the inner wall of the blind via hole and the third copper foil. Forming vias,
A manufacturing method of a build-up type multilayer printed wiring board characterized by the above.

Images