WO2011135900A1 - Build-up multilayer printed wiring board and production method therefor - Google Patents
Build-up multilayer printed wiring board and production method therefor Download PDFInfo
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- WO2011135900A1 WO2011135900A1 PCT/JP2011/053459 JP2011053459W WO2011135900A1 WO 2011135900 A1 WO2011135900 A1 WO 2011135900A1 JP 2011053459 W JP2011053459 W JP 2011053459W WO 2011135900 A1 WO2011135900 A1 WO 2011135900A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
Definitions
- the present invention relates to a build-up type multilayer printed wiring board having a stacked via structure and a method for manufacturing the same.
- a build-up type multilayer printed wiring board generally has a double-sided printed wiring board having a through hole or a multilayer printed wiring board as a core substrate, and has about one or two build-up layers on both sides or one side of the core substrate. It is provided.
- This build-up type multilayer printed wiring board is a bottomed type that electrically connects a circuit (inner layer circuit pattern) provided on a core substrate and a circuit (outer layer circuit pattern) provided on a build-up layer. Interlayer conduction part (blind via) is provided.
- This blind via is composed of a plating layer formed on the inner wall of a bottomed via hole (blind via hole) that penetrates the build-up layer and exposes the receiving land portion provided as a part of the inner circuit pattern on the bottom surface.
- This is an interlayer conductive path.
- each of the members constituting the printed wiring board is thermally expanded, so that the blind via is easily broken. Furthermore, when a plating layer is formed on the inner wall of a bottomed via hole to obtain interlayer conduction, the plating solution tends to stay at the bottom of the via hole, so that a desired plating thickness cannot be obtained. For this reason, as the depth of the blind via increases, it becomes more difficult to ensure the reliability as the interlayer conductive path.
- the thickness of the plating layer formed on the inner wall of the bottomed via hole increases, the thickness of the conductor layer formed on the buildup layer inevitably increases accordingly.
- the outer layer circuit pattern is formed by wet etching the conductor layer on the build-up layer according to a desired pattern. For this reason, it becomes difficult to miniaturize the outer layer circuit pattern as the thickness of the conductor layer on the buildup layer increases. As a result, there is a problem that it becomes difficult to satisfy the demand for high-density mounting.
- the stack via structure is a structure that electrically connects the outer layer circuit pattern and the inner layer circuit pattern on the interlayer connection portion that electrically connects the inner layer circuit patterns formed on the front surface and the back surface of the core substrate.
- This is a structure in which the interlayer connection parts are stacked.
- a method described in Patent Document 2 is known as one of methods for manufacturing a build-up type multilayer printed wiring board having a stacked via structure.
- FIG. 4 is a process cross-sectional view illustrating a method for manufacturing a conventional build-up type multilayer printed wiring board.
- a flexible double-sided copper-clad laminate 104 having a copper foil 102 and a copper foil 103 (each 12 ⁇ m thick) on both sides of a flexible insulating base material 101 (25 ⁇ m thick) made of a polyimide film is prepared. Then, as can be seen from FIG. 4A, through holes 105 ( ⁇ 100 ⁇ m) penetrating through the double-sided copper-clad laminate 104 in the thickness direction are formed using laser processing or NC drills.
- a conductive paste is filled into the through hole 105 by screen printing or the like, and then the filled conductive paste is cured to form the embedded via 106. Form.
- a lid plating layer 107 made of a copper plating film is formed on the exposed via 105 and the surrounding copper foils 102, 103 by performing an electrolytic copper plating process. ( ⁇ 200 ⁇ m, 10 ⁇ m thickness) is formed.
- the lid plating layer 107 reduces the contact resistance between the embedded via 106 and the copper foils 102 and 103, ensures the reliability of interlayer connection by the embedded via 106, and at the time of laser processing the blind via hole later. Formed to protect 106.
- the thickness of the lid plating layer 107 is determined in consideration of the resistance to the laser beam irradiated when forming the subsequent blind via hole. That is, the lid plating layer 107 needs to have a thickness that does not penetrate during laser processing.
- the copper foils 102 and 103 are processed by the photofabrication technique, and the inner layer circuit pattern having the receiving land portion 108 ( ⁇ 300 ⁇ m) having a larger diameter than the lid plating layer 107.
- the photofabrication method is a processing method for patterning a processing layer (copper foil or the like) into a predetermined pattern.
- the formation of a resist layer on the processing layer, exposure, development, It consists of a series of processes such as etching and stripping of the resist layer.
- the surface of the inner layer circuit pattern is roughened. This roughening treatment increases the absorption rate of carbon dioxide (CO 2 ) laser light (wavelength: about 9.8 ⁇ m) on the copper surface, so that the lid plating layer 107 is less resistant to laser processing.
- CO 2 carbon dioxide
- the polyimide film 109 (12 ⁇ m thickness) is adhered onto the inner layer circuit pattern via the adhesive layer 110 (25 ⁇ m thickness), and the coverlay 111 is formed.
- a cover lay 111 having a polyimide film 109 and an adhesive layer 110 formed on one side of the polyimide film 109 may be laminated on a substrate on which an inner layer circuit pattern is formed using a vacuum laminator or the like.
- the thickness of the adhesive layer 110 is determined so that the adhesive layer 110 can completely fill the lid plating layer 107 and the inner layer circuit pattern. For this reason, the greater the thickness of the lid plating layer 107, the greater the thickness of the adhesive layer 110.
- the double-sided core substrate 112 shown in FIG. 4A is obtained.
- a flexible single-sided copper-clad laminate 113 is prepared. As can be seen from FIG. 4B, an opening serving as a conformal mask is formed on the copper foil 113b of the single-sided copper-clad laminate 113 using a photofabrication technique.
- the single-sided copper clad laminate 113 has a copper foil 113b (12 ⁇ m thickness) on one side of a polyimide film 113a (thickness 25 ⁇ m).
- the single-sided copper-clad laminate 113 in which the copper foil 113 b has been processed in the previous step is laminated on both sides of the double-sided core substrate 112 via the adhesive layer 114. Glue.
- an electrolytic copper plating film is formed on the copper foil 113 b and the inner walls of the blind via holes 115 A and 115 B by conducting a conductive treatment and subsequent electrolytic copper plating treatment. To do.
- the thickness of the electrolytic copper plating film needs to be about 25 to 30 ⁇ m in order to ensure interlayer conduction.
- blind vias 116A and 116B that function as interlayer conductive paths are formed.
- the blind via 116A is stacked on the embedded via 106 of the core substrate via the lid plating layer 107, and a stacked via structure is formed.
- the blind via 116B does not constitute a stacked via structure.
- the electrolytic copper plating film formed in the previous step is processed using a photofabrication technique to form an outer layer circuit pattern 117.
- the build-up type multilayer printed wiring board 118 includes a component mounting portion 118a in which a build-up layer is laminated on the double-sided core substrate 112, and a flexible cable extending from the component mounting portion 118a. Part 118b.
- the flexible cable portion 118b is a part of the double-sided core substrate 112 that is not provided with a build-up layer.
- the lid plating layer 107 is used. It must be thickened. As the lid plating layer 107 becomes thicker, the thickness of the adhesive layer 110 that embeds the inner layer circuit pattern increases, so that the blind via holes 115A and 115B become deeper.
- the thickness of the electrolytic copper plating film formed on the blind via holes 115A and 115B and the copper foil 113b needs to be about 25 to 30 ⁇ m as described above in order to ensure the connection reliability of the blind vias 116A and 116B. .
- the total thickness of the conductor layer (copper foil 113b and electrolytic copper plating film) on the buildup layer is 37 to 42 ⁇ m, a fine outer layer circuit pattern with a pitch of about 100 ⁇ m, for example, should be formed with a high yield. Is extremely difficult in practice.
- the conventional build-up type multilayer printed wiring board having the step via structure has a problem that it cannot satisfy the demand for high-density mounting.
- the present invention has been made based on the above technical recognition, and provides a build-up type multilayer printed wiring board having a stack via structure capable of high-density mounting, and such a printed wiring board. It aims at providing the method of manufacturing cheaply and stably.
- a flexible insulating base material, an inner layer circuit pattern provided on both surfaces of the insulating base material and having receiving land portions, and the insulating base material are penetrated in the thickness direction.
- the inner layer circuit pattern and the outer layer are formed of a plating film formed on the inner wall of the blind via hole that penetrates the up layer in the thickness direction and the lid plating layer is exposed on the bottom surface.
- a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared.
- a through hole penetrating in the thickness direction is formed, and after filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and at least the surface layer is the first metal foil
- a lid plating layer made of a material resistant to the etchant is formed in a predetermined region, a resist layer having a predetermined pattern is formed on the first metal foil, and the resist layer and the lid plating layer are formed By etching the first metal foil as an etching resist, an inner layer circuit pattern having a receiving land portion covered with the lid plating layer is formed, thereby obtaining a double-sided circuit substrate.
- Method for manufacturing a preparative wiring board is provided.
- a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared, and the double-sided metal-clad laminate is After forming a through hole penetrating in the thickness direction and filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and the first metal foil and the exposed portion are exposed.
- first plating film Forming a first plating film on the embedded via, forming a resist layer having a predetermined pattern on the first plating film, and using the resist layer as an etching resist, By etching the first metal foil, an inner layer circuit pattern having a receiving land portion is formed, and at least the surface layer is made of a material having resistance to the etchant of the first metal foil.
- a plating layer is formed so as to cover the receiving land portion, thereby obtaining a double-sided circuit base material, and after roughening the surface of the inner layer circuit pattern, an insulating film and one side of the insulating film
- a layer is laminated on the double-sided core substrate via a second adhesive layer, and an infrared laser beam is irradiated to a predetermined position of the buildup layer to penetrate the buildup layer in the thickness direction.
- a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared, and the double-sided metal-clad laminate is After forming a through hole penetrating in the thickness direction and filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and the first metal foil and the exposed portion are exposed.
- a lid plating layer made of a material resistant to an etchant so as to cover the receiving land portion
- a double-sided core substrate is obtained, and the surface of the inner layer circuit pattern is subjected to a roughening treatment
- a build-up layer having a second metal foil on the surface is laminated on the double-sided core substrate in the component mounting portion via a second adhesive layer having a thickness equal to or greater than the thickness of the coverlay, and the build By irradiating infrared laser light at a predetermined position of the up layer, the build-up layer penetrates in the thickness direction, and a blind via hole in which the lid plating layer is exposed on the bottom surface is formed, A build that forms a blind via that electrically connects the second metal foil and the inner layer circuit pattern by forming a
- the present invention has the following effects.
- the build-up type multilayer printed wiring board according to the present invention has a lid plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern at a receiving land portion of a blind via hole. Since this lid plating layer has high resistance to infrared lasers, the thickness of the lid plating layer can be greatly reduced. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the buildup layer can be shallowed. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and the outer circuit pattern can be miniaturized. Therefore, the build-up type multilayer printed wiring board having the stacked via structure according to the present invention can satisfy the demand for high-density mounting.
- a cover plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern is formed on the receiving land portion of the build-up via hole.
- this lid plating layer has high resistance to infrared lasers, it can be formed significantly thinner. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the build-up layer can be formed shallow. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and a fine outer layer circuit pattern can be formed. Furthermore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same, so that productivity can be improved.
- FIGS. 1A to 1D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
- a direct laser processing method in which the resin (flexible insulating base material 1) is directly processed with a laser beam can be selected.
- a direct laser processing method that does not require a copper foil etching step by a photofabrication method was selected.
- the through-hole 5 is filled with the conductive paste 6A by screen printing or the like, and then the filled conductive paste 6A is cured.
- the conductive paste 6A preferably has a low volume resistivity and does not require a conductive treatment when a lid plating layer 9 described later is formed.
- AE1244 volume resistivity: 5 ⁇ 10 ⁇ 5 ⁇ ⁇ cm
- Tatsuta Electronics Co., Ltd. was used. In this step, as shown in FIG.
- the upper and lower portions of the through-hole 5 are filled until the conductive paste 6A overflows so that voids or the like do not occur in the through-hole 5 due to the lack of the conductive paste. It is preferable to do.
- the conductive paste is filled in the through hole instead of the blind via hole, the printing machine used in this process does not need to be a vacuum type and has a differential pressure enough to adsorb the double-sided copper clad laminate 4. As long as it has a mechanism capable of generating
- both surfaces of the double-sided copper clad laminate 4 in which the conductive paste 6A is filled in the through-hole 5 shown in FIG. 1A (2) are mechanically polished by a belt sander or a roll buff, or chemical mechanically polished (CMP : Polishing by Chemical Mechanical Polishing).
- CMP chemical mechanically polished by Chemical Mechanical Polishing
- the excess conductive paste 6A protruding from the through hole 5 is scraped, and the buried via 6 is formed.
- the copper foil 2 and the copper foil 3 are also shaved by polishing in this step, and the copper foil 2 and the copper foil 3 become a copper foil 2a and a copper foil 3a having a thickness of about 5 ⁇ m, respectively.
- the double-sided copper-clad laminate 4 is bonded to a hard substrate (several mm thick) via an adhesive sheet before polishing. ) Etc. and then polishing. By doing in this way, the polisher for hard substrates can be used.
- the double-sided copper-clad laminate 4 is adsorbed and held on a flat plate, the surface opposite to the adsorption surface is polished, and then the double-sided copper-clad laminate 4 is turned over and polished. This surface may be adsorbed on a flat plate, and the unpolished surface may be polished.
- a plating resist layer 7 is formed on each of the copper foil 2a and the copper foil 3a.
- This plating resist layer 7 has an opening 8a in a region where the embedded via 6 is exposed, and further has an opening 8b in a region which becomes a receiving land portion of a blind via hole without the embedded via 6.
- the diameters of the openings 8a and 8b are preferably determined in consideration of the diameter of the blind via hole and the alignment accuracy when forming the blind via hole. Here, it is set to ⁇ 200 ⁇ m.
- the lid plating layer 9 is formed in the openings 8a and 8b of the plating resist layer 7.
- the lid plating layer 9 is formed as follows. First, electrolytic copper plating is performed to form a copper plating layer 9a having a thickness of 2 ⁇ m on the bottom surfaces of the openings 8a and 8b. Thereafter, electroless silver plating is performed to form a silver plating layer 9b having a thickness of 0.5 ⁇ m on the copper plating layer 9a. This series of plating processes is performed with the plating resist layer 7 left.
- the lid plating layer 9 is not limited to the above configuration.
- a nickel plating layer by electroless nickel plating may be formed instead of the copper plating layer 9a.
- the plating layer constituting the surface layer of the lid plating layer 9 needs to have resistance to copper etchant (may be selective etching to copper).
- a gold plating layer by electroless gold plating or a nickel plating layer by electroless nickel plating may be formed instead of the silver plating layer 9b.
- a nickel plating layer and a gold plating layer may be sequentially formed on the copper plating layer 9a.
- the cover plating layer 9 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni).
- a plating layer made of nickel, copper, or the like can be configured singly or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the lid plating layer 9 composed of the copper plating layer 9a and the silver plating layer 9b is formed can be obtained.
- the configuration of the lid plating layer 9 is selected in consideration of productivity and cost.
- FIGS. 1B (5) and (6) Next, after the plating resist layer 7 is peeled off, as shown in FIGS. 1B (5) and (6), an etching resist having a predetermined pattern for forming inner layer circuit patterns 11A and 11B described later.
- the layer 10 is formed on the copper foils 2a and 2b.
- FIG. 1B (5) is a cross-sectional view taken along the line A-A 'of FIG. 1B (6). That is, FIG. 1B (6) is a view of the base material shown in FIG. 1B (5) as viewed from above.
- a dry film resist about 10 ⁇ m thick
- the lid plating layer 9 can be filled.
- the lid plating layer 9 functions as an etching resist during circuit pattern etching, it is not necessary to provide an etching resist layer for protecting the lid plating layer 9 as shown in FIGS. 1B (5) and (6). . Therefore, the shape of the lid plating layer 9 can be used as it is as the shape of the receiving land portion of the blind via hole without using an exposure machine capable of highly accurate alignment. This improves productivity and contributes to the manufacture of an inexpensive printed wiring board.
- the copper foil 2a and the copper foil 3a are etched using the etching resist layer 10 and the lid plating layer 9 as an etching resist, thereby providing flexible insulation.
- the inner layer circuit pattern 11A and the inner layer circuit pattern 11B are formed on the front surface and the back surface of the base material 1, respectively. Thereafter, the etching resist layer 10 is peeled off.
- the inner layer circuit patterns 11 ⁇ / b> A and 11 ⁇ / b> B have blind via hole receiving land portions covered with the cover plating layer 9.
- the etchant used in this step is one that etches the copper foils 2a and 3a but does not damage the lid plating layer 9 (silver plating layer 9b).
- an etchant using cupric chloride or ferric chloride can be used as such an etchant.
- the etching in this step is performed as selective etching using, for example, an ammonia-based alkali etchant.
- the double-sided circuit substrate 12 shown in FIG. 1B (7) is obtained.
- Inner layer circuit patterns 11A and 11B having receiving land portions are formed on the double-sided circuit substrate 12, and the embedded via 6 electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B.
- the lid plating layer 9 also has a function of reducing the contact resistance between the embedded via 6 and the copper foils 2 and 3 and ensuring the reliability of the embedded via 6 as an interlayer connection path.
- the surface of the inner layer circuit patterns 11A and 11B is subjected to a roughening process.
- the roughening process was performed using the multi bond 150 of Nippon Macder Mid Co., Ltd.
- the roughening treatment improves the adhesion between the copper foils 2a and 3a and the adhesive, but increases the absorption rate of the carbon dioxide laser light in the copper foils 2a and 3a.
- a silver plating layer 9b having copper etchant resistance is formed on the surface layer of the lid plating layer 9 covering the receiving land portion of the blind via hole. For this reason, the lid plating layer 9 is not roughened by the roughening treatment in this step, and the absorption rate of the carbon dioxide laser light in the receiving land portion does not increase.
- the absorption rate of the carbon dioxide laser beam was measured before and after the roughening treatment, the absorption rate increased from about 20% to about 30% on the surfaces of the copper foils 2a and 3a, but on the surface of the silver plating layer 9b. There was no increase in absorption.
- the thickness of the copper plating layer 9a and the copper foil 2a (3a) under the silver plating layer 9b is not reduced by the irradiation of the carbon dioxide laser beam, the resistance to thermal damage caused by laser processing is sufficiently ensured. Yes. Since the silver plating layer 9b hardly absorbs infrared laser light before this step (roughening treatment), the resistance of the lid plating layer 9 to the infrared laser light is maintained sufficiently high after the roughening treatment in this step. .
- a coverlay 15 having an insulating film 13 (for example, 12 ⁇ m thick) made of polyimide or the like and an adhesive layer 14 formed on one surface of the insulating film 13 is prepared.
- the adhesive layer 14 is made of an adhesive such as acrylic or epoxy.
- the lamination process which affixes the coverlay 15 to the double-sided circuit base material 12 using a vacuum laminator etc. is performed.
- the inner layer circuit patterns 11 A and 11 B and the cover plating layer 9 are filled with the adhesive layer 14.
- the insulating layer 13 may be formed on the adhesive layer 14 after forming the adhesive layer 14 filling the inner layer circuit pattern with the structures 11A and 11B and the lid plating layer 9.
- the thickness of the adhesive layer 14 is determined so that the inner layer circuit pattern 11A (11B) and the lid plating layer 9 can be completely filled.
- the thickest portion of the inner layer circuit pattern 11A (11B) is a receiving land portion of the blind via hole.
- the thickness of the receiving land portion is 7.5 ⁇ m (copper foil 2a (3a): 5 ⁇ m, lid plating layer 9: 2.5 ⁇ m), which is smaller than the conventional one due to the thinning of the lid plating layer 9. Therefore, the thickness of the adhesive layer 14 can be set to a value (8 ⁇ m) that is significantly smaller than the conventional one.
- the single-sided copper-clad laminate 17 on which the conformal mask 18 is formed is bonded to the double-sided core via an adhesive layer 19 made of an adhesive for building up.
- the substrate 16 is laminated and adhered.
- the adhesive used here is a flow-out such as a low-flow type prepreg or a bonding sheet so that the adhesive does not flow out to the flexible cable portion (double-sided core substrate 16 not covered with the single-sided copper-clad laminate 17). Those with less are preferred. Even if the single-sided copper clad laminate 17 having the unprocessed copper foil 17b is bonded to the double-sided core substrate 16 through the adhesive layer 19, the copper foil 17b is processed to form the conformal mask 18. Good.
- the diameter of the conformal mask 18 was set to 120 ⁇ m, which is 80 ⁇ m smaller than the diameter 200 ⁇ m of the receiving land portion of the blind via hole (the cover plating layer 9). Therefore, the conformal mask 18 may be formed by a technique that can obtain an alignment accuracy of ⁇ 40 ⁇ m.
- this alignment method for example, there are the following two methods.
- the first method is a method in which the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16 after the conformal mask 18 is formed.
- target marks are formed in advance on the double-sided core substrate 16. Then, after aligning the single-sided copper-clad laminate 17 using this target mark, the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16.
- the second method is a method in which the conformal mask 18 is formed after the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16.
- target marks are formed in advance on the double-sided core substrate 16.
- the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16 to form a resist layer on the copper foil 17b.
- the double-sided core substrate 16 and the photomask are aligned using the mark indicating the reference position provided on the photomask for exposure and the target mark of the double-sided core substrate 16.
- the resist layer is exposed and developed to form a conformal mask 18 at a predetermined position on the copper foil 17b.
- the details of the laser processing in this step will be described.
- the carbon dioxide laser processing machine ML605GTXIII-5100U2 manufactured by Mitsubishi Electric Corporation was used.
- the laser beam diameter was adjusted to 200 ⁇ m with a predetermined aperture or the like, the laser irradiation position was adjusted, and then 5 shots of laser pulses with a pulse width of 10 ⁇ Sec and a pulse energy of 5 mJ were irradiated to form blind via holes 20A and 20B.
- the thickness of the lid plating layer 9 is as thin as 2.5 ⁇ m, the absorption of the carbon dioxide laser beam of the silver plating layer 9 b is small, so that the laser beam penetrates the lid plating layer 9 or the lid plating layer 9 extends from the embedded via 6.
- Laser processing can be performed without peeling.
- a conductive layer on the flexible insulating base material 17a (copper foil 17b and the electrolytic copper plating film 21 thereon) is formed in a predetermined manner by a photofabrication technique.
- the outer layer circuit pattern 23 is formed by processing into a pattern.
- a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
- the double-sided core substrate 16 of the build-up type multilayer printed wiring board 24 includes a flexible insulating base material 1 and inner layer circuit patterns 11A and 11B provided on both surfaces of the flexible insulating base material 1 and having receiving land portions, An embedded via 6 that penetrates the flexible insulating base material 1 and the receiving land portion and electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B is provided. Further, a cover plating layer 9 made of a material that covers the receiving land portion where the embedded via 6 is exposed and whose surface layer is resistant to the metal etchant constituting the inner layer circuit patterns 11A and 11B is provided.
- a buildup layer having an outer layer circuit pattern 23 provided on the surface is laminated via an adhesive layer 19.
- the blind vias 22A and 22B are made of a plating film formed on the inner walls of the blind via holes 20A and 20B that penetrate the build-up layer in the thickness direction and the cover plating layer 9 is exposed on the bottom surface.
- the circuit patterns 11A and 11B and the outer layer circuit pattern 23 are electrically connected.
- the blind via 22A is arranged so as to overlap the embedded via 6 with the lid plating layer 9 interposed therebetween.
- the build-up type multilayer printed wiring board 24 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 22A.
- the build-up type multilayer printed wiring board 24 includes a component mounting portion 24a in which a build-up layer is laminated on the double-sided core substrate 16, and a flexible cable extending from the component mounting portion 24a. Part 24b.
- the flexible cable portion 24b is a part of the double-sided core substrate 16 where the buildup layer is not provided.
- the flexible cable portion 24b is not an essential component and may not be provided.
- the buildup layers are provided on the front and back surfaces of the double-sided core substrate 16, but the buildup layers may be provided only on one side.
- the lid plating layer 9 is formed in the region that becomes the receiving land portion of the blind via holes 20A and 20B that penetrate the build-up layer.
- the surface layer of the lid plating layer 9 is composed of a plating layer (silver plating layer 9b or the like) resistant to a copper etchant.
- the adhesive layer 14 of the coverlay 15 can be thinned.
- the blind via holes 20A and 20B can be formed shallowly. For example, it is about 10 ⁇ m smaller than the conventional one.
- membrane 21 with respect to the inner wall of blind via-hole 20A, 20B improves.
- the influence on the blind vias 22A and 22B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced.
- the adhesive constituting the adhesive layer 14 has a particularly large coefficient of thermal expansion, so that the effect of making the adhesive layer 14 thinner is great.
- the lid plating layer 9 has copper etchant resistance, it is not necessary to provide a resist layer for protecting the lid plating layer 9.
- covered with the lid plating layer 9 can be made the same as the lid plating layer 9, and densification of an inner-layer circuit pattern can be carried out. Can be planned.
- productivity can be improved and a printed wiring board can be manufactured at low cost.
- a lid plating layer 9 is provided on the receiving land portion of the blind via hole 20B that does not constitute a stacked via structure. Therefore, the structure of the blind via hole 20B (via depth and the like) is substantially the same as the blind via hole 20A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to the present embodiment, a large processing margin can be ensured and productivity can be improved.
- the build-up type multilayer printed wiring board according to the second embodiment has an inner layer terminal on the flexible insulating base material in the flexible cable portion.
- the plating layer that protects the surface of the inner layer terminal is formed in the same plating step as the lid plating layer formed on the embedded via and the receiving land portion.
- FIGS. 2A to 2D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
- electrolytic copper plating treatment is performed on both surfaces of the base material, and electrolytic copper plating films 31 and 32 (respectively on the copper foils 2a and 3a and the exposed embedded via 6) 2 ⁇ m thick).
- an etching resist layer 33 having a predetermined pattern is formed on the electrolytic copper plating films 31 and 32 to form inner layer circuit patterns 34A and 34B described later. To form.
- a plating resist layer 35 is formed on both surfaces of the base material obtained in the previous step.
- the plating resist layer 35 has an opening 36b in the receiving land portion of the blind via hole, and further has an opening 36c in a region where the inner layer terminal is formed.
- the plating resist layer 35 may have an opening 36a in a region where the embedded via 6 is exposed. Whether or not the opening 36a is provided is arbitrary.
- the plating layer constituting the surface layer of the lid plating layer 37 needs to have resistance to the copper etchant used in the subsequent roughening treatment.
- the silver plating layer satisfies this condition.
- a nickel plating layer by electroless nickel plating or a gold plating layer by electroless gold plating may be formed instead of the copper plating layer.
- a nickel plating layer by electroless nickel plating and a gold plating layer by electroless gold plating may be sequentially formed.
- the lid plating layer 37 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni).
- the plating layer which consists of nickel etc. can be comprised individually or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the silver plating layer is formed can be obtained.
- the configuration of the lid plating layer 37 is selected in consideration of productivity, cost, and the connection method to the inner layer terminal.
- the surface of the inner layer circuit patterns 34A and 34B is roughened. This roughening process can be performed in the same manner as the method described in the first embodiment.
- the lid plating layer 37 that covers the receiving land portion to be irradiated with laser light later is composed of a silver plating layer having copper etchant resistance. For this reason, the lid plating layer 37 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.
- a cover lay 41 having an insulating film 39 (for example, 12 ⁇ m thick) made of polyimide or the like and an adhesive layer 40 formed on one surface of the insulating film 39 is prepared.
- the adhesive layer 40 is made of an adhesive such as acrylic or epoxy.
- the lamination process which affixes the coverlay 41 to the double-sided circuit base material 38 is performed using a vacuum laminator etc.
- the inner layer circuit patterns 34 A and 34 B and the lid plating layer 37 in the component mounting portion are filled with the adhesive layer 40.
- the insulating layer 39 may be formed on the adhesive layer 40 after forming the adhesive layer 40 filling the inner layer circuit pattern with the structures 34 ⁇ / b> A and 34 ⁇ / b> B and the lid plating layer 37.
- the thickness of the adhesive layer 40 is determined so that the inner layer circuit pattern 34A (34B) and the lid plating layer 37 can be completely filled.
- the thickness of the thickest receiving land portion is 7.5 ⁇ m (copper foil 2a (3a): 5 ⁇ m, electrolytic copper plating film 31 (32): 2 ⁇ m, lid plating layer 37: 0. 5 ⁇ m). Therefore, the thickness of the adhesive layer 40 can be set to a value (8 ⁇ m) that is significantly smaller than the conventional one.
- a conformal mask 44 (opening) for forming blind via holes is formed in the copper foil 43b of the single-sided copper-clad laminate 43 using a photofabrication technique. .
- the single-sided copper-clad laminate 43 on which the conformal mask 44 is formed is made of an adhesive for build-up.
- the adhesive layer 45 is laminated and adhered to the front and back surfaces of the double-sided core substrate 42.
- the blind via holes 46A and 46B are formed by performing laser processing using the conformal mask 44 in the same manner as in the first embodiment. To do. (11) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 46A and 46B are formed.
- the conductive layer on the build-up layer (copper foil 43b and electrolytic copper plating film 47 thereon) is processed into a predetermined pattern by a photofabrication technique.
- the outer layer circuit pattern 49 is formed.
- a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
- the build-up type multilayer printed wiring board 51 according to the second embodiment is obtained.
- the build-up type multilayer printed wiring board 51 according to the present embodiment has a stacked via structure including embedded vias 6 and blind vias 48A.
- the build-up type multilayer printed wiring board 51 includes a component mounting part 51a in which a build-up layer is laminated on a double-sided core substrate 42, and a flexible film extending from the component mounting part 51a. Cable portion 51b.
- the flexible cable portion 51b is a part of the double-sided core substrate 42 that is not provided with a buildup layer.
- the flexible cable portion 51 b is provided with an inner layer terminal 50 exposed on the flexible insulating base material 1.
- a protective plating film made of the same material as the lid plating layer 37 is formed on the surface of the inner layer terminal 50.
- a plurality of inner layer terminals 50 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.
- the buildup layers are provided on the front and back surfaces of the double-sided core substrate 42, but the buildup layers may be provided only on one side.
- the surface plating layer of the inner layer terminal 50 can be formed simultaneously with the formation of the lid plating layer 37. Thereby, it becomes possible to reduce the number of processes and improve productivity.
- the adhesive layer 40 of the cover lay 41 can be made much thinner than before.
- the blind via holes 46A and 46B can be formed shallowly. For example, it is about 10 ⁇ m smaller than the conventional one.
- the ease of electrodeposition of the electrolytic copper plating film 47 to the inner walls of the blind via holes 46A and 46B is improved.
- the influence on the blind vias 48A and 48B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced. For this reason, it is possible to reduce the thickness of the electrolytic copper plating film 47 necessary for improving yield and ensuring connection reliability.
- a lid plating layer 37 is provided on the receiving land portion of the blind via hole 46B that does not constitute a stacked via structure.
- the structure of the blind via hole 48B (via depth and the like) is substantially the same as the blind via hole 48A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.
- FIGS. 3A to 3C are process cross-sectional views illustrating the method for manufacturing the build-up type multilayer printed wiring board according to the present embodiment.
- a coverlay 63 having an insulating film 61 (for example, 12 ⁇ m thick) made of polyimide or the like and an adhesive layer 62 (for example, 8 ⁇ m thick) formed on one surface of the insulating film 61 is prepared.
- the adhesive layer 62 is made of an adhesive such as acrylic or epoxy.
- the double-sided circuit base material inner circuit pattern 34A, 34B was formed in the boundary area
- the insulating film 61 may be formed on the adhesive layer 62.
- a plating resist layer 64 is formed in the regions to be the component mounting portions 76a on both sides of the base material obtained in the previous step.
- the plating resist layer 64 has an opening 65b in the receiving land portion of the blind via hole.
- the coverlay 63 becomes a plating resist layer so that FIG. 3A (2) may show.
- the plating resist layer 64 may have an opening 65a in a region where the embedded via 6 is exposed. Whether or not the opening 65a is provided is arbitrary.
- a silver plating layer (lid plating layer 66) serving as a terminal protective film is also formed on the surface of the copper plating layer serving as the inner layer terminal by the plating treatment in this step, and the inner layer terminal 67 is formed. Is completed.
- the plating layer constituting the surface layer of the lid plating layer 66 needs to have resistance to the copper etchant used in the subsequent roughening treatment.
- the silver plating layer satisfies this condition.
- the lid plating layer 66 can adopt the same material and configuration as the lid plating layer 37 in the second embodiment.
- the surface of the inner layer circuit patterns 34A and 34B is subjected to a roughening treatment.
- This roughening process can be performed in the same manner as the method described in the first embodiment.
- the lid plating layer 66 which is a portion to be irradiated with laser light later, is composed of a silver plating layer having copper etchant resistance, as in the first embodiment. For this reason, the lid plating layer 66 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.
- the adhesive layer 71 filling the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion is formed.
- the cover lay 63 functions like a dam that prevents the adhesive from flowing out from the component mounting region 76a to the flexible cable portion 76b. Therefore, in this step, an adhesive with a high flow-out can be used in addition to an adhesive with a low flow-out such as a low-flow type prepreg or a bonding sheet.
- a conformal mask 70 opening for forming blind via holes is formed in the copper foil 69b of the single-sided copper-clad laminate 69 using the photofabrication technique. .
- the substrate 68 is laminated and adhered to the front and back surfaces.
- blind via holes 72A and 72B conduction holes.
- a desmear process is performed in order to remove the resin residue generated when the blind via holes 72A and 72B are formed.
- the conductive layer (copper foil 69b and the electrolytic copper plating film 73 thereon) is processed into a predetermined pattern by a photofabrication technique.
- the outer layer circuit pattern 75 is formed.
- a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
- the build-up type multilayer printed wiring board 76 according to the third embodiment is obtained.
- the build-up type multilayer printed wiring board 76 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 74A.
- the build-up type multilayer printed wiring board 76 includes a component mounting portion 76a in which a build-up layer is laminated on a double-sided core substrate 68, and a flexible cable extending from the component mounting portion 76a. Part 76b.
- the flexible cable portion 24b is a part of the double-sided core board 68 that is not provided with a buildup layer.
- the flexible cable portion 76 b is provided with an inner layer terminal 67 exposed on the flexible insulating base material 1.
- a plurality of inner layer terminals 67 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.
- the cover lay 63 configured by sequentially laminating the adhesive layer 62 and the insulating film 61 is formed in the boundary region between the component mounting portion 76a and the flexible cable portion 76b. It is provided on the flexible insulating base material 1.
- the adhesive layer 71 is filled with the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion 76a.
- the thickness of the adhesive layer 71 needs to be equal to or greater than the thickness of the cover lay 63 and is preferably the same as the thickness of the cover lay 63.
- the buildup layers are provided on the front and back surfaces of the double-sided core substrate 68, but the buildup layers may be provided only on one side.
- the coverlay 63 is provided in the boundary region between the component mounting portion 76a and the flexible cable portion 76b, and is not provided inside the component mounting portion 76a. For this reason, it is not necessary to consider the flow of the adhesive filling the inner layer circuit patterns 34A and 34B of the component mounting portion 76a to the flexible cable portion 76b. Therefore, the choice of the adhesive used for forming the adhesive layer 71 is eliminated. Spread. Furthermore, since the thickness of the printed wiring board in the component mounting portion 76a can be reduced, the blind via holes 72A and 72B can be further shallowed. As a result, according to the present embodiment, the outer layer circuit pattern 75 can be further finely formed.
- the lid plating layer 66 is provided on the receiving land portion of the blind via hole 72B that does not constitute the stacked via structure. Therefore, the structure of the blind via hole 72B (via depth, etc.) is substantially the same as the blind via hole 72A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.
- the surface plating layer of the inner layer terminal 67 can be formed simultaneously with the formation of the lid plating layer 66. Therefore, it becomes possible to reduce the number of processes and improve productivity.
- the wiring pattern and the plating film are made of copper.
- the present invention is not limited to this, and other metals such as aluminum and silver may be used.
- a coverlay is laminated on a substrate on which an inner layer circuit pattern is formed to produce a double-sided core substrate, and then a build-up layer is laminated and adhered to the double-sided core substrate,
- the build-up layer may be laminated directly on the substrate via an adhesive layer filling the inner layer circuit pattern and the lid plating layer.
- a coverlay having a copper foil on the surface can be used.
- FIG. 5A shows a cover having the double-sided circuit substrate 12 described in the first embodiment (see FIG.
- FIG. 5B shows a cover having the double-sided circuit substrate 38 described in the second embodiment (see FIG. 2B (5)) having a copper foil 41a and an adhesive layer 40 on the front and back surfaces of the insulating film 39, respectively. It is sectional drawing which shows the state which laminated
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Abstract
In order to provide a method for inexpensively and stably producing build-up multilayer printed circuit boards having a stacked via structure allowing high-density mounting, a build-up multilayer printed circuit board is provided with: a flexible insulating base material (1); inner-layer circuit patterns (11A, 11B) formed on both sides of the insulating base material (1); and a double-sided core substrate (16). Said double-sided core substrate (16) comprises: an embedded via (6) that passes through the insulating base material (1) and is electrically connected to the inner circuit patterns (11A and 11B); and a cover plating layer (9) that covers the receiving land sections of the inner layer circuit patterns (11A, 11B) exposed by the embedded via (6), and the surface layer of which comprises gold, silver or nickel. The build-up multilayer printed circuit board is further provided with a build-up layer laminated on the double-sided core substrate (16). The build-up layer comprises an outer layer circuit pattern (23) on the surface layer, and a blind via (22A) that is electrically connected to the outer layer circuit pattern (23) and the inner-layer circuit pattern (11A). The blind via (22A) constitutes the embedded via (6) and a stack via structure.
Description
本発明は、スタックビア構造を有するビルドアップ型多層プリント配線板、及びその製造方法に関する。
The present invention relates to a build-up type multilayer printed wiring board having a stacked via structure and a method for manufacturing the same.
近年、電子機器の小型化および高機能化がますます進展しており、プリント配線板に対する高密度実装の要求が高まっている。高密度実装が可能なプリント配線板を実現するために、微細な回路配線パターンを設けることが可能なビルドアップ型多層プリント配線板が知られている(例えば、特許文献1参照)。
In recent years, miniaturization and higher functionality of electronic devices have been further advanced, and the demand for high-density mounting on printed wiring boards has increased. In order to realize a printed wiring board capable of high-density mounting, a build-up type multilayer printed wiring board capable of providing a fine circuit wiring pattern is known (for example, see Patent Document 1).
ビルドアップ型多層プリント配線板は、一般的には、スルーホールを有する両面プリント配線板若しくは多層プリント配線板をコア基板とし、このコア基板の両面若しくは片面に1~2層程度のビルドアップ層を設けたものである。このビルドアップ型多層プリント配線板は、コア基板上に設けられた回路(内層回路パターン)と、ビルドアップ層上に設けられた回路(外層回路パターン)とを電気的に接続する有底型の層間導通部(ブラインドビア)を備える。このブラインドビアは、ビルドアップ層を貫通し、底面に内層回路パターンの一部として設けられた受けランド部が露出した有底型のビアホール(ブラインドビアホール)の内壁に形成されためっき層から構成される層間導電路である。
A build-up type multilayer printed wiring board generally has a double-sided printed wiring board having a through hole or a multilayer printed wiring board as a core substrate, and has about one or two build-up layers on both sides or one side of the core substrate. It is provided. This build-up type multilayer printed wiring board is a bottomed type that electrically connects a circuit (inner layer circuit pattern) provided on a core substrate and a circuit (outer layer circuit pattern) provided on a build-up layer. Interlayer conduction part (blind via) is provided. This blind via is composed of a plating layer formed on the inner wall of a bottomed via hole (blind via hole) that penetrates the build-up layer and exposes the receiving land portion provided as a part of the inner circuit pattern on the bottom surface. This is an interlayer conductive path.
しかし、ブラインドビアの深さが増すにつれて、次のような問題が生じる。まず、プリント配線板を構成する部材の各々が熱膨張することによって、ブラインドビアが破壊され易くなる。さらに、層間導通を得るために有底型のビアホールの内壁にめっき層を形成する際、めっき液がビアホールの底部に滞留し易くなるため、所望のめっき厚が得られない。このような理由から、ブラインドビアの深さが増すほど、その層間導電路としての信頼性を確保することが困難となる。
However, the following problems arise as the depth of the blind via increases. First, each of the members constituting the printed wiring board is thermally expanded, so that the blind via is easily broken. Furthermore, when a plating layer is formed on the inner wall of a bottomed via hole to obtain interlayer conduction, the plating solution tends to stay at the bottom of the via hole, so that a desired plating thickness cannot be obtained. For this reason, as the depth of the blind via increases, it becomes more difficult to ensure the reliability as the interlayer conductive path.
上記の問題の対策として、有底型のビアホールの内壁に十分厚くめっき層を形成することが考えられる。しかし、有底型のビアホールの内壁に形成されるめっき層の厚みが増すと、それに応じて、ビルドアップ層上に形成される導体層の厚みも大きくなることが避けられない。外層回路パターンは、ビルドアップ層上の導体層を所望のパターンに従ってウェットエッチングすることにより形成される。このため、ビルドアップ層上の導体層の厚みが増すにつれて、外層回路パターンを微細化することが困難となる。その結果、高密度実装の要求を満足することが困難になるという問題がある。
As a countermeasure against the above problem, it is conceivable to form a sufficiently thick plating layer on the inner wall of the bottomed via hole. However, as the thickness of the plating layer formed on the inner wall of the bottomed via hole increases, the thickness of the conductor layer formed on the buildup layer inevitably increases accordingly. The outer layer circuit pattern is formed by wet etching the conductor layer on the build-up layer according to a desired pattern. For this reason, it becomes difficult to miniaturize the outer layer circuit pattern as the thickness of the conductor layer on the buildup layer increases. As a result, there is a problem that it becomes difficult to satisfy the demand for high-density mounting.
ところで、ビルドアップ型多層プリント配線板のうち、特に、スタックビア構造を有するビルドアップ型多層プリント配線板が、高密度化および設計自由度の向上の観点から求められている。ここで、スタックビア構造とは、コア基板の表面及び裏面に形成された内層回路パターン同士を電気的に接続する層間接続部の上に、外層回路パターンと内層回路パターンを電気的に接続する別の層間接続部を重ねて配置した構造をいう。従来、スタックビア構造を有するビルドアップ型多層プリント配線板の製造方法の一つとして、特許文献2に記載の方法が知られている。
By the way, among the build-up type multilayer printed wiring boards, in particular, a build-up type multilayer printed wiring board having a stack via structure is required from the viewpoint of increasing the density and improving the design flexibility. Here, the stack via structure is a structure that electrically connects the outer layer circuit pattern and the inner layer circuit pattern on the interlayer connection portion that electrically connects the inner layer circuit patterns formed on the front surface and the back surface of the core substrate. This is a structure in which the interlayer connection parts are stacked. Conventionally, a method described in Patent Document 2 is known as one of methods for manufacturing a build-up type multilayer printed wiring board having a stacked via structure.
次に、従来技術の問題点を明確にするために、図4を用いて、スタックビア構造を有する従来のビルドアップ型多層プリント配線板の製造方法を説明する。図4は、従来のビルドアップ型多層プリント配線板の製造方法を示す工程断面図である。
Next, in order to clarify the problems of the prior art, a manufacturing method of a conventional build-up type multilayer printed wiring board having a stack via structure will be described with reference to FIG. FIG. 4 is a process cross-sectional view illustrating a method for manufacturing a conventional build-up type multilayer printed wiring board.
(1)ポリイミドフィルムからなる可撓性絶縁ベース材101(25μm厚)の両面に、銅箔102及び銅箔103(各々12μm厚)を有する、可撓性の両面銅張積層板104を準備する。そして、図4(1)からわかるように、レーザ加工又はNCドリル等を用いて、この両面銅張積層板104を厚さ方向に貫通するスルーホール105(φ100μm)を形成する。
(1) A flexible double-sided copper-clad laminate 104 having a copper foil 102 and a copper foil 103 (each 12 μm thick) on both sides of a flexible insulating base material 101 (25 μm thick) made of a polyimide film is prepared. . Then, as can be seen from FIG. 4A, through holes 105 (φ100 μm) penetrating through the double-sided copper-clad laminate 104 in the thickness direction are formed using laser processing or NC drills.
(2)次に、図4(1)からわかるように、スクリーン印刷法等によりスルーホール105の内部に導電性ペーストを充填し、その後、充填した導電性ペーストを硬化させて、埋め込みビア106を形成する。
(2) Next, as can be seen from FIG. 4 (1), a conductive paste is filled into the through hole 105 by screen printing or the like, and then the filled conductive paste is cured to form the embedded via 106. Form.
(3)次に、図4(1)からわかるように、電解銅めっき処理を施すことにより、露出したビア105とその周辺の銅箔102,103上に、銅めっき皮膜からなる蓋めっき層107(φ200μm,10μm厚)を形成する。この蓋めっき層107は、埋込みビア106と銅箔102,103との接触抵抗を低減し、埋込みビア106による層間接続の信頼性を確保するとともに、後のブラインドビアホールをレーザ加工する際に埋込みビア106を保護するために形成される。なお、蓋めっき層107の厚みは、後のブラインドビアホールを形成する際に照射されるレーザ光に対する耐性を考慮して決められる。即ち、蓋めっき層107は、レーザ加工時に貫通しない程度の厚みにする必要がある。
(3) Next, as can be seen from FIG. 4 (1), a lid plating layer 107 made of a copper plating film is formed on the exposed via 105 and the surrounding copper foils 102, 103 by performing an electrolytic copper plating process. (Φ200 μm, 10 μm thickness) is formed. The lid plating layer 107 reduces the contact resistance between the embedded via 106 and the copper foils 102 and 103, ensures the reliability of interlayer connection by the embedded via 106, and at the time of laser processing the blind via hole later. Formed to protect 106. Note that the thickness of the lid plating layer 107 is determined in consideration of the resistance to the laser beam irradiated when forming the subsequent blind via hole. That is, the lid plating layer 107 needs to have a thickness that does not penetrate during laser processing.
(4)次に、図4(1)からわかるように、フォトファブリケーション手法により銅箔102及び103を加工し、蓋めっき層107より大きい径の受けランド部108(φ300μm)を有する内層回路パターンを、可撓性絶縁ベース材101の両面に形成する。ここで、フォトファブリケーション手法とは、被加工層(銅箔等)を所定のパターンにパターニングするための加工方法であり、被加工層上のレジスト層の形成、露光、現像、被加工層のエッチング及びレジスト層の剥離等の一連の工程からなる。なお、本工程において、蓋めっき層107がダメージを受けないように蓋めっき層107全体をレジスト層で覆う必要がある。このため、受けランド部108の径は蓋めっき層107の径よりも大きくならざるを得ない。このことは、内層回路パターンの高密度化を妨げる要因となる。
(4) Next, as can be seen from FIG. 4 (1), the copper foils 102 and 103 are processed by the photofabrication technique, and the inner layer circuit pattern having the receiving land portion 108 (φ300 μm) having a larger diameter than the lid plating layer 107. Are formed on both surfaces of the flexible insulating base material 101. Here, the photofabrication method is a processing method for patterning a processing layer (copper foil or the like) into a predetermined pattern. The formation of a resist layer on the processing layer, exposure, development, It consists of a series of processes such as etching and stripping of the resist layer. In this step, it is necessary to cover the entire lid plating layer 107 with a resist layer so that the lid plating layer 107 is not damaged. For this reason, the diameter of the receiving land portion 108 must be larger than the diameter of the lid plating layer 107. This becomes a factor that prevents the inner layer circuit pattern from being densified.
(5)次に、ビルドアップ層の積層に用いる接着材との密着性を向上させるために、内層回路パターンの表面に粗化処理を施す。この粗化処理によって銅表面における炭酸ガス(CO2)レーザ光(波長:約9.8μm)の吸収率が増加するため、蓋めっき層107のレーザ加工に対する耐性が低下してしまう。
(5) Next, in order to improve the adhesion with the adhesive used for laminating the build-up layer, the surface of the inner layer circuit pattern is roughened. This roughening treatment increases the absorption rate of carbon dioxide (CO 2 ) laser light (wavelength: about 9.8 μm) on the copper surface, so that the lid plating layer 107 is less resistant to laser processing.
(6)次に、図4(1)からわかるように、ポリイミドフィルム109(12μm厚)を、接着材層110(25μm厚)を介して、内層回路パターン上に接着して、カバーレイ111を形成する。なお、真空ラミネータ等を用いて、ポリイミドフィルム109と、このポリイミドフィルム109の片面に形成された接着剤層110とを有するカバーレイ111を、内層回路パターンが形成された基板にラミネートしてもよい。ここで、接着材層110の厚さは、接着材層110が蓋めっき層107及び内層回路パターンを完全に充填できるように決められる。このため、蓋めっき層107の厚みが大きいほど、接着剤層110の厚みも大きくならざるを得ない。
ここまでの工程で、図4(1)に示す両面コア基板112を得る。 (6) Next, as can be seen from FIG. 4 (1), the polyimide film 109 (12 μm thickness) is adhered onto the inner layer circuit pattern via the adhesive layer 110 (25 μm thickness), and thecoverlay 111 is formed. Form. A cover lay 111 having a polyimide film 109 and an adhesive layer 110 formed on one side of the polyimide film 109 may be laminated on a substrate on which an inner layer circuit pattern is formed using a vacuum laminator or the like. . Here, the thickness of the adhesive layer 110 is determined so that the adhesive layer 110 can completely fill the lid plating layer 107 and the inner layer circuit pattern. For this reason, the greater the thickness of the lid plating layer 107, the greater the thickness of the adhesive layer 110.
Up to this step, the double-sidedcore substrate 112 shown in FIG. 4A is obtained.
ここまでの工程で、図4(1)に示す両面コア基板112を得る。 (6) Next, as can be seen from FIG. 4 (1), the polyimide film 109 (12 μm thickness) is adhered onto the inner layer circuit pattern via the adhesive layer 110 (25 μm thickness), and the
Up to this step, the double-sided
(7)次に、可撓性の片面銅張積層板113を準備する。そして、図4(2)からわかるように、この片面銅張積層板113の銅箔113bに対し、フォトファブリケーション手法を用いて、コンフォーマルマスクとなる開口部を形成する。ここで、片面銅張積層板113は、ポリイミドフィルム113a(厚さ25μm)の片面に銅箔113b(12μm厚)を有するものである。
(7) Next, a flexible single-sided copper-clad laminate 113 is prepared. As can be seen from FIG. 4B, an opening serving as a conformal mask is formed on the copper foil 113b of the single-sided copper-clad laminate 113 using a photofabrication technique. Here, the single-sided copper clad laminate 113 has a copper foil 113b (12 μm thickness) on one side of a polyimide film 113a (thickness 25 μm).
(8)次に、図4(2)からわかるように、前工程で銅箔113bが加工された片面銅張積層板113を、接着剤層114を介して、両面コア基板112の両面に積層接着する。
(8) Next, as can be seen from FIG. 4 (2), the single-sided copper-clad laminate 113 in which the copper foil 113 b has been processed in the previous step is laminated on both sides of the double-sided core substrate 112 via the adhesive layer 114. Glue.
(9)次に、図4(2)に示すように、銅箔113bに形成したコンフォーマルマスクを用いてレーザ加工を行い、ブラインドビアホール(導通用孔)115A,115Bを形成する。
本工程のレーザ加工は、生産性を考慮し、炭酸ガスレーザを用いる場合が多い。しかし、粗化処理された銅表面は、炭酸ガスレーザによる熱ダメージを受けやすいため、レーザ加工の条件(レーザ光のパルスエネルギーなど)に注意が必要となる。蓋めっき層107を貫通しないようにする方法として、2つの方法、即ち、レーザ光のパワーを低下する方法と、蓋めっき層107の厚みを大きくする方法がある。前者の方法は、加工速度が低下し生産性が低下してしまうため、採用できない。一方、後者の方法を用いる場合、後に詳述するように微細な外層回路パターンを形成することが困難となるため、プリント配線板の高密度実装の要求を満足することができない。 (9) Next, as shown in FIG. 4B, laser processing is performed using a conformal mask formed on thecopper foil 113b to form blind via holes (conduction holes) 115A and 115B.
In the laser processing in this step, a carbon dioxide laser is often used in consideration of productivity. However, since the roughened copper surface is susceptible to thermal damage by a carbon dioxide laser, attention must be paid to laser processing conditions (such as pulse energy of laser light). There are two methods for preventing penetration of thelid plating layer 107, that is, a method of reducing the power of the laser beam and a method of increasing the thickness of the lid plating layer 107. The former method cannot be employed because the processing speed decreases and the productivity decreases. On the other hand, when the latter method is used, it is difficult to form a fine outer layer circuit pattern as will be described in detail later, so that the demand for high-density mounting of the printed wiring board cannot be satisfied.
本工程のレーザ加工は、生産性を考慮し、炭酸ガスレーザを用いる場合が多い。しかし、粗化処理された銅表面は、炭酸ガスレーザによる熱ダメージを受けやすいため、レーザ加工の条件(レーザ光のパルスエネルギーなど)に注意が必要となる。蓋めっき層107を貫通しないようにする方法として、2つの方法、即ち、レーザ光のパワーを低下する方法と、蓋めっき層107の厚みを大きくする方法がある。前者の方法は、加工速度が低下し生産性が低下してしまうため、採用できない。一方、後者の方法を用いる場合、後に詳述するように微細な外層回路パターンを形成することが困難となるため、プリント配線板の高密度実装の要求を満足することができない。 (9) Next, as shown in FIG. 4B, laser processing is performed using a conformal mask formed on the
In the laser processing in this step, a carbon dioxide laser is often used in consideration of productivity. However, since the roughened copper surface is susceptible to thermal damage by a carbon dioxide laser, attention must be paid to laser processing conditions (such as pulse energy of laser light). There are two methods for preventing penetration of the
(10)次に、図4(3)からわかるように、導電化処理とそれに続く電解銅めっき処理を施すことにより、銅箔113b上及びブラインドビアホール115A,115Bの内壁に電解銅めっき皮膜を形成する。この電解銅めっき被膜の厚みは、層間導通を確保するために25~30μm程度にする必要がある。本工程により、層間導電路として機能するブラインドビア116A,116Bが形成される。ブラインドビア116Aは、蓋めっき層107を介して、コア基板の埋め込みビア106上にスタックされており、スタックビア構造が形成されている。一方、ブラインドビア116Bはスタックビア構造を構成しない。
(10) Next, as can be seen from FIG. 4 (3), an electrolytic copper plating film is formed on the copper foil 113 b and the inner walls of the blind via holes 115 A and 115 B by conducting a conductive treatment and subsequent electrolytic copper plating treatment. To do. The thickness of the electrolytic copper plating film needs to be about 25 to 30 μm in order to ensure interlayer conduction. By this step, blind vias 116A and 116B that function as interlayer conductive paths are formed. The blind via 116A is stacked on the embedded via 106 of the core substrate via the lid plating layer 107, and a stacked via structure is formed. On the other hand, the blind via 116B does not constitute a stacked via structure.
(11)次に、図4(3)に示すように、フォトファブリケーション手法を用いて、前工程で形成された電解銅めっき被膜を加工し、外層回路パターン117を形成する。図4(3)からわかるように、ビルドアップ型多層プリント配線板118は、両面コア基板112にビルドアップ層が積層された部品実装部118aと、この部品実装部118aから延伸する可撓性ケーブル部118bとを有する。この可撓性ケーブル部118bは、ビルドアップ層が設けられていない両面コア基板112の一部である。
(11) Next, as shown in FIG. 4 (3), the electrolytic copper plating film formed in the previous step is processed using a photofabrication technique to form an outer layer circuit pattern 117. As can be seen from FIG. 4 (3), the build-up type multilayer printed wiring board 118 includes a component mounting portion 118a in which a build-up layer is laminated on the double-sided core substrate 112, and a flexible cable extending from the component mounting portion 118a. Part 118b. The flexible cable portion 118b is a part of the double-sided core substrate 112 that is not provided with a build-up layer.
以上の工程を経て、ステップビア構造を有する従来のビルドアップ型多層プリント配線板118が製造される。
Through the above steps, a conventional build-up type multilayer printed wiring board 118 having a step via structure is manufactured.
従来技術の問題点一つとして、前述のように、生産性を維持しながら、ブラインドビアホール115A,115Bをレーザ加工で形成する際に蓋めっき層107が貫通しないようにするため、蓋めっき層107を厚くせざるを得ないことが挙げられる。蓋めっき層107が厚くなるにつれて、内層回路パターンを埋め込む接着材層110の厚みが大きくなるため、ブラインドビアホール115A,115Bが深くなる。ブラインドビアホール115A,115B及び銅箔113b上に形成される電解銅めっき皮膜の厚みは、ブラインドビア116A,116Bの接続信頼性を確保するために、上述のように25~30μm程度にする必要がある。この場合、ビルドアップ層上の導体層(銅箔113b及び電解銅めっき被膜)の厚みは、トータルで37~42μmにもなるため、例えばピッチ100μm程度の微細な外層回路パターンを歩留まり良く形成することは実際上極めて困難となる。
As one of the problems of the prior art, as described above, in order to prevent the lid plating layer 107 from penetrating when forming the blind via holes 115A and 115B by laser processing while maintaining productivity, the lid plating layer 107 is used. It must be thickened. As the lid plating layer 107 becomes thicker, the thickness of the adhesive layer 110 that embeds the inner layer circuit pattern increases, so that the blind via holes 115A and 115B become deeper. The thickness of the electrolytic copper plating film formed on the blind via holes 115A and 115B and the copper foil 113b needs to be about 25 to 30 μm as described above in order to ensure the connection reliability of the blind vias 116A and 116B. . In this case, since the total thickness of the conductor layer (copper foil 113b and electrolytic copper plating film) on the buildup layer is 37 to 42 μm, a fine outer layer circuit pattern with a pitch of about 100 μm, for example, should be formed with a high yield. Is extremely difficult in practice.
このように、ステップビア構造を有する従来のビルドアップ形多層プリント配線板では、高密度実装の要求を満足することができないという問題があった。
As described above, the conventional build-up type multilayer printed wiring board having the step via structure has a problem that it cannot satisfy the demand for high-density mounting.
本発明は、上記の技術的な認識に基づいてなされたものであり、高密度実装可能なスタックビア構造を有するビルドアップ型多層プリント配線板を提供すること、及び、このようなプリント配線板を安価かつ安定的に製造する方法を提供することを目的とする。
The present invention has been made based on the above technical recognition, and provides a build-up type multilayer printed wiring board having a stack via structure capable of high-density mounting, and such a printed wiring board. It aims at providing the method of manufacturing cheaply and stably.
本発明の第1の態様によれば、可撓性の絶縁ベース材と、前記絶縁ベース材の両面に設けられ、受けランド部を有する内層回路パターンと、前記絶縁ベース材を厚さ方向に貫通し、前記絶縁ベース材の表面及び裏面の前記内層回路パターンを電気的に接続する埋込みビアとを有する、両面回路基材と、前記両面回路基材に絶縁層を介して積層された、表面に外層回路パターンを有するビルドアップ層と、を備えるとともに、表層が前記内層回路パターンを構成する金属のエッチャントに対して耐性を有する材料からなり、前記受けランド部を被覆する蓋めっき層と、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールの内壁に形成されためっき皮膜からなり、前記内層回路パターンと前記外層回路パターンを電気的に接続するブラインドビアと、を備えるビルドアップ型多層プリント配線板が提供される。
According to the first aspect of the present invention, a flexible insulating base material, an inner layer circuit pattern provided on both surfaces of the insulating base material and having receiving land portions, and the insulating base material are penetrated in the thickness direction. A double-sided circuit base material having embedded vias for electrically connecting the inner layer circuit patterns on the front surface and the back surface of the insulating base material, and laminated on the double-sided circuit base material with an insulating layer on the surface. A build-up layer having an outer layer circuit pattern, and a cover plating layer that covers the receiving land portion, the surface layer being made of a material having resistance to a metal etchant constituting the inner layer circuit pattern, and the build The inner layer circuit pattern and the outer layer are formed of a plating film formed on the inner wall of the blind via hole that penetrates the up layer in the thickness direction and the lid plating layer is exposed on the bottom surface. Build-up multilayer printed wiring board having a blind via that electrically connects the road pattern, is provided.
本発明の第2の態様によれば、可撓性の絶縁ベース材と、その両面に設けられた第1の金属箔とを有する両面金属張積層板を準備し、前記両面金属張積層板を厚さ方向に貫通するスルーホールを形成し、前記スルーホールの内部に導電性ペーストを充填した後、前記導電性ペーストを硬化させて、埋込みビアを形成し、少なくとも表層が前記第1の金属箔のエッチャントに対して耐性を有する材料からなる蓋めっき層を所定の領域に形成し、所定のパターンを有するレジスト層を前記第1の金属箔上に形成し、前記レジスト層及び前記蓋めっき層をエッチングレジストとして用いて前記第1の金属箔をエッチングすることにより、前記蓋めっき層で覆われた受けランド部を有する内層回路パターンを形成し、これにより、両面回路基材を得、前記内層回路パターンの表面に粗化処理を施した後、絶縁フィルムと、前記絶縁フィルムの片面に形成された第1の接着剤層とを有するカバーレイを、前記両面回路基材に貼り付けるラミネート工程を行い、これにより、両面コア基板を得、表面に第2の金属箔を有するビルドアップ層を、第2の接着剤層を介して前記両面コア基板に積層し、前記ビルドアップ層の所定の位置に赤外レーザ光を照射することにより、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールを形成し、前記ブラインドビアホールの内壁及び前記第2の金属箔上にめっき皮膜を形成することにより、前記第2の金属箔と前記内層回路パターンとを電気的に接続するブラインドビアを形成する、ビルドアップ型多層プリント配線板の製造方法が提供される。
According to the second aspect of the present invention, a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared. A through hole penetrating in the thickness direction is formed, and after filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and at least the surface layer is the first metal foil A lid plating layer made of a material resistant to the etchant is formed in a predetermined region, a resist layer having a predetermined pattern is formed on the first metal foil, and the resist layer and the lid plating layer are formed By etching the first metal foil as an etching resist, an inner layer circuit pattern having a receiving land portion covered with the lid plating layer is formed, thereby obtaining a double-sided circuit substrate. Laminate for applying a coverlay having an insulating film and a first adhesive layer formed on one side of the insulating film to the double-sided circuit substrate after roughening the surface of the inner layer circuit pattern Performing a process, thereby obtaining a double-sided core substrate, laminating a build-up layer having a second metal foil on the surface thereof on the double-sided core substrate via a second adhesive layer, Is irradiated with infrared laser light to form a blind via hole penetrating the build-up layer in the thickness direction and exposing the lid plating layer on the bottom surface, and the inner wall of the blind via hole and the second A build-up type multilayer pre-form that forms a blind via for electrically connecting the second metal foil and the inner layer circuit pattern by forming a plating film on the metal foil. Method for manufacturing a preparative wiring board is provided.
本発明の第3の態様によれば、可撓性の絶縁ベース材と、その両面に設けられた第1の金属箔とを有する両面金属張積層板を準備し、前記両面金属張積層板を厚さ方向に貫通するスルーホールを形成し、前記スルーホールの内部に導電性ペーストを充填した後、前記導電性ペーストを硬化させて、埋込みビアを形成し、前記第1の金属箔及び露出した前記埋込みビアの上に第1のめっき皮膜を形成し、前記第1のめっき皮膜上に所定のパターンを有するレジスト層を形成し、前記レジスト層をエッチングレジストとして用いて前記第1のめっき皮膜及び前記第1の金属箔をエッチングすることにより、受けランド部を有する内層回路パターンを形成し、少なくとも表層が前記第1の金属箔のエッチャントに対して耐性を有する材料からなる蓋めっき層を、前記受けランド部を被覆するように形成し、これにより、両面回路基材を得、前記内層回路パターンの表面に粗化処理を施した後、絶縁フィルムと、前記絶縁フィルムの片面に形成された第1の接着剤層とを有するカバーレイを、前記両面回路基材に貼り付けるラミネート工程を行い、これにより、両面コア基板を得、表層に第2の金属箔を有するビルドアップ層を、第2の接着剤層を介して前記両面コア基板に積層し、前記ビルドアップ層の所定の位置に赤外レーザ光を照射することにより、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールを形成し、前記ブラインドビアホールの内壁及び前記第2の金属箔上に第2のめっき皮膜を形成することにより、前記第2の金属箔と前記内層回路パターンとを電気的に接続するブラインドビアを形成する、ビルドアップ型多層プリント配線板の製造方法が提供される。
According to the third aspect of the present invention, a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared, and the double-sided metal-clad laminate is After forming a through hole penetrating in the thickness direction and filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and the first metal foil and the exposed portion are exposed. Forming a first plating film on the embedded via, forming a resist layer having a predetermined pattern on the first plating film, and using the resist layer as an etching resist, By etching the first metal foil, an inner layer circuit pattern having a receiving land portion is formed, and at least the surface layer is made of a material having resistance to the etchant of the first metal foil. A plating layer is formed so as to cover the receiving land portion, thereby obtaining a double-sided circuit base material, and after roughening the surface of the inner layer circuit pattern, an insulating film and one side of the insulating film A laminating step of attaching a coverlay having a first adhesive layer formed on the double-sided circuit base material to the double-sided circuit substrate, thereby obtaining a double-sided core substrate and having a second metal foil on the surface layer A layer is laminated on the double-sided core substrate via a second adhesive layer, and an infrared laser beam is irradiated to a predetermined position of the buildup layer to penetrate the buildup layer in the thickness direction. Forming a blind via hole with the cover plating layer exposed on the bottom surface, and forming a second plating film on the inner wall of the blind via hole and the second metal foil; Serial to form a blind via that electrically connects the inner layer circuit pattern, the manufacturing method of the buildup type multilayer printed wiring board is provided.
本発明の第4の態様によれば、可撓性の絶縁ベース材と、その両面に設けられた第1の金属箔とを有する両面金属張積層板を準備し、前記両面金属張積層板を厚さ方向に貫通するスルーホールを形成し、前記スルーホールの内部に導電性ペーストを充填した後、前記導電性ペーストを硬化させて、埋込みビアを形成し、前記第1の金属箔及び露出した前記埋込みビアの上に第1のめっき皮膜を形成し、前記第1のめっき皮膜上に所定のパターンを有するレジスト層を形成し、前記レジスト層をエッチングレジストとして用いて前記第1のめっき皮膜及び前記第1の金属箔をエッチングすることにより、受けランド部を有する内層回路パターンを形成し、これにより、両面回路基材を得、絶縁フィルムと、前記絶縁フィルムの片面に形成された第1の接着剤層とを有するカバーレイを、部品実装部と可撓性ケーブル部との境界領域における前記両面回路基材に貼り付けるラミネート工程を行い、少なくとも表層が前記第1の金属箔のエッチャントに対して耐性を有する材料からなる蓋めっき層を、前記受けランド部を被覆するように形成し、これにより、両面コア基板を得、前記内層回路パターンの表面に粗化処理を施した後、表面に第2の金属箔を有するビルドアップ層を、前記カバーレイの厚み以上の厚みを有する第2の接着剤層を介して、前記部品実装部における前記両面コア基板に積層し、前記ビルドアップ層の所定の位置に赤外レーザ光を照射することにより、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールを形成し、前記ブラインドビアホールの内壁及び前記第2の金属箔上に第2のめっき皮膜を形成することにより、前記第2の金属箔と前記内層回路パターンとを電気的に接続するブラインドビアを形成する、ビルドアップ型多層プリント配線板の製造方法が提供される。
According to the fourth aspect of the present invention, a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof is prepared, and the double-sided metal-clad laminate is After forming a through hole penetrating in the thickness direction and filling the through hole with a conductive paste, the conductive paste is cured to form a buried via, and the first metal foil and the exposed portion are exposed. Forming a first plating film on the embedded via, forming a resist layer having a predetermined pattern on the first plating film, and using the resist layer as an etching resist, By etching the first metal foil, an inner layer circuit pattern having a receiving land portion is formed, thereby obtaining a double-sided circuit base material, which is formed on one side of the insulating film and the insulating film. A laminating step of attaching a coverlay having a first adhesive layer to the double-sided circuit base material in a boundary region between the component mounting portion and the flexible cable portion, and at least a surface layer of the first metal foil After forming a lid plating layer made of a material resistant to an etchant so as to cover the receiving land portion, a double-sided core substrate is obtained, and the surface of the inner layer circuit pattern is subjected to a roughening treatment A build-up layer having a second metal foil on the surface is laminated on the double-sided core substrate in the component mounting portion via a second adhesive layer having a thickness equal to or greater than the thickness of the coverlay, and the build By irradiating infrared laser light at a predetermined position of the up layer, the build-up layer penetrates in the thickness direction, and a blind via hole in which the lid plating layer is exposed on the bottom surface is formed, A build that forms a blind via that electrically connects the second metal foil and the inner layer circuit pattern by forming a second plating film on the inner wall of the blind via hole and the second metal foil. A method for manufacturing an up-type multilayer printed wiring board is provided.
これらの特徴により、本発明は次のような効果を奏する。
Due to these features, the present invention has the following effects.
本発明に係るビルドアップ型多層プリント配線板は、ブラインドビアホールの受けランド部に、表層が内層回路パターンを構成する金属のエッチャントに対して耐性を有する材料からなる蓋めっき層を有する。この蓋めっき層は赤外レーザに対する耐性が高いため、蓋めっき層の厚みを大幅に低減することができる。これにより、内層回路パターン及び蓋めっき層を充填する接着材層の厚みを低減し、ビルドアップ層を貫通するブラインドビアホールを浅くすることができる。その結果、層間導通を確保するのに必要なめっき層の厚みを低減することができ、外層回路パターンを微細化することができる。よって、本発明に係るスタックビア構造を有するビルドアップ型多層プリント配線板は、高密度実装の要求を満たすことができる。
The build-up type multilayer printed wiring board according to the present invention has a lid plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern at a receiving land portion of a blind via hole. Since this lid plating layer has high resistance to infrared lasers, the thickness of the lid plating layer can be greatly reduced. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the buildup layer can be shallowed. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and the outer circuit pattern can be miniaturized. Therefore, the build-up type multilayer printed wiring board having the stacked via structure according to the present invention can satisfy the demand for high-density mounting.
また、本発明に係るビルドアップ型多層プリント配線板の製造方法では、ビルドアップビアホールの受けランド部に、表層が内層回路パターンを構成する金属のエッチャントに対して耐性を有する材料からなる蓋めっき層を形成する。この蓋めっき層は、赤外レーザに対する耐性が高いため、大幅に薄く形成することができる。これにより、内層回路パターン及び蓋めっき層を充填する接着材層の厚みを低減することができ、ビルドアップ層を貫通するブラインドビアホールを浅くする形成することができる。その結果、層間導通を確保するのに必要なめっき層の厚みを低減し、微細な外層回路パターンを形成することができる。さらに、スタックビア構造用か否かに拘わらず、ブラインドビアホールを形成する際におけるレーザ加工の条件及びデスミア工程の条件を同一とすることができるため、生産性を向上させることができる。
Further, in the method for manufacturing a build-up type multilayer printed wiring board according to the present invention, a cover plating layer made of a material having resistance to a metal etchant whose surface layer constitutes an inner layer circuit pattern is formed on the receiving land portion of the build-up via hole. Form. Since this lid plating layer has high resistance to infrared lasers, it can be formed significantly thinner. Thereby, the thickness of the adhesive layer filling the inner layer circuit pattern and the lid plating layer can be reduced, and the blind via hole penetrating the build-up layer can be formed shallow. As a result, the thickness of the plating layer necessary to ensure interlayer conduction can be reduced, and a fine outer layer circuit pattern can be formed. Furthermore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same, so that productivity can be improved.
以下、図面を参照しながら、本発明に係る3つの実施形態ついて説明する。
Hereinafter, three embodiments according to the present invention will be described with reference to the drawings.
なお、各図において同等の機能を有する構成要素には同一の符号を付し、同一符号の構成要素の詳しい説明は繰り返さない。実施形態の説明中の数値はいずれも例示的な値であり、本発明はそれらの値に限定されるものではない。また、図面は模式的なものであり、各実施形態に係る特徴部分を中心に示すものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なる。
In addition, in each figure, the same code | symbol is attached | subjected to the component which has an equivalent function, and the detailed description of the component of the same code | symbol is not repeated. The numerical values in the description of the embodiments are all exemplary values, and the present invention is not limited to these values. Further, the drawings are schematic and mainly show characteristic portions according to each embodiment, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones.
(第1の実施形態)
図1A~図1Dを用いて、第1の実施形態に係るスタックビア構造を有するビルドアップ型多層プリント配線板の製造方法について説明する。図1A~図1Dは、本実施形態に係るビルドアップ型多層プリント配線板の製造方法を示す工程断面図である。 (First embodiment)
A method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure according to the first embodiment will be described with reference to FIGS. 1A to 1D. 1A to 1D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
図1A~図1Dを用いて、第1の実施形態に係るスタックビア構造を有するビルドアップ型多層プリント配線板の製造方法について説明する。図1A~図1Dは、本実施形態に係るビルドアップ型多層プリント配線板の製造方法を示す工程断面図である。 (First embodiment)
A method for manufacturing a build-up type multilayer printed wiring board having a stacked via structure according to the first embodiment will be described with reference to FIGS. 1A to 1D. 1A to 1D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
(1)ポリイミドフィルム等の可撓性絶縁ベース材1(厚さ25μm)の表面及び裏面にそれぞれ銅箔2及び銅箔3(各々12μm厚)を有する、可撓性の両面銅張積層板4を準備する。そして、図1A(1)に示すように、レーザ加工又はNCドリル等を用いて、この両面銅張積層板4を厚さ方向に貫通するスルーホール5(φ100μm)を形成する。なお、スルーホール5をレーザ加工により形成する場合には、所定のパターンに加工された銅箔2,3をメタルマスクとするコンフォーマルレーザ加工法、又は、銅箔2,3及びその下の絶縁樹脂(可撓性絶縁ベース材1)をレーザ光で直接加工するダイレクトレーザ加工法を選択可能である。ここでは、生産性を考慮して、フォトファブリケーション手法による銅箔のエッチング工程が不要なダイレクトレーザ加工法を選択した。
(1) Flexible double-sided copper clad laminate 4 having copper foil 2 and copper foil 3 (each 12 μm thick) on the front and back surfaces of flexible insulating base material 1 (thickness 25 μm) such as polyimide film, respectively. Prepare. Then, as shown in FIG. 1A (1), through holes 5 (φ100 μm) penetrating through the double-sided copper-clad laminate 4 in the thickness direction are formed by using laser processing, NC drills, or the like. When the through hole 5 is formed by laser processing, the conformal laser processing method using the copper foils 2 and 3 processed into a predetermined pattern as a metal mask, or the copper foils 2 and 3 and the insulation below them. A direct laser processing method in which the resin (flexible insulating base material 1) is directly processed with a laser beam can be selected. Here, in consideration of productivity, a direct laser processing method that does not require a copper foil etching step by a photofabrication method was selected.
(2)次に、図1A(2)に示すように、スクリーン印刷法等によりスルーホール5の内部に導電性ペースト6Aを充填し、その後、充填した導電性ペースト6Aを硬化させる。工程数の削減及び電気特性の観点から、この導電性ペースト6Aは、体積抵抗率が低く、且つ、後述の蓋めっき層9を形成する際に導電化処理が不要であるものが好ましい。ここでは、タツタエレクトロニクス社製のAE1244(体積抵抗率:5×10-5Ω・cm)を用いた。本工程では、導電性ペーストの不足によってボイド等がスルーホール5内に発生しないように、図1A(2)に示すように、スルーホール5の上部及び下部ともに、導電性ペースト6Aが溢れるまで充填することが好ましい。なお、導電性ペーストはブラインドビアホールではなくスルーホールに充填されることから、本工程で用いる印刷機は、真空系のものである必要はなく、両面銅張積層板4を吸着する程度の差圧を発生可能な機構を備えるものであればよい。
(2) Next, as shown in FIG. 1A (2), the through-hole 5 is filled with the conductive paste 6A by screen printing or the like, and then the filled conductive paste 6A is cured. From the viewpoint of reduction in the number of steps and electrical characteristics, the conductive paste 6A preferably has a low volume resistivity and does not require a conductive treatment when a lid plating layer 9 described later is formed. Here, AE1244 (volume resistivity: 5 × 10 −5 Ω · cm) manufactured by Tatsuta Electronics Co., Ltd. was used. In this step, as shown in FIG. 1A (2), the upper and lower portions of the through-hole 5 are filled until the conductive paste 6A overflows so that voids or the like do not occur in the through-hole 5 due to the lack of the conductive paste. It is preferable to do. In addition, since the conductive paste is filled in the through hole instead of the blind via hole, the printing machine used in this process does not need to be a vacuum type and has a differential pressure enough to adsorb the double-sided copper clad laminate 4. As long as it has a mechanism capable of generating
(3)次に、図1A(2)に示すスルーホール5内に導電性ペースト6Aが充填された両面銅張積層板4の両面を、ベルトサンダー若しくはロールバフによる機械研磨、又は化学機械研磨(CMP:Chemical Mechanical Polishing)等により研磨する。これにより、図1A(3)に示すように、スルーホール5からはみ出した余分な導電ペースト6Aが削られ、埋込みビア6が形成される。本工程の研磨によって銅箔2及び銅箔3も削られ、銅箔2及び銅箔3はそれぞれ約5μm厚の銅箔2a及び銅箔3aとなる。
(3) Next, both surfaces of the double-sided copper clad laminate 4 in which the conductive paste 6A is filled in the through-hole 5 shown in FIG. 1A (2) are mechanically polished by a belt sander or a roll buff, or chemical mechanically polished (CMP : Polishing by Chemical Mechanical Polishing). As a result, as shown in FIG. 1A (3), the excess conductive paste 6A protruding from the through hole 5 is scraped, and the buried via 6 is formed. The copper foil 2 and the copper foil 3 are also shaved by polishing in this step, and the copper foil 2 and the copper foil 3 become a copper foil 2a and a copper foil 3a having a thickness of about 5 μm, respectively.
なお、本工程のように可撓性の薄い両面銅張積層板を研磨する場合には、研磨する前に、両面銅張積層板4を粘着性の接着シートを介して硬質基板(数mm厚)等へ張り合わせた後、研磨加工する。このようにすることで、硬質基板用の研磨装置を用いることができる。薄膜を研磨する他の方法として、両面銅張積層板4を平板に吸着させて保持した後、吸着面と反対側の面を研磨し、その後、両面銅張積層板4をひっくり返し、研磨済みの面を平板に吸着させて、未研磨の面を研磨するようにしてもよい。
When polishing a flexible thin double-sided copper-clad laminate as in this step, the double-sided copper-clad laminate 4 is bonded to a hard substrate (several mm thick) via an adhesive sheet before polishing. ) Etc. and then polishing. By doing in this way, the polisher for hard substrates can be used. As another method of polishing the thin film, the double-sided copper-clad laminate 4 is adsorbed and held on a flat plate, the surface opposite to the adsorption surface is polished, and then the double-sided copper-clad laminate 4 is turned over and polished. This surface may be adsorbed on a flat plate, and the unpolished surface may be polished.
(4)次に、図1A(4)からわかるように、銅箔2a及び銅箔3a上にめっきレジスト層7をそれぞれ形成する。このめっきレジスト層7は、埋込みビア6が露出している領域に開口部8aを有し、さらに、埋込みビア6がなくともブラインドビアホールの受けランド部となる領域に開口部8bを有する。なお、開口部8a,8bの直径は、ブラインドビアホールの直径と、ブラインドビアホールを形成する際の位置合わせ精度とを考慮して決めることが望ましい。ここでは、φ200μmとした。
(4) Next, as can be seen from FIG. 1A (4), a plating resist layer 7 is formed on each of the copper foil 2a and the copper foil 3a. This plating resist layer 7 has an opening 8a in a region where the embedded via 6 is exposed, and further has an opening 8b in a region which becomes a receiving land portion of a blind via hole without the embedded via 6. The diameters of the openings 8a and 8b are preferably determined in consideration of the diameter of the blind via hole and the alignment accuracy when forming the blind via hole. Here, it is set to φ200 μm.
(5)次に、図1A(4)に示すように、めっきレジスト層7を用いて電解または無電解めっきを行うことにより、めっきレジスト層7の開口部8a及び8bに蓋めっき層9を形成する。より詳細には、蓋めっき層9は次のようにして形成される。まず、電解銅めっきを行い、厚さ2μmの銅めっき層9aを開口部8a及び8bの底面に形成する。その後、無電解銀めっきを行い、厚さ0.5μmの銀めっき層9bを銅めっき層9aの上に形成する。この一連のめっき処理は、めっきレジスト層7を残したままの状態で行う。
(5) Next, as shown in FIG. 1A (4), by performing electrolytic or electroless plating using the plating resist layer 7, the lid plating layer 9 is formed in the openings 8a and 8b of the plating resist layer 7. To do. More specifically, the lid plating layer 9 is formed as follows. First, electrolytic copper plating is performed to form a copper plating layer 9a having a thickness of 2 μm on the bottom surfaces of the openings 8a and 8b. Thereafter, electroless silver plating is performed to form a silver plating layer 9b having a thickness of 0.5 μm on the copper plating layer 9a. This series of plating processes is performed with the plating resist layer 7 left.
なお、蓋めっき層9は上記の構成に限られない。例えば、銅めっき層9aの代わりに、無電解ニッケルめっきによるニッケルめっき層を形成してもよい。また、蓋めっき層9は、電解または無電解めっきを用いて、1層の銀めっき層又はニッケルめっき層として構成してもよい。
The lid plating layer 9 is not limited to the above configuration. For example, a nickel plating layer by electroless nickel plating may be formed instead of the copper plating layer 9a. Moreover, you may comprise the lid plating layer 9 as one silver plating layer or a nickel plating layer using electrolysis or electroless plating.
蓋めっき層9の表層を構成するめっき層は、銅のエッチャントに対する耐性(銅に対する選択エッチング性でもよい。)を有することが必要である。この条件を満たすめっき層として、銀めっき層9bに代えて、無電解金めっきによる金めっき層、又は無電解ニッケルめっきによるニッケルめっき層を形成してもよい。その他、銀メッキ層9bの代わりに、銅めっき層9aの上に、ニッケルめっき層と金メッキ層を順次形成してもよい。このように、蓋めっき層9は、少なくとも表層が銀(Ag)、金(Au)、ニッケル(Ni)などといった銅のエッチャントに対して耐性を有する材料からなるという条件下で、銀、金、ニッケル、銅等からなるめっき層を、単独もしくは複数組み合わせて構成することができる。これらいずれの場合であっても以降の工程を変更する必要はなく、銅めっき層9aと銀めっき層9bからなる蓋めっき層9を形成した場合と同様の効果が得られる。蓋めっき層9の構成は、生産性及びコスト等を考慮して選択される。
The plating layer constituting the surface layer of the lid plating layer 9 needs to have resistance to copper etchant (may be selective etching to copper). As a plating layer that satisfies this condition, a gold plating layer by electroless gold plating or a nickel plating layer by electroless nickel plating may be formed instead of the silver plating layer 9b. In addition, instead of the silver plating layer 9b, a nickel plating layer and a gold plating layer may be sequentially formed on the copper plating layer 9a. Thus, the cover plating layer 9 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni). A plating layer made of nickel, copper, or the like can be configured singly or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the lid plating layer 9 composed of the copper plating layer 9a and the silver plating layer 9b is formed can be obtained. The configuration of the lid plating layer 9 is selected in consideration of productivity and cost.
(6)次に、めっきレジスト層7を剥離した後、図1B(5)及び(6)に示すように、後述の内層回路パターン11A,11Bを形成するための、所定のパターンを有するエッチングレジスト層10を、銅箔2a,2b上に形成する。ここで、図1B(5)は、図1B(6)のA-A’線に沿う断面図である。つまり、図1B(6)は、図1B(5)に示す基材を上面からみた図である。なお、エッチングレジスト層10を形成するために、微細配線形成用のドライフィルムレジスト(約10μm厚)を用いてもよい。この場合でも、前述のように蓋めっき層9の厚みは2.5μmと薄いため、蓋めっき層9を充填することが可能である。
(6) Next, after the plating resist layer 7 is peeled off, as shown in FIGS. 1B (5) and (6), an etching resist having a predetermined pattern for forming inner layer circuit patterns 11A and 11B described later. The layer 10 is formed on the copper foils 2a and 2b. Here, FIG. 1B (5) is a cross-sectional view taken along the line A-A 'of FIG. 1B (6). That is, FIG. 1B (6) is a view of the base material shown in FIG. 1B (5) as viewed from above. In order to form the etching resist layer 10, a dry film resist (about 10 μm thick) for forming a fine wiring may be used. Even in this case, since the thickness of the lid plating layer 9 is as thin as 2.5 μm as described above, the lid plating layer 9 can be filled.
蓋めっき層9は、回路パターンエッチングの際にエッチングレジストとして機能するため、図1B(5)及び(6)に示すように、蓋めっき層9を保護するためのエッチングレジスト層を設ける必要はない。よって、高精度な位置合わせが可能な露光機を用いなくとも、蓋めっき層9の形状をそのままブラインドビアホールの受けランド部の形状とすることが可能である。このことは、生産性を向上させるとともに、安価なプリント配線板の製造に寄与する。
Since the lid plating layer 9 functions as an etching resist during circuit pattern etching, it is not necessary to provide an etching resist layer for protecting the lid plating layer 9 as shown in FIGS. 1B (5) and (6). . Therefore, the shape of the lid plating layer 9 can be used as it is as the shape of the receiving land portion of the blind via hole without using an exposure machine capable of highly accurate alignment. This improves productivity and contributes to the manufacture of an inexpensive printed wiring board.
(7)次に、図1B(7)からわかるように、エッチングレジスト層10及び蓋めっき層9をエッチングレジストとして用いて、銅箔2a及び銅箔3aのエッチングを行うことにより、可撓性絶縁ベース材1の表面及び裏面に内層回路パターン11A及び内層回路パターン11Bをそれぞれ形成する。その後、エッチングレジスト層10を剥離する。この内層回路パターン11A,11Bは、蓋めっき層9で覆われた、ブラインドビアホールの受けランド部を有する。
(7) Next, as can be seen from FIG. 1B (7), the copper foil 2a and the copper foil 3a are etched using the etching resist layer 10 and the lid plating layer 9 as an etching resist, thereby providing flexible insulation. The inner layer circuit pattern 11A and the inner layer circuit pattern 11B are formed on the front surface and the back surface of the base material 1, respectively. Thereafter, the etching resist layer 10 is peeled off. The inner layer circuit patterns 11 </ b> A and 11 </ b> B have blind via hole receiving land portions covered with the cover plating layer 9.
本工程におけるエッチャントは、銅箔2a,3aをエッチングする一方、蓋めっき層9(銀めっき層9b)にはダメージを与えないものを用いる。例えば、このようなエッチャントとして、塩化第二銅又は塩化第二鉄を用いたエッチャントを用いることができる。
The etchant used in this step is one that etches the copper foils 2a and 3a but does not damage the lid plating layer 9 (silver plating layer 9b). For example, an etchant using cupric chloride or ferric chloride can be used as such an etchant.
なお、蓋めっき層9の表層をニッケルめっき層で構成した場合、本工程のエッチングは、例えばアンモニア系のアルカリエッチャントを用いて、選択エッチングとして行う。
In addition, when the surface layer of the lid plating layer 9 is composed of a nickel plating layer, the etching in this step is performed as selective etching using, for example, an ammonia-based alkali etchant.
ここまでの工程を経て、図1B(7)に示す両面回路基材12を得る。両面回路基材12には、受けランド部を有する内層回路パターン11A,11Bが形成されており、埋込みビア6が内層回路パターン11Aと内層回路パターン11Bを電気的に接続している。この蓋めっき層9は、埋込みビア6と銅箔2,3との接触抵抗を低減し、埋込みビア6の層間接続路としての信頼性を確保する機能も有する。
Through the steps so far, the double-sided circuit substrate 12 shown in FIG. 1B (7) is obtained. Inner layer circuit patterns 11A and 11B having receiving land portions are formed on the double-sided circuit substrate 12, and the embedded via 6 electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B. The lid plating layer 9 also has a function of reducing the contact resistance between the embedded via 6 and the copper foils 2 and 3 and ensuring the reliability of the embedded via 6 as an interlayer connection path.
(8)次に、後述のカバーレイ15の接着材層14との密着性を向上させるために、内層回路パターン11A,11Bの表面に粗化処理を施す。ここでは、日本マクダーミッド(株)のマルチボンド150を用いて粗化処理を行った。その他、(株)荏原電産製のネオブラウンプロセスNBDシリーズなどを用いて粗化処理を行ってもよい。
(8) Next, in order to improve the adhesion of the cover lay 15 described later to the adhesive layer 14, the surface of the inner layer circuit patterns 11A and 11B is subjected to a roughening process. Here, the roughening process was performed using the multi bond 150 of Nippon Macder Mid Co., Ltd. In addition, you may perform a roughening process using the neo-brown process NBD series etc. by Ebara Densan.
前述のように、粗化処理により銅箔2a,3aと接着剤との密着性が向上する反面、銅箔2a,3aにおける炭酸ガスレーザ光の吸収率が増加してしまう。しかし、本実施形態では、ブラインドビアホールの受けランド部を覆う蓋めっき層9の表層には、銅エッチャント耐性を有する銀めっき層9bが形成されている。このため、本工程の粗化処理によって、蓋めっき層9は粗化されず、受けランド部における炭酸ガスレーザ光の吸収率は増加しない。実際に、粗化処理の前後で炭酸ガスレーザ光の吸収率を測定したところ、吸収率は銅箔2a,3aの表面では約20%から約30%に増加したが、銀めっき層9bの表面における吸収率の増加は認められなかった。また、炭酸ガスレーザ光の照射によって銀めっき層9bの下にある銅めっき層9a及び銅箔2a(3a)の厚みが減少しないことからも、レーザ加工に伴う熱ダメージに対する耐性は十分に確保されている。銀めっき層9bは本工程(粗化処理)前において殆ど赤外レーザ光を吸収しないことから、本工程の粗化処理後において赤外レーザ光に対する蓋めっき層9の耐性は十分高く維持される。
As described above, the roughening treatment improves the adhesion between the copper foils 2a and 3a and the adhesive, but increases the absorption rate of the carbon dioxide laser light in the copper foils 2a and 3a. However, in this embodiment, a silver plating layer 9b having copper etchant resistance is formed on the surface layer of the lid plating layer 9 covering the receiving land portion of the blind via hole. For this reason, the lid plating layer 9 is not roughened by the roughening treatment in this step, and the absorption rate of the carbon dioxide laser light in the receiving land portion does not increase. Actually, when the absorption rate of the carbon dioxide laser beam was measured before and after the roughening treatment, the absorption rate increased from about 20% to about 30% on the surfaces of the copper foils 2a and 3a, but on the surface of the silver plating layer 9b. There was no increase in absorption. In addition, since the thickness of the copper plating layer 9a and the copper foil 2a (3a) under the silver plating layer 9b is not reduced by the irradiation of the carbon dioxide laser beam, the resistance to thermal damage caused by laser processing is sufficiently ensured. Yes. Since the silver plating layer 9b hardly absorbs infrared laser light before this step (roughening treatment), the resistance of the lid plating layer 9 to the infrared laser light is maintained sufficiently high after the roughening treatment in this step. .
(9)次に、ポリイミド等からなる絶縁フィルム13(例えば12μm厚)と、絶縁フィルム13の片面に形成された接着剤層14とを有するカバーレイ15を準備する。接着剤層14は、例えばアクリル、エポキシ等の接着剤からなる。そして、真空ラミネータ等を用いて、両面回路基材12にカバーレイ15を貼り付けるラミネート工程を行う。これにより、図1B(8)に示すように、内層回路パターン11A,11B及び蓋めっき層9は接着剤層14により充填される。他の方法として、内層回路パターンを構成11A,11B及び蓋めっき層9を充填する接着剤層14を形成した後、この接着剤層14の上に絶縁フィルム13を形成してもよい。
(9) Next, a coverlay 15 having an insulating film 13 (for example, 12 μm thick) made of polyimide or the like and an adhesive layer 14 formed on one surface of the insulating film 13 is prepared. The adhesive layer 14 is made of an adhesive such as acrylic or epoxy. And the lamination process which affixes the coverlay 15 to the double-sided circuit base material 12 using a vacuum laminator etc. is performed. Thereby, as shown in FIG. 1B (8), the inner layer circuit patterns 11 A and 11 B and the cover plating layer 9 are filled with the adhesive layer 14. As another method, the insulating layer 13 may be formed on the adhesive layer 14 after forming the adhesive layer 14 filling the inner layer circuit pattern with the structures 11A and 11B and the lid plating layer 9.
接着材層14の厚みは、内層回路パターン11A(11B)及び蓋めっき層9を完全に充填できるように決められる。内層回路パターン11A(11B)のうち最も厚い部分はブラインドビアホールの受けランド部である。この受けランド部の厚さは、蓋めっき層9の薄化により、7.5μm(銅箔2a(3a):5μm、蓋めっき層9:2.5μm)と従来よりも小さい。したがって、接着剤層14の厚みは従来よりも大幅に小さい値(8μm)とすることができる。
The thickness of the adhesive layer 14 is determined so that the inner layer circuit pattern 11A (11B) and the lid plating layer 9 can be completely filled. The thickest portion of the inner layer circuit pattern 11A (11B) is a receiving land portion of the blind via hole. The thickness of the receiving land portion is 7.5 μm (copper foil 2a (3a): 5 μm, lid plating layer 9: 2.5 μm), which is smaller than the conventional one due to the thinning of the lid plating layer 9. Therefore, the thickness of the adhesive layer 14 can be set to a value (8 μm) that is significantly smaller than the conventional one.
ここまでの工程を経て、図1B(8)に示す両面コア基板16を得る。
Through the steps so far, a double-sided core substrate 16 shown in FIG. 1B (8) is obtained.
(10)次に、図1C(9)からわかるように、可撓性絶縁ベース材17a(例えば厚さ25μmのポリイミドフィルム)の片面に、銅箔17b(12μm厚)を有する片面銅張積層板17を準備する。そして、フォトファブリケーション手法を用いて、片面銅張積層板17の銅箔17bに、ブラインドビアホールを形成するためのコンフォーマルマスク18(開口部)を形成する。
(10) Next, as can be seen from FIG. 1C (9), a single-sided copper-clad laminate having a copper foil 17b (12 μm thick) on one side of a flexible insulating base material 17a (for example, a polyimide film having a thickness of 25 μm). 17 is prepared. And the conformal mask 18 (opening part) for forming a blind via hole is formed in the copper foil 17b of the single-sided copper clad laminated board 17 using the photofabrication method.
(11)次に、図1C(9)に示すように、コンフォーマルマスク18が形成された片面銅張積層板17を、ビルドアップするための接着剤からなる接着剤層19を介して両面コア基板16に積層接着する。ここで用いる接着材としては、接着剤が可撓性ケーブル部(片面銅張積層板17で覆われない両面コア基板16)に流れ出さないように、ローフロータイプのプリプレグやボンディングシート等といった流れ出しの少ないものが好ましい。なお、未加工の銅箔17bを有する片面銅張積層板17を、接着材層19を介して両面コア基板16に接着した後、銅箔17bを加工し、コンフォーマルマスク18を形成してもよい。
(11) Next, as shown in FIG. 1C (9), the single-sided copper-clad laminate 17 on which the conformal mask 18 is formed is bonded to the double-sided core via an adhesive layer 19 made of an adhesive for building up. The substrate 16 is laminated and adhered. The adhesive used here is a flow-out such as a low-flow type prepreg or a bonding sheet so that the adhesive does not flow out to the flexible cable portion (double-sided core substrate 16 not covered with the single-sided copper-clad laminate 17). Those with less are preferred. Even if the single-sided copper clad laminate 17 having the unprocessed copper foil 17b is bonded to the double-sided core substrate 16 through the adhesive layer 19, the copper foil 17b is processed to form the conformal mask 18. Good.
ここでは、コンフォーマルマスク18の直径は、ブラインドビアホールの受けランド部(蓋めっき層9)の直径200μmに対して80μm小さい値である120μmとした。よって、コンフォーマルマスク18は、±40μmの位置合わせ精度が得られる手法で形成すれば良い。この位置合わせの方法として、例えば次の2つの方法がある。
Here, the diameter of the conformal mask 18 was set to 120 μm, which is 80 μm smaller than the diameter 200 μm of the receiving land portion of the blind via hole (the cover plating layer 9). Therefore, the conformal mask 18 may be formed by a technique that can obtain an alignment accuracy of ± 40 μm. As this alignment method, for example, there are the following two methods.
1つめの方法は、コンフォーマルマスク18を形成した後、片面銅張積層板17を両面コア基板16に積層する場合の方法である。この方法では、両面コア基板16にターゲットマークを予め形成しておく。そして、このターゲットマークを用いて片面銅張積層板17の位置合わせを行った後、片面銅張積層板17を両面コア基板16に積層する。
The first method is a method in which the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16 after the conformal mask 18 is formed. In this method, target marks are formed in advance on the double-sided core substrate 16. Then, after aligning the single-sided copper-clad laminate 17 using this target mark, the single-sided copper-clad laminate 17 is laminated on the double-sided core substrate 16.
2つめの方法は、片面銅張積層板17を両面コア基板16に積層接着した後にコンフォーマルマスク18を形成する場合の方法である。この方法では、まず、両面コア基板16にターゲットマークを予め形成しておく。そして、片面銅張積層板17を両面コア基板16に積層接着し、銅箔17b上にレジスト層を形成する。その後、露光用のフォトマスクに設けられた基準位置を示すマークと、両面コア基板16のターゲットマークを用いて、両面コア基板16とフォトマスクの位置合わせを行う。そして、レジスト層への露光および現像を行い、銅箔17bの所定の位置にコンフォーマルマスク18を形成する。
The second method is a method in which the conformal mask 18 is formed after the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16. In this method, first, target marks are formed in advance on the double-sided core substrate 16. Then, the single-sided copper-clad laminate 17 is laminated and bonded to the double-sided core substrate 16 to form a resist layer on the copper foil 17b. Thereafter, the double-sided core substrate 16 and the photomask are aligned using the mark indicating the reference position provided on the photomask for exposure and the target mark of the double-sided core substrate 16. Then, the resist layer is exposed and developed to form a conformal mask 18 at a predetermined position on the copper foil 17b.
(12)次に、図1C(10)に示すように、前工程で形成したコンフォーマルマスク18を用いてレーザ加工を行い、底面に蓋めっき層9が露出したブラインドビアホール20A,20B(導通用孔)を形成する。より詳細には、コンフォーマルマスク18における可撓性絶縁ベース材17a、接着剤層19、絶縁フィルム13及び接着剤層14を除去する。本工程のレーザ加工法においては、加工速度が速く、生産性に優れた炭酸ガスレーザを用いることが好ましいが、より一般的には赤外レーザを用いることができる。
(12) Next, as shown in FIG. 1C (10), laser processing is performed using the conformal mask 18 formed in the previous step, and the blind via holes 20A and 20B with the cover plating layer 9 exposed on the bottom surface (for conduction) Hole). More specifically, the flexible insulating base material 17a, the adhesive layer 19, the insulating film 13, and the adhesive layer 14 in the conformal mask 18 are removed. In the laser processing method in this step, it is preferable to use a carbon dioxide laser having a high processing speed and excellent productivity, but more generally, an infrared laser can be used.
ここで、本工程におけるレーザ加工の詳細について説明する。炭酸ガスレーザ加工機としては、三菱電機(株)製のML605GTXIII-5100U2を用いた。所定のアパーチャー等でレーザのビーム径を200μmに調整し、レーザ照射位置を調整した後、パルス幅10μSec,パルスエネルギー5mJのレーザパルスを5ショット照射して、ブラインドビアホール20A,20Bを形成した。蓋めっき層9の厚みは2.5μmと薄いものの、銀めっき層9bの炭酸ガスレーザ光の吸収が少ないことから、レーザ光が蓋めっき層9を貫通したり、蓋めっき層9が埋込みビア6から剥離することなく、レーザ加工を行うことができる。
Here, the details of the laser processing in this step will be described. As the carbon dioxide laser processing machine, ML605GTXIII-5100U2 manufactured by Mitsubishi Electric Corporation was used. The laser beam diameter was adjusted to 200 μm with a predetermined aperture or the like, the laser irradiation position was adjusted, and then 5 shots of laser pulses with a pulse width of 10 μSec and a pulse energy of 5 mJ were irradiated to form blind via holes 20A and 20B. Although the thickness of the lid plating layer 9 is as thin as 2.5 μm, the absorption of the carbon dioxide laser beam of the silver plating layer 9 b is small, so that the laser beam penetrates the lid plating layer 9 or the lid plating layer 9 extends from the embedded via 6. Laser processing can be performed without peeling.
(13)次に、ブラインドビアホール20A,20Bを形成する際に生じた樹脂残渣を除去するために、デスミア工程を行う。
(13) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 20A and 20B are formed.
(14)次に、図1D(11)に示すように、導電化処理とそれに続く電解銅めっき処理を施すことにより、ブラインドビアホール20A,20Bの内壁(側面および底面)及び銅箔17b上に、電解銅めっき皮膜21を形成する。この電解銅めっき皮膜21の厚みは、層間導通を確保するために15~20μm程度とした。これにより、外層の導電膜(銅箔17bと電解銅めっき皮膜21)と内層回路パターン11A,11Bを電気的に接続し、層間導電路として機能するブラインドビア22A,22Bが形成される。
(14) Next, as shown in FIG. 1D (11), by conducting a conductive treatment and subsequent electrolytic copper plating treatment, on the inner walls (side and bottom surfaces) of the blind via holes 20A and 20B and the copper foil 17b, An electrolytic copper plating film 21 is formed. The thickness of the electrolytic copper plating film 21 was set to about 15 to 20 μm in order to ensure interlayer conduction. As a result, the outer conductive film (copper foil 17b and electrolytic copper plating film 21) and the inner circuit patterns 11A and 11B are electrically connected to form blind vias 22A and 22B that function as interlayer conductive paths.
(15)次に、図1D(12)に示すように、フォトファブリケーション手法により、可撓性絶縁ベース材17a上の導電層(銅箔17b及びその上の電解銅めっき被膜21)を所定のパターンに加工して、外層回路パターン23を形成する。
(15) Next, as shown in FIG. 1D (12), a conductive layer on the flexible insulating base material 17a (copper foil 17b and the electrolytic copper plating film 21 thereon) is formed in a predetermined manner by a photofabrication technique. The outer layer circuit pattern 23 is formed by processing into a pattern.
この後、図示しないが、必要に応じて、はんだ付けが不要な部分には保護用のフォトソルダーレジスト層を形成し、ランド部等の表面には半田めっき、ニッケルめっき、金めっき等の表面処理を施す。その後、金型による抜き打ち等により外形加工を行う。
After this, although not shown, if necessary, a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
以上の工程を経て、第1の実施形態に係るビルドアップ型多層プリント配線板24を得る。ビルドアップ型多層プリント配線板24の両面コア基板16は、可撓性絶縁ベース材1と、可撓性絶縁ベース材1の両面に設けられ、受けランド部を有する内層回路パターン11A,11Bと、可撓性絶縁ベース材1と受けランド部を貫通し、内層回路パターン11Aと内層回路パターン11Bを電気的に接続する埋込みビア6を備える。また、埋込みビア6が露出した受けランド部を被覆し、且つ表層が内層回路パターン11A,11Bを構成する金属のエッチャントに対して耐性を有する材料からなる蓋めっき層9を有する。
Through the above steps, the build-up type multilayer printed wiring board 24 according to the first embodiment is obtained. The double-sided core substrate 16 of the build-up type multilayer printed wiring board 24 includes a flexible insulating base material 1 and inner layer circuit patterns 11A and 11B provided on both surfaces of the flexible insulating base material 1 and having receiving land portions, An embedded via 6 that penetrates the flexible insulating base material 1 and the receiving land portion and electrically connects the inner layer circuit pattern 11A and the inner layer circuit pattern 11B is provided. Further, a cover plating layer 9 made of a material that covers the receiving land portion where the embedded via 6 is exposed and whose surface layer is resistant to the metal etchant constituting the inner layer circuit patterns 11A and 11B is provided.
両面コア基板16の上には、接着剤層19を介して、表面に外層回路パターン23が設けられたビルドアップ層が積層されている。
On the double-sided core substrate 16, a buildup layer having an outer layer circuit pattern 23 provided on the surface is laminated via an adhesive layer 19.
ブラインドビア22A及び22Bはビルドアップ層を厚さ方向に貫通し、底面に蓋めっき層9が露出したブラインドビアホール20A,20Bの内壁に形成されためっき皮膜からなり、蓋めっき層9を介して内層回路パターン11A,11Bと外層回路パターン23を電気的に接続している。さらに、図1D(12)に示すように、ブラインドビア22Aは蓋めっき層9を介して、埋込みビア6上に重なるように配置されている。このように、本実施形態に係るビルドアップ型多層プリント配線板24は、埋込みビア6とブラインドビア22Aから構成されるスタックビア構造を有する。
The blind vias 22A and 22B are made of a plating film formed on the inner walls of the blind via holes 20A and 20B that penetrate the build-up layer in the thickness direction and the cover plating layer 9 is exposed on the bottom surface. The circuit patterns 11A and 11B and the outer layer circuit pattern 23 are electrically connected. Further, as shown in FIG. 1D (12), the blind via 22A is arranged so as to overlap the embedded via 6 with the lid plating layer 9 interposed therebetween. Thus, the build-up type multilayer printed wiring board 24 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 22A.
図1D(12)に示すように、ビルドアップ型多層プリント配線板24は、両面コア基板16にビルドアップ層が積層された部品実装部24aと、この部品実装部24aから延伸する可撓性ケーブル部24bとを有する。この可撓性ケーブル部24bは、ビルドアップ層が設けられていない両面コア基板16の一部である。この可撓性ケーブル部24bは必須の構成要素ではなく、設けられていなくともよい。
As shown in FIG. 1D (12), the build-up type multilayer printed wiring board 24 includes a component mounting portion 24a in which a build-up layer is laminated on the double-sided core substrate 16, and a flexible cable extending from the component mounting portion 24a. Part 24b. The flexible cable portion 24b is a part of the double-sided core substrate 16 where the buildup layer is not provided. The flexible cable portion 24b is not an essential component and may not be provided.
なお、本実施形態では、両面コア基板16の表面および裏面にビルドアップ層を設けたが、片面にのみビルドアップ層を設けるようにしてもよい。
In the present embodiment, the buildup layers are provided on the front and back surfaces of the double-sided core substrate 16, but the buildup layers may be provided only on one side.
以上説明したように、本実施形態では、ビルドアップ層を貫通するブラインドビアホール20A,20Bの受けランド部となる領域に、蓋めっき層9を形成しておく。この蓋めっき層9の表層は、銅のエッチャントに対して耐性があるめっき層(銀めっき層9bなど)で構成される。これにより、銅膜2a,3aを粗化する際に蓋めっき層9は粗化されないため、ブラインドビアホール20A,20Bをレーザ加工で形成する際、受けランド部(蓋めっき層9)の表面におけるレーザ光の吸収はほとんどなく、蓋めっき層9は薄い場合でもレーザ光による熱ダメージを受けない。したがって、蓋めっき層9を従来に比べて大幅に薄くすることができる。
As described above, in the present embodiment, the lid plating layer 9 is formed in the region that becomes the receiving land portion of the blind via holes 20A and 20B that penetrate the build-up layer. The surface layer of the lid plating layer 9 is composed of a plating layer (silver plating layer 9b or the like) resistant to a copper etchant. Thereby, since the lid plating layer 9 is not roughened when the copper films 2a and 3a are roughened, the laser on the surface of the receiving land portion (lid plating layer 9) is formed when the blind via holes 20A and 20B are formed by laser processing. There is almost no light absorption, and even when the lid plating layer 9 is thin, it is not damaged by the laser beam. Therefore, the lid plating layer 9 can be made much thinner than conventional.
蓋めっき層9の薄化により、カバーレイ15の接着材層14を薄くすることができる。これにより、ブラインドビアホール20A,20Bを浅く形成することができる。例えば、従来に比べて10μm程度小さくなる。これにより、ブラインドビアホール20A,20Bの内壁に対する電解銅めっき皮膜21の電着容易性が向上する。さらに、多層プリント配線板の構成部材が熱膨張することによる、ブラインドビア22A,22Bへの影響が低減する。ビルドアップ型多層プリント配線板24を構成する部材のうち、接着剤層14を構成する接着剤は特に熱膨張率が大きいため、接着剤層14が薄くなることによる効果は大きい。このため、歩留まりの向上及び接続信頼性を確保するのに必要な電解銅めっき皮膜21の厚みを低減することができる。この結果、本実施形態によれば、微細な外層回路パターン23を形成することが可能となり、高密度実装の要求を満たす、スタックビア構造を有するビルドアップ型多層プリント配線板24を得ることができる。
By thinning the lid plating layer 9, the adhesive layer 14 of the coverlay 15 can be thinned. Thereby, the blind via holes 20A and 20B can be formed shallowly. For example, it is about 10 μm smaller than the conventional one. Thereby, the electrodeposition easiness of the electrolytic copper plating film | membrane 21 with respect to the inner wall of blind via- hole 20A, 20B improves. Furthermore, the influence on the blind vias 22A and 22B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced. Of the members constituting the build-up type multilayer printed wiring board 24, the adhesive constituting the adhesive layer 14 has a particularly large coefficient of thermal expansion, so that the effect of making the adhesive layer 14 thinner is great. For this reason, it is possible to reduce the thickness of the electrolytic copper plating film 21 necessary for improving yield and ensuring connection reliability. As a result, according to the present embodiment, it is possible to form a fine outer layer circuit pattern 23, and it is possible to obtain a build-up type multilayer printed wiring board 24 having a stacked via structure that satisfies the requirements for high-density mounting. .
さらに、内層回路パターン11を形成するために銅箔2a,3aをエッチングの際、蓋めっき層9は銅エッチャント耐性を有するため、蓋めっき層9を保護するためのレジスト層を設ける必要がない。これにより、本発明によれば、蓋めっき層9で被覆された受けランド部(銅箔2a,3a)の径を蓋めっき層9と同じにすることができ、内層回路パターンの高密度化を図ることができる。また、高精度な位置合わせが可能な露光機を用いなくてもよいため、生産性を向上させるとともに、安価にプリント配線板を製造することができる。
Furthermore, when the copper foils 2a and 3a are etched to form the inner layer circuit pattern 11, since the lid plating layer 9 has copper etchant resistance, it is not necessary to provide a resist layer for protecting the lid plating layer 9. Thereby, according to this invention, the diameter of the receiving land part ( copper foil 2a, 3a) coat | covered with the lid plating layer 9 can be made the same as the lid plating layer 9, and densification of an inner-layer circuit pattern can be carried out. Can be planned. In addition, since it is not necessary to use an exposure machine capable of highly accurate alignment, productivity can be improved and a printed wiring board can be manufactured at low cost.
さらに、スタックビア構造を構成しないブラインドビアホール20Bについても、受けランド部に蓋めっき層9を設けている。このため、ブラインドビアホール20Bの構造(ビアの深さ等)は、スタックビア構造用のブラインドビアホール20Aとほぼ同じになる。よって、スタックビア構造用か否かに拘わらず、ブラインドビアホールを形成する際のレーザ加工の条件及びデスミア工程の条件を同一とすることができる。その結果、本実施形態によれば、大きな加工マージンを確保することができるとともに、生産性を向上させることができる。
Furthermore, a lid plating layer 9 is provided on the receiving land portion of the blind via hole 20B that does not constitute a stacked via structure. Therefore, the structure of the blind via hole 20B (via depth and the like) is substantially the same as the blind via hole 20A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to the present embodiment, a large processing margin can be ensured and productivity can be improved.
(第2の実施形態)
次に、第2の実施形態に係るビルドアップ型多層プリント配線板について説明する。第2の実施形態と第1の実施形態の相違点の一つは、第2の実施形態に係るビルドアップ型多層プリント配線板は可撓性ケーブル部における可撓性絶縁ベース材上に内層端子を有し、この内層端子の表面を保護するめっき層を、埋込みビア及び受けランド部の上に形成する蓋めっき層と同じめっき工程で形成することである。これにより、工程数を削減し、生産性を向上させることができる。 (Second Embodiment)
Next, a build-up type multilayer printed wiring board according to the second embodiment will be described. One of the differences between the second embodiment and the first embodiment is that the build-up type multilayer printed wiring board according to the second embodiment has an inner layer terminal on the flexible insulating base material in the flexible cable portion. The plating layer that protects the surface of the inner layer terminal is formed in the same plating step as the lid plating layer formed on the embedded via and the receiving land portion. Thereby, the number of processes can be reduced and productivity can be improved.
次に、第2の実施形態に係るビルドアップ型多層プリント配線板について説明する。第2の実施形態と第1の実施形態の相違点の一つは、第2の実施形態に係るビルドアップ型多層プリント配線板は可撓性ケーブル部における可撓性絶縁ベース材上に内層端子を有し、この内層端子の表面を保護するめっき層を、埋込みビア及び受けランド部の上に形成する蓋めっき層と同じめっき工程で形成することである。これにより、工程数を削減し、生産性を向上させることができる。 (Second Embodiment)
Next, a build-up type multilayer printed wiring board according to the second embodiment will be described. One of the differences between the second embodiment and the first embodiment is that the build-up type multilayer printed wiring board according to the second embodiment has an inner layer terminal on the flexible insulating base material in the flexible cable portion. The plating layer that protects the surface of the inner layer terminal is formed in the same plating step as the lid plating layer formed on the embedded via and the receiving land portion. Thereby, the number of processes can be reduced and productivity can be improved.
図2A~図2Dを用いて、本実施形態に係るスタックビア構造を有するビルドアップ型多層プリント配線板の製造方法について説明する。図2A~図2Dは、本実施形態に係るビルドアップ型多層プリント配線板の製造方法を示す工程断面図である。
A method for manufacturing a build-up type multilayer printed wiring board having a stack via structure according to the present embodiment will be described with reference to FIGS. 2A to 2D. 2A to 2D are process cross-sectional views illustrating a method for manufacturing a build-up type multilayer printed wiring board according to the present embodiment.
第1の実施形態の図1A(3)に示す基材を得るまでの工程は、第1の実施形態と同じであるため、説明を省略し、それ以降の工程から説明する。
Since the process until obtaining the base material shown in FIG. 1A (3) of the first embodiment is the same as that of the first embodiment, the description thereof will be omitted and the subsequent processes will be described.
(1)図2A(1)に示すように、基材の両面に電解銅めっき処理を施し、銅箔2a及び3aと、露出した埋込みビア6の上に、電解銅めっき皮膜31及び32(各2μm厚)を形成する。
(1) As shown in FIG. 2A (1), electrolytic copper plating treatment is performed on both surfaces of the base material, and electrolytic copper plating films 31 and 32 (respectively on the copper foils 2a and 3a and the exposed embedded via 6) 2 μm thick).
(2)次に、図2A(2)に示すように、後述の内層回路パターン34A,34Bを形成するための、所定のパターンを有するエッチングレジスト層33を、電解銅めっき皮膜31及び32の上に形成する。
(2) Next, as shown in FIG. 2A (2), an etching resist layer 33 having a predetermined pattern is formed on the electrolytic copper plating films 31 and 32 to form inner layer circuit patterns 34A and 34B described later. To form.
(3)次に、図2A(3)に示すように、エッチングレジスト層33を用いて、電解銅めっき皮膜31,32及び銅箔2a,3aをエッチングし、それにより、ブラインドビアホールの受けランド部を有する内層回路パターン34A及び34Bを形成する。その後、エッチングレジスト層33を剥離する。本工程のエッチングでは、例えば、塩化第二銅又は塩化第二鉄を用いたエッチャントを用いることができる。
(3) Next, as shown in FIG. 2A (3), using the etching resist layer 33, the electrolytic copper plating films 31, 32 and the copper foils 2a, 3a are etched, thereby receiving blind via hole receiving land portions. Inner layer circuit patterns 34A and 34B are formed. Thereafter, the etching resist layer 33 is peeled off. In the etching in this step, for example, an etchant using cupric chloride or ferric chloride can be used.
(4)次に、図2B(4)からわかるように、前工程で得られた基材の両面にめっきレジスト層35を形成する。このめっきレジスト層35は、ブラインドビアホールの受けランド部に開口部36bを有し、さらに、内層端子が形成される領域に開口部36cを有する。なお、図2B(4)に示すように、めっきレジスト層35は、埋込みビア6が露出している領域に開口部36aを有してもよい。この開口部36aを設けるか否かは任意である。
(4) Next, as can be seen from FIG. 2B (4), a plating resist layer 35 is formed on both surfaces of the base material obtained in the previous step. The plating resist layer 35 has an opening 36b in the receiving land portion of the blind via hole, and further has an opening 36c in a region where the inner layer terminal is formed. 2B (4), the plating resist layer 35 may have an opening 36a in a region where the embedded via 6 is exposed. Whether or not the opening 36a is provided is arbitrary.
(5)次に、図2B(4)に示すように、めっきレジスト層35を用いて電解または無電解めっきを行うことにより、めっきレジスト層35の開口部36a,36b,36cに露出した電解銅めっき皮膜31及び32上に、銀めっき層からなる蓋めっき層37(0.5μm厚)を形成する。その後、めっきレジスト層35を剥離する。なお、めっきリードが繋がらない部分が存在する場合、無電解めっきを行う。図2B(4)からわかるように、本工程のめっき処理により、開口部36cに露出した内層端子となる内層回路パターンの一部にも、端子保護膜となる銀めっき層(蓋めっき層37)が形成され、内層端子50が完成する。
(5) Next, as shown in FIG. 2B (4), electrolytic copper exposed to the openings 36a, 36b, 36c of the plating resist layer 35 by performing electrolysis or electroless plating using the plating resist layer 35. A lid plating layer 37 (0.5 μm thickness) made of a silver plating layer is formed on the plating films 31 and 32. Thereafter, the plating resist layer 35 is peeled off. If there is a portion where the plating lead is not connected, electroless plating is performed. As can be seen from FIG. 2B (4), a silver plating layer (lid plating layer 37) serving as a terminal protective film is formed on a part of the inner layer circuit pattern serving as an inner layer terminal exposed to the opening 36c by the plating process in this step. Is formed, and the inner layer terminal 50 is completed.
蓋めっき層37の表層を構成するめっき層は、後の粗化処理で用いられる銅エッチャントに対する耐性を有することが必要である。銀めっき層はこの条件を満たす。また、蓋めっき層37として、銅めっき層の代わりに、無電解ニッケルめっきによるニッケルめっき層、又は無電解金めっきによる金めっき層を形成してもよい。他に、蓋めっき層37として、無電解ニッケルめっきによるニッケルめっき層、及び無電解金めっきによる金めっき層を順次形成してもよい。このように、蓋めっき層37は、少なくとも表層が銀(Ag)、金(Au)、ニッケル(Ni)などといった銅のエッチャントに対して耐性を有する材料からなるという条件下で、銀、金、ニッケル等からなるめっき層を、単独もしくは複数組み合わせて構成することができる。これらいずれの場合であっても以降の工程を変更する必要はなく、銀めっき層を形成した場合と同様の効果が得られる。蓋めっき層37の構成は、生産性及びコスト等のほか、内層端子への接続方式を考慮して選択される。
The plating layer constituting the surface layer of the lid plating layer 37 needs to have resistance to the copper etchant used in the subsequent roughening treatment. The silver plating layer satisfies this condition. Further, as the lid plating layer 37, a nickel plating layer by electroless nickel plating or a gold plating layer by electroless gold plating may be formed instead of the copper plating layer. In addition, as the lid plating layer 37, a nickel plating layer by electroless nickel plating and a gold plating layer by electroless gold plating may be sequentially formed. Thus, the lid plating layer 37 is made of silver, gold, under the condition that at least the surface layer is made of a material resistant to a copper etchant such as silver (Ag), gold (Au), nickel (Ni). The plating layer which consists of nickel etc. can be comprised individually or in combination. In any of these cases, it is not necessary to change the subsequent steps, and the same effect as when the silver plating layer is formed can be obtained. The configuration of the lid plating layer 37 is selected in consideration of productivity, cost, and the connection method to the inner layer terminal.
ここまでの工程を経て、図2B(5)に示す両面回路基材38を得る。
Through the steps so far, a double-sided circuit substrate 38 shown in FIG. 2B (5) is obtained.
(6)次に、ビルドアップ層の積層に用いる接着材(後述の接着材層40)との密着性を向上させるために、内層回路パターン34A及び34Bの表面に粗化処理を施す。この粗化処理は第1の実施形態で説明した方法と同様にして行うことができる。
(6) Next, in order to improve the adhesiveness with the adhesive (adhesive layer 40 described later) used for stacking the buildup layers, the surface of the inner layer circuit patterns 34A and 34B is roughened. This roughening process can be performed in the same manner as the method described in the first embodiment.
本実施形態においては、後にレーザ光を照射される受けランド部を被覆する蓋めっき層37は、銅エッチャント耐性を有する銀めっき層で構成されている。このため、本工程の粗化処理によって、蓋めっき層37は粗化されない。したがって、受けランド部における炭酸ガスレーザ光の吸収率は増加せず、低い吸収率が維持される。
In the present embodiment, the lid plating layer 37 that covers the receiving land portion to be irradiated with laser light later is composed of a silver plating layer having copper etchant resistance. For this reason, the lid plating layer 37 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.
(7)次に、ポリイミド等からなる絶縁フィルム39(例えば12μm厚)と、絶縁フィルム39の片面に形成された接着剤層40とを有するカバーレイ41を準備する。接着剤層40は、例えばアクリル、エポキシ等の接着剤からなる。そして、真空ラミネータ等を用いて、両面回路基材38にカバーレイ41を貼り付けるラミネート工程を行う。これにより、図2B(6)に示すように、部品実装部における内層回路パターン34A,34B及び蓋めっき層37は接着剤層40により充填される。他の方法として、内層回路パターンを構成34A,34B及び蓋めっき層37を充填する接着剤層40を形成した後、この接着剤層40の上に絶縁フィルム39を形成してもよい。
(7) Next, a cover lay 41 having an insulating film 39 (for example, 12 μm thick) made of polyimide or the like and an adhesive layer 40 formed on one surface of the insulating film 39 is prepared. The adhesive layer 40 is made of an adhesive such as acrylic or epoxy. And the lamination process which affixes the coverlay 41 to the double-sided circuit base material 38 is performed using a vacuum laminator etc. Thereby, as shown in FIG. 2B (6), the inner layer circuit patterns 34 A and 34 B and the lid plating layer 37 in the component mounting portion are filled with the adhesive layer 40. As another method, the insulating layer 39 may be formed on the adhesive layer 40 after forming the adhesive layer 40 filling the inner layer circuit pattern with the structures 34 </ b> A and 34 </ b> B and the lid plating layer 37.
この接着材層40の厚みは、内層回路パターン34A(34B)及び蓋めっき層37を完全に充填できるように決められる。内層回路パターン34A(34B)のうち最も厚い受けランド部の厚さは、7.5μm(銅箔2a(3a):5μm、電解銅めっき皮膜31(32):2μm、蓋めっき層37:0.5μm)である。したがって、接着剤層40の厚みは従来よりも大幅に小さい値(8μm)とすることができる。
The thickness of the adhesive layer 40 is determined so that the inner layer circuit pattern 34A (34B) and the lid plating layer 37 can be completely filled. Among the inner layer circuit pattern 34A (34B), the thickness of the thickest receiving land portion is 7.5 μm (copper foil 2a (3a): 5 μm, electrolytic copper plating film 31 (32): 2 μm, lid plating layer 37: 0. 5 μm). Therefore, the thickness of the adhesive layer 40 can be set to a value (8 μm) that is significantly smaller than the conventional one.
ここまでの工程を経て、図2B(6)に示す両面コア基板42を得る。
Through the steps so far, a double-sided core substrate 42 shown in FIG. 2B (6) is obtained.
(8)次に、図2C(7)からわかるように、可撓性絶縁ベース材43a(例えば厚さ25μmのポリイミドフィルム)の片面に、銅箔43b(12μm厚)を有する片面銅張積層板43を準備する。そして、第1の実施形態と同様にして、フォトファブリケーション手法を用いて、片面銅張積層板43の銅箔43bに、ブラインドビアホールを形成するためのコンフォーマルマスク44(開口部)を形成する。
(8) Next, as can be seen from FIG. 2C (7), a single-sided copper-clad laminate having a copper foil 43b (12 μm thick) on one side of a flexible insulating base material 43a (for example, a polyimide film having a thickness of 25 μm). Prepare 43. In the same manner as in the first embodiment, a conformal mask 44 (opening) for forming blind via holes is formed in the copper foil 43b of the single-sided copper-clad laminate 43 using a photofabrication technique. .
(9)次に、図2C(7)に示すように、第1の実施形態と同様にして、コンフォーマルマスク44が形成された片面銅張積層板43を、ビルドアップするための接着剤からなる接着剤層45を介して両面コア基板42の表面及び裏面に積層接着する。
(9) Next, as shown in FIG. 2C (7), in the same manner as in the first embodiment, the single-sided copper-clad laminate 43 on which the conformal mask 44 is formed is made of an adhesive for build-up. The adhesive layer 45 is laminated and adhered to the front and back surfaces of the double-sided core substrate 42.
(10)次に、図2C(8)に示すように、第1の実施形態と同様にして、コンフォーマルマスク44を用いてレーザ加工を行い、ブラインドビアホール46A,46B(導通用孔)を形成する。
(11)次に、ブラインドビアホール46A,46Bを形成する際に生じた樹脂残渣を除去するために、デスミア工程を行う。 (10) Next, as shown in FIG. 2C (8), the blind via holes 46A and 46B (conduction holes) are formed by performing laser processing using the conformal mask 44 in the same manner as in the first embodiment. To do.
(11) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 46A and 46B are formed.
(11)次に、ブラインドビアホール46A,46Bを形成する際に生じた樹脂残渣を除去するために、デスミア工程を行う。 (10) Next, as shown in FIG. 2C (8), the blind via
(11) Next, a desmear process is performed in order to remove the resin residue generated when the blind via
(12)次に、図2D(9)に示すように、導電化処理とそれに続く電解銅めっき処理を施すことにより、ブラインドビアホール46A,46Bの内壁(側面および底面)及び蓋めっき層37上に、電解銅めっき皮膜47を形成する。この電解銅めっき皮膜47の厚みは、層間導通を確保するために15~20μm程度とした。これにより、層間導電路として機能するブラインドビア48A,48Bが形成される。
(12) Next, as shown in FIG. 2D (9), by conducting a conductive treatment and a subsequent electrolytic copper plating treatment, the inner walls (side and bottom surfaces) of the blind via holes 46A and 46B and the lid plating layer 37 are formed. Then, an electrolytic copper plating film 47 is formed. The thickness of the electrolytic copper plating film 47 was set to about 15 to 20 μm in order to ensure interlayer conduction. Thereby, blind vias 48A and 48B functioning as interlayer conductive paths are formed.
(13)次に、図2D(10)に示すように、フォトファブリケーション手法により、ビルドアップ層上の導電層(銅箔43b及びその上の電解銅めっき被膜47)を所定のパターンに加工して、外層回路パターン49を形成する。
(13) Next, as shown in FIG. 2D (10), the conductive layer on the build-up layer (copper foil 43b and electrolytic copper plating film 47 thereon) is processed into a predetermined pattern by a photofabrication technique. Thus, the outer layer circuit pattern 49 is formed.
この後、図示しないが、必要に応じて、はんだ付けが不要な部分には保護用のフォトソルダーレジスト層を形成し、ランド部等の表面には半田めっき、ニッケルめっき、金めっき等の表面処理を施す。その後、金型による抜き打ち等により外形加工を行う。
After this, although not shown, if necessary, a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
以上の工程を経て、第2の実施形態に係るビルドアップ型多層プリント配線板51を得る。図2D(10)に示すように、本実施形態に係るビルドアップ型多層プリント配線板51は、埋込みビア6とブラインドビア48Aから構成されるスタックビア構造を有する。
Through the above steps, the build-up type multilayer printed wiring board 51 according to the second embodiment is obtained. As shown in FIG. 2D (10), the build-up type multilayer printed wiring board 51 according to the present embodiment has a stacked via structure including embedded vias 6 and blind vias 48A.
また、図2D(10)に示すように、ビルドアップ型多層プリント配線板51は、両面コア基板42にビルドアップ層が積層された部品実装部51aと、この部品実装部51aから延伸する可撓性ケーブル部51bとを有する。この可撓性ケーブル部51bは、ビルドアップ層が設けられていない両面コア基板42の一部である。この可撓性ケーブル部51bには、可撓性絶縁ベース材1上に露出した内層端子50が設けられている。この内層端子50の表面には蓋めっき層37と同じ材料からなる保護めっき膜が形成されている。なお、内層端子50を可撓性絶縁ベース材1上に複数形成し、可撓性のコネクタ領域を構成してもよい。
Further, as shown in FIG. 2D (10), the build-up type multilayer printed wiring board 51 includes a component mounting part 51a in which a build-up layer is laminated on a double-sided core substrate 42, and a flexible film extending from the component mounting part 51a. Cable portion 51b. The flexible cable portion 51b is a part of the double-sided core substrate 42 that is not provided with a buildup layer. The flexible cable portion 51 b is provided with an inner layer terminal 50 exposed on the flexible insulating base material 1. A protective plating film made of the same material as the lid plating layer 37 is formed on the surface of the inner layer terminal 50. A plurality of inner layer terminals 50 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.
なお、本実施形態では、両面コア基板42の表面および裏面にビルドアップ層を設けたが、片面にのみビルドアップ層を設けるようにしてもよい。
In the present embodiment, the buildup layers are provided on the front and back surfaces of the double-sided core substrate 42, but the buildup layers may be provided only on one side.
以上、説明したように、本実施形態によれば、内層端子50の表面めっき層の形成を、蓋めっき層37の形成と同時に行うことができる。これにより、工程数を削減し、生産性を向上させることが可能となる。
As described above, according to the present embodiment, the surface plating layer of the inner layer terminal 50 can be formed simultaneously with the formation of the lid plating layer 37. Thereby, it becomes possible to reduce the number of processes and improve productivity.
さらに、本実施形態によれば、次の効果を得ることができる。
Furthermore, according to the present embodiment, the following effects can be obtained.
まず、第1の実施形態と同様、蓋めっき層37の薄化により、カバーレイ41の接着剤層40を従来に比べて大幅に薄くすることができる。これにより、ブラインドビアホール46A,46Bを浅く形成することができる。例えば、従来に比べて10μm程度小さくなる。これにより、ブラインドビアホール46A,46Bの内壁に対する電解銅めっき皮膜47の電着容易性が向上する。さらに、多層プリント配線板の構成部材が熱膨張することによる、ブラインドビア48A,48Bへの影響が低減する。このため、歩留まりの向上及び接続信頼性を確保するのに必要な電解銅めっき皮膜47の厚みを低減することができる。この結果、本実施形態によれば、微細な外層回路パターン49を形成することが可能となり、高密度実装の要求を満たす、スタックビア構造を有するビルドアップ型多層プリント配線板51を得ることができる。
First, as in the first embodiment, by thinning the lid plating layer 37, the adhesive layer 40 of the cover lay 41 can be made much thinner than before. Thereby, the blind via holes 46A and 46B can be formed shallowly. For example, it is about 10 μm smaller than the conventional one. Thereby, the ease of electrodeposition of the electrolytic copper plating film 47 to the inner walls of the blind via holes 46A and 46B is improved. Furthermore, the influence on the blind vias 48A and 48B due to the thermal expansion of the constituent members of the multilayer printed wiring board is reduced. For this reason, it is possible to reduce the thickness of the electrolytic copper plating film 47 necessary for improving yield and ensuring connection reliability. As a result, according to the present embodiment, it is possible to form a fine outer layer circuit pattern 49, and to obtain a build-up type multilayer printed wiring board 51 having a stack via structure that satisfies the requirements for high-density mounting. .
さらに、スタックビア構造を構成しないブラインドビアホール46Bについても、受けランド部に蓋めっき層37を設けている。このため、ブラインドビアホール48Bの構造(ビアの深さ等)は、スタックビア構造用のブラインドビアホール48Aとほぼ同じになる。よって、スタックビア構造用か否かに拘わらず、ブラインドビアホールを形成する際のレーザ加工の条件及びデスミア工程の条件を同一とすることができる。その結果、本実施形態によれば、大きな加工マージンを確保することができ、生産性を向上させることができる。
Furthermore, a lid plating layer 37 is provided on the receiving land portion of the blind via hole 46B that does not constitute a stacked via structure. For this reason, the structure of the blind via hole 48B (via depth and the like) is substantially the same as the blind via hole 48A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.
(第3の実施形態)
次に、第3の実施形態に係るビルドアップ型多層プリント配線板について説明する。第3の実施形態と第2の実施形態の相違点の一つは、カバーレイを、部品実装部の内部には設けず、プリント配線板の部品実装部と可撓性ケーブル部との境界領域に設けることである。これにより、部品実装部の内層回路パターンを充填する接着剤の流れ出しを考慮する必要がなくなるため、接着剤の選択肢が広がる。さらに、部品実装部におけるプリント配線板の厚みを低減することができるため、外層回路パターンをより微細化することができる。 (Third embodiment)
Next, a build-up type multilayer printed wiring board according to the third embodiment will be described. One of the differences between the third embodiment and the second embodiment is that the coverlay is not provided inside the component mounting portion, and the boundary region between the component mounting portion of the printed wiring board and the flexible cable portion. It is to provide. As a result, there is no need to consider the flow of the adhesive filling the inner layer circuit pattern of the component mounting portion, so the options for the adhesive are expanded. Furthermore, since the thickness of the printed wiring board in the component mounting portion can be reduced, the outer layer circuit pattern can be further miniaturized.
次に、第3の実施形態に係るビルドアップ型多層プリント配線板について説明する。第3の実施形態と第2の実施形態の相違点の一つは、カバーレイを、部品実装部の内部には設けず、プリント配線板の部品実装部と可撓性ケーブル部との境界領域に設けることである。これにより、部品実装部の内層回路パターンを充填する接着剤の流れ出しを考慮する必要がなくなるため、接着剤の選択肢が広がる。さらに、部品実装部におけるプリント配線板の厚みを低減することができるため、外層回路パターンをより微細化することができる。 (Third embodiment)
Next, a build-up type multilayer printed wiring board according to the third embodiment will be described. One of the differences between the third embodiment and the second embodiment is that the coverlay is not provided inside the component mounting portion, and the boundary region between the component mounting portion of the printed wiring board and the flexible cable portion. It is to provide. As a result, there is no need to consider the flow of the adhesive filling the inner layer circuit pattern of the component mounting portion, so the options for the adhesive are expanded. Furthermore, since the thickness of the printed wiring board in the component mounting portion can be reduced, the outer layer circuit pattern can be further miniaturized.
図3A~図3Cを用いて、本実施形態に係るスタックビア構造を有するビルドアップ型多層プリント配線板の製造方法について説明する。図3A~図3Cは、本実施形態に係るビルドアップ型多層プリント配線板の製造方法を示す工程断面図である。
A method for manufacturing a build-up type multilayer printed wiring board having a stack via structure according to the present embodiment will be described with reference to FIGS. 3A to 3C. 3A to 3C are process cross-sectional views illustrating the method for manufacturing the build-up type multilayer printed wiring board according to the present embodiment.
第2の実施形態の図2A(3)に示す基材を得るまでの工程は、第2の実施形態と同じであるため、説明を省略し、それ以降の工程から説明する。
Since the process until obtaining the base material shown in FIG. 2A (3) of the second embodiment is the same as that of the second embodiment, the description thereof will be omitted and the subsequent processes will be described.
(1)ポリイミド等からなる絶縁フィルム61(例えば12μm厚)と、絶縁フィルム61の片面に形成された接着剤層62(例えば8μm厚)とを有するカバーレイ63を準備する。接着剤層62は、例えばアクリル、エポキシ等の接着剤からなる。そして、図3A(1)に示すように、真空ラミネータ等を用いて、部品実装部76aと可撓性ケーブル部76bとの境界領域における両面回路基材(内層回路パターン34A,34Bが形成された基板)にカバーレイ63を貼り付けるラミネート工程を行う。他の方法として、境界領域に接着剤層62を形成した後、この接着剤層62の上に絶縁フィルム61を形成してもよい。
(1) A coverlay 63 having an insulating film 61 (for example, 12 μm thick) made of polyimide or the like and an adhesive layer 62 (for example, 8 μm thick) formed on one surface of the insulating film 61 is prepared. The adhesive layer 62 is made of an adhesive such as acrylic or epoxy. And as shown to FIG. 3A (1), the double-sided circuit base material ( inner circuit pattern 34A, 34B was formed in the boundary area | region of the component mounting part 76a and the flexible cable part 76b using a vacuum laminator etc. A laminating process of attaching the coverlay 63 to the substrate) is performed. As another method, after the adhesive layer 62 is formed in the boundary region, the insulating film 61 may be formed on the adhesive layer 62.
(2)次に、図3A(2)からわかるように、前工程で得られた基材の両面の部品実装部76aとなる領域にめっきレジスト層64を形成する。このめっきレジスト層64は、ブラインドビアホールの受けランド部に開口部65bを有する。なお、内層端子が形成される領域については、図3A(2)からわかるように、カバーレイ63がめっきレジスト層となる。また、図3A(2)に示すように、めっきレジスト層64は、埋込みビア6が露出している領域に開口部65aを有してもよい。この開口部65aを設けるか否かは任意である。
(2) Next, as can be seen from FIG. 3A (2), a plating resist layer 64 is formed in the regions to be the component mounting portions 76a on both sides of the base material obtained in the previous step. The plating resist layer 64 has an opening 65b in the receiving land portion of the blind via hole. In addition, as for the area | region in which an inner layer terminal is formed, the coverlay 63 becomes a plating resist layer so that FIG. 3A (2) may show. Further, as shown in FIG. 3A (2), the plating resist layer 64 may have an opening 65a in a region where the embedded via 6 is exposed. Whether or not the opening 65a is provided is arbitrary.
(3)次に、図3A(2)に示すように、めっきレジスト層64及びカバーレイ63を用いて電解または無電解めっきを行うことにより、めっきレジスト層64の開口部65a,65bに露出した電解銅めっき皮膜31及び32上に、銀めっき層(0.5μm厚)からなる蓋めっき層66を形成する。その後、めっきレジスト層64を剥離する。なお、めっきリードが繋がらない部分が存在する場合、無電解めっきを行う。図3A(2)からわかるように、本工程のめっき処理により、内層端子となる銅めっき層の表面にも、端子保護膜となる銀めっき層(蓋めっき層66)が形成され、内層端子67が完成する。
(3) Next, as shown in FIG. 3A (2), by performing electrolysis or electroless plating using the plating resist layer 64 and the coverlay 63, the openings 65a and 65b of the plating resist layer 64 are exposed. A lid plating layer 66 made of a silver plating layer (0.5 μm thick) is formed on the electrolytic copper plating films 31 and 32. Thereafter, the plating resist layer 64 is peeled off. If there is a portion where the plating lead is not connected, electroless plating is performed. As can be seen from FIG. 3A (2), a silver plating layer (lid plating layer 66) serving as a terminal protective film is also formed on the surface of the copper plating layer serving as the inner layer terminal by the plating treatment in this step, and the inner layer terminal 67 is formed. Is completed.
蓋めっき層66の表層を構成するめっき層は、後の粗化処理で用いられる銅エッチャントに対する耐性を有することが必要である。銀めっき層はこの条件を満たす。この蓋めっき層66は、第2の実施形態における蓋めっき層37と同様な材料及び構成を採ることができる。
The plating layer constituting the surface layer of the lid plating layer 66 needs to have resistance to the copper etchant used in the subsequent roughening treatment. The silver plating layer satisfies this condition. The lid plating layer 66 can adopt the same material and configuration as the lid plating layer 37 in the second embodiment.
ここまでの工程を経て、図3A(3)に示す両面コア基板68を得る。
Through the steps so far, a double-sided core substrate 68 shown in FIG. 3A (3) is obtained.
(4)次に、ビルドアップ層の積層に用いる接着材(後述の接着材層71)との密着性を向上させるために、内層回路パターン34A及び34Bの表面に粗化処理を施す。この粗化処理は第1の実施形態で説明した方法と同様にして行うことができる。
(4) Next, in order to improve the adhesiveness with the adhesive (adhesive material layer 71 described later) used for stacking the buildup layers, the surface of the inner layer circuit patterns 34A and 34B is subjected to a roughening treatment. This roughening process can be performed in the same manner as the method described in the first embodiment.
後にレーザ光を照射される部分である蓋めっき層66は、第1の実施形態と同様、銅エッチャント耐性を有する銀めっき層で構成されている。このため、本工程の粗化処理によって、蓋めっき層66は粗化されない。したがって、受けランド部における炭酸ガスレーザ光の吸収率は増加せず、低い吸収率が維持される。
The lid plating layer 66, which is a portion to be irradiated with laser light later, is composed of a silver plating layer having copper etchant resistance, as in the first embodiment. For this reason, the lid plating layer 66 is not roughened by the roughening treatment in this step. Therefore, the absorption rate of the carbon dioxide laser beam in the receiving land portion does not increase, and a low absorption rate is maintained.
(5)次に、部品実装部における内層回路パターン34A,34B及び蓋めっき層66を充填する接着剤層71を形成する。この接着剤層71を形成する際、カバーレイ63は、接着剤が部品実装領域76aから可撓性ケーブル部76bに流れ出すのを防ぐダムのように働く。よって、本工程では、ローフロータイプのプリプレグやボンディングシート等といった流れ出しの少ない接着剤の他、流れ出しの多い接着剤を使用することもできる。
(5) Next, the adhesive layer 71 filling the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion is formed. When the adhesive layer 71 is formed, the cover lay 63 functions like a dam that prevents the adhesive from flowing out from the component mounting region 76a to the flexible cable portion 76b. Therefore, in this step, an adhesive with a high flow-out can be used in addition to an adhesive with a low flow-out such as a low-flow type prepreg or a bonding sheet.
(6)次に、図3B(4)に示すように、可撓性絶縁ベース材69a(例えば厚さ25μmのポリイミドフィルム)の片面に、銅箔69b(12μm厚)を有する片面銅張積層板69を準備する。そして、第1の実施形態と同様にして、フォトファブリケーション手法を用いて、片面銅張積層板69の銅箔69bに、ブラインドビアホールを形成するためのコンフォーマルマスク70(開口部)を形成する。
(6) Next, as shown in FIG. 3B (4), a single-sided copper-clad laminate having a copper foil 69b (12 μm thick) on one side of a flexible insulating base material 69a (for example, a polyimide film having a thickness of 25 μm). Prepare 69. In the same manner as in the first embodiment, a conformal mask 70 (opening) for forming blind via holes is formed in the copper foil 69b of the single-sided copper-clad laminate 69 using the photofabrication technique. .
(7)次に、図3B(4)に示すように、コンフォーマルマスク70が形成された片面銅張積層板69を、ビルドアップするための接着剤からなる接着剤層71を介して両面コア基板68の表面及び裏面に積層接着する。
(7) Next, as shown in FIG. 3B (4), the single-sided copper-clad laminate 69 with the conformal mask 70 formed on the double-sided core via an adhesive layer 71 made of an adhesive for build-up. The substrate 68 is laminated and adhered to the front and back surfaces.
(8)次に、図3B(5)に示すように、第1の実施形態と同様にして、コンフォーマルマスク70を用いてレーザ加工を行い、ブラインドビアホール72A,72B(導通用孔)を形成する。
(9)次に、ブラインドビアホール72A,72Bを形成する際に生じた樹脂残渣を除去するために、デスミア工程を行う。 (8) Next, as shown in FIG. 3B (5), in the same manner as in the first embodiment, laser processing is performed using theconformal mask 70 to form blind via holes 72A and 72B (conduction holes). To do.
(9) Next, a desmear process is performed in order to remove the resin residue generated when the blind via holes 72A and 72B are formed.
(9)次に、ブラインドビアホール72A,72Bを形成する際に生じた樹脂残渣を除去するために、デスミア工程を行う。 (8) Next, as shown in FIG. 3B (5), in the same manner as in the first embodiment, laser processing is performed using the
(9) Next, a desmear process is performed in order to remove the resin residue generated when the blind via
(10)次に、図3C(6)に示すように、導電化処理とそれに続く電解銅めっき処理を施すことにより、ブラインドビアホール72A,72Bの内壁(側面および底面)及び蓋めっき層66上に、電解銅めっき皮膜73を形成する。この電解銅めっき皮膜73の厚みは、層間導通を確保するために15~20μm程度とした。これにより、層間導電路として機能するブラインドビア74A,74Bが形成される。
(10) Next, as shown in FIG. 3C (6), by conducting a conductive treatment and a subsequent electrolytic copper plating treatment, the inner walls (side and bottom surfaces) of the blind via holes 72A and 72B and the lid plating layer 66 are formed. Then, an electrolytic copper plating film 73 is formed. The thickness of the electrolytic copper plating film 73 was set to about 15 to 20 μm in order to ensure interlayer conduction. Thereby, blind vias 74A and 74B functioning as interlayer conductive paths are formed.
(11)次に、図3C(7)に示すように、フォトファブリケーション手法により、ビルドアップ層上の導電層(銅箔69b及びその上の電解銅めっき被膜73)を所定のパターンに加工して、外層回路パターン75を形成する。
(11) Next, as shown in FIG. 3C (7), the conductive layer (copper foil 69b and the electrolytic copper plating film 73 thereon) is processed into a predetermined pattern by a photofabrication technique. Thus, the outer layer circuit pattern 75 is formed.
この後、図示しないが、必要に応じて、はんだ付けが不要な部分には保護用のフォトソルダーレジスト層を形成し、ランド部等の表面には半田めっき、ニッケルめっき、金めっき等の表面処理を施す。その後、金型による抜き打ち等により外形加工を行う。
After this, although not shown, if necessary, a protective photo solder resist layer is formed on the part where soldering is not required, and the surface of the land part or the like is subjected to surface treatment such as solder plating, nickel plating, or gold plating. Apply. Thereafter, the outer shape is processed by punching with a mold or the like.
以上の工程を経て、第3の実施形態に係るビルドアップ型多層プリント配線板76を得る。図3C(7)に示すように、本実施形態に係るビルドアップ型多層プリント配線板76は、埋込みビア6とブラインドビア74Aから構成されるスタックビア構造を有する。
Through the above steps, the build-up type multilayer printed wiring board 76 according to the third embodiment is obtained. As shown in FIG. 3C (7), the build-up type multilayer printed wiring board 76 according to the present embodiment has a stacked via structure including the embedded via 6 and the blind via 74A.
図3C(7)に示すように、ビルドアップ型多層プリント配線板76は、両面コア基板68にビルドアップ層が積層された部品実装部76aと、この部品実装部76aから延伸する可撓性ケーブル部76bとを有する。この可撓性ケーブル部24bは、ビルドアップ層が設けられていない両面コア基板68の一部である。この可撓性ケーブル部76bには、可撓性絶縁ベース材1上に露出した内層端子67が設けられている。この内層端子67を可撓性絶縁ベース材1上に複数形成し、可撓性のコネクタ領域を構成してもよい。
As shown in FIG. 3C (7), the build-up type multilayer printed wiring board 76 includes a component mounting portion 76a in which a build-up layer is laminated on a double-sided core substrate 68, and a flexible cable extending from the component mounting portion 76a. Part 76b. The flexible cable portion 24b is a part of the double-sided core board 68 that is not provided with a buildup layer. The flexible cable portion 76 b is provided with an inner layer terminal 67 exposed on the flexible insulating base material 1. A plurality of inner layer terminals 67 may be formed on the flexible insulating base material 1 to constitute a flexible connector region.
また、図3C(7)に示すように、接着剤層62及び絶縁フィルム61を順次積層したものとして構成されたカバーレイ63が、 部品実装部76aと可撓性ケーブル部76bの境界領域における可撓性絶縁ベース材1の上に設けられている。
Further, as shown in FIG. 3C (7), the cover lay 63 configured by sequentially laminating the adhesive layer 62 and the insulating film 61 is formed in the boundary region between the component mounting portion 76a and the flexible cable portion 76b. It is provided on the flexible insulating base material 1.
接着剤層71は、部品実装部76aにおける内層回路パターン34A,34B及び蓋めっき層66を充填する。この接着剤層71の厚みは、カバーレイ63の厚み以上である必要があり、好ましくはカバーレイ63の厚みと同じである。
The adhesive layer 71 is filled with the inner layer circuit patterns 34A and 34B and the lid plating layer 66 in the component mounting portion 76a. The thickness of the adhesive layer 71 needs to be equal to or greater than the thickness of the cover lay 63 and is preferably the same as the thickness of the cover lay 63.
なお,本実施形態では、両面コア基板68の表面および裏面にビルドアップ層を設けたが、片面にのみビルドアップ層を設けるようにしてもよい。
In this embodiment, the buildup layers are provided on the front and back surfaces of the double-sided core substrate 68, but the buildup layers may be provided only on one side.
以上説明したように、本実施形態では、カバーレイ63は、部品実装部76aと可撓性ケーブル部76bの境界領域に設けられ、部品実装部76aの内部には設けられない。このため、部品実装部76aの内層回路パターン34A,34Bを充填する接着剤の可撓性ケーブル部76bへの流れ出しを考慮する必要がなくなるため、接着剤層71の形成に用いられる接着剤の選択肢が広がる。さらに、部品実装部76aにおけるプリント配線板の厚みを低減することができるため、ブラインドビアホール72A,72Bをさらに浅くすることができる。この結果、本実施形態によれば、外層回路パターン75をさらに微細に形成することが可能となる。
As described above, in the present embodiment, the coverlay 63 is provided in the boundary region between the component mounting portion 76a and the flexible cable portion 76b, and is not provided inside the component mounting portion 76a. For this reason, it is not necessary to consider the flow of the adhesive filling the inner layer circuit patterns 34A and 34B of the component mounting portion 76a to the flexible cable portion 76b. Therefore, the choice of the adhesive used for forming the adhesive layer 71 is eliminated. Spread. Furthermore, since the thickness of the printed wiring board in the component mounting portion 76a can be reduced, the blind via holes 72A and 72B can be further shallowed. As a result, according to the present embodiment, the outer layer circuit pattern 75 can be further finely formed.
さらに、第1及び第2の実施形態と同様、本実施形態においては、スタックビア構造を構成しないブラインドビアホール72Bについても、受けランド部に蓋めっき層66を設けている。このため、ブラインドビアホール72Bの構造(ビアの深さ等)は、スタックビア構造用のブラインドビアホール72Aとほぼ同じになる。よって、スタックビア構造用か否かに拘わらず、ブラインドビアホールを形成する際のレーザ加工の条件及びデスミア工程の条件を同一とすることができる。その結果、本実施形態によれば、大きな加工マージンを確保することができ、生産性を向上させることができる。
Furthermore, as in the first and second embodiments, in this embodiment, the lid plating layer 66 is provided on the receiving land portion of the blind via hole 72B that does not constitute the stacked via structure. Therefore, the structure of the blind via hole 72B (via depth, etc.) is substantially the same as the blind via hole 72A for the stacked via structure. Therefore, regardless of whether it is for the stacked via structure or not, the laser processing conditions and the desmear process conditions when forming the blind via holes can be made the same. As a result, according to this embodiment, a large processing margin can be ensured and productivity can be improved.
さらに、第2の実施形態と同様、内層端子67の表面めっき層の形成を、蓋めっき層66の形成と同時に行うことができる。これにより、工程数を削減し、生産性を向上させることが可能となる。
Furthermore, as in the second embodiment, the surface plating layer of the inner layer terminal 67 can be formed simultaneously with the formation of the lid plating layer 66. Thereby, it becomes possible to reduce the number of processes and improve productivity.
以上、本発明に係る3つの実施形態について説明した。上記実施形態の説明では、配線パターン及びめっき皮膜は銅からなるものとしたが、本発明はこれに限定されるものではなく、例えばアルミニウムや銀など他の金属でもよい。
The three embodiments according to the present invention have been described above. In the description of the above embodiment, the wiring pattern and the plating film are made of copper. However, the present invention is not limited to this, and other metals such as aluminum and silver may be used.
また、第1および第2の実施形態では、内層回路パターンが形成された基板にカバーレイをラミネートして、両面コア基板を作製し、その後、両面コア基板にビルドアップ層を積層接着して、ビルドアップ型多層プリント配線板を作製したが、本発明はこれに限らない。即ち、内層回路パターン及び蓋めっき層を充填する接着剤層を介して、基板に直接、ビルドアップ層を積層してもよい。例えば、表面に銅箔を有するカバーレイを使用することができる。図5(a)は、第1の実施形態で説明した両面回路基材12(図1B(7)参照)に、絶縁フィルム13の表面および裏面にそれぞれ銅箔15aおよび接着剤層14を有するカバーレイ15Xをラミネートした状態を示す断面図である。図5(b)は、第2の実施形態で説明した両面回路基材38(図2B(5)参照)に、絶縁フィルム39の表面および裏面にそれぞれ銅箔41aおよび接着剤層40を有するカバーレイ41Xをラミネートした状態を示す断面図である。このような構成によれば、部品実装部におけるプリント配線板の厚みをさらに低減し、外層回路パターンをより微細化することができる。
In the first and second embodiments, a coverlay is laminated on a substrate on which an inner layer circuit pattern is formed to produce a double-sided core substrate, and then a build-up layer is laminated and adhered to the double-sided core substrate, Although a build-up type multilayer printed wiring board was produced, the present invention is not limited to this. That is, the build-up layer may be laminated directly on the substrate via an adhesive layer filling the inner layer circuit pattern and the lid plating layer. For example, a coverlay having a copper foil on the surface can be used. FIG. 5A shows a cover having the double-sided circuit substrate 12 described in the first embodiment (see FIG. 1B (7)) having a copper foil 15a and an adhesive layer 14 on the front and back surfaces of the insulating film 13, respectively. It is sectional drawing which shows the state which laminated | laid the ray 15X. FIG. 5B shows a cover having the double-sided circuit substrate 38 described in the second embodiment (see FIG. 2B (5)) having a copper foil 41a and an adhesive layer 40 on the front and back surfaces of the insulating film 39, respectively. It is sectional drawing which shows the state which laminated | stacked the ray 41X. According to such a configuration, the thickness of the printed wiring board in the component mounting portion can be further reduced, and the outer layer circuit pattern can be further miniaturized.
上記の記載に基づいて、当業者であれば、本発明の追加の効果や種々の変形を想到できるかもしれないが、本発明の態様は、上述した個々の実施形態に限定されるものではない。異なる実施形態にわたる構成要素を適宜組み合わせてもよい。特許請求の範囲に規定された内容及びその均等物から導き出される本発明の概念的な思想と趣旨を逸脱しない範囲で種々の追加、変更及び部分的削除が可能である。
Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the individual embodiments described above. . You may combine suitably the component covering different embodiment. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.
1,101 可撓性絶縁ベース材
2,2a,3,3a,102,103 銅箔
4,104 両面銅張積層板
5,105 スルーホール
6A 導電性ペースト
6,106 埋込みビア
7,35,64 めっきレジスト層
8a,8b,36a,36b,36c,65a,65b 開口部
9,37,66,107 蓋めっき層
9a 銅めっき層
9b 銀めっき層
10,33 エッチングレジスト層
11A,11B,34A,34B 内層回路パターン
12,38 両面回路基材
13,39,61 絶縁フィルム
14,40,62,110 接着材層
15,41,63,111,15X,41X カバーレイ
15a,41a 銅箔
16,42,68,112 両面コア基板
17,43,69,113 片面銅張積層板
17a,43a,69a,113a 可撓性絶縁ベース材
17b,43b,69b,113b 銅箔
18,44,70 コンフォーマルマスク
19,45,71,114 接着材層
20A,20B,46A,46B,72A,72B,115A,115B ブラインドビアホール(導通用孔)
21,31,32,47,73 電解銅めっき皮膜
22A,22B,48A,48B,74A,74B,116A,116B ブラインドビア
23,49,75,117 外層回路パターン
24,51,76,118 ビルドアップ型多層プリント配線板
24a,51a,76a,118a 部品実装部
24b,51b,76b,118b 可撓性ケーブル部
50,67 内層端子
108 受けランド部
109 ポリイミドフィルム 1,101 Flexible insulating base material 2,2a, 3,3a, 102,103 Copper foil 4,104 Double-sided copper-clad laminate 5,105 Through hole 6A Conductive paste 6,106 Embedded via 7,35,64 Plating Resist layer 8a, 8b, 36a, 36b, 36c, 65a, 65b Opening 9, 37, 66, 107 Lid plating layer 9a Copper plating layer 9b Silver plating layer 10, 33 Etching resist layer 11A, 11B, 34A, 34B Inner layer circuit Pattern 12, 38 Double-sided circuit base material 13, 39, 61 Insulating film 14, 40, 62, 110 Adhesive layer 15, 41, 63, 111, 15X, 41X Coverlay 15a, 41a Copper foil 16, 42, 68, 112 Double- sided core substrate 17, 43, 69, 113 Single-sided copper-clad laminate 17a, 43a, 69a, 113a Flexible insulating base material 17b, 43b, 69b, 113b Copper foil 18, 44, 70 Conformal masks 19, 45, 71, 114 Adhesive layers 20A, 20B, 46A, 46B, 72A, 72B, 115A, 115B Blind via holes (conduction holes)
21, 31, 32, 47, 73 Electrolytic copper plating film 22A, 22B, 48A, 48B, 74A, 74B, 116A, 116B Blind via 23, 49, 75, 117 Outer circuit pattern 24, 51, 76, 118 Build-up type Multilayer printed wiring boards 24a, 51a, 76a, 118a Component mounting parts 24b, 51b, 76b, 118b Flexible cable parts 50, 67 Inner layer terminal 108 Receiving land part 109 Polyimide film
2,2a,3,3a,102,103 銅箔
4,104 両面銅張積層板
5,105 スルーホール
6A 導電性ペースト
6,106 埋込みビア
7,35,64 めっきレジスト層
8a,8b,36a,36b,36c,65a,65b 開口部
9,37,66,107 蓋めっき層
9a 銅めっき層
9b 銀めっき層
10,33 エッチングレジスト層
11A,11B,34A,34B 内層回路パターン
12,38 両面回路基材
13,39,61 絶縁フィルム
14,40,62,110 接着材層
15,41,63,111,15X,41X カバーレイ
15a,41a 銅箔
16,42,68,112 両面コア基板
17,43,69,113 片面銅張積層板
17a,43a,69a,113a 可撓性絶縁ベース材
17b,43b,69b,113b 銅箔
18,44,70 コンフォーマルマスク
19,45,71,114 接着材層
20A,20B,46A,46B,72A,72B,115A,115B ブラインドビアホール(導通用孔)
21,31,32,47,73 電解銅めっき皮膜
22A,22B,48A,48B,74A,74B,116A,116B ブラインドビア
23,49,75,117 外層回路パターン
24,51,76,118 ビルドアップ型多層プリント配線板
24a,51a,76a,118a 部品実装部
24b,51b,76b,118b 可撓性ケーブル部
50,67 内層端子
108 受けランド部
109 ポリイミドフィルム 1,101 Flexible insulating
21, 31, 32, 47, 73 Electrolytic
Claims (12)
- 可撓性の絶縁ベース材と、前記絶縁ベース材の両面に設けられ、受けランド部を有する内層回路パターンと、前記絶縁ベース材を厚さ方向に貫通し、前記絶縁ベース材の表面及び裏面の前記内層回路パターンを電気的に接続する埋込みビアとを有する、両面回路基材と、
前記両面回路基材に絶縁層を介して積層された、表面に外層回路パターンを有するビルドアップ層と、を備えるとともに、
表層が前記内層回路パターンを構成する金属のエッチャントに対して耐性を有する材料からなり、前記受けランド部を被覆する蓋めっき層と、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールの内壁に形成されためっき皮膜からなり、前記内層回路パターンと前記外層回路パターンを電気的に接続するブラインドビアとを備えることを特徴とするビルドアップ型多層プリント配線板。 A flexible insulating base material, an inner layer circuit pattern provided on both surfaces of the insulating base material and having receiving land portions, and through the insulating base material in the thickness direction, and on the front and back surfaces of the insulating base material A double-sided circuit substrate having embedded vias to electrically connect the inner layer circuit pattern;
With a build-up layer laminated on the double-sided circuit substrate via an insulating layer and having an outer layer circuit pattern on the surface,
The surface layer is made of a material resistant to the metal etchant constituting the inner layer circuit pattern, penetrates the receiving land portion in the thickness direction, penetrates the build-up layer in the thickness direction, and has the lid on the bottom surface. A build-up type multilayer printed wiring board comprising a plating film formed on an inner wall of a blind via hole having an exposed plating layer, and comprising a blind via for electrically connecting the inner layer circuit pattern and the outer layer circuit pattern . - 前記内層回路パターンは銅からなり、前記蓋めっき層の少なくとも表層は、銀、金、又はニッケルからなることを特徴とする請求項1に記載のビルドアップ型多層プリント配線板。 The build-up type multilayer printed wiring board according to claim 1, wherein the inner layer circuit pattern is made of copper, and at least the surface layer of the lid plating layer is made of silver, gold, or nickel.
- 絶縁フィルムと、前記絶縁フィルムの上に形成された接着剤層と有するカバーレイであって、前記両面回路基材のうち前記ビルドアップ層が積層された部品実装部と、前記両面回路基材のうち前記ビルドアップ層が積層されていない可撓性ケーブル部との境界領域における、前記両面回路基材の上に形成されたカバーレイをさらに備え、前記絶縁層は、前記カバーレイの厚み以上の厚みを有することを特徴とする請求項1に記載のビルドアップ型多層プリント配線板。 A cover lay having an insulating film and an adhesive layer formed on the insulating film, wherein the component mounting part in which the build-up layer is laminated among the double-sided circuit bases, and the double-sided circuit bases Among them, a cover lay formed on the double-sided circuit base material in a boundary region with the flexible cable portion where the build-up layer is not laminated is further provided, and the insulating layer has a thickness equal to or greater than the thickness of the cover lay. The build-up type multilayer printed wiring board according to claim 1, which has a thickness.
- 前記内層回路パターンは銅からなり、前記蓋めっき層の少なくとも表層は、銀、金、又はニッケルからなることを特徴とする請求項3に記載のビルドアップ型多層プリント配線板。 The build-up type multilayer printed wiring board according to claim 3, wherein the inner layer circuit pattern is made of copper, and at least a surface layer of the lid plating layer is made of silver, gold, or nickel.
- 可撓性の絶縁ベース材と、その両面に設けられた第1の金属箔とを有する両面金属張積層板を準備し、
前記両面金属張積層板を厚さ方向に貫通するスルーホールを形成し、
前記スルーホールの内部に導電性ペーストを充填した後、前記導電性ペーストを硬化させて、埋込みビアを形成し、
少なくとも表層が前記第1の金属箔のエッチャントに対して耐性を有する材料からなる蓋めっき層を所定の領域に形成し、
所定のパターンを有するレジスト層を前記第1の金属箔上に形成し、
前記レジスト層及び前記蓋めっき層をエッチングレジストとして用いて前記第1の金属箔をエッチングすることにより、前記蓋めっき層で覆われた受けランド部を有する内層回路パターンを形成し、これにより、両面回路基材を得、
前記内層回路パターンの表面に粗化処理を施した後、絶縁フィルムと、前記絶縁フィルムの片面に形成された第1の接着剤層とを有するカバーレイを、前記両面回路基材に貼り付けるラミネート工程を行い、これにより、両面コア基板を得、
表面に第2の金属箔を有するビルドアップ層を、第2の接着剤層を介して前記両面コア基板に積層し、
前記ビルドアップ層の所定の位置に赤外レーザ光を照射することにより、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールを形成し、
前記ブラインドビアホールの内壁及び前記第2の金属箔上にめっき皮膜を形成することにより、前記第2の金属箔と前記内層回路パターンとを電気的に接続するブラインドビアを形成する、
ことを特徴とするビルドアップ型多層プリント配線板の製造方法。 Preparing a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof;
Forming a through hole penetrating the double-sided metal-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a lid plating layer made of a material having at least a surface layer resistant to the etchant of the first metal foil in a predetermined region;
Forming a resist layer having a predetermined pattern on the first metal foil;
By etching the first metal foil using the resist layer and the lid plating layer as an etching resist, an inner layer circuit pattern having a receiving land portion covered with the lid plating layer is formed. Obtain a circuit substrate,
Laminate for applying a coverlay having an insulating film and a first adhesive layer formed on one side of the insulating film to the double-sided circuit substrate after roughening the surface of the inner layer circuit pattern Perform the process, thereby obtaining a double-sided core substrate,
A build-up layer having a second metal foil on the surface is laminated on the double-sided core substrate via a second adhesive layer,
By irradiating a predetermined position of the build-up layer with infrared laser light, the build-up layer penetrates in the thickness direction, and a blind via hole in which the lid plating layer is exposed on the bottom surface is formed,
By forming a plating film on the inner wall of the blind via hole and the second metal foil, a blind via that electrically connects the second metal foil and the inner layer circuit pattern is formed.
A manufacturing method of a build-up type multilayer printed wiring board characterized by the above. - 前記第1の金属箔は銅箔であり、前記蓋めっき層の少なくとも表層は、銀、金、又はニッケルからなることを特徴とする請求項5に記載のビルドアップ型多層プリント配線板の製造方法。 6. The method of manufacturing a build-up type multilayer printed wiring board according to claim 5, wherein the first metal foil is a copper foil, and at least a surface layer of the lid plating layer is made of silver, gold, or nickel. .
- 可撓性の絶縁ベース材と、その両面に設けられた第1の金属箔とを有する両面金属張積層板を準備し、
前記両面金属張積層板を厚さ方向に貫通するスルーホールを形成し、
前記スルーホールの内部に導電性ペーストを充填した後、前記導電性ペーストを硬化させて、埋込みビアを形成し、
前記第1の金属箔及び露出した前記埋込みビアの上に第1のめっき皮膜を形成し、
前記第1のめっき皮膜上に所定のパターンを有するレジスト層を形成し、
前記レジスト層をエッチングレジストとして用いて前記第1のめっき皮膜及び前記第1の金属箔をエッチングすることにより、受けランド部を有する内層回路パターンを形成し、
少なくとも表層が前記第1の金属箔のエッチャントに対して耐性を有する材料からなる蓋めっき層を、前記受けランド部を被覆するように形成し、これにより、両面回路基材を得、
前記内層回路パターンの表面に粗化処理を施した後、絶縁フィルムと、前記絶縁フィルムの片面に形成された第1の接着剤層とを有するカバーレイを、前記両面回路基材に貼り付けるラミネート工程を行い、これにより、両面コア基板を得、
表層に第2の金属箔を有するビルドアップ層を、第2の接着剤層を介して前記両面コア基板に積層し、
前記ビルドアップ層の所定の位置に赤外レーザ光を照射することにより、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールを形成し、
前記ブラインドビアホールの内壁及び前記第2の金属箔上に第2のめっき皮膜を形成することにより、前記第2の金属箔と前記内層回路パターンとを電気的に接続するブラインドビアを形成する、
ことを特徴とするビルドアップ型多層プリント配線板の製造方法。 Preparing a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof;
Forming a through hole penetrating the double-sided metal-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a first plating film on the first metal foil and the exposed buried via;
Forming a resist layer having a predetermined pattern on the first plating film;
Etching the first plating film and the first metal foil using the resist layer as an etching resist to form an inner layer circuit pattern having a receiving land portion,
A cover plating layer made of a material having at least a surface layer resistant to the etchant of the first metal foil is formed so as to cover the receiving land portion, thereby obtaining a double-sided circuit base material,
Laminate for applying a coverlay having an insulating film and a first adhesive layer formed on one side of the insulating film to the double-sided circuit substrate after roughening the surface of the inner layer circuit pattern Perform the process, thereby obtaining a double-sided core substrate,
A build-up layer having a second metal foil on the surface layer is laminated on the double-sided core substrate via a second adhesive layer,
By irradiating a predetermined position of the build-up layer with infrared laser light, the build-up layer penetrates in the thickness direction, and a blind via hole in which the lid plating layer is exposed on the bottom surface is formed,
By forming a second plating film on the inner wall of the blind via hole and the second metal foil, a blind via that electrically connects the second metal foil and the inner layer circuit pattern is formed.
A manufacturing method of a build-up type multilayer printed wiring board characterized by the above. - 前記第1の金属箔は銅箔であり、前記蓋めっき層の少なくとも表層は、銀、金、又はニッケルからなることを特徴とする請求項7に記載のビルドアップ型多層プリント配線板の製造方法。 The method of manufacturing a build-up type multilayer printed wiring board according to claim 7, wherein the first metal foil is a copper foil, and at least a surface layer of the lid plating layer is made of silver, gold, or nickel. .
- 前記蓋めっき層を形成するめっき処理により、内層端子となる前記内層回路パターンの一部に端子保護膜を形成することを特徴とする請求項7に記載のビルドアップ型多層プリント配線板の製造方法。 8. The method of manufacturing a build-up type multilayer printed wiring board according to claim 7, wherein a terminal protective film is formed on a part of the inner layer circuit pattern serving as an inner layer terminal by a plating process for forming the lid plating layer. .
- 可撓性の絶縁ベース材と、その両面に設けられた第1の金属箔とを有する両面金属張積層板を準備し、
前記両面金属張積層板を厚さ方向に貫通するスルーホールを形成し、
前記スルーホールの内部に導電性ペーストを充填した後、前記導電性ペーストを硬化させて、埋込みビアを形成し、
前記第1の金属箔及び露出した前記埋込みビアの上に第1のめっき皮膜を形成し、
前記第1のめっき皮膜上に所定のパターンを有するレジスト層を形成し、
前記レジスト層をエッチングレジストとして用いて前記第1のめっき皮膜及び前記第1の金属箔をエッチングすることにより、受けランド部を有する内層回路パターンを形成し、これにより、両面回路基材を得、
絶縁フィルムと、前記絶縁フィルムの片面に形成された第1の接着剤層とを有するカバーレイを、部品実装部と可撓性ケーブル部との境界領域における前記両面回路基材に貼り付けるラミネート工程を行い、
少なくとも表層が前記第1の金属箔のエッチャントに対して耐性を有する材料からなる蓋めっき層を、前記受けランド部を被覆するように形成し、これにより、両面コア基板を得、
前記内層回路パターンの表面に粗化処理を施した後、表面に第2の金属箔を有するビルドアップ層を、前記カバーレイの厚み以上の厚みを有する第2の接着剤層を介して、前記部品実装部における前記両面コア基板に積層し、
前記ビルドアップ層の所定の位置に赤外レーザ光を照射することにより、前記ビルドアップ層を厚さ方向に貫通し、底面に前記蓋めっき層が露出したブラインドビアホールを形成し、
前記ブラインドビアホールの内壁及び前記第2の金属箔上に第2のめっき皮膜を形成することにより、前記第2の金属箔と前記内層回路パターンとを電気的に接続するブラインドビアを形成する、
ことを特徴とするビルドアップ型多層プリント配線板の製造方法。 Preparing a double-sided metal-clad laminate having a flexible insulating base material and a first metal foil provided on both sides thereof;
Forming a through hole penetrating the double-sided metal-clad laminate in the thickness direction;
After filling the through hole with a conductive paste, the conductive paste is cured to form a buried via,
Forming a first plating film on the first metal foil and the exposed buried via;
Forming a resist layer having a predetermined pattern on the first plating film;
By etching the first plating film and the first metal foil using the resist layer as an etching resist, an inner layer circuit pattern having a receiving land portion is formed, thereby obtaining a double-sided circuit base material,
A laminating step of attaching a coverlay having an insulating film and a first adhesive layer formed on one side of the insulating film to the double-sided circuit substrate in a boundary region between a component mounting portion and a flexible cable portion And
A cover plating layer made of a material having at least a surface layer resistant to the etchant of the first metal foil is formed so as to cover the receiving land portion, thereby obtaining a double-sided core substrate,
After roughening the surface of the inner layer circuit pattern, the build-up layer having the second metal foil on the surface is passed through the second adhesive layer having a thickness equal to or greater than the thickness of the coverlay. Laminated on the double-sided core board in the component mounting part,
By irradiating a predetermined position of the build-up layer with infrared laser light, the build-up layer penetrates in the thickness direction, and a blind via hole in which the lid plating layer is exposed on the bottom surface is formed,
By forming a second plating film on the inner wall of the blind via hole and the second metal foil, a blind via that electrically connects the second metal foil and the inner layer circuit pattern is formed.
A manufacturing method of a build-up type multilayer printed wiring board characterized by the above. - 前記第1の金属箔は銅箔であり、前記蓋めっき層の少なくとも表層は、銀、金、又はニッケルからなることを特徴とする請求項10に記載のビルドアップ型多層プリント配線板の製造方法。 The method of manufacturing a build-up type multilayer printed wiring board according to claim 10, wherein the first metal foil is a copper foil, and at least a surface layer of the lid plating layer is made of silver, gold, or nickel. .
- 前記蓋めっき層を形成するめっき処理により、内層端子となる前記内層回路パターンの一部に端子保護膜を形成することを特徴とする請求項10に記載のビルドアップ型多層プリント配線板の製造方法。 The method for producing a build-up type multilayer printed wiring board according to claim 10, wherein a terminal protective film is formed on a part of the inner layer circuit pattern serving as an inner layer terminal by a plating process for forming the lid plating layer. .
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